Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

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ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_ll_fsmc.h
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief Header file of FSMC HAL module.
ganlikun 0:13413ea9a877 8 ******************************************************************************
ganlikun 0:13413ea9a877 9 * @attention
ganlikun 0:13413ea9a877 10 *
ganlikun 0:13413ea9a877 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 12 *
ganlikun 0:13413ea9a877 13 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 14 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 15 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 16 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 18 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 19 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 21 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 22 * without specific prior written permission.
ganlikun 0:13413ea9a877 23 *
ganlikun 0:13413ea9a877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 34 *
ganlikun 0:13413ea9a877 35 ******************************************************************************
ganlikun 0:13413ea9a877 36 */
ganlikun 0:13413ea9a877 37
ganlikun 0:13413ea9a877 38 /* Define to prevent recursive inclusion -------------------------------------*/
ganlikun 0:13413ea9a877 39 #ifndef __STM32F4xx_LL_FSMC_H
ganlikun 0:13413ea9a877 40 #define __STM32F4xx_LL_FSMC_H
ganlikun 0:13413ea9a877 41
ganlikun 0:13413ea9a877 42 #ifdef __cplusplus
ganlikun 0:13413ea9a877 43 extern "C" {
ganlikun 0:13413ea9a877 44 #endif
ganlikun 0:13413ea9a877 45
ganlikun 0:13413ea9a877 46 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 47 #include "stm32f4xx_hal_def.h"
ganlikun 0:13413ea9a877 48
ganlikun 0:13413ea9a877 49 /** @addtogroup STM32F4xx_HAL_Driver
ganlikun 0:13413ea9a877 50 * @{
ganlikun 0:13413ea9a877 51 */
ganlikun 0:13413ea9a877 52
ganlikun 0:13413ea9a877 53 /** @addtogroup FSMC_LL
ganlikun 0:13413ea9a877 54 * @{
ganlikun 0:13413ea9a877 55 */
ganlikun 0:13413ea9a877 56
ganlikun 0:13413ea9a877 57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
ganlikun 0:13413ea9a877 58 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
ganlikun 0:13413ea9a877 59 /* Private types -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 60 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
ganlikun 0:13413ea9a877 61 * @{
ganlikun 0:13413ea9a877 62 */
ganlikun 0:13413ea9a877 63
ganlikun 0:13413ea9a877 64 /**
ganlikun 0:13413ea9a877 65 * @brief FSMC NORSRAM Configuration Structure definition
ganlikun 0:13413ea9a877 66 */
ganlikun 0:13413ea9a877 67 typedef struct
ganlikun 0:13413ea9a877 68 {
ganlikun 0:13413ea9a877 69 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
ganlikun 0:13413ea9a877 70 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
ganlikun 0:13413ea9a877 71
ganlikun 0:13413ea9a877 72 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
ganlikun 0:13413ea9a877 73 multiplexed on the data bus or not.
ganlikun 0:13413ea9a877 74 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
ganlikun 0:13413ea9a877 75
ganlikun 0:13413ea9a877 76 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
ganlikun 0:13413ea9a877 77 the corresponding memory device.
ganlikun 0:13413ea9a877 78 This parameter can be a value of @ref FSMC_Memory_Type */
ganlikun 0:13413ea9a877 79
ganlikun 0:13413ea9a877 80 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
ganlikun 0:13413ea9a877 81 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
ganlikun 0:13413ea9a877 82
ganlikun 0:13413ea9a877 83 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
ganlikun 0:13413ea9a877 84 valid only with synchronous burst Flash memories.
ganlikun 0:13413ea9a877 85 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
ganlikun 0:13413ea9a877 86
ganlikun 0:13413ea9a877 87 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
ganlikun 0:13413ea9a877 88 the Flash memory in burst mode.
ganlikun 0:13413ea9a877 89 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
ganlikun 0:13413ea9a877 90
ganlikun 0:13413ea9a877 91 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
ganlikun 0:13413ea9a877 92 memory, valid only when accessing Flash memories in burst mode.
ganlikun 0:13413ea9a877 93 This parameter can be a value of @ref FSMC_Wrap_Mode
ganlikun 0:13413ea9a877 94 This mode is available only for the STM32F405/407/4015/417xx devices */
ganlikun 0:13413ea9a877 95
ganlikun 0:13413ea9a877 96 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
ganlikun 0:13413ea9a877 97 clock cycle before the wait state or during the wait state,
ganlikun 0:13413ea9a877 98 valid only when accessing memories in burst mode.
ganlikun 0:13413ea9a877 99 This parameter can be a value of @ref FSMC_Wait_Timing */
ganlikun 0:13413ea9a877 100
ganlikun 0:13413ea9a877 101 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
ganlikun 0:13413ea9a877 102 This parameter can be a value of @ref FSMC_Write_Operation */
ganlikun 0:13413ea9a877 103
ganlikun 0:13413ea9a877 104 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
ganlikun 0:13413ea9a877 105 signal, valid for Flash memory access in burst mode.
ganlikun 0:13413ea9a877 106 This parameter can be a value of @ref FSMC_Wait_Signal */
ganlikun 0:13413ea9a877 107
ganlikun 0:13413ea9a877 108 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
ganlikun 0:13413ea9a877 109 This parameter can be a value of @ref FSMC_Extended_Mode */
ganlikun 0:13413ea9a877 110
ganlikun 0:13413ea9a877 111 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
ganlikun 0:13413ea9a877 112 valid only with asynchronous Flash memories.
ganlikun 0:13413ea9a877 113 This parameter can be a value of @ref FSMC_AsynchronousWait */
ganlikun 0:13413ea9a877 114
ganlikun 0:13413ea9a877 115 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
ganlikun 0:13413ea9a877 116 This parameter can be a value of @ref FSMC_Write_Burst */
ganlikun 0:13413ea9a877 117
ganlikun 0:13413ea9a877 118 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
ganlikun 0:13413ea9a877 119 This parameter is only enabled through the FMC_BCR1 register, and don't care
ganlikun 0:13413ea9a877 120 through FMC_BCR2..4 registers.
ganlikun 0:13413ea9a877 121 This parameter can be a value of @ref FMC_Continous_Clock
ganlikun 0:13413ea9a877 122 This mode is available only for the STM32F412Vx/Zx/Rx devices */
ganlikun 0:13413ea9a877 123
ganlikun 0:13413ea9a877 124 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
ganlikun 0:13413ea9a877 125 This parameter is only enabled through the FMC_BCR1 register, and don't care
ganlikun 0:13413ea9a877 126 through FMC_BCR2..4 registers.
ganlikun 0:13413ea9a877 127 This parameter can be a value of @ref FMC_Write_FIFO
ganlikun 0:13413ea9a877 128 This mode is available only for the STM32F412Vx/Vx devices */
ganlikun 0:13413ea9a877 129
ganlikun 0:13413ea9a877 130 uint32_t PageSize; /*!< Specifies the memory page size.
ganlikun 0:13413ea9a877 131 This parameter can be a value of @ref FMC_Page_Size */
ganlikun 0:13413ea9a877 132 }FSMC_NORSRAM_InitTypeDef;
ganlikun 0:13413ea9a877 133
ganlikun 0:13413ea9a877 134 /**
ganlikun 0:13413ea9a877 135 * @brief FSMC NORSRAM Timing parameters structure definition
ganlikun 0:13413ea9a877 136 */
ganlikun 0:13413ea9a877 137 typedef struct
ganlikun 0:13413ea9a877 138 {
ganlikun 0:13413ea9a877 139 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
ganlikun 0:13413ea9a877 140 the duration of the address setup time.
ganlikun 0:13413ea9a877 141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
ganlikun 0:13413ea9a877 142 @note This parameter is not used with synchronous NOR Flash memories. */
ganlikun 0:13413ea9a877 143
ganlikun 0:13413ea9a877 144 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
ganlikun 0:13413ea9a877 145 the duration of the address hold time.
ganlikun 0:13413ea9a877 146 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
ganlikun 0:13413ea9a877 147 @note This parameter is not used with synchronous NOR Flash memories. */
ganlikun 0:13413ea9a877 148
ganlikun 0:13413ea9a877 149 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
ganlikun 0:13413ea9a877 150 the duration of the data setup time.
ganlikun 0:13413ea9a877 151 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
ganlikun 0:13413ea9a877 152 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
ganlikun 0:13413ea9a877 153 NOR Flash memories. */
ganlikun 0:13413ea9a877 154
ganlikun 0:13413ea9a877 155 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
ganlikun 0:13413ea9a877 156 the duration of the bus turnaround.
ganlikun 0:13413ea9a877 157 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
ganlikun 0:13413ea9a877 158 @note This parameter is only used for multiplexed NOR Flash memories. */
ganlikun 0:13413ea9a877 159
ganlikun 0:13413ea9a877 160 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
ganlikun 0:13413ea9a877 161 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
ganlikun 0:13413ea9a877 162 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
ganlikun 0:13413ea9a877 163 accesses. */
ganlikun 0:13413ea9a877 164
ganlikun 0:13413ea9a877 165 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
ganlikun 0:13413ea9a877 166 to the memory before getting the first data.
ganlikun 0:13413ea9a877 167 The parameter value depends on the memory type as shown below:
ganlikun 0:13413ea9a877 168 - It must be set to 0 in case of a CRAM
ganlikun 0:13413ea9a877 169 - It is don't care in asynchronous NOR, SRAM or ROM accesses
ganlikun 0:13413ea9a877 170 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
ganlikun 0:13413ea9a877 171 with synchronous burst mode enable */
ganlikun 0:13413ea9a877 172
ganlikun 0:13413ea9a877 173 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
ganlikun 0:13413ea9a877 174 This parameter can be a value of @ref FSMC_Access_Mode */
ganlikun 0:13413ea9a877 175
ganlikun 0:13413ea9a877 176 }FSMC_NORSRAM_TimingTypeDef;
ganlikun 0:13413ea9a877 177
ganlikun 0:13413ea9a877 178 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 179 /**
ganlikun 0:13413ea9a877 180 * @brief FSMC NAND Configuration Structure definition
ganlikun 0:13413ea9a877 181 */
ganlikun 0:13413ea9a877 182 typedef struct
ganlikun 0:13413ea9a877 183 {
ganlikun 0:13413ea9a877 184 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
ganlikun 0:13413ea9a877 185 This parameter can be a value of @ref FSMC_NAND_Bank */
ganlikun 0:13413ea9a877 186
ganlikun 0:13413ea9a877 187 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
ganlikun 0:13413ea9a877 188 This parameter can be any value of @ref FSMC_Wait_feature */
ganlikun 0:13413ea9a877 189
ganlikun 0:13413ea9a877 190 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
ganlikun 0:13413ea9a877 191 This parameter can be any value of @ref FSMC_NAND_Data_Width */
ganlikun 0:13413ea9a877 192
ganlikun 0:13413ea9a877 193 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
ganlikun 0:13413ea9a877 194 This parameter can be any value of @ref FSMC_ECC */
ganlikun 0:13413ea9a877 195
ganlikun 0:13413ea9a877 196 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
ganlikun 0:13413ea9a877 197 This parameter can be any value of @ref FSMC_ECC_Page_Size */
ganlikun 0:13413ea9a877 198
ganlikun 0:13413ea9a877 199 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun 0:13413ea9a877 200 delay between CLE low and RE low.
ganlikun 0:13413ea9a877 201 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 202
ganlikun 0:13413ea9a877 203 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun 0:13413ea9a877 204 delay between ALE low and RE low.
ganlikun 0:13413ea9a877 205 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 206
ganlikun 0:13413ea9a877 207 }FSMC_NAND_InitTypeDef;
ganlikun 0:13413ea9a877 208
ganlikun 0:13413ea9a877 209 /**
ganlikun 0:13413ea9a877 210 * @brief FSMC NAND/PCCARD Timing parameters structure definition
ganlikun 0:13413ea9a877 211 */
ganlikun 0:13413ea9a877 212 typedef struct
ganlikun 0:13413ea9a877 213 {
ganlikun 0:13413ea9a877 214 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
ganlikun 0:13413ea9a877 215 the command assertion for NAND-Flash read or write access
ganlikun 0:13413ea9a877 216 to common/Attribute or I/O memory space (depending on
ganlikun 0:13413ea9a877 217 the memory space timing to be configured).
ganlikun 0:13413ea9a877 218 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 219
ganlikun 0:13413ea9a877 220 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
ganlikun 0:13413ea9a877 221 command for NAND-Flash read or write access to
ganlikun 0:13413ea9a877 222 common/Attribute or I/O memory space (depending on the
ganlikun 0:13413ea9a877 223 memory space timing to be configured).
ganlikun 0:13413ea9a877 224 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 225
ganlikun 0:13413ea9a877 226 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
ganlikun 0:13413ea9a877 227 (and data for write access) after the command de-assertion
ganlikun 0:13413ea9a877 228 for NAND-Flash read or write access to common/Attribute
ganlikun 0:13413ea9a877 229 or I/O memory space (depending on the memory space timing
ganlikun 0:13413ea9a877 230 to be configured).
ganlikun 0:13413ea9a877 231 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 232
ganlikun 0:13413ea9a877 233 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
ganlikun 0:13413ea9a877 234 data bus is kept in HiZ after the start of a NAND-Flash
ganlikun 0:13413ea9a877 235 write access to common/Attribute or I/O memory space (depending
ganlikun 0:13413ea9a877 236 on the memory space timing to be configured).
ganlikun 0:13413ea9a877 237 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 238
ganlikun 0:13413ea9a877 239 }FSMC_NAND_PCC_TimingTypeDef;
ganlikun 0:13413ea9a877 240
ganlikun 0:13413ea9a877 241 /**
ganlikun 0:13413ea9a877 242 * @brief FSMC NAND Configuration Structure definition
ganlikun 0:13413ea9a877 243 */
ganlikun 0:13413ea9a877 244 typedef struct
ganlikun 0:13413ea9a877 245 {
ganlikun 0:13413ea9a877 246 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
ganlikun 0:13413ea9a877 247 This parameter can be any value of @ref FSMC_Wait_feature */
ganlikun 0:13413ea9a877 248
ganlikun 0:13413ea9a877 249 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun 0:13413ea9a877 250 delay between CLE low and RE low.
ganlikun 0:13413ea9a877 251 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 252
ganlikun 0:13413ea9a877 253 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun 0:13413ea9a877 254 delay between ALE low and RE low.
ganlikun 0:13413ea9a877 255 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun 0:13413ea9a877 256
ganlikun 0:13413ea9a877 257 }FSMC_PCCARD_InitTypeDef;
ganlikun 0:13413ea9a877 258 /**
ganlikun 0:13413ea9a877 259 * @}
ganlikun 0:13413ea9a877 260 */
ganlikun 0:13413ea9a877 261 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 262
ganlikun 0:13413ea9a877 263 /* Private constants ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 264 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
ganlikun 0:13413ea9a877 265 * @{
ganlikun 0:13413ea9a877 266 */
ganlikun 0:13413ea9a877 267
ganlikun 0:13413ea9a877 268 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
ganlikun 0:13413ea9a877 269 * @{
ganlikun 0:13413ea9a877 270 */
ganlikun 0:13413ea9a877 271 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
ganlikun 0:13413ea9a877 272 * @{
ganlikun 0:13413ea9a877 273 */
ganlikun 0:13413ea9a877 274 #define FSMC_NORSRAM_BANK1 0x00000000U
ganlikun 0:13413ea9a877 275 #define FSMC_NORSRAM_BANK2 0x00000002U
ganlikun 0:13413ea9a877 276 #define FSMC_NORSRAM_BANK3 0x00000004U
ganlikun 0:13413ea9a877 277 #define FSMC_NORSRAM_BANK4 0x00000006U
ganlikun 0:13413ea9a877 278 /**
ganlikun 0:13413ea9a877 279 * @}
ganlikun 0:13413ea9a877 280 */
ganlikun 0:13413ea9a877 281
ganlikun 0:13413ea9a877 282 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
ganlikun 0:13413ea9a877 283 * @{
ganlikun 0:13413ea9a877 284 */
ganlikun 0:13413ea9a877 285 #define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 286 #define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
ganlikun 0:13413ea9a877 287 /**
ganlikun 0:13413ea9a877 288 * @}
ganlikun 0:13413ea9a877 289 */
ganlikun 0:13413ea9a877 290
ganlikun 0:13413ea9a877 291 /** @defgroup FSMC_Memory_Type FSMC Memory Type
ganlikun 0:13413ea9a877 292 * @{
ganlikun 0:13413ea9a877 293 */
ganlikun 0:13413ea9a877 294 #define FSMC_MEMORY_TYPE_SRAM 0x00000000U
ganlikun 0:13413ea9a877 295 #define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
ganlikun 0:13413ea9a877 296 #define FSMC_MEMORY_TYPE_NOR 0x00000008U
ganlikun 0:13413ea9a877 297 /**
ganlikun 0:13413ea9a877 298 * @}
ganlikun 0:13413ea9a877 299 */
ganlikun 0:13413ea9a877 300
ganlikun 0:13413ea9a877 301 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
ganlikun 0:13413ea9a877 302 * @{
ganlikun 0:13413ea9a877 303 */
ganlikun 0:13413ea9a877 304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
ganlikun 0:13413ea9a877 305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
ganlikun 0:13413ea9a877 306 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
ganlikun 0:13413ea9a877 307 /**
ganlikun 0:13413ea9a877 308 * @}
ganlikun 0:13413ea9a877 309 */
ganlikun 0:13413ea9a877 310
ganlikun 0:13413ea9a877 311 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
ganlikun 0:13413ea9a877 312 * @{
ganlikun 0:13413ea9a877 313 */
ganlikun 0:13413ea9a877 314 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
ganlikun 0:13413ea9a877 315 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 316 /**
ganlikun 0:13413ea9a877 317 * @}
ganlikun 0:13413ea9a877 318 */
ganlikun 0:13413ea9a877 319
ganlikun 0:13413ea9a877 320 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
ganlikun 0:13413ea9a877 321 * @{
ganlikun 0:13413ea9a877 322 */
ganlikun 0:13413ea9a877 323 #define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 324 #define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
ganlikun 0:13413ea9a877 325 /**
ganlikun 0:13413ea9a877 326 * @}
ganlikun 0:13413ea9a877 327 */
ganlikun 0:13413ea9a877 328
ganlikun 0:13413ea9a877 329 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
ganlikun 0:13413ea9a877 330 * @{
ganlikun 0:13413ea9a877 331 */
ganlikun 0:13413ea9a877 332 #define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
ganlikun 0:13413ea9a877 333 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
ganlikun 0:13413ea9a877 334 /**
ganlikun 0:13413ea9a877 335 * @}
ganlikun 0:13413ea9a877 336 */
ganlikun 0:13413ea9a877 337
ganlikun 0:13413ea9a877 338 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
ganlikun 0:13413ea9a877 339 * @note These values are available only for the STM32F405/415/407/417xx devices.
ganlikun 0:13413ea9a877 340 * @{
ganlikun 0:13413ea9a877 341 */
ganlikun 0:13413ea9a877 342 #define FSMC_WRAP_MODE_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 343 #define FSMC_WRAP_MODE_ENABLE 0x00000400U
ganlikun 0:13413ea9a877 344 /**
ganlikun 0:13413ea9a877 345 * @}
ganlikun 0:13413ea9a877 346 */
ganlikun 0:13413ea9a877 347
ganlikun 0:13413ea9a877 348 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
ganlikun 0:13413ea9a877 349 * @{
ganlikun 0:13413ea9a877 350 */
ganlikun 0:13413ea9a877 351 #define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
ganlikun 0:13413ea9a877 352 #define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
ganlikun 0:13413ea9a877 353 /**
ganlikun 0:13413ea9a877 354 * @}
ganlikun 0:13413ea9a877 355 */
ganlikun 0:13413ea9a877 356
ganlikun 0:13413ea9a877 357 /** @defgroup FSMC_Write_Operation FSMC Write Operation
ganlikun 0:13413ea9a877 358 * @{
ganlikun 0:13413ea9a877 359 */
ganlikun 0:13413ea9a877 360 #define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 361 #define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
ganlikun 0:13413ea9a877 362 /**
ganlikun 0:13413ea9a877 363 * @}
ganlikun 0:13413ea9a877 364 */
ganlikun 0:13413ea9a877 365
ganlikun 0:13413ea9a877 366 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
ganlikun 0:13413ea9a877 367 * @{
ganlikun 0:13413ea9a877 368 */
ganlikun 0:13413ea9a877 369 #define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 370 #define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
ganlikun 0:13413ea9a877 371 /**
ganlikun 0:13413ea9a877 372 * @}
ganlikun 0:13413ea9a877 373 */
ganlikun 0:13413ea9a877 374
ganlikun 0:13413ea9a877 375 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
ganlikun 0:13413ea9a877 376 * @{
ganlikun 0:13413ea9a877 377 */
ganlikun 0:13413ea9a877 378 #define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 379 #define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
ganlikun 0:13413ea9a877 380 /**
ganlikun 0:13413ea9a877 381 * @}
ganlikun 0:13413ea9a877 382 */
ganlikun 0:13413ea9a877 383
ganlikun 0:13413ea9a877 384 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
ganlikun 0:13413ea9a877 385 * @{
ganlikun 0:13413ea9a877 386 */
ganlikun 0:13413ea9a877 387 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 388 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
ganlikun 0:13413ea9a877 389 /**
ganlikun 0:13413ea9a877 390 * @}
ganlikun 0:13413ea9a877 391 */
ganlikun 0:13413ea9a877 392
ganlikun 0:13413ea9a877 393 /** @defgroup FSMC_Page_Size FSMC Page Size
ganlikun 0:13413ea9a877 394 * @{
ganlikun 0:13413ea9a877 395 */
ganlikun 0:13413ea9a877 396 #define FSMC_PAGE_SIZE_NONE 0x00000000U
ganlikun 0:13413ea9a877 397 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
ganlikun 0:13413ea9a877 398 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
ganlikun 0:13413ea9a877 399 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
ganlikun 0:13413ea9a877 400 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
ganlikun 0:13413ea9a877 401 /**
ganlikun 0:13413ea9a877 402 * @}
ganlikun 0:13413ea9a877 403 */
ganlikun 0:13413ea9a877 404
ganlikun 0:13413ea9a877 405 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO
ganlikun 0:13413ea9a877 406 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
ganlikun 0:13413ea9a877 407 * @{
ganlikun 0:13413ea9a877 408 */
ganlikun 0:13413ea9a877 409 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
ganlikun 0:13413ea9a877 410 #define FSMC_WRITE_FIFO_ENABLE 0x00000000U
ganlikun 0:13413ea9a877 411 /**
ganlikun 0:13413ea9a877 412 * @}
ganlikun 0:13413ea9a877 413 */
ganlikun 0:13413ea9a877 414
ganlikun 0:13413ea9a877 415 /** @defgroup FSMC_Write_Burst FSMC Write Burst
ganlikun 0:13413ea9a877 416 * @{
ganlikun 0:13413ea9a877 417 */
ganlikun 0:13413ea9a877 418 #define FSMC_WRITE_BURST_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 419 #define FSMC_WRITE_BURST_ENABLE 0x00080000U
ganlikun 0:13413ea9a877 420 /**
ganlikun 0:13413ea9a877 421 * @}
ganlikun 0:13413ea9a877 422 */
ganlikun 0:13413ea9a877 423
ganlikun 0:13413ea9a877 424 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
ganlikun 0:13413ea9a877 425 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
ganlikun 0:13413ea9a877 426 * @{
ganlikun 0:13413ea9a877 427 */
ganlikun 0:13413ea9a877 428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
ganlikun 0:13413ea9a877 429 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
ganlikun 0:13413ea9a877 430 /**
ganlikun 0:13413ea9a877 431 * @}
ganlikun 0:13413ea9a877 432 */
ganlikun 0:13413ea9a877 433
ganlikun 0:13413ea9a877 434 /** @defgroup FSMC_Access_Mode FSMC Access Mode
ganlikun 0:13413ea9a877 435 * @{
ganlikun 0:13413ea9a877 436 */
ganlikun 0:13413ea9a877 437 #define FSMC_ACCESS_MODE_A 0x00000000U
ganlikun 0:13413ea9a877 438 #define FSMC_ACCESS_MODE_B 0x10000000U
ganlikun 0:13413ea9a877 439 #define FSMC_ACCESS_MODE_C 0x20000000U
ganlikun 0:13413ea9a877 440 #define FSMC_ACCESS_MODE_D 0x30000000U
ganlikun 0:13413ea9a877 441 /**
ganlikun 0:13413ea9a877 442 * @}
ganlikun 0:13413ea9a877 443 */
ganlikun 0:13413ea9a877 444 /**
ganlikun 0:13413ea9a877 445 * @}
ganlikun 0:13413ea9a877 446 */
ganlikun 0:13413ea9a877 447
ganlikun 0:13413ea9a877 448 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 449 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
ganlikun 0:13413ea9a877 450 * @{
ganlikun 0:13413ea9a877 451 */
ganlikun 0:13413ea9a877 452 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
ganlikun 0:13413ea9a877 453 * @{
ganlikun 0:13413ea9a877 454 */
ganlikun 0:13413ea9a877 455 #define FSMC_NAND_BANK2 0x00000010U
ganlikun 0:13413ea9a877 456 #define FSMC_NAND_BANK3 0x00000100U
ganlikun 0:13413ea9a877 457 /**
ganlikun 0:13413ea9a877 458 * @}
ganlikun 0:13413ea9a877 459 */
ganlikun 0:13413ea9a877 460
ganlikun 0:13413ea9a877 461 /** @defgroup FSMC_Wait_feature FSMC Wait feature
ganlikun 0:13413ea9a877 462 * @{
ganlikun 0:13413ea9a877 463 */
ganlikun 0:13413ea9a877 464 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 465 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
ganlikun 0:13413ea9a877 466 /**
ganlikun 0:13413ea9a877 467 * @}
ganlikun 0:13413ea9a877 468 */
ganlikun 0:13413ea9a877 469
ganlikun 0:13413ea9a877 470 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
ganlikun 0:13413ea9a877 471 * @{
ganlikun 0:13413ea9a877 472 */
ganlikun 0:13413ea9a877 473 #define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
ganlikun 0:13413ea9a877 474 #define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
ganlikun 0:13413ea9a877 475 /**
ganlikun 0:13413ea9a877 476 * @}
ganlikun 0:13413ea9a877 477 */
ganlikun 0:13413ea9a877 478
ganlikun 0:13413ea9a877 479 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
ganlikun 0:13413ea9a877 480 * @{
ganlikun 0:13413ea9a877 481 */
ganlikun 0:13413ea9a877 482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
ganlikun 0:13413ea9a877 483 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
ganlikun 0:13413ea9a877 484 /**
ganlikun 0:13413ea9a877 485 * @}
ganlikun 0:13413ea9a877 486 */
ganlikun 0:13413ea9a877 487
ganlikun 0:13413ea9a877 488 /** @defgroup FSMC_ECC FSMC ECC
ganlikun 0:13413ea9a877 489 * @{
ganlikun 0:13413ea9a877 490 */
ganlikun 0:13413ea9a877 491 #define FSMC_NAND_ECC_DISABLE 0x00000000U
ganlikun 0:13413ea9a877 492 #define FSMC_NAND_ECC_ENABLE 0x00000040U
ganlikun 0:13413ea9a877 493 /**
ganlikun 0:13413ea9a877 494 * @}
ganlikun 0:13413ea9a877 495 */
ganlikun 0:13413ea9a877 496
ganlikun 0:13413ea9a877 497 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
ganlikun 0:13413ea9a877 498 * @{
ganlikun 0:13413ea9a877 499 */
ganlikun 0:13413ea9a877 500 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
ganlikun 0:13413ea9a877 501 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
ganlikun 0:13413ea9a877 502 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
ganlikun 0:13413ea9a877 503 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
ganlikun 0:13413ea9a877 504 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
ganlikun 0:13413ea9a877 505 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
ganlikun 0:13413ea9a877 506 /**
ganlikun 0:13413ea9a877 507 * @}
ganlikun 0:13413ea9a877 508 */
ganlikun 0:13413ea9a877 509 /**
ganlikun 0:13413ea9a877 510 * @}
ganlikun 0:13413ea9a877 511 */
ganlikun 0:13413ea9a877 512 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 513
ganlikun 0:13413ea9a877 514 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
ganlikun 0:13413ea9a877 515 * @{
ganlikun 0:13413ea9a877 516 */
ganlikun 0:13413ea9a877 517 #define FSMC_IT_RISING_EDGE 0x00000008U
ganlikun 0:13413ea9a877 518 #define FSMC_IT_LEVEL 0x00000010U
ganlikun 0:13413ea9a877 519 #define FSMC_IT_FALLING_EDGE 0x00000020U
ganlikun 0:13413ea9a877 520 #define FSMC_IT_REFRESH_ERROR 0x00004000U
ganlikun 0:13413ea9a877 521 /**
ganlikun 0:13413ea9a877 522 * @}
ganlikun 0:13413ea9a877 523 */
ganlikun 0:13413ea9a877 524
ganlikun 0:13413ea9a877 525 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
ganlikun 0:13413ea9a877 526 * @{
ganlikun 0:13413ea9a877 527 */
ganlikun 0:13413ea9a877 528 #define FSMC_FLAG_RISING_EDGE 0x00000001U
ganlikun 0:13413ea9a877 529 #define FSMC_FLAG_LEVEL 0x00000002U
ganlikun 0:13413ea9a877 530 #define FSMC_FLAG_FALLING_EDGE 0x00000004U
ganlikun 0:13413ea9a877 531 #define FSMC_FLAG_FEMPT 0x00000040U
ganlikun 0:13413ea9a877 532 /**
ganlikun 0:13413ea9a877 533 * @}
ganlikun 0:13413ea9a877 534 */
ganlikun 0:13413ea9a877 535
ganlikun 0:13413ea9a877 536 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
ganlikun 0:13413ea9a877 537 * @{
ganlikun 0:13413ea9a877 538 */
ganlikun 0:13413ea9a877 539 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
ganlikun 0:13413ea9a877 540 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
ganlikun 0:13413ea9a877 541 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 542 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
ganlikun 0:13413ea9a877 543 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
ganlikun 0:13413ea9a877 544 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 545
ganlikun 0:13413ea9a877 546 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
ganlikun 0:13413ea9a877 547 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
ganlikun 0:13413ea9a877 548 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 549 #define FSMC_NAND_DEVICE FSMC_Bank2_3
ganlikun 0:13413ea9a877 550 #define FSMC_PCCARD_DEVICE FSMC_Bank4
ganlikun 0:13413ea9a877 551 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 552
ganlikun 0:13413ea9a877 553 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
ganlikun 0:13413ea9a877 554 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
ganlikun 0:13413ea9a877 555 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
ganlikun 0:13413ea9a877 556
ganlikun 0:13413ea9a877 557 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
ganlikun 0:13413ea9a877 558 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
ganlikun 0:13413ea9a877 559 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
ganlikun 0:13413ea9a877 560 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
ganlikun 0:13413ea9a877 561
ganlikun 0:13413ea9a877 562 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
ganlikun 0:13413ea9a877 563 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
ganlikun 0:13413ea9a877 564 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
ganlikun 0:13413ea9a877 565 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
ganlikun 0:13413ea9a877 566 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
ganlikun 0:13413ea9a877 567 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
ganlikun 0:13413ea9a877 568
ganlikun 0:13413ea9a877 569 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
ganlikun 0:13413ea9a877 570 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
ganlikun 0:13413ea9a877 571
ganlikun 0:13413ea9a877 572 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 573 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
ganlikun 0:13413ea9a877 574 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
ganlikun 0:13413ea9a877 575 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
ganlikun 0:13413ea9a877 576
ganlikun 0:13413ea9a877 577 #define FMC_NAND_Init FSMC_NAND_Init
ganlikun 0:13413ea9a877 578 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
ganlikun 0:13413ea9a877 579 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
ganlikun 0:13413ea9a877 580 #define FMC_NAND_DeInit FSMC_NAND_DeInit
ganlikun 0:13413ea9a877 581 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
ganlikun 0:13413ea9a877 582 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
ganlikun 0:13413ea9a877 583 #define FMC_NAND_GetECC FSMC_NAND_GetECC
ganlikun 0:13413ea9a877 584 #define FMC_PCCARD_Init FSMC_PCCARD_Init
ganlikun 0:13413ea9a877 585 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
ganlikun 0:13413ea9a877 586 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
ganlikun 0:13413ea9a877 587 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
ganlikun 0:13413ea9a877 588 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
ganlikun 0:13413ea9a877 589
ganlikun 0:13413ea9a877 590 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
ganlikun 0:13413ea9a877 591 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
ganlikun 0:13413ea9a877 592 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
ganlikun 0:13413ea9a877 593 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
ganlikun 0:13413ea9a877 594 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
ganlikun 0:13413ea9a877 595 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
ganlikun 0:13413ea9a877 596 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
ganlikun 0:13413ea9a877 597 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
ganlikun 0:13413ea9a877 598 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
ganlikun 0:13413ea9a877 599 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
ganlikun 0:13413ea9a877 600 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
ganlikun 0:13413ea9a877 601 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
ganlikun 0:13413ea9a877 602 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 603
ganlikun 0:13413ea9a877 604 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
ganlikun 0:13413ea9a877 605 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
ganlikun 0:13413ea9a877 606 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 607 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
ganlikun 0:13413ea9a877 608 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
ganlikun 0:13413ea9a877 609 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 610
ganlikun 0:13413ea9a877 611 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
ganlikun 0:13413ea9a877 612 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
ganlikun 0:13413ea9a877 613 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 614 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
ganlikun 0:13413ea9a877 615 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
ganlikun 0:13413ea9a877 616
ganlikun 0:13413ea9a877 617 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
ganlikun 0:13413ea9a877 618 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 619
ganlikun 0:13413ea9a877 620 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
ganlikun 0:13413ea9a877 621 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
ganlikun 0:13413ea9a877 622 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
ganlikun 0:13413ea9a877 623
ganlikun 0:13413ea9a877 624 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
ganlikun 0:13413ea9a877 625 #define FMC_IT_LEVEL FSMC_IT_LEVEL
ganlikun 0:13413ea9a877 626 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
ganlikun 0:13413ea9a877 627 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
ganlikun 0:13413ea9a877 628
ganlikun 0:13413ea9a877 629 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
ganlikun 0:13413ea9a877 630 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
ganlikun 0:13413ea9a877 631 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
ganlikun 0:13413ea9a877 632 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
ganlikun 0:13413ea9a877 633 /**
ganlikun 0:13413ea9a877 634 * @}
ganlikun 0:13413ea9a877 635 */
ganlikun 0:13413ea9a877 636
ganlikun 0:13413ea9a877 637 /**
ganlikun 0:13413ea9a877 638 * @}
ganlikun 0:13413ea9a877 639 */
ganlikun 0:13413ea9a877 640
ganlikun 0:13413ea9a877 641 /* Private macro -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 642 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
ganlikun 0:13413ea9a877 643 * @{
ganlikun 0:13413ea9a877 644 */
ganlikun 0:13413ea9a877 645
ganlikun 0:13413ea9a877 646 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
ganlikun 0:13413ea9a877 647 * @brief macros to handle NOR device enable/disable and read/write operations
ganlikun 0:13413ea9a877 648 * @{
ganlikun 0:13413ea9a877 649 */
ganlikun 0:13413ea9a877 650 /**
ganlikun 0:13413ea9a877 651 * @brief Enable the NORSRAM device access.
ganlikun 0:13413ea9a877 652 * @param __INSTANCE__: FSMC_NORSRAM Instance
ganlikun 0:13413ea9a877 653 * @param __BANK__: FSMC_NORSRAM Bank
ganlikun 0:13413ea9a877 654 * @retval none
ganlikun 0:13413ea9a877 655 */
ganlikun 0:13413ea9a877 656 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
ganlikun 0:13413ea9a877 657
ganlikun 0:13413ea9a877 658 /**
ganlikun 0:13413ea9a877 659 * @brief Disable the NORSRAM device access.
ganlikun 0:13413ea9a877 660 * @param __INSTANCE__: FSMC_NORSRAM Instance
ganlikun 0:13413ea9a877 661 * @param __BANK__: FSMC_NORSRAM Bank
ganlikun 0:13413ea9a877 662 * @retval none
ganlikun 0:13413ea9a877 663 */
ganlikun 0:13413ea9a877 664 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
ganlikun 0:13413ea9a877 665 /**
ganlikun 0:13413ea9a877 666 * @}
ganlikun 0:13413ea9a877 667 */
ganlikun 0:13413ea9a877 668
ganlikun 0:13413ea9a877 669 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
ganlikun 0:13413ea9a877 670 * @brief macros to handle NAND device enable/disable
ganlikun 0:13413ea9a877 671 * @{
ganlikun 0:13413ea9a877 672 */
ganlikun 0:13413ea9a877 673 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 674 /**
ganlikun 0:13413ea9a877 675 * @brief Enable the NAND device access.
ganlikun 0:13413ea9a877 676 * @param __INSTANCE__: FSMC_NAND Instance
ganlikun 0:13413ea9a877 677 * @param __BANK__: FSMC_NAND Bank
ganlikun 0:13413ea9a877 678 * @retval none
ganlikun 0:13413ea9a877 679 */
ganlikun 0:13413ea9a877 680 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
ganlikun 0:13413ea9a877 681 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
ganlikun 0:13413ea9a877 682
ganlikun 0:13413ea9a877 683 /**
ganlikun 0:13413ea9a877 684 * @brief Disable the NAND device access.
ganlikun 0:13413ea9a877 685 * @param __INSTANCE__: FSMC_NAND Instance
ganlikun 0:13413ea9a877 686 * @param __BANK__: FSMC_NAND Bank
ganlikun 0:13413ea9a877 687 * @retval none
ganlikun 0:13413ea9a877 688 */
ganlikun 0:13413ea9a877 689 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
ganlikun 0:13413ea9a877 690 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
ganlikun 0:13413ea9a877 691 /**
ganlikun 0:13413ea9a877 692 * @}
ganlikun 0:13413ea9a877 693 */
ganlikun 0:13413ea9a877 694
ganlikun 0:13413ea9a877 695 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
ganlikun 0:13413ea9a877 696 * @brief macros to handle SRAM read/write operations
ganlikun 0:13413ea9a877 697 * @{
ganlikun 0:13413ea9a877 698 */
ganlikun 0:13413ea9a877 699 /**
ganlikun 0:13413ea9a877 700 * @brief Enable the PCCARD device access.
ganlikun 0:13413ea9a877 701 * @param __INSTANCE__: FSMC_PCCARD Instance
ganlikun 0:13413ea9a877 702 * @retval none
ganlikun 0:13413ea9a877 703 */
ganlikun 0:13413ea9a877 704 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
ganlikun 0:13413ea9a877 705
ganlikun 0:13413ea9a877 706 /**
ganlikun 0:13413ea9a877 707 * @brief Disable the PCCARD device access.
ganlikun 0:13413ea9a877 708 * @param __INSTANCE__: FSMC_PCCARD Instance
ganlikun 0:13413ea9a877 709 * @retval none
ganlikun 0:13413ea9a877 710 */
ganlikun 0:13413ea9a877 711 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
ganlikun 0:13413ea9a877 712 /**
ganlikun 0:13413ea9a877 713 * @}
ganlikun 0:13413ea9a877 714 */
ganlikun 0:13413ea9a877 715
ganlikun 0:13413ea9a877 716 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
ganlikun 0:13413ea9a877 717 * @brief macros to handle FSMC flags and interrupts
ganlikun 0:13413ea9a877 718 * @{
ganlikun 0:13413ea9a877 719 */
ganlikun 0:13413ea9a877 720 /**
ganlikun 0:13413ea9a877 721 * @brief Enable the NAND device interrupt.
ganlikun 0:13413ea9a877 722 * @param __INSTANCE__: FSMC_NAND Instance
ganlikun 0:13413ea9a877 723 * @param __BANK__: FSMC_NAND Bank
ganlikun 0:13413ea9a877 724 * @param __INTERRUPT__: FSMC_NAND interrupt
ganlikun 0:13413ea9a877 725 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 726 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun 0:13413ea9a877 727 * @arg FSMC_IT_LEVEL: Interrupt level.
ganlikun 0:13413ea9a877 728 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun 0:13413ea9a877 729 * @retval None
ganlikun 0:13413ea9a877 730 */
ganlikun 0:13413ea9a877 731 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
ganlikun 0:13413ea9a877 732 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
ganlikun 0:13413ea9a877 733
ganlikun 0:13413ea9a877 734 /**
ganlikun 0:13413ea9a877 735 * @brief Disable the NAND device interrupt.
ganlikun 0:13413ea9a877 736 * @param __INSTANCE__: FSMC_NAND Instance
ganlikun 0:13413ea9a877 737 * @param __BANK__: FSMC_NAND Bank
ganlikun 0:13413ea9a877 738 * @param __INTERRUPT__: FSMC_NAND interrupt
ganlikun 0:13413ea9a877 739 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 740 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun 0:13413ea9a877 741 * @arg FSMC_IT_LEVEL: Interrupt level.
ganlikun 0:13413ea9a877 742 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun 0:13413ea9a877 743 * @retval None
ganlikun 0:13413ea9a877 744 */
ganlikun 0:13413ea9a877 745 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
ganlikun 0:13413ea9a877 746 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
ganlikun 0:13413ea9a877 747
ganlikun 0:13413ea9a877 748 /**
ganlikun 0:13413ea9a877 749 * @brief Get flag status of the NAND device.
ganlikun 0:13413ea9a877 750 * @param __INSTANCE__: FSMC_NAND Instance
ganlikun 0:13413ea9a877 751 * @param __BANK__ : FSMC_NAND Bank
ganlikun 0:13413ea9a877 752 * @param __FLAG__ : FSMC_NAND flag
ganlikun 0:13413ea9a877 753 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 754 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun 0:13413ea9a877 755 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun 0:13413ea9a877 756 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun 0:13413ea9a877 757 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
ganlikun 0:13413ea9a877 758 * @retval The state of FLAG (SET or RESET).
ganlikun 0:13413ea9a877 759 */
ganlikun 0:13413ea9a877 760 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
ganlikun 0:13413ea9a877 761 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
ganlikun 0:13413ea9a877 762
ganlikun 0:13413ea9a877 763 /**
ganlikun 0:13413ea9a877 764 * @brief Clear flag status of the NAND device.
ganlikun 0:13413ea9a877 765 * @param __INSTANCE__: FSMC_NAND Instance
ganlikun 0:13413ea9a877 766 * @param __BANK__: FSMC_NAND Bank
ganlikun 0:13413ea9a877 767 * @param __FLAG__: FSMC_NAND flag
ganlikun 0:13413ea9a877 768 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 769 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun 0:13413ea9a877 770 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun 0:13413ea9a877 771 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun 0:13413ea9a877 772 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
ganlikun 0:13413ea9a877 773 * @retval None
ganlikun 0:13413ea9a877 774 */
ganlikun 0:13413ea9a877 775 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
ganlikun 0:13413ea9a877 776 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
ganlikun 0:13413ea9a877 777
ganlikun 0:13413ea9a877 778 /**
ganlikun 0:13413ea9a877 779 * @brief Enable the PCCARD device interrupt.
ganlikun 0:13413ea9a877 780 * @param __INSTANCE__: FSMC_PCCARD Instance
ganlikun 0:13413ea9a877 781 * @param __INTERRUPT__: FSMC_PCCARD interrupt
ganlikun 0:13413ea9a877 782 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 783 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun 0:13413ea9a877 784 * @arg FSMC_IT_LEVEL: Interrupt level.
ganlikun 0:13413ea9a877 785 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun 0:13413ea9a877 786 * @retval None
ganlikun 0:13413ea9a877 787 */
ganlikun 0:13413ea9a877 788 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
ganlikun 0:13413ea9a877 789
ganlikun 0:13413ea9a877 790 /**
ganlikun 0:13413ea9a877 791 * @brief Disable the PCCARD device interrupt.
ganlikun 0:13413ea9a877 792 * @param __INSTANCE__: FSMC_PCCARD Instance
ganlikun 0:13413ea9a877 793 * @param __INTERRUPT__: FSMC_PCCARD interrupt
ganlikun 0:13413ea9a877 794 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 795 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun 0:13413ea9a877 796 * @arg FSMC_IT_LEVEL: Interrupt level.
ganlikun 0:13413ea9a877 797 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun 0:13413ea9a877 798 * @retval None
ganlikun 0:13413ea9a877 799 */
ganlikun 0:13413ea9a877 800 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
ganlikun 0:13413ea9a877 801
ganlikun 0:13413ea9a877 802 /**
ganlikun 0:13413ea9a877 803 * @brief Get flag status of the PCCARD device.
ganlikun 0:13413ea9a877 804 * @param __INSTANCE__: FSMC_PCCARD Instance
ganlikun 0:13413ea9a877 805 * @param __FLAG__: FSMC_PCCARD flag
ganlikun 0:13413ea9a877 806 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 807 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun 0:13413ea9a877 808 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun 0:13413ea9a877 809 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun 0:13413ea9a877 810 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
ganlikun 0:13413ea9a877 811 * @retval The state of FLAG (SET or RESET).
ganlikun 0:13413ea9a877 812 */
ganlikun 0:13413ea9a877 813 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
ganlikun 0:13413ea9a877 814
ganlikun 0:13413ea9a877 815 /**
ganlikun 0:13413ea9a877 816 * @brief Clear flag status of the PCCARD device.
ganlikun 0:13413ea9a877 817 * @param __INSTANCE__: FSMC_PCCARD Instance
ganlikun 0:13413ea9a877 818 * @param __FLAG__: FSMC_PCCARD flag
ganlikun 0:13413ea9a877 819 * This parameter can be any combination of the following values:
ganlikun 0:13413ea9a877 820 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun 0:13413ea9a877 821 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun 0:13413ea9a877 822 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun 0:13413ea9a877 823 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
ganlikun 0:13413ea9a877 824 * @retval None
ganlikun 0:13413ea9a877 825 */
ganlikun 0:13413ea9a877 826 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
ganlikun 0:13413ea9a877 827 /**
ganlikun 0:13413ea9a877 828 * @}
ganlikun 0:13413ea9a877 829 */
ganlikun 0:13413ea9a877 830 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 831
ganlikun 0:13413ea9a877 832 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
ganlikun 0:13413ea9a877 833 * @{
ganlikun 0:13413ea9a877 834 */
ganlikun 0:13413ea9a877 835 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
ganlikun 0:13413ea9a877 836 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
ganlikun 0:13413ea9a877 837 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
ganlikun 0:13413ea9a877 838 ((__BANK__) == FSMC_NORSRAM_BANK4))
ganlikun 0:13413ea9a877 839
ganlikun 0:13413ea9a877 840 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
ganlikun 0:13413ea9a877 841 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
ganlikun 0:13413ea9a877 842
ganlikun 0:13413ea9a877 843 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
ganlikun 0:13413ea9a877 844 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
ganlikun 0:13413ea9a877 845 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
ganlikun 0:13413ea9a877 846
ganlikun 0:13413ea9a877 847 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
ganlikun 0:13413ea9a877 848 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
ganlikun 0:13413ea9a877 849 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
ganlikun 0:13413ea9a877 850
ganlikun 0:13413ea9a877 851 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
ganlikun 0:13413ea9a877 852 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
ganlikun 0:13413ea9a877 853 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
ganlikun 0:13413ea9a877 854 ((__MODE__) == FSMC_ACCESS_MODE_D))
ganlikun 0:13413ea9a877 855
ganlikun 0:13413ea9a877 856 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
ganlikun 0:13413ea9a877 857 ((BANK) == FSMC_NAND_BANK3))
ganlikun 0:13413ea9a877 858
ganlikun 0:13413ea9a877 859 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
ganlikun 0:13413ea9a877 860 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
ganlikun 0:13413ea9a877 861
ganlikun 0:13413ea9a877 862 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
ganlikun 0:13413ea9a877 863 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
ganlikun 0:13413ea9a877 864
ganlikun 0:13413ea9a877 865 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
ganlikun 0:13413ea9a877 866 ((STATE) == FSMC_NAND_ECC_ENABLE))
ganlikun 0:13413ea9a877 867
ganlikun 0:13413ea9a877 868 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
ganlikun 0:13413ea9a877 869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
ganlikun 0:13413ea9a877 870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
ganlikun 0:13413ea9a877 871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
ganlikun 0:13413ea9a877 872 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
ganlikun 0:13413ea9a877 873 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
ganlikun 0:13413ea9a877 874
ganlikun 0:13413ea9a877 875 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
ganlikun 0:13413ea9a877 876
ganlikun 0:13413ea9a877 877 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
ganlikun 0:13413ea9a877 878
ganlikun 0:13413ea9a877 879 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
ganlikun 0:13413ea9a877 880
ganlikun 0:13413ea9a877 881 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
ganlikun 0:13413ea9a877 882
ganlikun 0:13413ea9a877 883 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
ganlikun 0:13413ea9a877 884
ganlikun 0:13413ea9a877 885 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
ganlikun 0:13413ea9a877 886
ganlikun 0:13413ea9a877 887 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
ganlikun 0:13413ea9a877 888
ganlikun 0:13413ea9a877 889 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
ganlikun 0:13413ea9a877 890
ganlikun 0:13413ea9a877 891 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
ganlikun 0:13413ea9a877 892
ganlikun 0:13413ea9a877 893 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
ganlikun 0:13413ea9a877 894
ganlikun 0:13413ea9a877 895 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
ganlikun 0:13413ea9a877 896 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
ganlikun 0:13413ea9a877 897
ganlikun 0:13413ea9a877 898 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
ganlikun 0:13413ea9a877 899 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
ganlikun 0:13413ea9a877 900
ganlikun 0:13413ea9a877 901 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
ganlikun 0:13413ea9a877 902 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
ganlikun 0:13413ea9a877 903
ganlikun 0:13413ea9a877 904 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
ganlikun 0:13413ea9a877 905 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
ganlikun 0:13413ea9a877 906
ganlikun 0:13413ea9a877 907 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
ganlikun 0:13413ea9a877 908 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
ganlikun 0:13413ea9a877 909
ganlikun 0:13413ea9a877 910 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
ganlikun 0:13413ea9a877 911 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
ganlikun 0:13413ea9a877 912
ganlikun 0:13413ea9a877 913 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
ganlikun 0:13413ea9a877 914 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
ganlikun 0:13413ea9a877 915
ganlikun 0:13413ea9a877 916 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
ganlikun 0:13413ea9a877 917 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
ganlikun 0:13413ea9a877 918
ganlikun 0:13413ea9a877 919 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
ganlikun 0:13413ea9a877 920
ganlikun 0:13413ea9a877 921 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
ganlikun 0:13413ea9a877 922 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
ganlikun 0:13413ea9a877 923
ganlikun 0:13413ea9a877 924 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
ganlikun 0:13413ea9a877 925
ganlikun 0:13413ea9a877 926 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
ganlikun 0:13413ea9a877 927
ganlikun 0:13413ea9a877 928 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
ganlikun 0:13413ea9a877 929
ganlikun 0:13413ea9a877 930 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
ganlikun 0:13413ea9a877 931
ganlikun 0:13413ea9a877 932 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
ganlikun 0:13413ea9a877 933 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
ganlikun 0:13413ea9a877 934
ganlikun 0:13413ea9a877 935 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
ganlikun 0:13413ea9a877 936
ganlikun 0:13413ea9a877 937 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
ganlikun 0:13413ea9a877 938 ((SIZE) == FSMC_PAGE_SIZE_128) || \
ganlikun 0:13413ea9a877 939 ((SIZE) == FSMC_PAGE_SIZE_256) || \
ganlikun 0:13413ea9a877 940 ((SIZE) == FSMC_PAGE_SIZE_512) || \
ganlikun 0:13413ea9a877 941 ((SIZE) == FSMC_PAGE_SIZE_1024))
ganlikun 0:13413ea9a877 942
ganlikun 0:13413ea9a877 943 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
ganlikun 0:13413ea9a877 944 ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
ganlikun 0:13413ea9a877 945
ganlikun 0:13413ea9a877 946 /**
ganlikun 0:13413ea9a877 947 * @}
ganlikun 0:13413ea9a877 948 */
ganlikun 0:13413ea9a877 949 /**
ganlikun 0:13413ea9a877 950 * @}
ganlikun 0:13413ea9a877 951 */
ganlikun 0:13413ea9a877 952
ganlikun 0:13413ea9a877 953 /* Private functions ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 954 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
ganlikun 0:13413ea9a877 955 * @{
ganlikun 0:13413ea9a877 956 */
ganlikun 0:13413ea9a877 957
ganlikun 0:13413ea9a877 958 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
ganlikun 0:13413ea9a877 959 * @{
ganlikun 0:13413ea9a877 960 */
ganlikun 0:13413ea9a877 961
ganlikun 0:13413ea9a877 962 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
ganlikun 0:13413ea9a877 963 * @{
ganlikun 0:13413ea9a877 964 */
ganlikun 0:13413ea9a877 965 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
ganlikun 0:13413ea9a877 966 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
ganlikun 0:13413ea9a877 967 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
ganlikun 0:13413ea9a877 968 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
ganlikun 0:13413ea9a877 969 /**
ganlikun 0:13413ea9a877 970 * @}
ganlikun 0:13413ea9a877 971 */
ganlikun 0:13413ea9a877 972
ganlikun 0:13413ea9a877 973 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
ganlikun 0:13413ea9a877 974 * @{
ganlikun 0:13413ea9a877 975 */
ganlikun 0:13413ea9a877 976 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
ganlikun 0:13413ea9a877 977 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
ganlikun 0:13413ea9a877 978 /**
ganlikun 0:13413ea9a877 979 * @}
ganlikun 0:13413ea9a877 980 */
ganlikun 0:13413ea9a877 981 /**
ganlikun 0:13413ea9a877 982 * @}
ganlikun 0:13413ea9a877 983 */
ganlikun 0:13413ea9a877 984
ganlikun 0:13413ea9a877 985 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 986 /** @defgroup FSMC_LL_NAND NAND
ganlikun 0:13413ea9a877 987 * @{
ganlikun 0:13413ea9a877 988 */
ganlikun 0:13413ea9a877 989 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
ganlikun 0:13413ea9a877 990 * @{
ganlikun 0:13413ea9a877 991 */
ganlikun 0:13413ea9a877 992 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
ganlikun 0:13413ea9a877 993 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
ganlikun 0:13413ea9a877 994 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
ganlikun 0:13413ea9a877 995 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
ganlikun 0:13413ea9a877 996 /**
ganlikun 0:13413ea9a877 997 * @}
ganlikun 0:13413ea9a877 998 */
ganlikun 0:13413ea9a877 999
ganlikun 0:13413ea9a877 1000 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
ganlikun 0:13413ea9a877 1001 * @{
ganlikun 0:13413ea9a877 1002 */
ganlikun 0:13413ea9a877 1003 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
ganlikun 0:13413ea9a877 1004 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
ganlikun 0:13413ea9a877 1005 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
ganlikun 0:13413ea9a877 1006 /**
ganlikun 0:13413ea9a877 1007 * @}
ganlikun 0:13413ea9a877 1008 */
ganlikun 0:13413ea9a877 1009 /**
ganlikun 0:13413ea9a877 1010 * @}
ganlikun 0:13413ea9a877 1011 */
ganlikun 0:13413ea9a877 1012
ganlikun 0:13413ea9a877 1013 /** @defgroup FSMC_LL_PCCARD PCCARD
ganlikun 0:13413ea9a877 1014 * @{
ganlikun 0:13413ea9a877 1015 */
ganlikun 0:13413ea9a877 1016 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
ganlikun 0:13413ea9a877 1017 * @{
ganlikun 0:13413ea9a877 1018 */
ganlikun 0:13413ea9a877 1019 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
ganlikun 0:13413ea9a877 1020 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
ganlikun 0:13413ea9a877 1021 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
ganlikun 0:13413ea9a877 1022 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
ganlikun 0:13413ea9a877 1023 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
ganlikun 0:13413ea9a877 1024 /**
ganlikun 0:13413ea9a877 1025 * @}
ganlikun 0:13413ea9a877 1026 */
ganlikun 0:13413ea9a877 1027 /**
ganlikun 0:13413ea9a877 1028 * @}
ganlikun 0:13413ea9a877 1029 */
ganlikun 0:13413ea9a877 1030 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
ganlikun 0:13413ea9a877 1031
ganlikun 0:13413ea9a877 1032 /**
ganlikun 0:13413ea9a877 1033 * @}
ganlikun 0:13413ea9a877 1034 */
ganlikun 0:13413ea9a877 1035 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
ganlikun 0:13413ea9a877 1036
ganlikun 0:13413ea9a877 1037 /**
ganlikun 0:13413ea9a877 1038 * @}
ganlikun 0:13413ea9a877 1039 */
ganlikun 0:13413ea9a877 1040
ganlikun 0:13413ea9a877 1041 /**
ganlikun 0:13413ea9a877 1042 * @}
ganlikun 0:13413ea9a877 1043 */
ganlikun 0:13413ea9a877 1044
ganlikun 0:13413ea9a877 1045 #ifdef __cplusplus
ganlikun 0:13413ea9a877 1046 }
ganlikun 0:13413ea9a877 1047 #endif
ganlikun 0:13413ea9a877 1048
ganlikun 0:13413ea9a877 1049 #endif /* __STM32F4xx_LL_FSMC_H */
ganlikun 0:13413ea9a877 1050
ganlikun 0:13413ea9a877 1051 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 1052