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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_fmc.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of FMC HAL module.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37
ganlikun	0:13413ea9a877	38	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	39	#ifndef __STM32F4xx_LL_FMC_H
ganlikun	0:13413ea9a877	40	#define __STM32F4xx_LL_FMC_H
ganlikun	0:13413ea9a877	41
ganlikun	0:13413ea9a877	42	#ifdef __cplusplus
ganlikun	0:13413ea9a877	43	extern "C" {
ganlikun	0:13413ea9a877	44	#endif
ganlikun	0:13413ea9a877	45
ganlikun	0:13413ea9a877	46	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	47	#include "stm32f4xx_hal_def.h"
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	/** @addtogroup STM32F4xx_HAL_Driver
ganlikun	0:13413ea9a877	50	* @{
ganlikun	0:13413ea9a877	51	*/
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	/** @addtogroup FMC_LL
ganlikun	0:13413ea9a877	54	* @{
ganlikun	0:13413ea9a877	55	*/
ganlikun	0:13413ea9a877	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	58	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
ganlikun	0:13413ea9a877	60	* @{
ganlikun	0:13413ea9a877	61	*/
ganlikun	0:13413ea9a877	62
ganlikun	0:13413ea9a877	63	/**
ganlikun	0:13413ea9a877	64	* @brief FMC NORSRAM Configuration Structure definition
ganlikun	0:13413ea9a877	65	*/
ganlikun	0:13413ea9a877	66	typedef struct
ganlikun	0:13413ea9a877	67	{
ganlikun	0:13413ea9a877	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
ganlikun	0:13413ea9a877	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
ganlikun	0:13413ea9a877	70
ganlikun	0:13413ea9a877	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
ganlikun	0:13413ea9a877	72	multiplexed on the data bus or not.
ganlikun	0:13413ea9a877	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
ganlikun	0:13413ea9a877	74
ganlikun	0:13413ea9a877	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
ganlikun	0:13413ea9a877	76	the corresponding memory device.
ganlikun	0:13413ea9a877	77	This parameter can be a value of @ref FMC_Memory_Type */
ganlikun	0:13413ea9a877	78
ganlikun	0:13413ea9a877	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
ganlikun	0:13413ea9a877	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
ganlikun	0:13413ea9a877	81
ganlikun	0:13413ea9a877	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
ganlikun	0:13413ea9a877	83	valid only with synchronous burst Flash memories.
ganlikun	0:13413ea9a877	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
ganlikun	0:13413ea9a877	85
ganlikun	0:13413ea9a877	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
ganlikun	0:13413ea9a877	87	the Flash memory in burst mode.
ganlikun	0:13413ea9a877	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
ganlikun	0:13413ea9a877	89
ganlikun	0:13413ea9a877	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
ganlikun	0:13413ea9a877	91	memory, valid only when accessing Flash memories in burst mode.
ganlikun	0:13413ea9a877	92	This parameter can be a value of @ref FMC_Wrap_Mode
ganlikun	0:13413ea9a877	93	This mode is not available for the STM32F446/467/479xx devices */
ganlikun	0:13413ea9a877	94
ganlikun	0:13413ea9a877	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
ganlikun	0:13413ea9a877	96	clock cycle before the wait state or during the wait state,
ganlikun	0:13413ea9a877	97	valid only when accessing memories in burst mode.
ganlikun	0:13413ea9a877	98	This parameter can be a value of @ref FMC_Wait_Timing */
ganlikun	0:13413ea9a877	99
ganlikun	0:13413ea9a877	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
ganlikun	0:13413ea9a877	101	This parameter can be a value of @ref FMC_Write_Operation */
ganlikun	0:13413ea9a877	102
ganlikun	0:13413ea9a877	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
ganlikun	0:13413ea9a877	104	signal, valid for Flash memory access in burst mode.
ganlikun	0:13413ea9a877	105	This parameter can be a value of @ref FMC_Wait_Signal */
ganlikun	0:13413ea9a877	106
ganlikun	0:13413ea9a877	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
ganlikun	0:13413ea9a877	108	This parameter can be a value of @ref FMC_Extended_Mode */
ganlikun	0:13413ea9a877	109
ganlikun	0:13413ea9a877	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
ganlikun	0:13413ea9a877	111	valid only with asynchronous Flash memories.
ganlikun	0:13413ea9a877	112	This parameter can be a value of @ref FMC_AsynchronousWait */
ganlikun	0:13413ea9a877	113
ganlikun	0:13413ea9a877	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
ganlikun	0:13413ea9a877	115	This parameter can be a value of @ref FMC_Write_Burst */
ganlikun	0:13413ea9a877	116
ganlikun	0:13413ea9a877	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
ganlikun	0:13413ea9a877	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
ganlikun	0:13413ea9a877	119	through FMC_BCR2..4 registers.
ganlikun	0:13413ea9a877	120	This parameter can be a value of @ref FMC_Continous_Clock */
ganlikun	0:13413ea9a877	121
ganlikun	0:13413ea9a877	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
ganlikun	0:13413ea9a877	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
ganlikun	0:13413ea9a877	124	through FMC_BCR2..4 registers.
ganlikun	0:13413ea9a877	125	This parameter can be a value of @ref FMC_Write_FIFO
ganlikun	0:13413ea9a877	126	This mode is available only for the STM32F446/469/479xx devices */
ganlikun	0:13413ea9a877	127
ganlikun	0:13413ea9a877	128	uint32_t PageSize; /*!< Specifies the memory page size.
ganlikun	0:13413ea9a877	129	This parameter can be a value of @ref FMC_Page_Size */
ganlikun	0:13413ea9a877	130	}FMC_NORSRAM_InitTypeDef;
ganlikun	0:13413ea9a877	131
ganlikun	0:13413ea9a877	132	/**
ganlikun	0:13413ea9a877	133	* @brief FMC NORSRAM Timing parameters structure definition
ganlikun	0:13413ea9a877	134	*/
ganlikun	0:13413ea9a877	135	typedef struct
ganlikun	0:13413ea9a877	136	{
ganlikun	0:13413ea9a877	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
ganlikun	0:13413ea9a877	138	the duration of the address setup time.
ganlikun	0:13413ea9a877	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
ganlikun	0:13413ea9a877	140	@note This parameter is not used with synchronous NOR Flash memories. */
ganlikun	0:13413ea9a877	141
ganlikun	0:13413ea9a877	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
ganlikun	0:13413ea9a877	143	the duration of the address hold time.
ganlikun	0:13413ea9a877	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
ganlikun	0:13413ea9a877	145	@note This parameter is not used with synchronous NOR Flash memories. */
ganlikun	0:13413ea9a877	146
ganlikun	0:13413ea9a877	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
ganlikun	0:13413ea9a877	148	the duration of the data setup time.
ganlikun	0:13413ea9a877	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
ganlikun	0:13413ea9a877	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
ganlikun	0:13413ea9a877	151	NOR Flash memories. */
ganlikun	0:13413ea9a877	152
ganlikun	0:13413ea9a877	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
ganlikun	0:13413ea9a877	154	the duration of the bus turnaround.
ganlikun	0:13413ea9a877	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
ganlikun	0:13413ea9a877	156	@note This parameter is only used for multiplexed NOR Flash memories. */
ganlikun	0:13413ea9a877	157
ganlikun	0:13413ea9a877	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
ganlikun	0:13413ea9a877	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
ganlikun	0:13413ea9a877	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
ganlikun	0:13413ea9a877	161	accesses. */
ganlikun	0:13413ea9a877	162
ganlikun	0:13413ea9a877	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
ganlikun	0:13413ea9a877	164	to the memory before getting the first data.
ganlikun	0:13413ea9a877	165	The parameter value depends on the memory type as shown below:
ganlikun	0:13413ea9a877	166	- It must be set to 0 in case of a CRAM
ganlikun	0:13413ea9a877	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
ganlikun	0:13413ea9a877	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
ganlikun	0:13413ea9a877	169	with synchronous burst mode enable */
ganlikun	0:13413ea9a877	170
ganlikun	0:13413ea9a877	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
ganlikun	0:13413ea9a877	172	This parameter can be a value of @ref FMC_Access_Mode */
ganlikun	0:13413ea9a877	173	}FMC_NORSRAM_TimingTypeDef;
ganlikun	0:13413ea9a877	174
ganlikun	0:13413ea9a877	175	/**
ganlikun	0:13413ea9a877	176	* @brief FMC NAND Configuration Structure definition
ganlikun	0:13413ea9a877	177	*/
ganlikun	0:13413ea9a877	178	typedef struct
ganlikun	0:13413ea9a877	179	{
ganlikun	0:13413ea9a877	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
ganlikun	0:13413ea9a877	181	This parameter can be a value of @ref FMC_NAND_Bank */
ganlikun	0:13413ea9a877	182
ganlikun	0:13413ea9a877	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
ganlikun	0:13413ea9a877	184	This parameter can be any value of @ref FMC_Wait_feature */
ganlikun	0:13413ea9a877	185
ganlikun	0:13413ea9a877	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
ganlikun	0:13413ea9a877	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
ganlikun	0:13413ea9a877	188
ganlikun	0:13413ea9a877	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
ganlikun	0:13413ea9a877	190	This parameter can be any value of @ref FMC_ECC */
ganlikun	0:13413ea9a877	191
ganlikun	0:13413ea9a877	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
ganlikun	0:13413ea9a877	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
ganlikun	0:13413ea9a877	194
ganlikun	0:13413ea9a877	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun	0:13413ea9a877	196	delay between CLE low and RE low.
ganlikun	0:13413ea9a877	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	198
ganlikun	0:13413ea9a877	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun	0:13413ea9a877	200	delay between ALE low and RE low.
ganlikun	0:13413ea9a877	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	202	}FMC_NAND_InitTypeDef;
ganlikun	0:13413ea9a877	203
ganlikun	0:13413ea9a877	204	/**
ganlikun	0:13413ea9a877	205	* @brief FMC NAND/PCCARD Timing parameters structure definition
ganlikun	0:13413ea9a877	206	*/
ganlikun	0:13413ea9a877	207	typedef struct
ganlikun	0:13413ea9a877	208	{
ganlikun	0:13413ea9a877	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
ganlikun	0:13413ea9a877	210	the command assertion for NAND-Flash read or write access
ganlikun	0:13413ea9a877	211	to common/Attribute or I/O memory space (depending on
ganlikun	0:13413ea9a877	212	the memory space timing to be configured).
ganlikun	0:13413ea9a877	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	214
ganlikun	0:13413ea9a877	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
ganlikun	0:13413ea9a877	216	command for NAND-Flash read or write access to
ganlikun	0:13413ea9a877	217	common/Attribute or I/O memory space (depending on the
ganlikun	0:13413ea9a877	218	memory space timing to be configured).
ganlikun	0:13413ea9a877	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	220
ganlikun	0:13413ea9a877	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
ganlikun	0:13413ea9a877	222	(and data for write access) after the command de-assertion
ganlikun	0:13413ea9a877	223	for NAND-Flash read or write access to common/Attribute
ganlikun	0:13413ea9a877	224	or I/O memory space (depending on the memory space timing
ganlikun	0:13413ea9a877	225	to be configured).
ganlikun	0:13413ea9a877	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	227
ganlikun	0:13413ea9a877	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
ganlikun	0:13413ea9a877	229	data bus is kept in HiZ after the start of a NAND-Flash
ganlikun	0:13413ea9a877	230	write access to common/Attribute or I/O memory space (depending
ganlikun	0:13413ea9a877	231	on the memory space timing to be configured).
ganlikun	0:13413ea9a877	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	233	}FMC_NAND_PCC_TimingTypeDef;
ganlikun	0:13413ea9a877	234
ganlikun	0:13413ea9a877	235	/**
ganlikun	0:13413ea9a877	236	* @brief FMC NAND Configuration Structure definition
ganlikun	0:13413ea9a877	237	*/
ganlikun	0:13413ea9a877	238	typedef struct
ganlikun	0:13413ea9a877	239	{
ganlikun	0:13413ea9a877	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
ganlikun	0:13413ea9a877	241	This parameter can be any value of @ref FMC_Wait_feature */
ganlikun	0:13413ea9a877	242
ganlikun	0:13413ea9a877	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun	0:13413ea9a877	244	delay between CLE low and RE low.
ganlikun	0:13413ea9a877	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	246
ganlikun	0:13413ea9a877	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
ganlikun	0:13413ea9a877	248	delay between ALE low and RE low.
ganlikun	0:13413ea9a877	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	250	}FMC_PCCARD_InitTypeDef;
ganlikun	0:13413ea9a877	251
ganlikun	0:13413ea9a877	252	/**
ganlikun	0:13413ea9a877	253	* @brief FMC SDRAM Configuration Structure definition
ganlikun	0:13413ea9a877	254	*/
ganlikun	0:13413ea9a877	255	typedef struct
ganlikun	0:13413ea9a877	256	{
ganlikun	0:13413ea9a877	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
ganlikun	0:13413ea9a877	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
ganlikun	0:13413ea9a877	259
ganlikun	0:13413ea9a877	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
ganlikun	0:13413ea9a877	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
ganlikun	0:13413ea9a877	262
ganlikun	0:13413ea9a877	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
ganlikun	0:13413ea9a877	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
ganlikun	0:13413ea9a877	265
ganlikun	0:13413ea9a877	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
ganlikun	0:13413ea9a877	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
ganlikun	0:13413ea9a877	268
ganlikun	0:13413ea9a877	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
ganlikun	0:13413ea9a877	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
ganlikun	0:13413ea9a877	271
ganlikun	0:13413ea9a877	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
ganlikun	0:13413ea9a877	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
ganlikun	0:13413ea9a877	274
ganlikun	0:13413ea9a877	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
ganlikun	0:13413ea9a877	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
ganlikun	0:13413ea9a877	277
ganlikun	0:13413ea9a877	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
ganlikun	0:13413ea9a877	279	to disable the clock before changing frequency.
ganlikun	0:13413ea9a877	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
ganlikun	0:13413ea9a877	281
ganlikun	0:13413ea9a877	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
ganlikun	0:13413ea9a877	283	commands during the CAS latency and stores data in the Read FIFO.
ganlikun	0:13413ea9a877	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
ganlikun	0:13413ea9a877	285
ganlikun	0:13413ea9a877	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
ganlikun	0:13413ea9a877	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
ganlikun	0:13413ea9a877	288	}FMC_SDRAM_InitTypeDef;
ganlikun	0:13413ea9a877	289
ganlikun	0:13413ea9a877	290	/**
ganlikun	0:13413ea9a877	291	* @brief FMC SDRAM Timing parameters structure definition
ganlikun	0:13413ea9a877	292	*/
ganlikun	0:13413ea9a877	293	typedef struct
ganlikun	0:13413ea9a877	294	{
ganlikun	0:13413ea9a877	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
ganlikun	0:13413ea9a877	296	an active or Refresh command in number of memory clock cycles.
ganlikun	0:13413ea9a877	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	298
ganlikun	0:13413ea9a877	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
ganlikun	0:13413ea9a877	300	issuing the Activate command in number of memory clock cycles.
ganlikun	0:13413ea9a877	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	302
ganlikun	0:13413ea9a877	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
ganlikun	0:13413ea9a877	304	cycles.
ganlikun	0:13413ea9a877	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	306
ganlikun	0:13413ea9a877	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
ganlikun	0:13413ea9a877	308	and the delay between two consecutive Refresh commands in number of
ganlikun	0:13413ea9a877	309	memory clock cycles.
ganlikun	0:13413ea9a877	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	311
ganlikun	0:13413ea9a877	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
ganlikun	0:13413ea9a877	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	314
ganlikun	0:13413ea9a877	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
ganlikun	0:13413ea9a877	316	in number of memory clock cycles.
ganlikun	0:13413ea9a877	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	318
ganlikun	0:13413ea9a877	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
ganlikun	0:13413ea9a877	320	command in number of memory clock cycles.
ganlikun	0:13413ea9a877	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	322	}FMC_SDRAM_TimingTypeDef;
ganlikun	0:13413ea9a877	323
ganlikun	0:13413ea9a877	324	/**
ganlikun	0:13413ea9a877	325	* @brief SDRAM command parameters structure definition
ganlikun	0:13413ea9a877	326	*/
ganlikun	0:13413ea9a877	327	typedef struct
ganlikun	0:13413ea9a877	328	{
ganlikun	0:13413ea9a877	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
ganlikun	0:13413ea9a877	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
ganlikun	0:13413ea9a877	331
ganlikun	0:13413ea9a877	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
ganlikun	0:13413ea9a877	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
ganlikun	0:13413ea9a877	334
ganlikun	0:13413ea9a877	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
ganlikun	0:13413ea9a877	336	in auto refresh mode.
ganlikun	0:13413ea9a877	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
ganlikun	0:13413ea9a877	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
ganlikun	0:13413ea9a877	339	}FMC_SDRAM_CommandTypeDef;
ganlikun	0:13413ea9a877	340	/**
ganlikun	0:13413ea9a877	341	* @}
ganlikun	0:13413ea9a877	342	*/
ganlikun	0:13413ea9a877	343
ganlikun	0:13413ea9a877	344	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	345	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
ganlikun	0:13413ea9a877	346	* @{
ganlikun	0:13413ea9a877	347	*/
ganlikun	0:13413ea9a877	348
ganlikun	0:13413ea9a877	349	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
ganlikun	0:13413ea9a877	350	* @{
ganlikun	0:13413ea9a877	351	*/
ganlikun	0:13413ea9a877	352	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
ganlikun	0:13413ea9a877	353	* @{
ganlikun	0:13413ea9a877	354	*/
ganlikun	0:13413ea9a877	355	#define FMC_NORSRAM_BANK1 0x00000000U
ganlikun	0:13413ea9a877	356	#define FMC_NORSRAM_BANK2 0x00000002U
ganlikun	0:13413ea9a877	357	#define FMC_NORSRAM_BANK3 0x00000004U
ganlikun	0:13413ea9a877	358	#define FMC_NORSRAM_BANK4 0x00000006U
ganlikun	0:13413ea9a877	359	/**
ganlikun	0:13413ea9a877	360	* @}
ganlikun	0:13413ea9a877	361	*/
ganlikun	0:13413ea9a877	362
ganlikun	0:13413ea9a877	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
ganlikun	0:13413ea9a877	364	* @{
ganlikun	0:13413ea9a877	365	*/
ganlikun	0:13413ea9a877	366	#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	367	#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
ganlikun	0:13413ea9a877	368	/**
ganlikun	0:13413ea9a877	369	* @}
ganlikun	0:13413ea9a877	370	*/
ganlikun	0:13413ea9a877	371
ganlikun	0:13413ea9a877	372	/** @defgroup FMC_Memory_Type FMC Memory Type
ganlikun	0:13413ea9a877	373	* @{
ganlikun	0:13413ea9a877	374	*/
ganlikun	0:13413ea9a877	375	#define FMC_MEMORY_TYPE_SRAM 0x00000000U
ganlikun	0:13413ea9a877	376	#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
ganlikun	0:13413ea9a877	377	#define FMC_MEMORY_TYPE_NOR 0x00000008U
ganlikun	0:13413ea9a877	378	/**
ganlikun	0:13413ea9a877	379	* @}
ganlikun	0:13413ea9a877	380	*/
ganlikun	0:13413ea9a877	381
ganlikun	0:13413ea9a877	382	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
ganlikun	0:13413ea9a877	383	* @{
ganlikun	0:13413ea9a877	384	*/
ganlikun	0:13413ea9a877	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
ganlikun	0:13413ea9a877	386	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
ganlikun	0:13413ea9a877	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
ganlikun	0:13413ea9a877	388	/**
ganlikun	0:13413ea9a877	389	* @}
ganlikun	0:13413ea9a877	390	*/
ganlikun	0:13413ea9a877	391
ganlikun	0:13413ea9a877	392	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
ganlikun	0:13413ea9a877	393	* @{
ganlikun	0:13413ea9a877	394	*/
ganlikun	0:13413ea9a877	395	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
ganlikun	0:13413ea9a877	396	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	397	/**
ganlikun	0:13413ea9a877	398	* @}
ganlikun	0:13413ea9a877	399	*/
ganlikun	0:13413ea9a877	400
ganlikun	0:13413ea9a877	401	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
ganlikun	0:13413ea9a877	402	* @{
ganlikun	0:13413ea9a877	403	*/
ganlikun	0:13413ea9a877	404	#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	405	#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
ganlikun	0:13413ea9a877	406	/**
ganlikun	0:13413ea9a877	407	* @}
ganlikun	0:13413ea9a877	408	*/
ganlikun	0:13413ea9a877	409
ganlikun	0:13413ea9a877	410	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
ganlikun	0:13413ea9a877	411	* @{
ganlikun	0:13413ea9a877	412	*/
ganlikun	0:13413ea9a877	413	#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
ganlikun	0:13413ea9a877	414	#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
ganlikun	0:13413ea9a877	415	/**
ganlikun	0:13413ea9a877	416	* @}
ganlikun	0:13413ea9a877	417	*/
ganlikun	0:13413ea9a877	418
ganlikun	0:13413ea9a877	419	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
ganlikun	0:13413ea9a877	420	* @{
ganlikun	0:13413ea9a877	421	*/
ganlikun	0:13413ea9a877	422	/** @note This mode is not available for the STM32F446/469/479xx devices
ganlikun	0:13413ea9a877	423	*/
ganlikun	0:13413ea9a877	424	#define FMC_WRAP_MODE_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	425	#define FMC_WRAP_MODE_ENABLE 0x00000400U
ganlikun	0:13413ea9a877	426	/**
ganlikun	0:13413ea9a877	427	* @}
ganlikun	0:13413ea9a877	428	*/
ganlikun	0:13413ea9a877	429
ganlikun	0:13413ea9a877	430	/** @defgroup FMC_Wait_Timing FMC Wait Timing
ganlikun	0:13413ea9a877	431	* @{
ganlikun	0:13413ea9a877	432	*/
ganlikun	0:13413ea9a877	433	#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
ganlikun	0:13413ea9a877	434	#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
ganlikun	0:13413ea9a877	435	/**
ganlikun	0:13413ea9a877	436	* @}
ganlikun	0:13413ea9a877	437	*/
ganlikun	0:13413ea9a877	438
ganlikun	0:13413ea9a877	439	/** @defgroup FMC_Write_Operation FMC Write Operation
ganlikun	0:13413ea9a877	440	* @{
ganlikun	0:13413ea9a877	441	*/
ganlikun	0:13413ea9a877	442	#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	443	#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
ganlikun	0:13413ea9a877	444	/**
ganlikun	0:13413ea9a877	445	* @}
ganlikun	0:13413ea9a877	446	*/
ganlikun	0:13413ea9a877	447
ganlikun	0:13413ea9a877	448	/** @defgroup FMC_Wait_Signal FMC Wait Signal
ganlikun	0:13413ea9a877	449	* @{
ganlikun	0:13413ea9a877	450	*/
ganlikun	0:13413ea9a877	451	#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	452	#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
ganlikun	0:13413ea9a877	453	/**
ganlikun	0:13413ea9a877	454	* @}
ganlikun	0:13413ea9a877	455	*/
ganlikun	0:13413ea9a877	456
ganlikun	0:13413ea9a877	457	/** @defgroup FMC_Extended_Mode FMC Extended Mode
ganlikun	0:13413ea9a877	458	* @{
ganlikun	0:13413ea9a877	459	*/
ganlikun	0:13413ea9a877	460	#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	461	#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
ganlikun	0:13413ea9a877	462	/**
ganlikun	0:13413ea9a877	463	* @}
ganlikun	0:13413ea9a877	464	*/
ganlikun	0:13413ea9a877	465
ganlikun	0:13413ea9a877	466	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
ganlikun	0:13413ea9a877	467	* @{
ganlikun	0:13413ea9a877	468	*/
ganlikun	0:13413ea9a877	469	#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	470	#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
ganlikun	0:13413ea9a877	471	/**
ganlikun	0:13413ea9a877	472	* @}
ganlikun	0:13413ea9a877	473	*/
ganlikun	0:13413ea9a877	474
ganlikun	0:13413ea9a877	475	/** @defgroup FMC_Page_Size FMC Page Size
ganlikun	0:13413ea9a877	476	* @{
ganlikun	0:13413ea9a877	477	*/
ganlikun	0:13413ea9a877	478	#define FMC_PAGE_SIZE_NONE 0x00000000U
ganlikun	0:13413ea9a877	479	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
ganlikun	0:13413ea9a877	480	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
ganlikun	0:13413ea9a877	481	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
ganlikun	0:13413ea9a877	482	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
ganlikun	0:13413ea9a877	483	/**
ganlikun	0:13413ea9a877	484	* @}
ganlikun	0:13413ea9a877	485	*/
ganlikun	0:13413ea9a877	486
ganlikun	0:13413ea9a877	487	/** @defgroup FMC_Write_FIFO FMC Write FIFO
ganlikun	0:13413ea9a877	488	* @note These values are available only for the STM32F446/469/479xx devices.
ganlikun	0:13413ea9a877	489	* @{
ganlikun	0:13413ea9a877	490	*/
ganlikun	0:13413ea9a877	491	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
ganlikun	0:13413ea9a877	492	#define FMC_WRITE_FIFO_ENABLE 0x00000000U
ganlikun	0:13413ea9a877	493	/**
ganlikun	0:13413ea9a877	494	* @}
ganlikun	0:13413ea9a877	495	*/
ganlikun	0:13413ea9a877	496
ganlikun	0:13413ea9a877	497	/** @defgroup FMC_Write_Burst FMC Write Burst
ganlikun	0:13413ea9a877	498	* @{
ganlikun	0:13413ea9a877	499	*/
ganlikun	0:13413ea9a877	500	#define FMC_WRITE_BURST_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	501	#define FMC_WRITE_BURST_ENABLE 0x00080000U
ganlikun	0:13413ea9a877	502	/**
ganlikun	0:13413ea9a877	503	* @}
ganlikun	0:13413ea9a877	504	*/
ganlikun	0:13413ea9a877	505
ganlikun	0:13413ea9a877	506	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
ganlikun	0:13413ea9a877	507	* @{
ganlikun	0:13413ea9a877	508	*/
ganlikun	0:13413ea9a877	509	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
ganlikun	0:13413ea9a877	510	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
ganlikun	0:13413ea9a877	511	/**
ganlikun	0:13413ea9a877	512	* @}
ganlikun	0:13413ea9a877	513	*/
ganlikun	0:13413ea9a877	514
ganlikun	0:13413ea9a877	515	/** @defgroup FMC_Access_Mode FMC Access Mode
ganlikun	0:13413ea9a877	516	* @{
ganlikun	0:13413ea9a877	517	*/
ganlikun	0:13413ea9a877	518	#define FMC_ACCESS_MODE_A 0x00000000U
ganlikun	0:13413ea9a877	519	#define FMC_ACCESS_MODE_B 0x10000000U
ganlikun	0:13413ea9a877	520	#define FMC_ACCESS_MODE_C 0x20000000U
ganlikun	0:13413ea9a877	521	#define FMC_ACCESS_MODE_D 0x30000000U
ganlikun	0:13413ea9a877	522	/**
ganlikun	0:13413ea9a877	523	* @}
ganlikun	0:13413ea9a877	524	*/
ganlikun	0:13413ea9a877	525
ganlikun	0:13413ea9a877	526	/**
ganlikun	0:13413ea9a877	527	* @}
ganlikun	0:13413ea9a877	528	*/
ganlikun	0:13413ea9a877	529
ganlikun	0:13413ea9a877	530	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
ganlikun	0:13413ea9a877	531	* @{
ganlikun	0:13413ea9a877	532	*/
ganlikun	0:13413ea9a877	533	/** @defgroup FMC_NAND_Bank FMC NAND Bank
ganlikun	0:13413ea9a877	534	* @{
ganlikun	0:13413ea9a877	535	*/
ganlikun	0:13413ea9a877	536	#define FMC_NAND_BANK2 0x00000010U
ganlikun	0:13413ea9a877	537	#define FMC_NAND_BANK3 0x00000100U
ganlikun	0:13413ea9a877	538	/**
ganlikun	0:13413ea9a877	539	* @}
ganlikun	0:13413ea9a877	540	*/
ganlikun	0:13413ea9a877	541
ganlikun	0:13413ea9a877	542	/** @defgroup FMC_Wait_feature FMC Wait feature
ganlikun	0:13413ea9a877	543	* @{
ganlikun	0:13413ea9a877	544	*/
ganlikun	0:13413ea9a877	545	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	546	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
ganlikun	0:13413ea9a877	547	/**
ganlikun	0:13413ea9a877	548	* @}
ganlikun	0:13413ea9a877	549	*/
ganlikun	0:13413ea9a877	550
ganlikun	0:13413ea9a877	551	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
ganlikun	0:13413ea9a877	552	* @{
ganlikun	0:13413ea9a877	553	*/
ganlikun	0:13413ea9a877	554	#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
ganlikun	0:13413ea9a877	555	#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
ganlikun	0:13413ea9a877	556	/**
ganlikun	0:13413ea9a877	557	* @}
ganlikun	0:13413ea9a877	558	*/
ganlikun	0:13413ea9a877	559
ganlikun	0:13413ea9a877	560	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
ganlikun	0:13413ea9a877	561	* @{
ganlikun	0:13413ea9a877	562	*/
ganlikun	0:13413ea9a877	563	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
ganlikun	0:13413ea9a877	564	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
ganlikun	0:13413ea9a877	565	/**
ganlikun	0:13413ea9a877	566	* @}
ganlikun	0:13413ea9a877	567	*/
ganlikun	0:13413ea9a877	568
ganlikun	0:13413ea9a877	569	/** @defgroup FMC_ECC FMC ECC
ganlikun	0:13413ea9a877	570	* @{
ganlikun	0:13413ea9a877	571	*/
ganlikun	0:13413ea9a877	572	#define FMC_NAND_ECC_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	573	#define FMC_NAND_ECC_ENABLE 0x00000040U
ganlikun	0:13413ea9a877	574	/**
ganlikun	0:13413ea9a877	575	* @}
ganlikun	0:13413ea9a877	576	*/
ganlikun	0:13413ea9a877	577
ganlikun	0:13413ea9a877	578	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
ganlikun	0:13413ea9a877	579	* @{
ganlikun	0:13413ea9a877	580	*/
ganlikun	0:13413ea9a877	581	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
ganlikun	0:13413ea9a877	582	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
ganlikun	0:13413ea9a877	583	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
ganlikun	0:13413ea9a877	584	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
ganlikun	0:13413ea9a877	585	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
ganlikun	0:13413ea9a877	586	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
ganlikun	0:13413ea9a877	587	/**
ganlikun	0:13413ea9a877	588	* @}
ganlikun	0:13413ea9a877	589	*/
ganlikun	0:13413ea9a877	590
ganlikun	0:13413ea9a877	591	/**
ganlikun	0:13413ea9a877	592	* @}
ganlikun	0:13413ea9a877	593	*/
ganlikun	0:13413ea9a877	594
ganlikun	0:13413ea9a877	595	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
ganlikun	0:13413ea9a877	596	* @{
ganlikun	0:13413ea9a877	597	*/
ganlikun	0:13413ea9a877	598	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
ganlikun	0:13413ea9a877	599	* @{
ganlikun	0:13413ea9a877	600	*/
ganlikun	0:13413ea9a877	601	#define FMC_SDRAM_BANK1 0x00000000U
ganlikun	0:13413ea9a877	602	#define FMC_SDRAM_BANK2 0x00000001U
ganlikun	0:13413ea9a877	603	/**
ganlikun	0:13413ea9a877	604	* @}
ganlikun	0:13413ea9a877	605	*/
ganlikun	0:13413ea9a877	606
ganlikun	0:13413ea9a877	607	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
ganlikun	0:13413ea9a877	608	* @{
ganlikun	0:13413ea9a877	609	*/
ganlikun	0:13413ea9a877	610	#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
ganlikun	0:13413ea9a877	611	#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
ganlikun	0:13413ea9a877	612	#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
ganlikun	0:13413ea9a877	613	#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
ganlikun	0:13413ea9a877	614	/**
ganlikun	0:13413ea9a877	615	* @}
ganlikun	0:13413ea9a877	616	*/
ganlikun	0:13413ea9a877	617
ganlikun	0:13413ea9a877	618	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
ganlikun	0:13413ea9a877	619	* @{
ganlikun	0:13413ea9a877	620	*/
ganlikun	0:13413ea9a877	621	#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
ganlikun	0:13413ea9a877	622	#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
ganlikun	0:13413ea9a877	623	#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
ganlikun	0:13413ea9a877	624	/**
ganlikun	0:13413ea9a877	625	* @}
ganlikun	0:13413ea9a877	626	*/
ganlikun	0:13413ea9a877	627
ganlikun	0:13413ea9a877	628	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
ganlikun	0:13413ea9a877	629	* @{
ganlikun	0:13413ea9a877	630	*/
ganlikun	0:13413ea9a877	631	#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
ganlikun	0:13413ea9a877	632	#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
ganlikun	0:13413ea9a877	633	#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
ganlikun	0:13413ea9a877	634	/**
ganlikun	0:13413ea9a877	635	* @}
ganlikun	0:13413ea9a877	636	*/
ganlikun	0:13413ea9a877	637
ganlikun	0:13413ea9a877	638	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
ganlikun	0:13413ea9a877	639	* @{
ganlikun	0:13413ea9a877	640	*/
ganlikun	0:13413ea9a877	641	#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
ganlikun	0:13413ea9a877	642	#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
ganlikun	0:13413ea9a877	643	/**
ganlikun	0:13413ea9a877	644	* @}
ganlikun	0:13413ea9a877	645	*/
ganlikun	0:13413ea9a877	646
ganlikun	0:13413ea9a877	647	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
ganlikun	0:13413ea9a877	648	* @{
ganlikun	0:13413ea9a877	649	*/
ganlikun	0:13413ea9a877	650	#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
ganlikun	0:13413ea9a877	651	#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
ganlikun	0:13413ea9a877	652	#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
ganlikun	0:13413ea9a877	653	/**
ganlikun	0:13413ea9a877	654	* @}
ganlikun	0:13413ea9a877	655	*/
ganlikun	0:13413ea9a877	656
ganlikun	0:13413ea9a877	657	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
ganlikun	0:13413ea9a877	658	* @{
ganlikun	0:13413ea9a877	659	*/
ganlikun	0:13413ea9a877	660	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	661	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
ganlikun	0:13413ea9a877	662
ganlikun	0:13413ea9a877	663	/**
ganlikun	0:13413ea9a877	664	* @}
ganlikun	0:13413ea9a877	665	*/
ganlikun	0:13413ea9a877	666
ganlikun	0:13413ea9a877	667	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
ganlikun	0:13413ea9a877	668	* @{
ganlikun	0:13413ea9a877	669	*/
ganlikun	0:13413ea9a877	670	#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	671	#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
ganlikun	0:13413ea9a877	672	#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
ganlikun	0:13413ea9a877	673	/**
ganlikun	0:13413ea9a877	674	* @}
ganlikun	0:13413ea9a877	675	*/
ganlikun	0:13413ea9a877	676
ganlikun	0:13413ea9a877	677	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
ganlikun	0:13413ea9a877	678	* @{
ganlikun	0:13413ea9a877	679	*/
ganlikun	0:13413ea9a877	680	#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	681	#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
ganlikun	0:13413ea9a877	682	/**
ganlikun	0:13413ea9a877	683	* @}
ganlikun	0:13413ea9a877	684	*/
ganlikun	0:13413ea9a877	685
ganlikun	0:13413ea9a877	686	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
ganlikun	0:13413ea9a877	687	* @{
ganlikun	0:13413ea9a877	688	*/
ganlikun	0:13413ea9a877	689	#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
ganlikun	0:13413ea9a877	690	#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
ganlikun	0:13413ea9a877	691	#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
ganlikun	0:13413ea9a877	692	/**
ganlikun	0:13413ea9a877	693	* @}
ganlikun	0:13413ea9a877	694	*/
ganlikun	0:13413ea9a877	695
ganlikun	0:13413ea9a877	696	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
ganlikun	0:13413ea9a877	697	* @{
ganlikun	0:13413ea9a877	698	*/
ganlikun	0:13413ea9a877	699	#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
ganlikun	0:13413ea9a877	700	#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
ganlikun	0:13413ea9a877	701	#define FMC_SDRAM_CMD_PALL 0x00000002U
ganlikun	0:13413ea9a877	702	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
ganlikun	0:13413ea9a877	703	#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
ganlikun	0:13413ea9a877	704	#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
ganlikun	0:13413ea9a877	705	#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
ganlikun	0:13413ea9a877	706	/**
ganlikun	0:13413ea9a877	707	* @}
ganlikun	0:13413ea9a877	708	*/
ganlikun	0:13413ea9a877	709
ganlikun	0:13413ea9a877	710	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
ganlikun	0:13413ea9a877	711	* @{
ganlikun	0:13413ea9a877	712	*/
ganlikun	0:13413ea9a877	713	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
ganlikun	0:13413ea9a877	714	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
ganlikun	0:13413ea9a877	715	#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
ganlikun	0:13413ea9a877	716	/**
ganlikun	0:13413ea9a877	717	* @}
ganlikun	0:13413ea9a877	718	*/
ganlikun	0:13413ea9a877	719
ganlikun	0:13413ea9a877	720	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
ganlikun	0:13413ea9a877	721	* @{
ganlikun	0:13413ea9a877	722	*/
ganlikun	0:13413ea9a877	723	#define FMC_SDRAM_NORMAL_MODE 0x00000000U
ganlikun	0:13413ea9a877	724	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
ganlikun	0:13413ea9a877	725	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
ganlikun	0:13413ea9a877	726	/**
ganlikun	0:13413ea9a877	727	* @}
ganlikun	0:13413ea9a877	728	*/
ganlikun	0:13413ea9a877	729
ganlikun	0:13413ea9a877	730	/**
ganlikun	0:13413ea9a877	731	* @}
ganlikun	0:13413ea9a877	732	*/
ganlikun	0:13413ea9a877	733
ganlikun	0:13413ea9a877	734	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
ganlikun	0:13413ea9a877	735	* @{
ganlikun	0:13413ea9a877	736	*/
ganlikun	0:13413ea9a877	737	#define FMC_IT_RISING_EDGE 0x00000008U
ganlikun	0:13413ea9a877	738	#define FMC_IT_LEVEL 0x00000010U
ganlikun	0:13413ea9a877	739	#define FMC_IT_FALLING_EDGE 0x00000020U
ganlikun	0:13413ea9a877	740	#define FMC_IT_REFRESH_ERROR 0x00004000U
ganlikun	0:13413ea9a877	741	/**
ganlikun	0:13413ea9a877	742	* @}
ganlikun	0:13413ea9a877	743	*/
ganlikun	0:13413ea9a877	744
ganlikun	0:13413ea9a877	745	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
ganlikun	0:13413ea9a877	746	* @{
ganlikun	0:13413ea9a877	747	*/
ganlikun	0:13413ea9a877	748	#define FMC_FLAG_RISING_EDGE 0x00000001U
ganlikun	0:13413ea9a877	749	#define FMC_FLAG_LEVEL 0x00000002U
ganlikun	0:13413ea9a877	750	#define FMC_FLAG_FALLING_EDGE 0x00000004U
ganlikun	0:13413ea9a877	751	#define FMC_FLAG_FEMPT 0x00000040U
ganlikun	0:13413ea9a877	752	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
ganlikun	0:13413ea9a877	753	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
ganlikun	0:13413ea9a877	754	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
ganlikun	0:13413ea9a877	755	/**
ganlikun	0:13413ea9a877	756	* @}
ganlikun	0:13413ea9a877	757	*/
ganlikun	0:13413ea9a877	758
ganlikun	0:13413ea9a877	759	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
ganlikun	0:13413ea9a877	760	* @{
ganlikun	0:13413ea9a877	761	*/
ganlikun	0:13413ea9a877	762	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	763	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
ganlikun	0:13413ea9a877	764	#else
ganlikun	0:13413ea9a877	765	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
ganlikun	0:13413ea9a877	766	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
ganlikun	0:13413ea9a877	767	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	768	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
ganlikun	0:13413ea9a877	769	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
ganlikun	0:13413ea9a877	770	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
ganlikun	0:13413ea9a877	771
ganlikun	0:13413ea9a877	772
ganlikun	0:13413ea9a877	773	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	774	#define FMC_NAND_DEVICE FMC_Bank3
ganlikun	0:13413ea9a877	775	#else
ganlikun	0:13413ea9a877	776	#define FMC_NAND_DEVICE FMC_Bank2_3
ganlikun	0:13413ea9a877	777	#define FMC_PCCARD_DEVICE FMC_Bank4
ganlikun	0:13413ea9a877	778	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	779	#define FMC_NORSRAM_DEVICE FMC_Bank1
ganlikun	0:13413ea9a877	780	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
ganlikun	0:13413ea9a877	781	#define FMC_SDRAM_DEVICE FMC_Bank5_6
ganlikun	0:13413ea9a877	782	/**
ganlikun	0:13413ea9a877	783	* @}
ganlikun	0:13413ea9a877	784	*/
ganlikun	0:13413ea9a877	785
ganlikun	0:13413ea9a877	786	/**
ganlikun	0:13413ea9a877	787	* @}
ganlikun	0:13413ea9a877	788	*/
ganlikun	0:13413ea9a877	789
ganlikun	0:13413ea9a877	790	/* Private macro -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	791	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
ganlikun	0:13413ea9a877	792	* @{
ganlikun	0:13413ea9a877	793	*/
ganlikun	0:13413ea9a877	794
ganlikun	0:13413ea9a877	795	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
ganlikun	0:13413ea9a877	796	* @brief macros to handle NOR device enable/disable and read/write operations
ganlikun	0:13413ea9a877	797	* @{
ganlikun	0:13413ea9a877	798	*/
ganlikun	0:13413ea9a877	799	/**
ganlikun	0:13413ea9a877	800	* @brief Enable the NORSRAM device access.
ganlikun	0:13413ea9a877	801	* @param __INSTANCE__: FMC_NORSRAM Instance
ganlikun	0:13413ea9a877	802	* @param __BANK__: FMC_NORSRAM Bank
ganlikun	0:13413ea9a877	803	* @retval None
ganlikun	0:13413ea9a877	804	*/
ganlikun	0:13413ea9a877	805	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
ganlikun	0:13413ea9a877	806
ganlikun	0:13413ea9a877	807	/**
ganlikun	0:13413ea9a877	808	* @brief Disable the NORSRAM device access.
ganlikun	0:13413ea9a877	809	* @param __INSTANCE__: FMC_NORSRAM Instance
ganlikun	0:13413ea9a877	810	* @param __BANK__: FMC_NORSRAM Bank
ganlikun	0:13413ea9a877	811	* @retval None
ganlikun	0:13413ea9a877	812	*/
ganlikun	0:13413ea9a877	813	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
ganlikun	0:13413ea9a877	814	/**
ganlikun	0:13413ea9a877	815	* @}
ganlikun	0:13413ea9a877	816	*/
ganlikun	0:13413ea9a877	817
ganlikun	0:13413ea9a877	818	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
ganlikun	0:13413ea9a877	819	* @brief macros to handle NAND device enable/disable
ganlikun	0:13413ea9a877	820	* @{
ganlikun	0:13413ea9a877	821	*/
ganlikun	0:13413ea9a877	822	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	823	/**
ganlikun	0:13413ea9a877	824	* @brief Enable the NAND device access.
ganlikun	0:13413ea9a877	825	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	826	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	827	* @retval None
ganlikun	0:13413ea9a877	828	*/
ganlikun	0:13413ea9a877	829	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
ganlikun	0:13413ea9a877	830
ganlikun	0:13413ea9a877	831	/**
ganlikun	0:13413ea9a877	832	* @brief Disable the NAND device access.
ganlikun	0:13413ea9a877	833	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	834	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	835	* @retval None
ganlikun	0:13413ea9a877	836	*/
ganlikun	0:13413ea9a877	837	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
ganlikun	0:13413ea9a877	838	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
ganlikun	0:13413ea9a877	839	/**
ganlikun	0:13413ea9a877	840	* @brief Enable the NAND device access.
ganlikun	0:13413ea9a877	841	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	842	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	843	* @retval None
ganlikun	0:13413ea9a877	844	*/
ganlikun	0:13413ea9a877	845	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
ganlikun	0:13413ea9a877	846	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
ganlikun	0:13413ea9a877	847
ganlikun	0:13413ea9a877	848	/**
ganlikun	0:13413ea9a877	849	* @brief Disable the NAND device access.
ganlikun	0:13413ea9a877	850	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	851	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	852	* @retval None
ganlikun	0:13413ea9a877	853	*/
ganlikun	0:13413ea9a877	854	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
ganlikun	0:13413ea9a877	855	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
ganlikun	0:13413ea9a877	856
ganlikun	0:13413ea9a877	857	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
ganlikun	0:13413ea9a877	858	/**
ganlikun	0:13413ea9a877	859	* @}
ganlikun	0:13413ea9a877	860	*/
ganlikun	0:13413ea9a877	861	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	862	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
ganlikun	0:13413ea9a877	863	* @brief macros to handle SRAM read/write operations
ganlikun	0:13413ea9a877	864	* @{
ganlikun	0:13413ea9a877	865	*/
ganlikun	0:13413ea9a877	866	/**
ganlikun	0:13413ea9a877	867	* @brief Enable the PCCARD device access.
ganlikun	0:13413ea9a877	868	* @param __INSTANCE__: FMC_PCCARD Instance
ganlikun	0:13413ea9a877	869	* @retval None
ganlikun	0:13413ea9a877	870	*/
ganlikun	0:13413ea9a877	871	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
ganlikun	0:13413ea9a877	872
ganlikun	0:13413ea9a877	873	/**
ganlikun	0:13413ea9a877	874	* @brief Disable the PCCARD device access.
ganlikun	0:13413ea9a877	875	* @param __INSTANCE__: FMC_PCCARD Instance
ganlikun	0:13413ea9a877	876	* @retval None
ganlikun	0:13413ea9a877	877	*/
ganlikun	0:13413ea9a877	878	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
ganlikun	0:13413ea9a877	879	/**
ganlikun	0:13413ea9a877	880	* @}
ganlikun	0:13413ea9a877	881	*/
ganlikun	0:13413ea9a877	882	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
ganlikun	0:13413ea9a877	883
ganlikun	0:13413ea9a877	884	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
ganlikun	0:13413ea9a877	885	* @brief macros to handle FMC flags and interrupts
ganlikun	0:13413ea9a877	886	* @{
ganlikun	0:13413ea9a877	887	*/
ganlikun	0:13413ea9a877	888	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	889	/**
ganlikun	0:13413ea9a877	890	* @brief Enable the NAND device interrupt.
ganlikun	0:13413ea9a877	891	* @param __INSTANCE__: FMC_NAND instance
ganlikun	0:13413ea9a877	892	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	893	* @param __INTERRUPT__: FMC_NAND interrupt
ganlikun	0:13413ea9a877	894	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	895	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun	0:13413ea9a877	896	* @arg FMC_IT_LEVEL: Interrupt level.
ganlikun	0:13413ea9a877	897	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun	0:13413ea9a877	898	* @retval None
ganlikun	0:13413ea9a877	899	*/
ganlikun	0:13413ea9a877	900	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
ganlikun	0:13413ea9a877	901
ganlikun	0:13413ea9a877	902	/**
ganlikun	0:13413ea9a877	903	* @brief Disable the NAND device interrupt.
ganlikun	0:13413ea9a877	904	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	905	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	906	* @param __INTERRUPT__: FMC_NAND interrupt
ganlikun	0:13413ea9a877	907	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	908	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun	0:13413ea9a877	909	* @arg FMC_IT_LEVEL: Interrupt level.
ganlikun	0:13413ea9a877	910	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun	0:13413ea9a877	911	* @retval None
ganlikun	0:13413ea9a877	912	*/
ganlikun	0:13413ea9a877	913	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
ganlikun	0:13413ea9a877	914
ganlikun	0:13413ea9a877	915	/**
ganlikun	0:13413ea9a877	916	* @brief Get flag status of the NAND device.
ganlikun	0:13413ea9a877	917	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	918	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	919	* @param __FLAG__: FMC_NAND flag
ganlikun	0:13413ea9a877	920	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	921	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun	0:13413ea9a877	922	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun	0:13413ea9a877	923	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun	0:13413ea9a877	924	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
ganlikun	0:13413ea9a877	925	* @retval The state of FLAG (SET or RESET).
ganlikun	0:13413ea9a877	926	*/
ganlikun	0:13413ea9a877	927	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
ganlikun	0:13413ea9a877	928	/**
ganlikun	0:13413ea9a877	929	* @brief Clear flag status of the NAND device.
ganlikun	0:13413ea9a877	930	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	931	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	932	* @param __FLAG__: FMC_NAND flag
ganlikun	0:13413ea9a877	933	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	934	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun	0:13413ea9a877	935	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun	0:13413ea9a877	936	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun	0:13413ea9a877	937	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
ganlikun	0:13413ea9a877	938	* @retval None
ganlikun	0:13413ea9a877	939	*/
ganlikun	0:13413ea9a877	940	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
ganlikun	0:13413ea9a877	941	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
ganlikun	0:13413ea9a877	942	/**
ganlikun	0:13413ea9a877	943	* @brief Enable the NAND device interrupt.
ganlikun	0:13413ea9a877	944	* @param __INSTANCE__: FMC_NAND instance
ganlikun	0:13413ea9a877	945	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	946	* @param __INTERRUPT__: FMC_NAND interrupt
ganlikun	0:13413ea9a877	947	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	948	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun	0:13413ea9a877	949	* @arg FMC_IT_LEVEL: Interrupt level.
ganlikun	0:13413ea9a877	950	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun	0:13413ea9a877	951	* @retval None
ganlikun	0:13413ea9a877	952	*/
ganlikun	0:13413ea9a877	953	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
ganlikun	0:13413ea9a877	954	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
ganlikun	0:13413ea9a877	955
ganlikun	0:13413ea9a877	956	/**
ganlikun	0:13413ea9a877	957	* @brief Disable the NAND device interrupt.
ganlikun	0:13413ea9a877	958	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	959	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	960	* @param __INTERRUPT__: FMC_NAND interrupt
ganlikun	0:13413ea9a877	961	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	962	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun	0:13413ea9a877	963	* @arg FMC_IT_LEVEL: Interrupt level.
ganlikun	0:13413ea9a877	964	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun	0:13413ea9a877	965	* @retval None
ganlikun	0:13413ea9a877	966	*/
ganlikun	0:13413ea9a877	967	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
ganlikun	0:13413ea9a877	968	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
ganlikun	0:13413ea9a877	969
ganlikun	0:13413ea9a877	970	/**
ganlikun	0:13413ea9a877	971	* @brief Get flag status of the NAND device.
ganlikun	0:13413ea9a877	972	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	973	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	974	* @param __FLAG__: FMC_NAND flag
ganlikun	0:13413ea9a877	975	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	976	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun	0:13413ea9a877	977	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun	0:13413ea9a877	978	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun	0:13413ea9a877	979	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
ganlikun	0:13413ea9a877	980	* @retval The state of FLAG (SET or RESET).
ganlikun	0:13413ea9a877	981	*/
ganlikun	0:13413ea9a877	982	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
ganlikun	0:13413ea9a877	983	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
ganlikun	0:13413ea9a877	984	/**
ganlikun	0:13413ea9a877	985	* @brief Clear flag status of the NAND device.
ganlikun	0:13413ea9a877	986	* @param __INSTANCE__: FMC_NAND Instance
ganlikun	0:13413ea9a877	987	* @param __BANK__: FMC_NAND Bank
ganlikun	0:13413ea9a877	988	* @param __FLAG__: FMC_NAND flag
ganlikun	0:13413ea9a877	989	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	990	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun	0:13413ea9a877	991	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun	0:13413ea9a877	992	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun	0:13413ea9a877	993	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
ganlikun	0:13413ea9a877	994	* @retval None
ganlikun	0:13413ea9a877	995	*/
ganlikun	0:13413ea9a877	996	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
ganlikun	0:13413ea9a877	997	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
ganlikun	0:13413ea9a877	998	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
ganlikun	0:13413ea9a877	999
ganlikun	0:13413ea9a877	1000	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	1001	/**
ganlikun	0:13413ea9a877	1002	* @brief Enable the PCCARD device interrupt.
ganlikun	0:13413ea9a877	1003	* @param __INSTANCE__: FMC_PCCARD instance
ganlikun	0:13413ea9a877	1004	* @param __INTERRUPT__: FMC_PCCARD interrupt
ganlikun	0:13413ea9a877	1005	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1006	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun	0:13413ea9a877	1007	* @arg FMC_IT_LEVEL: Interrupt level.
ganlikun	0:13413ea9a877	1008	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun	0:13413ea9a877	1009	* @retval None
ganlikun	0:13413ea9a877	1010	*/
ganlikun	0:13413ea9a877	1011	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
ganlikun	0:13413ea9a877	1012
ganlikun	0:13413ea9a877	1013	/**
ganlikun	0:13413ea9a877	1014	* @brief Disable the PCCARD device interrupt.
ganlikun	0:13413ea9a877	1015	* @param __INSTANCE__: FMC_PCCARD instance
ganlikun	0:13413ea9a877	1016	* @param __INTERRUPT__: FMC_PCCARD interrupt
ganlikun	0:13413ea9a877	1017	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1018	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
ganlikun	0:13413ea9a877	1019	* @arg FMC_IT_LEVEL: Interrupt level.
ganlikun	0:13413ea9a877	1020	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
ganlikun	0:13413ea9a877	1021	* @retval None
ganlikun	0:13413ea9a877	1022	*/
ganlikun	0:13413ea9a877	1023	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
ganlikun	0:13413ea9a877	1024
ganlikun	0:13413ea9a877	1025	/**
ganlikun	0:13413ea9a877	1026	* @brief Get flag status of the PCCARD device.
ganlikun	0:13413ea9a877	1027	* @param __INSTANCE__: FMC_PCCARD instance
ganlikun	0:13413ea9a877	1028	* @param __FLAG__: FMC_PCCARD flag
ganlikun	0:13413ea9a877	1029	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1030	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun	0:13413ea9a877	1031	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun	0:13413ea9a877	1032	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun	0:13413ea9a877	1033	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
ganlikun	0:13413ea9a877	1034	* @retval The state of FLAG (SET or RESET).
ganlikun	0:13413ea9a877	1035	*/
ganlikun	0:13413ea9a877	1036	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
ganlikun	0:13413ea9a877	1037
ganlikun	0:13413ea9a877	1038	/**
ganlikun	0:13413ea9a877	1039	* @brief Clear flag status of the PCCARD device.
ganlikun	0:13413ea9a877	1040	* @param __INSTANCE__: FMC_PCCARD instance
ganlikun	0:13413ea9a877	1041	* @param __FLAG__: FMC_PCCARD flag
ganlikun	0:13413ea9a877	1042	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1043	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
ganlikun	0:13413ea9a877	1044	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
ganlikun	0:13413ea9a877	1045	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
ganlikun	0:13413ea9a877	1046	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
ganlikun	0:13413ea9a877	1047	* @retval None
ganlikun	0:13413ea9a877	1048	*/
ganlikun	0:13413ea9a877	1049	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
ganlikun	0:13413ea9a877	1050	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
ganlikun	0:13413ea9a877	1051
ganlikun	0:13413ea9a877	1052	/**
ganlikun	0:13413ea9a877	1053	* @brief Enable the SDRAM device interrupt.
ganlikun	0:13413ea9a877	1054	* @param __INSTANCE__: FMC_SDRAM instance
ganlikun	0:13413ea9a877	1055	* @param __INTERRUPT__: FMC_SDRAM interrupt
ganlikun	0:13413ea9a877	1056	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1057	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
ganlikun	0:13413ea9a877	1058	* @retval None
ganlikun	0:13413ea9a877	1059	*/
ganlikun	0:13413ea9a877	1060	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
ganlikun	0:13413ea9a877	1061
ganlikun	0:13413ea9a877	1062	/**
ganlikun	0:13413ea9a877	1063	* @brief Disable the SDRAM device interrupt.
ganlikun	0:13413ea9a877	1064	* @param __INSTANCE__: FMC_SDRAM instance
ganlikun	0:13413ea9a877	1065	* @param __INTERRUPT__: FMC_SDRAM interrupt
ganlikun	0:13413ea9a877	1066	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1067	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
ganlikun	0:13413ea9a877	1068	* @retval None
ganlikun	0:13413ea9a877	1069	*/
ganlikun	0:13413ea9a877	1070	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
ganlikun	0:13413ea9a877	1071
ganlikun	0:13413ea9a877	1072	/**
ganlikun	0:13413ea9a877	1073	* @brief Get flag status of the SDRAM device.
ganlikun	0:13413ea9a877	1074	* @param __INSTANCE__: FMC_SDRAM instance
ganlikun	0:13413ea9a877	1075	* @param __FLAG__: FMC_SDRAM flag
ganlikun	0:13413ea9a877	1076	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1077	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
ganlikun	0:13413ea9a877	1078	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
ganlikun	0:13413ea9a877	1079	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
ganlikun	0:13413ea9a877	1080	* @retval The state of FLAG (SET or RESET).
ganlikun	0:13413ea9a877	1081	*/
ganlikun	0:13413ea9a877	1082	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
ganlikun	0:13413ea9a877	1083
ganlikun	0:13413ea9a877	1084	/**
ganlikun	0:13413ea9a877	1085	* @brief Clear flag status of the SDRAM device.
ganlikun	0:13413ea9a877	1086	* @param __INSTANCE__: FMC_SDRAM instance
ganlikun	0:13413ea9a877	1087	* @param __FLAG__: FMC_SDRAM flag
ganlikun	0:13413ea9a877	1088	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1089	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
ganlikun	0:13413ea9a877	1090	* @retval None
ganlikun	0:13413ea9a877	1091	*/
ganlikun	0:13413ea9a877	1092	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
ganlikun	0:13413ea9a877	1093	/**
ganlikun	0:13413ea9a877	1094	* @}
ganlikun	0:13413ea9a877	1095	*/
ganlikun	0:13413ea9a877	1096
ganlikun	0:13413ea9a877	1097	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
ganlikun	0:13413ea9a877	1098	* @{
ganlikun	0:13413ea9a877	1099	*/
ganlikun	0:13413ea9a877	1100	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
ganlikun	0:13413ea9a877	1101	((BANK) == FMC_NORSRAM_BANK2) \|\| \
ganlikun	0:13413ea9a877	1102	((BANK) == FMC_NORSRAM_BANK3) \|\| \
ganlikun	0:13413ea9a877	1103	((BANK) == FMC_NORSRAM_BANK4))
ganlikun	0:13413ea9a877	1104
ganlikun	0:13413ea9a877	1105	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1106	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
ganlikun	0:13413ea9a877	1107
ganlikun	0:13413ea9a877	1108	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
ganlikun	0:13413ea9a877	1109	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
ganlikun	0:13413ea9a877	1110	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
ganlikun	0:13413ea9a877	1111
ganlikun	0:13413ea9a877	1112	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
ganlikun	0:13413ea9a877	1113	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
ganlikun	0:13413ea9a877	1114	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
ganlikun	0:13413ea9a877	1115
ganlikun	0:13413ea9a877	1116	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
ganlikun	0:13413ea9a877	1117	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
ganlikun	0:13413ea9a877	1118	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
ganlikun	0:13413ea9a877	1119	((__MODE__) == FMC_ACCESS_MODE_D))
ganlikun	0:13413ea9a877	1120
ganlikun	0:13413ea9a877	1121	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
ganlikun	0:13413ea9a877	1122	((BANK) == FMC_NAND_BANK3))
ganlikun	0:13413ea9a877	1123
ganlikun	0:13413ea9a877	1124	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1125	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
ganlikun	0:13413ea9a877	1126
ganlikun	0:13413ea9a877	1127	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
ganlikun	0:13413ea9a877	1128	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
ganlikun	0:13413ea9a877	1129
ganlikun	0:13413ea9a877	1130	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1131	((STATE) == FMC_NAND_ECC_ENABLE))
ganlikun	0:13413ea9a877	1132
ganlikun	0:13413ea9a877	1133	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
ganlikun	0:13413ea9a877	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
ganlikun	0:13413ea9a877	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
ganlikun	0:13413ea9a877	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
ganlikun	0:13413ea9a877	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
ganlikun	0:13413ea9a877	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
ganlikun	0:13413ea9a877	1139
ganlikun	0:13413ea9a877	1140	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
ganlikun	0:13413ea9a877	1141
ganlikun	0:13413ea9a877	1142	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
ganlikun	0:13413ea9a877	1143
ganlikun	0:13413ea9a877	1144	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
ganlikun	0:13413ea9a877	1145
ganlikun	0:13413ea9a877	1146	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
ganlikun	0:13413ea9a877	1147
ganlikun	0:13413ea9a877	1148	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
ganlikun	0:13413ea9a877	1149
ganlikun	0:13413ea9a877	1150	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
ganlikun	0:13413ea9a877	1151
ganlikun	0:13413ea9a877	1152	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
ganlikun	0:13413ea9a877	1153
ganlikun	0:13413ea9a877	1154	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
ganlikun	0:13413ea9a877	1155
ganlikun	0:13413ea9a877	1156	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
ganlikun	0:13413ea9a877	1157
ganlikun	0:13413ea9a877	1158	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
ganlikun	0:13413ea9a877	1159
ganlikun	0:13413ea9a877	1160	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1161	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
ganlikun	0:13413ea9a877	1162
ganlikun	0:13413ea9a877	1163	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
ganlikun	0:13413ea9a877	1164	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
ganlikun	0:13413ea9a877	1165
ganlikun	0:13413ea9a877	1166	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	1167	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1168	((__MODE__) == FMC_WRAP_MODE_ENABLE))
ganlikun	0:13413ea9a877	1169	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	1170
ganlikun	0:13413ea9a877	1171	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
ganlikun	0:13413ea9a877	1172	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
ganlikun	0:13413ea9a877	1173
ganlikun	0:13413ea9a877	1174	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1175	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
ganlikun	0:13413ea9a877	1176
ganlikun	0:13413ea9a877	1177	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1178	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
ganlikun	0:13413ea9a877	1179
ganlikun	0:13413ea9a877	1180	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1181	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
ganlikun	0:13413ea9a877	1182
ganlikun	0:13413ea9a877	1183	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1184	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
ganlikun	0:13413ea9a877	1185
ganlikun	0:13413ea9a877	1186	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1187	((__BURST__) == FMC_WRITE_BURST_ENABLE))
ganlikun	0:13413ea9a877	1188
ganlikun	0:13413ea9a877	1189	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
ganlikun	0:13413ea9a877	1190	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
ganlikun	0:13413ea9a877	1191
ganlikun	0:13413ea9a877	1192	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
ganlikun	0:13413ea9a877	1193
ganlikun	0:13413ea9a877	1194	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
ganlikun	0:13413ea9a877	1195
ganlikun	0:13413ea9a877	1196	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
ganlikun	0:13413ea9a877	1197
ganlikun	0:13413ea9a877	1198	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
ganlikun	0:13413ea9a877	1199
ganlikun	0:13413ea9a877	1200	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
ganlikun	0:13413ea9a877	1201
ganlikun	0:13413ea9a877	1202	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
ganlikun	0:13413ea9a877	1203
ganlikun	0:13413ea9a877	1204	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
ganlikun	0:13413ea9a877	1205	((BANK) == FMC_SDRAM_BANK2))
ganlikun	0:13413ea9a877	1206
ganlikun	0:13413ea9a877	1207	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
ganlikun	0:13413ea9a877	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
ganlikun	0:13413ea9a877	1209	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
ganlikun	0:13413ea9a877	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
ganlikun	0:13413ea9a877	1211
ganlikun	0:13413ea9a877	1212	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
ganlikun	0:13413ea9a877	1213	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
ganlikun	0:13413ea9a877	1214	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
ganlikun	0:13413ea9a877	1215
ganlikun	0:13413ea9a877	1216	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
ganlikun	0:13413ea9a877	1217	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
ganlikun	0:13413ea9a877	1218	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
ganlikun	0:13413ea9a877	1219
ganlikun	0:13413ea9a877	1220	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
ganlikun	0:13413ea9a877	1221	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
ganlikun	0:13413ea9a877	1222
ganlikun	0:13413ea9a877	1223
ganlikun	0:13413ea9a877	1224	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
ganlikun	0:13413ea9a877	1225	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
ganlikun	0:13413ea9a877	1226	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
ganlikun	0:13413ea9a877	1227
ganlikun	0:13413ea9a877	1228	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1229	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
ganlikun	0:13413ea9a877	1230	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
ganlikun	0:13413ea9a877	1231
ganlikun	0:13413ea9a877	1232	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1233	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
ganlikun	0:13413ea9a877	1234
ganlikun	0:13413ea9a877	1235
ganlikun	0:13413ea9a877	1236	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
ganlikun	0:13413ea9a877	1237	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
ganlikun	0:13413ea9a877	1238	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
ganlikun	0:13413ea9a877	1239
ganlikun	0:13413ea9a877	1240	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
ganlikun	0:13413ea9a877	1241
ganlikun	0:13413ea9a877	1242	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
ganlikun	0:13413ea9a877	1243
ganlikun	0:13413ea9a877	1244	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
ganlikun	0:13413ea9a877	1245
ganlikun	0:13413ea9a877	1246	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
ganlikun	0:13413ea9a877	1247
ganlikun	0:13413ea9a877	1248	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
ganlikun	0:13413ea9a877	1249
ganlikun	0:13413ea9a877	1250	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
ganlikun	0:13413ea9a877	1251
ganlikun	0:13413ea9a877	1252	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
ganlikun	0:13413ea9a877	1253
ganlikun	0:13413ea9a877	1254	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
ganlikun	0:13413ea9a877	1255	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
ganlikun	0:13413ea9a877	1256	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
ganlikun	0:13413ea9a877	1257	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
ganlikun	0:13413ea9a877	1258	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
ganlikun	0:13413ea9a877	1259	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
ganlikun	0:13413ea9a877	1260	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
ganlikun	0:13413ea9a877	1261
ganlikun	0:13413ea9a877	1262	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
ganlikun	0:13413ea9a877	1263	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
ganlikun	0:13413ea9a877	1264	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
ganlikun	0:13413ea9a877	1265
ganlikun	0:13413ea9a877	1266	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
ganlikun	0:13413ea9a877	1267
ganlikun	0:13413ea9a877	1268	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
ganlikun	0:13413ea9a877	1269
ganlikun	0:13413ea9a877	1270	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
ganlikun	0:13413ea9a877	1271
ganlikun	0:13413ea9a877	1272	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
ganlikun	0:13413ea9a877	1273
ganlikun	0:13413ea9a877	1274	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1275	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
ganlikun	0:13413ea9a877	1276
ganlikun	0:13413ea9a877	1277	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
ganlikun	0:13413ea9a877	1278	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
ganlikun	0:13413ea9a877	1279	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
ganlikun	0:13413ea9a877	1280	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
ganlikun	0:13413ea9a877	1281	((SIZE) == FMC_PAGE_SIZE_1024))
ganlikun	0:13413ea9a877	1282
ganlikun	0:13413ea9a877	1283	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1284	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
ganlikun	0:13413ea9a877	1285	((FIFO) == FMC_WRITE_FIFO_ENABLE))
ganlikun	0:13413ea9a877	1286	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1287
ganlikun	0:13413ea9a877	1288	/**
ganlikun	0:13413ea9a877	1289	* @}
ganlikun	0:13413ea9a877	1290	*/
ganlikun	0:13413ea9a877	1291
ganlikun	0:13413ea9a877	1292	/**
ganlikun	0:13413ea9a877	1293	* @}
ganlikun	0:13413ea9a877	1294	*/
ganlikun	0:13413ea9a877	1295
ganlikun	0:13413ea9a877	1296	/* Private functions ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	1297	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
ganlikun	0:13413ea9a877	1298	* @{
ganlikun	0:13413ea9a877	1299	*/
ganlikun	0:13413ea9a877	1300
ganlikun	0:13413ea9a877	1301	/** @defgroup FMC_LL_NORSRAM NOR SRAM
ganlikun	0:13413ea9a877	1302	* @{
ganlikun	0:13413ea9a877	1303	*/
ganlikun	0:13413ea9a877	1304	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
ganlikun	0:13413ea9a877	1305	* @{
ganlikun	0:13413ea9a877	1306	*/
ganlikun	0:13413ea9a877	1307	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
ganlikun	0:13413ea9a877	1308	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
ganlikun	0:13413ea9a877	1309	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
ganlikun	0:13413ea9a877	1310	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
ganlikun	0:13413ea9a877	1311	/**
ganlikun	0:13413ea9a877	1312	* @}
ganlikun	0:13413ea9a877	1313	*/
ganlikun	0:13413ea9a877	1314
ganlikun	0:13413ea9a877	1315	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
ganlikun	0:13413ea9a877	1316	* @{
ganlikun	0:13413ea9a877	1317	*/
ganlikun	0:13413ea9a877	1318	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1320	/**
ganlikun	0:13413ea9a877	1321	* @}
ganlikun	0:13413ea9a877	1322	*/
ganlikun	0:13413ea9a877	1323	/**
ganlikun	0:13413ea9a877	1324	* @}
ganlikun	0:13413ea9a877	1325	*/
ganlikun	0:13413ea9a877	1326
ganlikun	0:13413ea9a877	1327	/** @defgroup FMC_LL_NAND NAND
ganlikun	0:13413ea9a877	1328	* @{
ganlikun	0:13413ea9a877	1329	*/
ganlikun	0:13413ea9a877	1330	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
ganlikun	0:13413ea9a877	1331	* @{
ganlikun	0:13413ea9a877	1332	*/
ganlikun	0:13413ea9a877	1333	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
ganlikun	0:13413ea9a877	1334	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
ganlikun	0:13413ea9a877	1335	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
ganlikun	0:13413ea9a877	1336	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1337	/**
ganlikun	0:13413ea9a877	1338	* @}
ganlikun	0:13413ea9a877	1339	*/
ganlikun	0:13413ea9a877	1340
ganlikun	0:13413ea9a877	1341	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
ganlikun	0:13413ea9a877	1342	* @{
ganlikun	0:13413ea9a877	1343	*/
ganlikun	0:13413ea9a877	1344	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1345	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1346	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
ganlikun	0:13413ea9a877	1347
ganlikun	0:13413ea9a877	1348	/**
ganlikun	0:13413ea9a877	1349	* @}
ganlikun	0:13413ea9a877	1350	*/
ganlikun	0:13413ea9a877	1351	/**
ganlikun	0:13413ea9a877	1352	* @}
ganlikun	0:13413ea9a877	1353	*/
ganlikun	0:13413ea9a877	1354	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	1355	/** @defgroup FMC_LL_PCCARD PCCARD
ganlikun	0:13413ea9a877	1356	* @{
ganlikun	0:13413ea9a877	1357	*/
ganlikun	0:13413ea9a877	1358	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
ganlikun	0:13413ea9a877	1359	* @{
ganlikun	0:13413ea9a877	1360	*/
ganlikun	0:13413ea9a877	1361	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
ganlikun	0:13413ea9a877	1362	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
ganlikun	0:13413ea9a877	1363	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
ganlikun	0:13413ea9a877	1364	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
ganlikun	0:13413ea9a877	1365	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
ganlikun	0:13413ea9a877	1366	/**
ganlikun	0:13413ea9a877	1367	* @}
ganlikun	0:13413ea9a877	1368	*/
ganlikun	0:13413ea9a877	1369	/**
ganlikun	0:13413ea9a877	1370	* @}
ganlikun	0:13413ea9a877	1371	*/
ganlikun	0:13413ea9a877	1372	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	1373
ganlikun	0:13413ea9a877	1374	/** @defgroup FMC_LL_SDRAM SDRAM
ganlikun	0:13413ea9a877	1375	* @{
ganlikun	0:13413ea9a877	1376	*/
ganlikun	0:13413ea9a877	1377	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
ganlikun	0:13413ea9a877	1378	* @{
ganlikun	0:13413ea9a877	1379	*/
ganlikun	0:13413ea9a877	1380	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
ganlikun	0:13413ea9a877	1381	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
ganlikun	0:13413ea9a877	1382	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1383	/**
ganlikun	0:13413ea9a877	1384	* @}
ganlikun	0:13413ea9a877	1385	*/
ganlikun	0:13413ea9a877	1386
ganlikun	0:13413ea9a877	1387	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
ganlikun	0:13413ea9a877	1388	* @{
ganlikun	0:13413ea9a877	1389	*/
ganlikun	0:13413ea9a877	1390	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1392	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
ganlikun	0:13413ea9a877	1393	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
ganlikun	0:13413ea9a877	1394	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
ganlikun	0:13413ea9a877	1395	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
ganlikun	0:13413ea9a877	1396	/**
ganlikun	0:13413ea9a877	1397	* @}
ganlikun	0:13413ea9a877	1398	*/
ganlikun	0:13413ea9a877	1399	/**
ganlikun	0:13413ea9a877	1400	* @}
ganlikun	0:13413ea9a877	1401	*/
ganlikun	0:13413ea9a877	1402
ganlikun	0:13413ea9a877	1403	/**
ganlikun	0:13413ea9a877	1404	* @}
ganlikun	0:13413ea9a877	1405	*/
ganlikun	0:13413ea9a877	1406
ganlikun	0:13413ea9a877	1407	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1408	/**
ganlikun	0:13413ea9a877	1409	* @}
ganlikun	0:13413ea9a877	1410	*/
ganlikun	0:13413ea9a877	1411
ganlikun	0:13413ea9a877	1412	/**
ganlikun	0:13413ea9a877	1413	* @}
ganlikun	0:13413ea9a877	1414	*/
ganlikun	0:13413ea9a877	1415	#ifdef __cplusplus
ganlikun	0:13413ea9a877	1416	}
ganlikun	0:13413ea9a877	1417	#endif
ganlikun	0:13413ea9a877	1418
ganlikun	0:13413ea9a877	1419	#endif /* __STM32F4xx_LL_FMC_H */
ganlikun	0:13413ea9a877	1420
ganlikun	0:13413ea9a877	1421	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1422

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@0:13413ea9a877, 2022-06-12 (annotated)

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