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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

Who changed what in which revision?

User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_fmc.c
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief FMC Low Layer HAL module driver.
ganlikun	0:13413ea9a877	8	*
ganlikun	0:13413ea9a877	9	* This file provides firmware functions to manage the following
ganlikun	0:13413ea9a877	10	* functionalities of the Flexible Memory Controller (FMC) peripheral memories:
ganlikun	0:13413ea9a877	11	* + Initialization/de-initialization functions
ganlikun	0:13413ea9a877	12	* + Peripheral Control functions
ganlikun	0:13413ea9a877	13	* + Peripheral State functions
ganlikun	0:13413ea9a877	14	*
ganlikun	0:13413ea9a877	15	@verbatim
ganlikun	0:13413ea9a877	16	==============================================================================
ganlikun	0:13413ea9a877	17	##### FMC peripheral features #####
ganlikun	0:13413ea9a877	18	==============================================================================
ganlikun	0:13413ea9a877	19	[..] The Flexible memory controller (FMC) includes three memory controllers:
ganlikun	0:13413ea9a877	20	(+) The NOR/PSRAM memory controller
ganlikun	0:13413ea9a877	21	(+) The NAND/PC Card memory controller
ganlikun	0:13413ea9a877	22	(+) The Synchronous DRAM (SDRAM) controller
ganlikun	0:13413ea9a877	23
ganlikun	0:13413ea9a877	24	[..] The FMC functional block makes the interface with synchronous and asynchronous static
ganlikun	0:13413ea9a877	25	memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
ganlikun	0:13413ea9a877	26	(+) to translate AHB transactions into the appropriate external device protocol
ganlikun	0:13413ea9a877	27	(+) to meet the access time requirements of the external memory devices
ganlikun	0:13413ea9a877	28
ganlikun	0:13413ea9a877	29	[..] All external memories share the addresses, data and control signals with the controller.
ganlikun	0:13413ea9a877	30	Each external device is accessed by means of a unique Chip Select. The FMC performs
ganlikun	0:13413ea9a877	31	only one access at a time to an external device.
ganlikun	0:13413ea9a877	32	The main features of the FMC controller are the following:
ganlikun	0:13413ea9a877	33	(+) Interface with static-memory mapped devices including:
ganlikun	0:13413ea9a877	34	(++) Static random access memory (SRAM)
ganlikun	0:13413ea9a877	35	(++) Read-only memory (ROM)
ganlikun	0:13413ea9a877	36	(++) NOR Flash memory/OneNAND Flash memory
ganlikun	0:13413ea9a877	37	(++) PSRAM (4 memory banks)
ganlikun	0:13413ea9a877	38	(++) 16-bit PC Card compatible devices
ganlikun	0:13413ea9a877	39	(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
ganlikun	0:13413ea9a877	40	data
ganlikun	0:13413ea9a877	41	(+) Interface with synchronous DRAM (SDRAM) memories
ganlikun	0:13413ea9a877	42	(+) Independent Chip Select control for each memory bank
ganlikun	0:13413ea9a877	43	(+) Independent configuration for each memory bank
ganlikun	0:13413ea9a877	44
ganlikun	0:13413ea9a877	45	@endverbatim
ganlikun	0:13413ea9a877	46	******************************************************************************
ganlikun	0:13413ea9a877	47	* @attention
ganlikun	0:13413ea9a877	48	*
ganlikun	0:13413ea9a877	49	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	50	*
ganlikun	0:13413ea9a877	51	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	52	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	53	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	54	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	55	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	56	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	57	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	58	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	59	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	60	* without specific prior written permission.
ganlikun	0:13413ea9a877	61	*
ganlikun	0:13413ea9a877	62	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	63	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	64	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	65	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	66	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	67	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	68	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	69	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	70	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	71	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	72	*
ganlikun	0:13413ea9a877	73	******************************************************************************
ganlikun	0:13413ea9a877	74	*/
ganlikun	0:13413ea9a877	75
ganlikun	0:13413ea9a877	76	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	77	#include "stm32f4xx_hal.h"
ganlikun	0:13413ea9a877	78
ganlikun	0:13413ea9a877	79	/** @addtogroup STM32F4xx_HAL_Driver
ganlikun	0:13413ea9a877	80	* @{
ganlikun	0:13413ea9a877	81	*/
ganlikun	0:13413ea9a877	82
ganlikun	0:13413ea9a877	83	/** @defgroup FMC_LL FMC Low Layer
ganlikun	0:13413ea9a877	84	* @brief FMC driver modules
ganlikun	0:13413ea9a877	85	* @{
ganlikun	0:13413ea9a877	86	*/
ganlikun	0:13413ea9a877	87
ganlikun	0:13413ea9a877	88	#if defined (HAL_SRAM_MODULE_ENABLED) \|\| defined(HAL_NOR_MODULE_ENABLED) \|\| defined(HAL_NAND_MODULE_ENABLED) \|\| defined(HAL_PCCARD_MODULE_ENABLED) \|\| defined(HAL_SDRAM_MODULE_ENABLED)
ganlikun	0:13413ea9a877	89
ganlikun	0:13413ea9a877	90	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	91
ganlikun	0:13413ea9a877	92	/* Private typedef -----------------------------------------------------------*/
ganlikun	0:13413ea9a877	93	/* Private define ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	94	/* Private macro -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	95	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	96	/* Private function prototypes -----------------------------------------------*/
ganlikun	0:13413ea9a877	97	/* Private functions ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	98	/** @addtogroup FMC_LL_Private_Functions
ganlikun	0:13413ea9a877	99	* @{
ganlikun	0:13413ea9a877	100	*/
ganlikun	0:13413ea9a877	101
ganlikun	0:13413ea9a877	102	/** @addtogroup FMC_LL_NORSRAM
ganlikun	0:13413ea9a877	103	* @brief NORSRAM Controller functions
ganlikun	0:13413ea9a877	104	*
ganlikun	0:13413ea9a877	105	@verbatim
ganlikun	0:13413ea9a877	106	==============================================================================
ganlikun	0:13413ea9a877	107	##### How to use NORSRAM device driver #####
ganlikun	0:13413ea9a877	108	==============================================================================
ganlikun	0:13413ea9a877	109
ganlikun	0:13413ea9a877	110	[..]
ganlikun	0:13413ea9a877	111	This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
ganlikun	0:13413ea9a877	112	to run the NORSRAM external devices.
ganlikun	0:13413ea9a877	113
ganlikun	0:13413ea9a877	114	(+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
ganlikun	0:13413ea9a877	115	(+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
ganlikun	0:13413ea9a877	116	(+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
ganlikun	0:13413ea9a877	117	(+) FMC NORSRAM bank extended timing configuration using the function
ganlikun	0:13413ea9a877	118	FMC_NORSRAM_Extended_Timing_Init()
ganlikun	0:13413ea9a877	119	(+) FMC NORSRAM bank enable/disable write operation using the functions
ganlikun	0:13413ea9a877	120	FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
ganlikun	0:13413ea9a877	121
ganlikun	0:13413ea9a877	122
ganlikun	0:13413ea9a877	123	@endverbatim
ganlikun	0:13413ea9a877	124	* @{
ganlikun	0:13413ea9a877	125	*/
ganlikun	0:13413ea9a877	126
ganlikun	0:13413ea9a877	127	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
ganlikun	0:13413ea9a877	128	* @brief Initialization and Configuration functions
ganlikun	0:13413ea9a877	129	*
ganlikun	0:13413ea9a877	130	@verbatim
ganlikun	0:13413ea9a877	131	==============================================================================
ganlikun	0:13413ea9a877	132	##### Initialization and de_initialization functions #####
ganlikun	0:13413ea9a877	133	==============================================================================
ganlikun	0:13413ea9a877	134	[..]
ganlikun	0:13413ea9a877	135	This section provides functions allowing to:
ganlikun	0:13413ea9a877	136	(+) Initialize and configure the FMC NORSRAM interface
ganlikun	0:13413ea9a877	137	(+) De-initialize the FMC NORSRAM interface
ganlikun	0:13413ea9a877	138	(+) Configure the FMC clock and associated GPIOs
ganlikun	0:13413ea9a877	139
ganlikun	0:13413ea9a877	140	@endverbatim
ganlikun	0:13413ea9a877	141	* @{
ganlikun	0:13413ea9a877	142	*/
ganlikun	0:13413ea9a877	143
ganlikun	0:13413ea9a877	144	/**
ganlikun	0:13413ea9a877	145	* @brief Initialize the FMC_NORSRAM device according to the specified
ganlikun	0:13413ea9a877	146	* control parameters in the FMC_NORSRAM_InitTypeDef
ganlikun	0:13413ea9a877	147	* @param Device: Pointer to NORSRAM device instance
ganlikun	0:13413ea9a877	148	* @param Init: Pointer to NORSRAM Initialization structure
ganlikun	0:13413ea9a877	149	* @retval HAL status
ganlikun	0:13413ea9a877	150	*/
ganlikun	0:13413ea9a877	151	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init)
ganlikun	0:13413ea9a877	152	{
ganlikun	0:13413ea9a877	153	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	154
ganlikun	0:13413ea9a877	155	/* Check the parameters */
ganlikun	0:13413ea9a877	156	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	157	assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
ganlikun	0:13413ea9a877	158	assert_param(IS_FMC_MUX(Init->DataAddressMux));
ganlikun	0:13413ea9a877	159	assert_param(IS_FMC_MEMORY(Init->MemoryType));
ganlikun	0:13413ea9a877	160	assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
ganlikun	0:13413ea9a877	161	assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
ganlikun	0:13413ea9a877	162	assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
ganlikun	0:13413ea9a877	163	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	164	assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
ganlikun	0:13413ea9a877	165	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	166	assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
ganlikun	0:13413ea9a877	167	assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
ganlikun	0:13413ea9a877	168	assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
ganlikun	0:13413ea9a877	169	assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
ganlikun	0:13413ea9a877	170	assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
ganlikun	0:13413ea9a877	171	assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
ganlikun	0:13413ea9a877	172	assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
ganlikun	0:13413ea9a877	173	assert_param(IS_FMC_PAGESIZE(Init->PageSize));
ganlikun	0:13413ea9a877	174	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	175	assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
ganlikun	0:13413ea9a877	176	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	177
ganlikun	0:13413ea9a877	178	/* Get the BTCR register value */
ganlikun	0:13413ea9a877	179	tmpr = Device->BTCR[Init->NSBank];
ganlikun	0:13413ea9a877	180
ganlikun	0:13413ea9a877	181	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	182	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
ganlikun	0:13413ea9a877	183	WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */
ganlikun	0:13413ea9a877	184	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
ganlikun	0:13413ea9a877	185	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
ganlikun	0:13413ea9a877	186	FMC_BCR1_WAITPOL \| FMC_BCR1_WRAPMOD \| FMC_BCR1_WAITCFG \| \
ganlikun	0:13413ea9a877	187	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
ganlikun	0:13413ea9a877	188	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CPSIZE \| FMC_BCR1_CBURSTRW \| \
ganlikun	0:13413ea9a877	189	FMC_BCR1_CCLKEN));
ganlikun	0:13413ea9a877	190
ganlikun	0:13413ea9a877	191	/* Set NORSRAM device control parameters */
ganlikun	0:13413ea9a877	192	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
ganlikun	0:13413ea9a877	193	Init->MemoryType \|\
ganlikun	0:13413ea9a877	194	Init->MemoryDataWidth \|\
ganlikun	0:13413ea9a877	195	Init->BurstAccessMode \|\
ganlikun	0:13413ea9a877	196	Init->WaitSignalPolarity \|\
ganlikun	0:13413ea9a877	197	Init->WrapMode \|\
ganlikun	0:13413ea9a877	198	Init->WaitSignalActive \|\
ganlikun	0:13413ea9a877	199	Init->WriteOperation \|\
ganlikun	0:13413ea9a877	200	Init->WaitSignal \|\
ganlikun	0:13413ea9a877	201	Init->ExtendedMode \|\
ganlikun	0:13413ea9a877	202	Init->AsynchronousWait \|\
ganlikun	0:13413ea9a877	203	Init->PageSize \|\
ganlikun	0:13413ea9a877	204	Init->WriteBurst \|\
ganlikun	0:13413ea9a877	205	Init->ContinuousClock);
ganlikun	0:13413ea9a877	206	#else /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
ganlikun	0:13413ea9a877	207	/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
ganlikun	0:13413ea9a877	208	WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
ganlikun	0:13413ea9a877	209	tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN \| FMC_BCR1_MUXEN \| FMC_BCR1_MTYP \| \
ganlikun	0:13413ea9a877	210	FMC_BCR1_MWID \| FMC_BCR1_FACCEN \| FMC_BCR1_BURSTEN \| \
ganlikun	0:13413ea9a877	211	FMC_BCR1_WAITPOL \| FMC_BCR1_WAITCFG \| FMC_BCR1_CPSIZE \| \
ganlikun	0:13413ea9a877	212	FMC_BCR1_WREN \| FMC_BCR1_WAITEN \| FMC_BCR1_EXTMOD \| \
ganlikun	0:13413ea9a877	213	FMC_BCR1_ASYNCWAIT \| FMC_BCR1_CBURSTRW \| FMC_BCR1_CCLKEN \| \
ganlikun	0:13413ea9a877	214	FMC_BCR1_WFDIS));
ganlikun	0:13413ea9a877	215
ganlikun	0:13413ea9a877	216	/* Set NORSRAM device control parameters */
ganlikun	0:13413ea9a877	217	tmpr \|= (uint32_t)(Init->DataAddressMux \|\
ganlikun	0:13413ea9a877	218	Init->MemoryType \|\
ganlikun	0:13413ea9a877	219	Init->MemoryDataWidth \|\
ganlikun	0:13413ea9a877	220	Init->BurstAccessMode \|\
ganlikun	0:13413ea9a877	221	Init->WaitSignalPolarity \|\
ganlikun	0:13413ea9a877	222	Init->WaitSignalActive \|\
ganlikun	0:13413ea9a877	223	Init->WriteOperation \|\
ganlikun	0:13413ea9a877	224	Init->WaitSignal \|\
ganlikun	0:13413ea9a877	225	Init->ExtendedMode \|\
ganlikun	0:13413ea9a877	226	Init->AsynchronousWait \|\
ganlikun	0:13413ea9a877	227	Init->WriteBurst \|\
ganlikun	0:13413ea9a877	228	Init->ContinuousClock \|\
ganlikun	0:13413ea9a877	229	Init->PageSize \|\
ganlikun	0:13413ea9a877	230	Init->WriteFifo);
ganlikun	0:13413ea9a877	231	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
ganlikun	0:13413ea9a877	232
ganlikun	0:13413ea9a877	233	if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
ganlikun	0:13413ea9a877	234	{
ganlikun	0:13413ea9a877	235	tmpr \|= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
ganlikun	0:13413ea9a877	236	}
ganlikun	0:13413ea9a877	237
ganlikun	0:13413ea9a877	238	Device->BTCR[Init->NSBank] = tmpr;
ganlikun	0:13413ea9a877	239
ganlikun	0:13413ea9a877	240	/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
ganlikun	0:13413ea9a877	241	if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
ganlikun	0:13413ea9a877	242	{
ganlikun	0:13413ea9a877	243	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->ContinuousClock);
ganlikun	0:13413ea9a877	244	}
ganlikun	0:13413ea9a877	245
ganlikun	0:13413ea9a877	246	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	247	if(Init->NSBank != FMC_NORSRAM_BANK1)
ganlikun	0:13413ea9a877	248	{
ganlikun	0:13413ea9a877	249	Device->BTCR[FMC_NORSRAM_BANK1] \|= (uint32_t)(Init->WriteFifo);
ganlikun	0:13413ea9a877	250	}
ganlikun	0:13413ea9a877	251	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	252
ganlikun	0:13413ea9a877	253	return HAL_OK;
ganlikun	0:13413ea9a877	254	}
ganlikun	0:13413ea9a877	255
ganlikun	0:13413ea9a877	256	/**
ganlikun	0:13413ea9a877	257	* @brief DeInitialize the FMC_NORSRAM peripheral
ganlikun	0:13413ea9a877	258	* @param Device: Pointer to NORSRAM device instance
ganlikun	0:13413ea9a877	259	* @param ExDevice: Pointer to NORSRAM extended mode device instance
ganlikun	0:13413ea9a877	260	* @param Bank: NORSRAM bank number
ganlikun	0:13413ea9a877	261	* @retval HAL status
ganlikun	0:13413ea9a877	262	*/
ganlikun	0:13413ea9a877	263	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank)
ganlikun	0:13413ea9a877	264	{
ganlikun	0:13413ea9a877	265	/* Check the parameters */
ganlikun	0:13413ea9a877	266	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	267	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
ganlikun	0:13413ea9a877	268	assert_param(IS_FMC_NORSRAM_BANK(Bank));
ganlikun	0:13413ea9a877	269
ganlikun	0:13413ea9a877	270	/* Disable the FMC_NORSRAM device */
ganlikun	0:13413ea9a877	271	__FMC_NORSRAM_DISABLE(Device, Bank);
ganlikun	0:13413ea9a877	272
ganlikun	0:13413ea9a877	273	/* De-initialize the FMC_NORSRAM device */
ganlikun	0:13413ea9a877	274	/* FMC_NORSRAM_BANK1 */
ganlikun	0:13413ea9a877	275	if(Bank == FMC_NORSRAM_BANK1)
ganlikun	0:13413ea9a877	276	{
ganlikun	0:13413ea9a877	277	Device->BTCR[Bank] = 0x000030DBU;
ganlikun	0:13413ea9a877	278	}
ganlikun	0:13413ea9a877	279	/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
ganlikun	0:13413ea9a877	280	else
ganlikun	0:13413ea9a877	281	{
ganlikun	0:13413ea9a877	282	Device->BTCR[Bank] = 0x000030D2U;
ganlikun	0:13413ea9a877	283	}
ganlikun	0:13413ea9a877	284
ganlikun	0:13413ea9a877	285	Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
ganlikun	0:13413ea9a877	286	ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
ganlikun	0:13413ea9a877	287
ganlikun	0:13413ea9a877	288	return HAL_OK;
ganlikun	0:13413ea9a877	289	}
ganlikun	0:13413ea9a877	290
ganlikun	0:13413ea9a877	291	/**
ganlikun	0:13413ea9a877	292	* @brief Initialize the FMC_NORSRAM Timing according to the specified
ganlikun	0:13413ea9a877	293	* parameters in the FMC_NORSRAM_TimingTypeDef
ganlikun	0:13413ea9a877	294	* @param Device: Pointer to NORSRAM device instance
ganlikun	0:13413ea9a877	295	* @param Timing: Pointer to NORSRAM Timing structure
ganlikun	0:13413ea9a877	296	* @param Bank: NORSRAM bank number
ganlikun	0:13413ea9a877	297	* @retval HAL status
ganlikun	0:13413ea9a877	298	*/
ganlikun	0:13413ea9a877	299	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank)
ganlikun	0:13413ea9a877	300	{
ganlikun	0:13413ea9a877	301	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	302
ganlikun	0:13413ea9a877	303	/* Check the parameters */
ganlikun	0:13413ea9a877	304	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	305	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
ganlikun	0:13413ea9a877	306	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
ganlikun	0:13413ea9a877	307	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
ganlikun	0:13413ea9a877	308	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
ganlikun	0:13413ea9a877	309	assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
ganlikun	0:13413ea9a877	310	assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
ganlikun	0:13413ea9a877	311	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
ganlikun	0:13413ea9a877	312	assert_param(IS_FMC_NORSRAM_BANK(Bank));
ganlikun	0:13413ea9a877	313
ganlikun	0:13413ea9a877	314	/* Get the BTCR register value */
ganlikun	0:13413ea9a877	315	tmpr = Device->BTCR[Bank + 1U];
ganlikun	0:13413ea9a877	316
ganlikun	0:13413ea9a877	317	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
ganlikun	0:13413ea9a877	318	tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET \| FMC_BTR1_ADDHLD \| FMC_BTR1_DATAST \| \
ganlikun	0:13413ea9a877	319	FMC_BTR1_BUSTURN \| FMC_BTR1_CLKDIV \| FMC_BTR1_DATLAT \| \
ganlikun	0:13413ea9a877	320	FMC_BTR1_ACCMOD));
ganlikun	0:13413ea9a877	321
ganlikun	0:13413ea9a877	322	/* Set FMC_NORSRAM device timing parameters */
ganlikun	0:13413ea9a877	323	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
ganlikun	0:13413ea9a877	324	((Timing->AddressHoldTime) << 4U) \|\
ganlikun	0:13413ea9a877	325	((Timing->DataSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	326	((Timing->BusTurnAroundDuration) << 16U) \|\
ganlikun	0:13413ea9a877	327	(((Timing->CLKDivision) - 1U) << 20U) \|\
ganlikun	0:13413ea9a877	328	(((Timing->DataLatency) - 2U) << 24U) \|\
ganlikun	0:13413ea9a877	329	(Timing->AccessMode));
ganlikun	0:13413ea9a877	330
ganlikun	0:13413ea9a877	331	Device->BTCR[Bank + 1U] = tmpr;
ganlikun	0:13413ea9a877	332
ganlikun	0:13413ea9a877	333	/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
ganlikun	0:13413ea9a877	334	if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
ganlikun	0:13413ea9a877	335	{
ganlikun	0:13413ea9a877	336	tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
ganlikun	0:13413ea9a877	337	tmpr \|= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U);
ganlikun	0:13413ea9a877	338	Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr;
ganlikun	0:13413ea9a877	339	}
ganlikun	0:13413ea9a877	340
ganlikun	0:13413ea9a877	341	return HAL_OK;
ganlikun	0:13413ea9a877	342	}
ganlikun	0:13413ea9a877	343
ganlikun	0:13413ea9a877	344	/**
ganlikun	0:13413ea9a877	345	* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
ganlikun	0:13413ea9a877	346	* parameters in the FMC_NORSRAM_TimingTypeDef
ganlikun	0:13413ea9a877	347	* @param Device: Pointer to NORSRAM device instance
ganlikun	0:13413ea9a877	348	* @param Timing: Pointer to NORSRAM Timing structure
ganlikun	0:13413ea9a877	349	* @param Bank: NORSRAM bank number
ganlikun	0:13413ea9a877	350	* @retval HAL status
ganlikun	0:13413ea9a877	351	*/
ganlikun	0:13413ea9a877	352	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode)
ganlikun	0:13413ea9a877	353	{
ganlikun	0:13413ea9a877	354	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	355
ganlikun	0:13413ea9a877	356	/* Check the parameters */
ganlikun	0:13413ea9a877	357	assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
ganlikun	0:13413ea9a877	358
ganlikun	0:13413ea9a877	359	/* Set NORSRAM device timing register for write configuration, if extended mode is used */
ganlikun	0:13413ea9a877	360	if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
ganlikun	0:13413ea9a877	361	{
ganlikun	0:13413ea9a877	362	/* Check the parameters */
ganlikun	0:13413ea9a877	363	assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
ganlikun	0:13413ea9a877	364	assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
ganlikun	0:13413ea9a877	365	assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
ganlikun	0:13413ea9a877	366	assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
ganlikun	0:13413ea9a877	367	assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
ganlikun	0:13413ea9a877	368	assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
ganlikun	0:13413ea9a877	369	assert_param(IS_FMC_NORSRAM_BANK(Bank));
ganlikun	0:13413ea9a877	370
ganlikun	0:13413ea9a877	371	/* Get the BWTR register value */
ganlikun	0:13413ea9a877	372	tmpr = Device->BWTR[Bank];
ganlikun	0:13413ea9a877	373
ganlikun	0:13413ea9a877	374	/* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
ganlikun	0:13413ea9a877	375	tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET \| FMC_BWTR1_ADDHLD \| FMC_BWTR1_DATAST \| \
ganlikun	0:13413ea9a877	376	FMC_BWTR1_BUSTURN \| FMC_BWTR1_ACCMOD));
ganlikun	0:13413ea9a877	377
ganlikun	0:13413ea9a877	378	tmpr \|= (uint32_t)(Timing->AddressSetupTime \|\
ganlikun	0:13413ea9a877	379	((Timing->AddressHoldTime) << 4U) \|\
ganlikun	0:13413ea9a877	380	((Timing->DataSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	381	((Timing->BusTurnAroundDuration) << 16U) \|\
ganlikun	0:13413ea9a877	382	(Timing->AccessMode));
ganlikun	0:13413ea9a877	383
ganlikun	0:13413ea9a877	384	Device->BWTR[Bank] = tmpr;
ganlikun	0:13413ea9a877	385	}
ganlikun	0:13413ea9a877	386	else
ganlikun	0:13413ea9a877	387	{
ganlikun	0:13413ea9a877	388	Device->BWTR[Bank] = 0x0FFFFFFFU;
ganlikun	0:13413ea9a877	389	}
ganlikun	0:13413ea9a877	390
ganlikun	0:13413ea9a877	391	return HAL_OK;
ganlikun	0:13413ea9a877	392	}
ganlikun	0:13413ea9a877	393	/**
ganlikun	0:13413ea9a877	394	* @}
ganlikun	0:13413ea9a877	395	*/
ganlikun	0:13413ea9a877	396
ganlikun	0:13413ea9a877	397	/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
ganlikun	0:13413ea9a877	398	* @brief management functions
ganlikun	0:13413ea9a877	399	*
ganlikun	0:13413ea9a877	400	@verbatim
ganlikun	0:13413ea9a877	401	==============================================================================
ganlikun	0:13413ea9a877	402	##### FMC_NORSRAM Control functions #####
ganlikun	0:13413ea9a877	403	==============================================================================
ganlikun	0:13413ea9a877	404	[..]
ganlikun	0:13413ea9a877	405	This subsection provides a set of functions allowing to control dynamically
ganlikun	0:13413ea9a877	406	the FMC NORSRAM interface.
ganlikun	0:13413ea9a877	407
ganlikun	0:13413ea9a877	408	@endverbatim
ganlikun	0:13413ea9a877	409	* @{
ganlikun	0:13413ea9a877	410	*/
ganlikun	0:13413ea9a877	411	/**
ganlikun	0:13413ea9a877	412	* @brief Enables dynamically FMC_NORSRAM write operation.
ganlikun	0:13413ea9a877	413	* @param Device: Pointer to NORSRAM device instance
ganlikun	0:13413ea9a877	414	* @param Bank: NORSRAM bank number
ganlikun	0:13413ea9a877	415	* @retval HAL status
ganlikun	0:13413ea9a877	416	*/
ganlikun	0:13413ea9a877	417	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	418	{
ganlikun	0:13413ea9a877	419	/* Check the parameters */
ganlikun	0:13413ea9a877	420	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	421	assert_param(IS_FMC_NORSRAM_BANK(Bank));
ganlikun	0:13413ea9a877	422
ganlikun	0:13413ea9a877	423	/* Enable write operation */
ganlikun	0:13413ea9a877	424	Device->BTCR[Bank] \|= FMC_WRITE_OPERATION_ENABLE;
ganlikun	0:13413ea9a877	425
ganlikun	0:13413ea9a877	426	return HAL_OK;
ganlikun	0:13413ea9a877	427	}
ganlikun	0:13413ea9a877	428
ganlikun	0:13413ea9a877	429	/**
ganlikun	0:13413ea9a877	430	* @brief Disables dynamically FMC_NORSRAM write operation.
ganlikun	0:13413ea9a877	431	* @param Device: Pointer to NORSRAM device instance
ganlikun	0:13413ea9a877	432	* @param Bank: NORSRAM bank number
ganlikun	0:13413ea9a877	433	* @retval HAL status
ganlikun	0:13413ea9a877	434	*/
ganlikun	0:13413ea9a877	435	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	436	{
ganlikun	0:13413ea9a877	437	/* Check the parameters */
ganlikun	0:13413ea9a877	438	assert_param(IS_FMC_NORSRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	439	assert_param(IS_FMC_NORSRAM_BANK(Bank));
ganlikun	0:13413ea9a877	440
ganlikun	0:13413ea9a877	441	/* Disable write operation */
ganlikun	0:13413ea9a877	442	Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
ganlikun	0:13413ea9a877	443
ganlikun	0:13413ea9a877	444	return HAL_OK;
ganlikun	0:13413ea9a877	445	}
ganlikun	0:13413ea9a877	446
ganlikun	0:13413ea9a877	447	/**
ganlikun	0:13413ea9a877	448	* @}
ganlikun	0:13413ea9a877	449	*/
ganlikun	0:13413ea9a877	450
ganlikun	0:13413ea9a877	451	/**
ganlikun	0:13413ea9a877	452	* @}
ganlikun	0:13413ea9a877	453	*/
ganlikun	0:13413ea9a877	454
ganlikun	0:13413ea9a877	455	/** @addtogroup FMC_LL_NAND
ganlikun	0:13413ea9a877	456	* @brief NAND Controller functions
ganlikun	0:13413ea9a877	457	*
ganlikun	0:13413ea9a877	458	@verbatim
ganlikun	0:13413ea9a877	459	==============================================================================
ganlikun	0:13413ea9a877	460	##### How to use NAND device driver #####
ganlikun	0:13413ea9a877	461	==============================================================================
ganlikun	0:13413ea9a877	462	[..]
ganlikun	0:13413ea9a877	463	This driver contains a set of APIs to interface with the FMC NAND banks in order
ganlikun	0:13413ea9a877	464	to run the NAND external devices.
ganlikun	0:13413ea9a877	465
ganlikun	0:13413ea9a877	466	(+) FMC NAND bank reset using the function FMC_NAND_DeInit()
ganlikun	0:13413ea9a877	467	(+) FMC NAND bank control configuration using the function FMC_NAND_Init()
ganlikun	0:13413ea9a877	468	(+) FMC NAND bank common space timing configuration using the function
ganlikun	0:13413ea9a877	469	FMC_NAND_CommonSpace_Timing_Init()
ganlikun	0:13413ea9a877	470	(+) FMC NAND bank attribute space timing configuration using the function
ganlikun	0:13413ea9a877	471	FMC_NAND_AttributeSpace_Timing_Init()
ganlikun	0:13413ea9a877	472	(+) FMC NAND bank enable/disable ECC correction feature using the functions
ganlikun	0:13413ea9a877	473	FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
ganlikun	0:13413ea9a877	474	(+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
ganlikun	0:13413ea9a877	475
ganlikun	0:13413ea9a877	476	@endverbatim
ganlikun	0:13413ea9a877	477	* @{
ganlikun	0:13413ea9a877	478	*/
ganlikun	0:13413ea9a877	479
ganlikun	0:13413ea9a877	480	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	481	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
ganlikun	0:13413ea9a877	482	* @brief Initialization and Configuration functions
ganlikun	0:13413ea9a877	483	*
ganlikun	0:13413ea9a877	484	@verbatim
ganlikun	0:13413ea9a877	485	==============================================================================
ganlikun	0:13413ea9a877	486	##### Initialization and de_initialization functions #####
ganlikun	0:13413ea9a877	487	==============================================================================
ganlikun	0:13413ea9a877	488	[..]
ganlikun	0:13413ea9a877	489	This section provides functions allowing to:
ganlikun	0:13413ea9a877	490	(+) Initialize and configure the FMC NAND interface
ganlikun	0:13413ea9a877	491	(+) De-initialize the FMC NAND interface
ganlikun	0:13413ea9a877	492	(+) Configure the FMC clock and associated GPIOs
ganlikun	0:13413ea9a877	493
ganlikun	0:13413ea9a877	494	@endverbatim
ganlikun	0:13413ea9a877	495	* @{
ganlikun	0:13413ea9a877	496	*/
ganlikun	0:13413ea9a877	497
ganlikun	0:13413ea9a877	498	/**
ganlikun	0:13413ea9a877	499	* @brief Initializes the FMC_NAND device according to the specified
ganlikun	0:13413ea9a877	500	* control parameters in the FMC_NAND_HandleTypeDef
ganlikun	0:13413ea9a877	501	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	502	* @param Init: Pointer to NAND Initialization structure
ganlikun	0:13413ea9a877	503	* @retval HAL status
ganlikun	0:13413ea9a877	504	*/
ganlikun	0:13413ea9a877	505	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
ganlikun	0:13413ea9a877	506	{
ganlikun	0:13413ea9a877	507	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	508
ganlikun	0:13413ea9a877	509	/* Check the parameters */
ganlikun	0:13413ea9a877	510	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	511	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
ganlikun	0:13413ea9a877	512	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
ganlikun	0:13413ea9a877	513	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
ganlikun	0:13413ea9a877	514	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
ganlikun	0:13413ea9a877	515	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
ganlikun	0:13413ea9a877	516	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
ganlikun	0:13413ea9a877	517	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
ganlikun	0:13413ea9a877	518
ganlikun	0:13413ea9a877	519	/* Get the NAND bank register value */
ganlikun	0:13413ea9a877	520	tmpr = Device->PCR;
ganlikun	0:13413ea9a877	521
ganlikun	0:13413ea9a877	522	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
ganlikun	0:13413ea9a877	523	tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN \| FMC_PCR_PBKEN \| FMC_PCR_PTYP \| \
ganlikun	0:13413ea9a877	524	FMC_PCR_PWID \| FMC_PCR_ECCEN \| FMC_PCR_TCLR \| \
ganlikun	0:13413ea9a877	525	FMC_PCR_TAR \| FMC_PCR_ECCPS));
ganlikun	0:13413ea9a877	526
ganlikun	0:13413ea9a877	527	/* Set NAND device control parameters */
ganlikun	0:13413ea9a877	528	tmpr \|= (uint32_t)(Init->Waitfeature \|\
ganlikun	0:13413ea9a877	529	FMC_PCR_MEMORY_TYPE_NAND \|\
ganlikun	0:13413ea9a877	530	Init->MemoryDataWidth \|\
ganlikun	0:13413ea9a877	531	Init->EccComputation \|\
ganlikun	0:13413ea9a877	532	Init->ECCPageSize \|\
ganlikun	0:13413ea9a877	533	((Init->TCLRSetupTime) << 9U) \|\
ganlikun	0:13413ea9a877	534	((Init->TARSetupTime) << 13U));
ganlikun	0:13413ea9a877	535
ganlikun	0:13413ea9a877	536	/* NAND bank registers configuration */
ganlikun	0:13413ea9a877	537	Device->PCR = tmpr;
ganlikun	0:13413ea9a877	538
ganlikun	0:13413ea9a877	539	return HAL_OK;
ganlikun	0:13413ea9a877	540	}
ganlikun	0:13413ea9a877	541
ganlikun	0:13413ea9a877	542	/**
ganlikun	0:13413ea9a877	543	* @brief Initializes the FMC_NAND Common space Timing according to the specified
ganlikun	0:13413ea9a877	544	* parameters in the FMC_NAND_PCC_TimingTypeDef
ganlikun	0:13413ea9a877	545	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	546	* @param Timing: Pointer to NAND timing structure
ganlikun	0:13413ea9a877	547	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	548	* @retval HAL status
ganlikun	0:13413ea9a877	549	*/
ganlikun	0:13413ea9a877	550	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
ganlikun	0:13413ea9a877	551	{
ganlikun	0:13413ea9a877	552	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	553
ganlikun	0:13413ea9a877	554	/* Check the parameters */
ganlikun	0:13413ea9a877	555	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	556	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ganlikun	0:13413ea9a877	557	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ganlikun	0:13413ea9a877	558	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ganlikun	0:13413ea9a877	559	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ganlikun	0:13413ea9a877	560	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	561
ganlikun	0:13413ea9a877	562	/* Get the NAND bank 2 register value */
ganlikun	0:13413ea9a877	563	tmpr = Device->PMEM;
ganlikun	0:13413ea9a877	564
ganlikun	0:13413ea9a877	565
ganlikun	0:13413ea9a877	566	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
ganlikun	0:13413ea9a877	567	tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 \| FMC_PMEM_MEMWAIT2 \| FMC_PMEM_MEMHOLD2 \| \
ganlikun	0:13413ea9a877	568	FMC_PMEM_MEMHIZ2));
ganlikun	0:13413ea9a877	569
ganlikun	0:13413ea9a877	570	/* Set FMC_NAND device timing parameters */
ganlikun	0:13413ea9a877	571	tmpr \|= (uint32_t)(Timing->SetupTime \|\
ganlikun	0:13413ea9a877	572	((Timing->WaitSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	573	((Timing->HoldSetupTime) << 16U) \|\
ganlikun	0:13413ea9a877	574	((Timing->HiZSetupTime) << 24U)
ganlikun	0:13413ea9a877	575	);
ganlikun	0:13413ea9a877	576
ganlikun	0:13413ea9a877	577	/* NAND bank registers configuration */
ganlikun	0:13413ea9a877	578	Device->PMEM = tmpr;
ganlikun	0:13413ea9a877	579
ganlikun	0:13413ea9a877	580	return HAL_OK;
ganlikun	0:13413ea9a877	581	}
ganlikun	0:13413ea9a877	582
ganlikun	0:13413ea9a877	583	/**
ganlikun	0:13413ea9a877	584	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
ganlikun	0:13413ea9a877	585	* parameters in the FMC_NAND_PCC_TimingTypeDef
ganlikun	0:13413ea9a877	586	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	587	* @param Timing: Pointer to NAND timing structure
ganlikun	0:13413ea9a877	588	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	589	* @retval HAL status
ganlikun	0:13413ea9a877	590	*/
ganlikun	0:13413ea9a877	591	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
ganlikun	0:13413ea9a877	592	{
ganlikun	0:13413ea9a877	593	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	594
ganlikun	0:13413ea9a877	595	/* Check the parameters */
ganlikun	0:13413ea9a877	596	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	597	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ganlikun	0:13413ea9a877	598	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ganlikun	0:13413ea9a877	599	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ganlikun	0:13413ea9a877	600	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ganlikun	0:13413ea9a877	601	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	602
ganlikun	0:13413ea9a877	603	/* Get the NAND bank register value */
ganlikun	0:13413ea9a877	604	tmpr = Device->PATT;
ganlikun	0:13413ea9a877	605
ganlikun	0:13413ea9a877	606	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
ganlikun	0:13413ea9a877	607	tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 \| FMC_PATT_ATTWAIT2 \| FMC_PATT_ATTHOLD2 \| \
ganlikun	0:13413ea9a877	608	FMC_PATT_ATTHIZ2));
ganlikun	0:13413ea9a877	609
ganlikun	0:13413ea9a877	610	/* Set FMC_NAND device timing parameters */
ganlikun	0:13413ea9a877	611	tmpr \|= (uint32_t)(Timing->SetupTime \|\
ganlikun	0:13413ea9a877	612	((Timing->WaitSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	613	((Timing->HoldSetupTime) << 16U) \|\
ganlikun	0:13413ea9a877	614	((Timing->HiZSetupTime) << 24U));
ganlikun	0:13413ea9a877	615
ganlikun	0:13413ea9a877	616	/* NAND bank registers configuration */
ganlikun	0:13413ea9a877	617	Device->PATT = tmpr;
ganlikun	0:13413ea9a877	618
ganlikun	0:13413ea9a877	619	return HAL_OK;
ganlikun	0:13413ea9a877	620	}
ganlikun	0:13413ea9a877	621
ganlikun	0:13413ea9a877	622
ganlikun	0:13413ea9a877	623	/**
ganlikun	0:13413ea9a877	624	* @brief DeInitializes the FMC_NAND device
ganlikun	0:13413ea9a877	625	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	626	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	627	* @retval HAL status
ganlikun	0:13413ea9a877	628	*/
ganlikun	0:13413ea9a877	629	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	630	{
ganlikun	0:13413ea9a877	631	/* Check the parameters */
ganlikun	0:13413ea9a877	632	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	633	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	634
ganlikun	0:13413ea9a877	635	/* Disable the NAND Bank */
ganlikun	0:13413ea9a877	636	__FMC_NAND_DISABLE(Device, Bank);
ganlikun	0:13413ea9a877	637
ganlikun	0:13413ea9a877	638	/* De-initialize the NAND Bank */
ganlikun	0:13413ea9a877	639	/* Set the FMC_NAND_BANK registers to their reset values */
ganlikun	0:13413ea9a877	640	Device->PCR = 0x00000018U;
ganlikun	0:13413ea9a877	641	Device->SR = 0x00000040U;
ganlikun	0:13413ea9a877	642	Device->PMEM = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	643	Device->PATT = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	644
ganlikun	0:13413ea9a877	645	return HAL_OK;
ganlikun	0:13413ea9a877	646	}
ganlikun	0:13413ea9a877	647
ganlikun	0:13413ea9a877	648	/**
ganlikun	0:13413ea9a877	649	* @}
ganlikun	0:13413ea9a877	650	*/
ganlikun	0:13413ea9a877	651
ganlikun	0:13413ea9a877	652
ganlikun	0:13413ea9a877	653	/** @defgroup HAL_FMC_NAND_Group2 Control functions
ganlikun	0:13413ea9a877	654	* @brief management functions
ganlikun	0:13413ea9a877	655	*
ganlikun	0:13413ea9a877	656	@verbatim
ganlikun	0:13413ea9a877	657	==============================================================================
ganlikun	0:13413ea9a877	658	##### FMC_NAND Control functions #####
ganlikun	0:13413ea9a877	659	==============================================================================
ganlikun	0:13413ea9a877	660	[..]
ganlikun	0:13413ea9a877	661	This subsection provides a set of functions allowing to control dynamically
ganlikun	0:13413ea9a877	662	the FMC NAND interface.
ganlikun	0:13413ea9a877	663
ganlikun	0:13413ea9a877	664	@endverbatim
ganlikun	0:13413ea9a877	665	* @{
ganlikun	0:13413ea9a877	666	*/
ganlikun	0:13413ea9a877	667
ganlikun	0:13413ea9a877	668
ganlikun	0:13413ea9a877	669	/**
ganlikun	0:13413ea9a877	670	* @brief Enables dynamically FMC_NAND ECC feature.
ganlikun	0:13413ea9a877	671	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	672	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	673	* @retval HAL status
ganlikun	0:13413ea9a877	674	*/
ganlikun	0:13413ea9a877	675	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	676	{
ganlikun	0:13413ea9a877	677	/* Check the parameters */
ganlikun	0:13413ea9a877	678	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	679	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	680
ganlikun	0:13413ea9a877	681	/* Enable ECC feature */
ganlikun	0:13413ea9a877	682	Device->PCR \|= FMC_PCR_ECCEN;
ganlikun	0:13413ea9a877	683
ganlikun	0:13413ea9a877	684	return HAL_OK;
ganlikun	0:13413ea9a877	685	}
ganlikun	0:13413ea9a877	686
ganlikun	0:13413ea9a877	687
ganlikun	0:13413ea9a877	688	/**
ganlikun	0:13413ea9a877	689	* @brief Disables dynamically FMC_NAND ECC feature.
ganlikun	0:13413ea9a877	690	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	691	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	692	* @retval HAL status
ganlikun	0:13413ea9a877	693	*/
ganlikun	0:13413ea9a877	694	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	695	{
ganlikun	0:13413ea9a877	696	/* Check the parameters */
ganlikun	0:13413ea9a877	697	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	698	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	699
ganlikun	0:13413ea9a877	700	/* Disable ECC feature */
ganlikun	0:13413ea9a877	701	Device->PCR &= ~FMC_PCR_ECCEN;
ganlikun	0:13413ea9a877	702
ganlikun	0:13413ea9a877	703	return HAL_OK;
ganlikun	0:13413ea9a877	704	}
ganlikun	0:13413ea9a877	705
ganlikun	0:13413ea9a877	706	/**
ganlikun	0:13413ea9a877	707	* @brief Disables dynamically FMC_NAND ECC feature.
ganlikun	0:13413ea9a877	708	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	709	* @param ECCval: Pointer to ECC value
ganlikun	0:13413ea9a877	710	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	711	* @param Timeout: Timeout wait value
ganlikun	0:13413ea9a877	712	* @retval HAL status
ganlikun	0:13413ea9a877	713	*/
ganlikun	0:13413ea9a877	714	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
ganlikun	0:13413ea9a877	715	{
ganlikun	0:13413ea9a877	716	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	717
ganlikun	0:13413ea9a877	718	/* Check the parameters */
ganlikun	0:13413ea9a877	719	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	720	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	721
ganlikun	0:13413ea9a877	722	/* Get tick */
ganlikun	0:13413ea9a877	723	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	724
ganlikun	0:13413ea9a877	725	/* Wait until FIFO is empty */
ganlikun	0:13413ea9a877	726	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
ganlikun	0:13413ea9a877	727	{
ganlikun	0:13413ea9a877	728	/* Check for the Timeout */
ganlikun	0:13413ea9a877	729	if(Timeout != HAL_MAX_DELAY)
ganlikun	0:13413ea9a877	730	{
ganlikun	0:13413ea9a877	731	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
ganlikun	0:13413ea9a877	732	{
ganlikun	0:13413ea9a877	733	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	734	}
ganlikun	0:13413ea9a877	735	}
ganlikun	0:13413ea9a877	736	}
ganlikun	0:13413ea9a877	737
ganlikun	0:13413ea9a877	738	/* Get the ECCR register value */
ganlikun	0:13413ea9a877	739	*ECCval = (uint32_t)Device->ECCR;
ganlikun	0:13413ea9a877	740
ganlikun	0:13413ea9a877	741	return HAL_OK;
ganlikun	0:13413ea9a877	742	}
ganlikun	0:13413ea9a877	743
ganlikun	0:13413ea9a877	744	/**
ganlikun	0:13413ea9a877	745	* @}
ganlikun	0:13413ea9a877	746	*/
ganlikun	0:13413ea9a877	747
ganlikun	0:13413ea9a877	748	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
ganlikun	0:13413ea9a877	749	/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
ganlikun	0:13413ea9a877	750	* @brief Initialization and Configuration functions
ganlikun	0:13413ea9a877	751	*
ganlikun	0:13413ea9a877	752	@verbatim
ganlikun	0:13413ea9a877	753	==============================================================================
ganlikun	0:13413ea9a877	754	##### Initialization and de_initialization functions #####
ganlikun	0:13413ea9a877	755	==============================================================================
ganlikun	0:13413ea9a877	756	[..]
ganlikun	0:13413ea9a877	757	This section provides functions allowing to:
ganlikun	0:13413ea9a877	758	(+) Initialize and configure the FMC NAND interface
ganlikun	0:13413ea9a877	759	(+) De-initialize the FMC NAND interface
ganlikun	0:13413ea9a877	760	(+) Configure the FMC clock and associated GPIOs
ganlikun	0:13413ea9a877	761
ganlikun	0:13413ea9a877	762	@endverbatim
ganlikun	0:13413ea9a877	763	* @{
ganlikun	0:13413ea9a877	764	*/
ganlikun	0:13413ea9a877	765	/**
ganlikun	0:13413ea9a877	766	* @brief Initializes the FMC_NAND device according to the specified
ganlikun	0:13413ea9a877	767	* control parameters in the FMC_NAND_HandleTypeDef
ganlikun	0:13413ea9a877	768	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	769	* @param Init: Pointer to NAND Initialization structure
ganlikun	0:13413ea9a877	770	* @retval HAL status
ganlikun	0:13413ea9a877	771	*/
ganlikun	0:13413ea9a877	772	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)
ganlikun	0:13413ea9a877	773	{
ganlikun	0:13413ea9a877	774	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	775
ganlikun	0:13413ea9a877	776	/* Check the parameters */
ganlikun	0:13413ea9a877	777	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	778	assert_param(IS_FMC_NAND_BANK(Init->NandBank));
ganlikun	0:13413ea9a877	779	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
ganlikun	0:13413ea9a877	780	assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
ganlikun	0:13413ea9a877	781	assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
ganlikun	0:13413ea9a877	782	assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
ganlikun	0:13413ea9a877	783	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
ganlikun	0:13413ea9a877	784	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
ganlikun	0:13413ea9a877	785
ganlikun	0:13413ea9a877	786	if(Init->NandBank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	787	{
ganlikun	0:13413ea9a877	788	/* Get the NAND bank 2 register value */
ganlikun	0:13413ea9a877	789	tmpr = Device->PCR2;
ganlikun	0:13413ea9a877	790	}
ganlikun	0:13413ea9a877	791	else
ganlikun	0:13413ea9a877	792	{
ganlikun	0:13413ea9a877	793	/* Get the NAND bank 3 register value */
ganlikun	0:13413ea9a877	794	tmpr = Device->PCR3;
ganlikun	0:13413ea9a877	795	}
ganlikun	0:13413ea9a877	796
ganlikun	0:13413ea9a877	797	/* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
ganlikun	0:13413ea9a877	798	tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN \| FMC_PCR2_PBKEN \| FMC_PCR2_PTYP \| \
ganlikun	0:13413ea9a877	799	FMC_PCR2_PWID \| FMC_PCR2_ECCEN \| FMC_PCR2_TCLR \| \
ganlikun	0:13413ea9a877	800	FMC_PCR2_TAR \| FMC_PCR2_ECCPS));
ganlikun	0:13413ea9a877	801
ganlikun	0:13413ea9a877	802	/* Set NAND device control parameters */
ganlikun	0:13413ea9a877	803	tmpr \|= (uint32_t)(Init->Waitfeature \|\
ganlikun	0:13413ea9a877	804	FMC_PCR_MEMORY_TYPE_NAND \|\
ganlikun	0:13413ea9a877	805	Init->MemoryDataWidth \|\
ganlikun	0:13413ea9a877	806	Init->EccComputation \|\
ganlikun	0:13413ea9a877	807	Init->ECCPageSize \|\
ganlikun	0:13413ea9a877	808	((Init->TCLRSetupTime) << 9U) \|\
ganlikun	0:13413ea9a877	809	((Init->TARSetupTime) << 13U));
ganlikun	0:13413ea9a877	810
ganlikun	0:13413ea9a877	811	if(Init->NandBank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	812	{
ganlikun	0:13413ea9a877	813	/* NAND bank 2 registers configuration */
ganlikun	0:13413ea9a877	814	Device->PCR2 = tmpr;
ganlikun	0:13413ea9a877	815	}
ganlikun	0:13413ea9a877	816	else
ganlikun	0:13413ea9a877	817	{
ganlikun	0:13413ea9a877	818	/* NAND bank 3 registers configuration */
ganlikun	0:13413ea9a877	819	Device->PCR3 = tmpr;
ganlikun	0:13413ea9a877	820	}
ganlikun	0:13413ea9a877	821
ganlikun	0:13413ea9a877	822	return HAL_OK;
ganlikun	0:13413ea9a877	823
ganlikun	0:13413ea9a877	824	}
ganlikun	0:13413ea9a877	825
ganlikun	0:13413ea9a877	826	/**
ganlikun	0:13413ea9a877	827	* @brief Initializes the FMC_NAND Common space Timing according to the specified
ganlikun	0:13413ea9a877	828	* parameters in the FMC_NAND_PCC_TimingTypeDef
ganlikun	0:13413ea9a877	829	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	830	* @param Timing: Pointer to NAND timing structure
ganlikun	0:13413ea9a877	831	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	832	* @retval HAL status
ganlikun	0:13413ea9a877	833	*/
ganlikun	0:13413ea9a877	834	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
ganlikun	0:13413ea9a877	835	{
ganlikun	0:13413ea9a877	836	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	837
ganlikun	0:13413ea9a877	838	/* Check the parameters */
ganlikun	0:13413ea9a877	839	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	840	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ganlikun	0:13413ea9a877	841	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ganlikun	0:13413ea9a877	842	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ganlikun	0:13413ea9a877	843	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ganlikun	0:13413ea9a877	844	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	845
ganlikun	0:13413ea9a877	846	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	847	{
ganlikun	0:13413ea9a877	848	/* Get the NAND bank 2 register value */
ganlikun	0:13413ea9a877	849	tmpr = Device->PMEM2;
ganlikun	0:13413ea9a877	850	}
ganlikun	0:13413ea9a877	851	else
ganlikun	0:13413ea9a877	852	{
ganlikun	0:13413ea9a877	853	/* Get the NAND bank 3 register value */
ganlikun	0:13413ea9a877	854	tmpr = Device->PMEM3;
ganlikun	0:13413ea9a877	855	}
ganlikun	0:13413ea9a877	856
ganlikun	0:13413ea9a877	857	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
ganlikun	0:13413ea9a877	858	tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 \| FMC_PMEM2_MEMWAIT2 \| FMC_PMEM2_MEMHOLD2 \| \
ganlikun	0:13413ea9a877	859	FMC_PMEM2_MEMHIZ2));
ganlikun	0:13413ea9a877	860
ganlikun	0:13413ea9a877	861	/* Set FMC_NAND device timing parameters */
ganlikun	0:13413ea9a877	862	tmpr \|= (uint32_t)(Timing->SetupTime \|\
ganlikun	0:13413ea9a877	863	((Timing->WaitSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	864	((Timing->HoldSetupTime) << 16U) \|\
ganlikun	0:13413ea9a877	865	((Timing->HiZSetupTime) << 24U)
ganlikun	0:13413ea9a877	866	);
ganlikun	0:13413ea9a877	867
ganlikun	0:13413ea9a877	868	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	869	{
ganlikun	0:13413ea9a877	870	/* NAND bank 2 registers configuration */
ganlikun	0:13413ea9a877	871	Device->PMEM2 = tmpr;
ganlikun	0:13413ea9a877	872	}
ganlikun	0:13413ea9a877	873	else
ganlikun	0:13413ea9a877	874	{
ganlikun	0:13413ea9a877	875	/* NAND bank 3 registers configuration */
ganlikun	0:13413ea9a877	876	Device->PMEM3 = tmpr;
ganlikun	0:13413ea9a877	877	}
ganlikun	0:13413ea9a877	878
ganlikun	0:13413ea9a877	879	return HAL_OK;
ganlikun	0:13413ea9a877	880	}
ganlikun	0:13413ea9a877	881
ganlikun	0:13413ea9a877	882	/**
ganlikun	0:13413ea9a877	883	* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
ganlikun	0:13413ea9a877	884	* parameters in the FMC_NAND_PCC_TimingTypeDef
ganlikun	0:13413ea9a877	885	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	886	* @param Timing: Pointer to NAND timing structure
ganlikun	0:13413ea9a877	887	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	888	* @retval HAL status
ganlikun	0:13413ea9a877	889	*/
ganlikun	0:13413ea9a877	890	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)
ganlikun	0:13413ea9a877	891	{
ganlikun	0:13413ea9a877	892	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	893
ganlikun	0:13413ea9a877	894	/* Check the parameters */
ganlikun	0:13413ea9a877	895	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	896	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ganlikun	0:13413ea9a877	897	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ganlikun	0:13413ea9a877	898	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ganlikun	0:13413ea9a877	899	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ganlikun	0:13413ea9a877	900	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	901
ganlikun	0:13413ea9a877	902	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	903	{
ganlikun	0:13413ea9a877	904	/* Get the NAND bank 2 register value */
ganlikun	0:13413ea9a877	905	tmpr = Device->PATT2;
ganlikun	0:13413ea9a877	906	}
ganlikun	0:13413ea9a877	907	else
ganlikun	0:13413ea9a877	908	{
ganlikun	0:13413ea9a877	909	/* Get the NAND bank 3 register value */
ganlikun	0:13413ea9a877	910	tmpr = Device->PATT3;
ganlikun	0:13413ea9a877	911	}
ganlikun	0:13413ea9a877	912
ganlikun	0:13413ea9a877	913	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
ganlikun	0:13413ea9a877	914	tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 \| FMC_PATT2_ATTWAIT2 \| FMC_PATT2_ATTHOLD2 \| \
ganlikun	0:13413ea9a877	915	FMC_PATT2_ATTHIZ2));
ganlikun	0:13413ea9a877	916
ganlikun	0:13413ea9a877	917	/* Set FMC_NAND device timing parameters */
ganlikun	0:13413ea9a877	918	tmpr \|= (uint32_t)(Timing->SetupTime \|\
ganlikun	0:13413ea9a877	919	((Timing->WaitSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	920	((Timing->HoldSetupTime) << 16U) \|\
ganlikun	0:13413ea9a877	921	((Timing->HiZSetupTime) << 24U));
ganlikun	0:13413ea9a877	922
ganlikun	0:13413ea9a877	923	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	924	{
ganlikun	0:13413ea9a877	925	/* NAND bank 2 registers configuration */
ganlikun	0:13413ea9a877	926	Device->PATT2 = tmpr;
ganlikun	0:13413ea9a877	927	}
ganlikun	0:13413ea9a877	928	else
ganlikun	0:13413ea9a877	929	{
ganlikun	0:13413ea9a877	930	/* NAND bank 3 registers configuration */
ganlikun	0:13413ea9a877	931	Device->PATT3 = tmpr;
ganlikun	0:13413ea9a877	932	}
ganlikun	0:13413ea9a877	933
ganlikun	0:13413ea9a877	934	return HAL_OK;
ganlikun	0:13413ea9a877	935	}
ganlikun	0:13413ea9a877	936
ganlikun	0:13413ea9a877	937	/**
ganlikun	0:13413ea9a877	938	* @brief DeInitializes the FMC_NAND device
ganlikun	0:13413ea9a877	939	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	940	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	941	* @retval HAL status
ganlikun	0:13413ea9a877	942	*/
ganlikun	0:13413ea9a877	943	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	944	{
ganlikun	0:13413ea9a877	945	/* Check the parameters */
ganlikun	0:13413ea9a877	946	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	947	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	948
ganlikun	0:13413ea9a877	949	/* Disable the NAND Bank */
ganlikun	0:13413ea9a877	950	__FMC_NAND_DISABLE(Device, Bank);
ganlikun	0:13413ea9a877	951
ganlikun	0:13413ea9a877	952	/* De-initialize the NAND Bank */
ganlikun	0:13413ea9a877	953	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	954	{
ganlikun	0:13413ea9a877	955	/* Set the FMC_NAND_BANK2 registers to their reset values */
ganlikun	0:13413ea9a877	956	Device->PCR2 = 0x00000018U;
ganlikun	0:13413ea9a877	957	Device->SR2 = 0x00000040U;
ganlikun	0:13413ea9a877	958	Device->PMEM2 = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	959	Device->PATT2 = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	960	}
ganlikun	0:13413ea9a877	961	/* FMC_Bank3_NAND */
ganlikun	0:13413ea9a877	962	else
ganlikun	0:13413ea9a877	963	{
ganlikun	0:13413ea9a877	964	/* Set the FMC_NAND_BANK3 registers to their reset values */
ganlikun	0:13413ea9a877	965	Device->PCR3 = 0x00000018U;
ganlikun	0:13413ea9a877	966	Device->SR3 = 0x00000040U;
ganlikun	0:13413ea9a877	967	Device->PMEM3 = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	968	Device->PATT3 = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	969	}
ganlikun	0:13413ea9a877	970
ganlikun	0:13413ea9a877	971	return HAL_OK;
ganlikun	0:13413ea9a877	972	}
ganlikun	0:13413ea9a877	973
ganlikun	0:13413ea9a877	974	/**
ganlikun	0:13413ea9a877	975	* @}
ganlikun	0:13413ea9a877	976	*/
ganlikun	0:13413ea9a877	977
ganlikun	0:13413ea9a877	978	/** @addtogroup FMC_LL_NAND_Private_Functions_Group2
ganlikun	0:13413ea9a877	979	* @brief management functions
ganlikun	0:13413ea9a877	980	*
ganlikun	0:13413ea9a877	981	@verbatim
ganlikun	0:13413ea9a877	982	==============================================================================
ganlikun	0:13413ea9a877	983	##### FMC_NAND Control functions #####
ganlikun	0:13413ea9a877	984	==============================================================================
ganlikun	0:13413ea9a877	985	[..]
ganlikun	0:13413ea9a877	986	This subsection provides a set of functions allowing to control dynamically
ganlikun	0:13413ea9a877	987	the FMC NAND interface.
ganlikun	0:13413ea9a877	988
ganlikun	0:13413ea9a877	989	@endverbatim
ganlikun	0:13413ea9a877	990	* @{
ganlikun	0:13413ea9a877	991	*/
ganlikun	0:13413ea9a877	992	/**
ganlikun	0:13413ea9a877	993	* @brief Enables dynamically FMC_NAND ECC feature.
ganlikun	0:13413ea9a877	994	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	995	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	996	* @retval HAL status
ganlikun	0:13413ea9a877	997	*/
ganlikun	0:13413ea9a877	998	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	999	{
ganlikun	0:13413ea9a877	1000	/* Check the parameters */
ganlikun	0:13413ea9a877	1001	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	1002	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	1003
ganlikun	0:13413ea9a877	1004	/* Enable ECC feature */
ganlikun	0:13413ea9a877	1005	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	1006	{
ganlikun	0:13413ea9a877	1007	Device->PCR2 \|= FMC_PCR2_ECCEN;
ganlikun	0:13413ea9a877	1008	}
ganlikun	0:13413ea9a877	1009	else
ganlikun	0:13413ea9a877	1010	{
ganlikun	0:13413ea9a877	1011	Device->PCR3 \|= FMC_PCR3_ECCEN;
ganlikun	0:13413ea9a877	1012	}
ganlikun	0:13413ea9a877	1013
ganlikun	0:13413ea9a877	1014	return HAL_OK;
ganlikun	0:13413ea9a877	1015	}
ganlikun	0:13413ea9a877	1016
ganlikun	0:13413ea9a877	1017	/**
ganlikun	0:13413ea9a877	1018	* @brief Disables dynamically FMC_NAND ECC feature.
ganlikun	0:13413ea9a877	1019	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	1020	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	1021	* @retval HAL status
ganlikun	0:13413ea9a877	1022	*/
ganlikun	0:13413ea9a877	1023	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	1024	{
ganlikun	0:13413ea9a877	1025	/* Check the parameters */
ganlikun	0:13413ea9a877	1026	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	1027	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	1028
ganlikun	0:13413ea9a877	1029	/* Disable ECC feature */
ganlikun	0:13413ea9a877	1030	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	1031	{
ganlikun	0:13413ea9a877	1032	Device->PCR2 &= ~FMC_PCR2_ECCEN;
ganlikun	0:13413ea9a877	1033	}
ganlikun	0:13413ea9a877	1034	else
ganlikun	0:13413ea9a877	1035	{
ganlikun	0:13413ea9a877	1036	Device->PCR3 &= ~FMC_PCR3_ECCEN;
ganlikun	0:13413ea9a877	1037	}
ganlikun	0:13413ea9a877	1038
ganlikun	0:13413ea9a877	1039	return HAL_OK;
ganlikun	0:13413ea9a877	1040	}
ganlikun	0:13413ea9a877	1041
ganlikun	0:13413ea9a877	1042	/**
ganlikun	0:13413ea9a877	1043	* @brief Disables dynamically FMC_NAND ECC feature.
ganlikun	0:13413ea9a877	1044	* @param Device: Pointer to NAND device instance
ganlikun	0:13413ea9a877	1045	* @param ECCval: Pointer to ECC value
ganlikun	0:13413ea9a877	1046	* @param Bank: NAND bank number
ganlikun	0:13413ea9a877	1047	* @param Timeout: Timeout wait value
ganlikun	0:13413ea9a877	1048	* @retval HAL status
ganlikun	0:13413ea9a877	1049	*/
ganlikun	0:13413ea9a877	1050	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)
ganlikun	0:13413ea9a877	1051	{
ganlikun	0:13413ea9a877	1052	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	1053
ganlikun	0:13413ea9a877	1054	/* Check the parameters */
ganlikun	0:13413ea9a877	1055	assert_param(IS_FMC_NAND_DEVICE(Device));
ganlikun	0:13413ea9a877	1056	assert_param(IS_FMC_NAND_BANK(Bank));
ganlikun	0:13413ea9a877	1057
ganlikun	0:13413ea9a877	1058	/* Get tick */
ganlikun	0:13413ea9a877	1059	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	1060
ganlikun	0:13413ea9a877	1061	/* Wait until FIFO is empty */
ganlikun	0:13413ea9a877	1062	while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
ganlikun	0:13413ea9a877	1063	{
ganlikun	0:13413ea9a877	1064	/* Check for the Timeout */
ganlikun	0:13413ea9a877	1065	if(Timeout != HAL_MAX_DELAY)
ganlikun	0:13413ea9a877	1066	{
ganlikun	0:13413ea9a877	1067	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
ganlikun	0:13413ea9a877	1068	{
ganlikun	0:13413ea9a877	1069	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	1070	}
ganlikun	0:13413ea9a877	1071	}
ganlikun	0:13413ea9a877	1072	}
ganlikun	0:13413ea9a877	1073
ganlikun	0:13413ea9a877	1074	if(Bank == FMC_NAND_BANK2)
ganlikun	0:13413ea9a877	1075	{
ganlikun	0:13413ea9a877	1076	/* Get the ECCR2 register value */
ganlikun	0:13413ea9a877	1077	*ECCval = (uint32_t)Device->ECCR2;
ganlikun	0:13413ea9a877	1078	}
ganlikun	0:13413ea9a877	1079	else
ganlikun	0:13413ea9a877	1080	{
ganlikun	0:13413ea9a877	1081	/* Get the ECCR3 register value */
ganlikun	0:13413ea9a877	1082	*ECCval = (uint32_t)Device->ECCR3;
ganlikun	0:13413ea9a877	1083	}
ganlikun	0:13413ea9a877	1084
ganlikun	0:13413ea9a877	1085	return HAL_OK;
ganlikun	0:13413ea9a877	1086	}
ganlikun	0:13413ea9a877	1087
ganlikun	0:13413ea9a877	1088	/**
ganlikun	0:13413ea9a877	1089	* @}
ganlikun	0:13413ea9a877	1090	*/
ganlikun	0:13413ea9a877	1091
ganlikun	0:13413ea9a877	1092	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
ganlikun	0:13413ea9a877	1093	/**
ganlikun	0:13413ea9a877	1094	* @}
ganlikun	0:13413ea9a877	1095	*/
ganlikun	0:13413ea9a877	1096
ganlikun	0:13413ea9a877	1097	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	1098	/** @addtogroup FMC_LL_PCCARD
ganlikun	0:13413ea9a877	1099	* @brief PCCARD Controller functions
ganlikun	0:13413ea9a877	1100	*
ganlikun	0:13413ea9a877	1101	@verbatim
ganlikun	0:13413ea9a877	1102	==============================================================================
ganlikun	0:13413ea9a877	1103	##### How to use PCCARD device driver #####
ganlikun	0:13413ea9a877	1104	==============================================================================
ganlikun	0:13413ea9a877	1105	[..]
ganlikun	0:13413ea9a877	1106	This driver contains a set of APIs to interface with the FMC PCCARD bank in order
ganlikun	0:13413ea9a877	1107	to run the PCCARD/compact flash external devices.
ganlikun	0:13413ea9a877	1108
ganlikun	0:13413ea9a877	1109	(+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
ganlikun	0:13413ea9a877	1110	(+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
ganlikun	0:13413ea9a877	1111	(+) FMC PCCARD bank common space timing configuration using the function
ganlikun	0:13413ea9a877	1112	FMC_PCCARD_CommonSpace_Timing_Init()
ganlikun	0:13413ea9a877	1113	(+) FMC PCCARD bank attribute space timing configuration using the function
ganlikun	0:13413ea9a877	1114	FMC_PCCARD_AttributeSpace_Timing_Init()
ganlikun	0:13413ea9a877	1115	(+) FMC PCCARD bank IO space timing configuration using the function
ganlikun	0:13413ea9a877	1116	FMC_PCCARD_IOSpace_Timing_Init()
ganlikun	0:13413ea9a877	1117	@endverbatim
ganlikun	0:13413ea9a877	1118	* @{
ganlikun	0:13413ea9a877	1119	*/
ganlikun	0:13413ea9a877	1120
ganlikun	0:13413ea9a877	1121	/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
ganlikun	0:13413ea9a877	1122	* @brief Initialization and Configuration functions
ganlikun	0:13413ea9a877	1123	*
ganlikun	0:13413ea9a877	1124	@verbatim
ganlikun	0:13413ea9a877	1125	==============================================================================
ganlikun	0:13413ea9a877	1126	##### Initialization and de_initialization functions #####
ganlikun	0:13413ea9a877	1127	==============================================================================
ganlikun	0:13413ea9a877	1128	[..]
ganlikun	0:13413ea9a877	1129	This section provides functions allowing to:
ganlikun	0:13413ea9a877	1130	(+) Initialize and configure the FMC PCCARD interface
ganlikun	0:13413ea9a877	1131	(+) De-initialize the FMC PCCARD interface
ganlikun	0:13413ea9a877	1132	(+) Configure the FMC clock and associated GPIOs
ganlikun	0:13413ea9a877	1133
ganlikun	0:13413ea9a877	1134	@endverbatim
ganlikun	0:13413ea9a877	1135	* @{
ganlikun	0:13413ea9a877	1136	*/
ganlikun	0:13413ea9a877	1137
ganlikun	0:13413ea9a877	1138	/**
ganlikun	0:13413ea9a877	1139	* @brief Initializes the FMC_PCCARD device according to the specified
ganlikun	0:13413ea9a877	1140	* control parameters in the FMC_PCCARD_HandleTypeDef
ganlikun	0:13413ea9a877	1141	* @param Device: Pointer to PCCARD device instance
ganlikun	0:13413ea9a877	1142	* @param Init: Pointer to PCCARD Initialization structure
ganlikun	0:13413ea9a877	1143	* @retval HAL status
ganlikun	0:13413ea9a877	1144	*/
ganlikun	0:13413ea9a877	1145	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init)
ganlikun	0:13413ea9a877	1146	{
ganlikun	0:13413ea9a877	1147	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	1148
ganlikun	0:13413ea9a877	1149	/* Check the parameters */
ganlikun	0:13413ea9a877	1150	assert_param(IS_FMC_PCCARD_DEVICE(Device));
ganlikun	0:13413ea9a877	1151	assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
ganlikun	0:13413ea9a877	1152	assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
ganlikun	0:13413ea9a877	1153	assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
ganlikun	0:13413ea9a877	1154
ganlikun	0:13413ea9a877	1155	/* Get PCCARD control register value */
ganlikun	0:13413ea9a877	1156	tmpr = Device->PCR4;
ganlikun	0:13413ea9a877	1157
ganlikun	0:13413ea9a877	1158	/* Clear TAR, TCLR, PWAITEN and PWID bits */
ganlikun	0:13413ea9a877	1159	tmpr &= ((uint32_t)~(FMC_PCR4_TAR \| FMC_PCR4_TCLR \| FMC_PCR4_PWAITEN \| \
ganlikun	0:13413ea9a877	1160	FMC_PCR4_PWID));
ganlikun	0:13413ea9a877	1161
ganlikun	0:13413ea9a877	1162	/* Set FMC_PCCARD device control parameters */
ganlikun	0:13413ea9a877	1163	tmpr \|= (uint32_t)(Init->Waitfeature \|\
ganlikun	0:13413ea9a877	1164	FMC_NAND_PCC_MEM_BUS_WIDTH_16 \|\
ganlikun	0:13413ea9a877	1165	(Init->TCLRSetupTime << 9U) \|\
ganlikun	0:13413ea9a877	1166	(Init->TARSetupTime << 13U));
ganlikun	0:13413ea9a877	1167
ganlikun	0:13413ea9a877	1168	Device->PCR4 = tmpr;
ganlikun	0:13413ea9a877	1169
ganlikun	0:13413ea9a877	1170	return HAL_OK;
ganlikun	0:13413ea9a877	1171	}
ganlikun	0:13413ea9a877	1172
ganlikun	0:13413ea9a877	1173	/**
ganlikun	0:13413ea9a877	1174	* @brief Initializes the FMC_PCCARD Common space Timing according to the specified
ganlikun	0:13413ea9a877	1175	* parameters in the FMC_NAND_PCC_TimingTypeDef
ganlikun	0:13413ea9a877	1176	* @param Device: Pointer to PCCARD device instance
ganlikun	0:13413ea9a877	1177	* @param Timing: Pointer to PCCARD timing structure
ganlikun	0:13413ea9a877	1178	* @retval HAL status
ganlikun	0:13413ea9a877	1179	*/
ganlikun	0:13413ea9a877	1180	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
ganlikun	0:13413ea9a877	1181	{
ganlikun	0:13413ea9a877	1182	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	1183
ganlikun	0:13413ea9a877	1184	/* Check the parameters */
ganlikun	0:13413ea9a877	1185	assert_param(IS_FMC_PCCARD_DEVICE(Device));
ganlikun	0:13413ea9a877	1186	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ganlikun	0:13413ea9a877	1187	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ganlikun	0:13413ea9a877	1188	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ganlikun	0:13413ea9a877	1189	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ganlikun	0:13413ea9a877	1190
ganlikun	0:13413ea9a877	1191	/* Get PCCARD common space timing register value */
ganlikun	0:13413ea9a877	1192	tmpr = Device->PMEM4;
ganlikun	0:13413ea9a877	1193
ganlikun	0:13413ea9a877	1194	/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
ganlikun	0:13413ea9a877	1195	tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 \| FMC_PMEM4_MEMWAIT4 \| FMC_PMEM4_MEMHOLD4 \| \
ganlikun	0:13413ea9a877	1196	FMC_PMEM4_MEMHIZ4));
ganlikun	0:13413ea9a877	1197	/* Set PCCARD timing parameters */
ganlikun	0:13413ea9a877	1198	tmpr \|= (uint32_t)(Timing->SetupTime \|\
ganlikun	0:13413ea9a877	1199	((Timing->WaitSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	1200	((Timing->HoldSetupTime) << 16U) \|\
ganlikun	0:13413ea9a877	1201	((Timing->HiZSetupTime) << 24U));
ganlikun	0:13413ea9a877	1202
ganlikun	0:13413ea9a877	1203	Device->PMEM4 = tmpr;
ganlikun	0:13413ea9a877	1204
ganlikun	0:13413ea9a877	1205	return HAL_OK;
ganlikun	0:13413ea9a877	1206	}
ganlikun	0:13413ea9a877	1207
ganlikun	0:13413ea9a877	1208	/**
ganlikun	0:13413ea9a877	1209	* @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
ganlikun	0:13413ea9a877	1210	* parameters in the FMC_NAND_PCC_TimingTypeDef
ganlikun	0:13413ea9a877	1211	* @param Device: Pointer to PCCARD device instance
ganlikun	0:13413ea9a877	1212	* @param Timing: Pointer to PCCARD timing structure
ganlikun	0:13413ea9a877	1213	* @retval HAL status
ganlikun	0:13413ea9a877	1214	*/
ganlikun	0:13413ea9a877	1215	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
ganlikun	0:13413ea9a877	1216	{
ganlikun	0:13413ea9a877	1217	uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	1218
ganlikun	0:13413ea9a877	1219	/* Check the parameters */
ganlikun	0:13413ea9a877	1220	assert_param(IS_FMC_PCCARD_DEVICE(Device));
ganlikun	0:13413ea9a877	1221	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ganlikun	0:13413ea9a877	1222	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ganlikun	0:13413ea9a877	1223	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ganlikun	0:13413ea9a877	1224	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ganlikun	0:13413ea9a877	1225
ganlikun	0:13413ea9a877	1226	/* Get PCCARD timing parameters */
ganlikun	0:13413ea9a877	1227	tmpr = Device->PATT4;
ganlikun	0:13413ea9a877	1228
ganlikun	0:13413ea9a877	1229	/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
ganlikun	0:13413ea9a877	1230	tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 \| FMC_PATT4_ATTWAIT4 \| FMC_PATT4_ATTHOLD4 \| \
ganlikun	0:13413ea9a877	1231	FMC_PATT4_ATTHIZ4));
ganlikun	0:13413ea9a877	1232
ganlikun	0:13413ea9a877	1233	/* Set PCCARD timing parameters */
ganlikun	0:13413ea9a877	1234	tmpr \|= (uint32_t)(Timing->SetupTime \|\
ganlikun	0:13413ea9a877	1235	((Timing->WaitSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	1236	((Timing->HoldSetupTime) << 16U) \|\
ganlikun	0:13413ea9a877	1237	((Timing->HiZSetupTime) << 24U));
ganlikun	0:13413ea9a877	1238	Device->PATT4 = tmpr;
ganlikun	0:13413ea9a877	1239
ganlikun	0:13413ea9a877	1240	return HAL_OK;
ganlikun	0:13413ea9a877	1241	}
ganlikun	0:13413ea9a877	1242
ganlikun	0:13413ea9a877	1243	/**
ganlikun	0:13413ea9a877	1244	* @brief Initializes the FMC_PCCARD IO space Timing according to the specified
ganlikun	0:13413ea9a877	1245	* parameters in the FMC_NAND_PCC_TimingTypeDef
ganlikun	0:13413ea9a877	1246	* @param Device: Pointer to PCCARD device instance
ganlikun	0:13413ea9a877	1247	* @param Timing: Pointer to PCCARD timing structure
ganlikun	0:13413ea9a877	1248	* @retval HAL status
ganlikun	0:13413ea9a877	1249	*/
ganlikun	0:13413ea9a877	1250	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing)
ganlikun	0:13413ea9a877	1251	{
ganlikun	0:13413ea9a877	1252	uint32_t tmpr = 0;
ganlikun	0:13413ea9a877	1253
ganlikun	0:13413ea9a877	1254	/* Check the parameters */
ganlikun	0:13413ea9a877	1255	assert_param(IS_FMC_PCCARD_DEVICE(Device));
ganlikun	0:13413ea9a877	1256	assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
ganlikun	0:13413ea9a877	1257	assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
ganlikun	0:13413ea9a877	1258	assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
ganlikun	0:13413ea9a877	1259	assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
ganlikun	0:13413ea9a877	1260
ganlikun	0:13413ea9a877	1261	/* Get FMC_PCCARD device timing parameters */
ganlikun	0:13413ea9a877	1262	tmpr = Device->PIO4;
ganlikun	0:13413ea9a877	1263
ganlikun	0:13413ea9a877	1264	/* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
ganlikun	0:13413ea9a877	1265	tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 \| FMC_PIO4_IOWAIT4 \| FMC_PIO4_IOHOLD4 \| \
ganlikun	0:13413ea9a877	1266	FMC_PIO4_IOHIZ4));
ganlikun	0:13413ea9a877	1267
ganlikun	0:13413ea9a877	1268	/* Set FMC_PCCARD device timing parameters */
ganlikun	0:13413ea9a877	1269	tmpr \|= (uint32_t)(Timing->SetupTime \|\
ganlikun	0:13413ea9a877	1270	((Timing->WaitSetupTime) << 8U) \|\
ganlikun	0:13413ea9a877	1271	((Timing->HoldSetupTime) << 16U) \|\
ganlikun	0:13413ea9a877	1272	((Timing->HiZSetupTime) << 24U));
ganlikun	0:13413ea9a877	1273
ganlikun	0:13413ea9a877	1274	Device->PIO4 = tmpr;
ganlikun	0:13413ea9a877	1275
ganlikun	0:13413ea9a877	1276	return HAL_OK;
ganlikun	0:13413ea9a877	1277	}
ganlikun	0:13413ea9a877	1278
ganlikun	0:13413ea9a877	1279	/**
ganlikun	0:13413ea9a877	1280	* @brief DeInitializes the FMC_PCCARD device
ganlikun	0:13413ea9a877	1281	* @param Device: Pointer to PCCARD device instance
ganlikun	0:13413ea9a877	1282	* @retval HAL status
ganlikun	0:13413ea9a877	1283	*/
ganlikun	0:13413ea9a877	1284	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
ganlikun	0:13413ea9a877	1285	{
ganlikun	0:13413ea9a877	1286	/* Check the parameters */
ganlikun	0:13413ea9a877	1287	assert_param(IS_FMC_PCCARD_DEVICE(Device));
ganlikun	0:13413ea9a877	1288
ganlikun	0:13413ea9a877	1289	/* Disable the FMC_PCCARD device */
ganlikun	0:13413ea9a877	1290	__FMC_PCCARD_DISABLE(Device);
ganlikun	0:13413ea9a877	1291
ganlikun	0:13413ea9a877	1292	/* De-initialize the FMC_PCCARD device */
ganlikun	0:13413ea9a877	1293	Device->PCR4 = 0x00000018U;
ganlikun	0:13413ea9a877	1294	Device->SR4 = 0x00000000U;
ganlikun	0:13413ea9a877	1295	Device->PMEM4 = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	1296	Device->PATT4 = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	1297	Device->PIO4 = 0xFCFCFCFCU;
ganlikun	0:13413ea9a877	1298
ganlikun	0:13413ea9a877	1299	return HAL_OK;
ganlikun	0:13413ea9a877	1300	}
ganlikun	0:13413ea9a877	1301
ganlikun	0:13413ea9a877	1302	/**
ganlikun	0:13413ea9a877	1303	* @}
ganlikun	0:13413ea9a877	1304	*/
ganlikun	0:13413ea9a877	1305	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	1306
ganlikun	0:13413ea9a877	1307
ganlikun	0:13413ea9a877	1308	/** @addtogroup FMC_LL_SDRAM
ganlikun	0:13413ea9a877	1309	* @brief SDRAM Controller functions
ganlikun	0:13413ea9a877	1310	*
ganlikun	0:13413ea9a877	1311	@verbatim
ganlikun	0:13413ea9a877	1312	==============================================================================
ganlikun	0:13413ea9a877	1313	##### How to use SDRAM device driver #####
ganlikun	0:13413ea9a877	1314	==============================================================================
ganlikun	0:13413ea9a877	1315	[..]
ganlikun	0:13413ea9a877	1316	This driver contains a set of APIs to interface with the FMC SDRAM banks in order
ganlikun	0:13413ea9a877	1317	to run the SDRAM external devices.
ganlikun	0:13413ea9a877	1318
ganlikun	0:13413ea9a877	1319	(+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
ganlikun	0:13413ea9a877	1320	(+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
ganlikun	0:13413ea9a877	1321	(+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
ganlikun	0:13413ea9a877	1322	(+) FMC SDRAM bank enable/disable write operation using the functions
ganlikun	0:13413ea9a877	1323	FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
ganlikun	0:13413ea9a877	1324	(+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
ganlikun	0:13413ea9a877	1325
ganlikun	0:13413ea9a877	1326	@endverbatim
ganlikun	0:13413ea9a877	1327	* @{
ganlikun	0:13413ea9a877	1328	*/
ganlikun	0:13413ea9a877	1329
ganlikun	0:13413ea9a877	1330	/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
ganlikun	0:13413ea9a877	1331	* @brief Initialization and Configuration functions
ganlikun	0:13413ea9a877	1332	*
ganlikun	0:13413ea9a877	1333	@verbatim
ganlikun	0:13413ea9a877	1334	==============================================================================
ganlikun	0:13413ea9a877	1335	##### Initialization and de_initialization functions #####
ganlikun	0:13413ea9a877	1336	==============================================================================
ganlikun	0:13413ea9a877	1337	[..]
ganlikun	0:13413ea9a877	1338	This section provides functions allowing to:
ganlikun	0:13413ea9a877	1339	(+) Initialize and configure the FMC SDRAM interface
ganlikun	0:13413ea9a877	1340	(+) De-initialize the FMC SDRAM interface
ganlikun	0:13413ea9a877	1341	(+) Configure the FMC clock and associated GPIOs
ganlikun	0:13413ea9a877	1342
ganlikun	0:13413ea9a877	1343	@endverbatim
ganlikun	0:13413ea9a877	1344	* @{
ganlikun	0:13413ea9a877	1345	*/
ganlikun	0:13413ea9a877	1346
ganlikun	0:13413ea9a877	1347	/**
ganlikun	0:13413ea9a877	1348	* @brief Initializes the FMC_SDRAM device according to the specified
ganlikun	0:13413ea9a877	1349	* control parameters in the FMC_SDRAM_InitTypeDef
ganlikun	0:13413ea9a877	1350	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1351	* @param Init: Pointer to SDRAM Initialization structure
ganlikun	0:13413ea9a877	1352	* @retval HAL status
ganlikun	0:13413ea9a877	1353	*/
ganlikun	0:13413ea9a877	1354	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init)
ganlikun	0:13413ea9a877	1355	{
ganlikun	0:13413ea9a877	1356	uint32_t tmpr1 = 0U;
ganlikun	0:13413ea9a877	1357	uint32_t tmpr2 = 0U;
ganlikun	0:13413ea9a877	1358
ganlikun	0:13413ea9a877	1359	/* Check the parameters */
ganlikun	0:13413ea9a877	1360	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1361	assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
ganlikun	0:13413ea9a877	1362	assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
ganlikun	0:13413ea9a877	1363	assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
ganlikun	0:13413ea9a877	1364	assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
ganlikun	0:13413ea9a877	1365	assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
ganlikun	0:13413ea9a877	1366	assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
ganlikun	0:13413ea9a877	1367	assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
ganlikun	0:13413ea9a877	1368	assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
ganlikun	0:13413ea9a877	1369	assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
ganlikun	0:13413ea9a877	1370	assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
ganlikun	0:13413ea9a877	1371
ganlikun	0:13413ea9a877	1372	/* Set SDRAM bank configuration parameters */
ganlikun	0:13413ea9a877	1373	if (Init->SDBank != FMC_SDRAM_BANK2)
ganlikun	0:13413ea9a877	1374	{
ganlikun	0:13413ea9a877	1375	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
ganlikun	0:13413ea9a877	1376
ganlikun	0:13413ea9a877	1377	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
ganlikun	0:13413ea9a877	1378	tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
ganlikun	0:13413ea9a877	1379	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
ganlikun	0:13413ea9a877	1380	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
ganlikun	0:13413ea9a877	1381
ganlikun	0:13413ea9a877	1382
ganlikun	0:13413ea9a877	1383	tmpr1 \|= (uint32_t)(Init->ColumnBitsNumber \|\
ganlikun	0:13413ea9a877	1384	Init->RowBitsNumber \|\
ganlikun	0:13413ea9a877	1385	Init->MemoryDataWidth \|\
ganlikun	0:13413ea9a877	1386	Init->InternalBankNumber \|\
ganlikun	0:13413ea9a877	1387	Init->CASLatency \|\
ganlikun	0:13413ea9a877	1388	Init->WriteProtection \|\
ganlikun	0:13413ea9a877	1389	Init->SDClockPeriod \|\
ganlikun	0:13413ea9a877	1390	Init->ReadBurst \|\
ganlikun	0:13413ea9a877	1391	Init->ReadPipeDelay
ganlikun	0:13413ea9a877	1392	);
ganlikun	0:13413ea9a877	1393	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
ganlikun	0:13413ea9a877	1394	}
ganlikun	0:13413ea9a877	1395	else /* FMC_Bank2_SDRAM */
ganlikun	0:13413ea9a877	1396	{
ganlikun	0:13413ea9a877	1397	tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
ganlikun	0:13413ea9a877	1398
ganlikun	0:13413ea9a877	1399	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
ganlikun	0:13413ea9a877	1400	tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
ganlikun	0:13413ea9a877	1401
ganlikun	0:13413ea9a877	1402	tmpr1 \|= (uint32_t)(Init->SDClockPeriod \|\
ganlikun	0:13413ea9a877	1403	Init->ReadBurst \|\
ganlikun	0:13413ea9a877	1404	Init->ReadPipeDelay);
ganlikun	0:13413ea9a877	1405
ganlikun	0:13413ea9a877	1406	tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
ganlikun	0:13413ea9a877	1407
ganlikun	0:13413ea9a877	1408	/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
ganlikun	0:13413ea9a877	1409	tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC \| FMC_SDCR1_NR \| FMC_SDCR1_MWID \| \
ganlikun	0:13413ea9a877	1410	FMC_SDCR1_NB \| FMC_SDCR1_CAS \| FMC_SDCR1_WP \| \
ganlikun	0:13413ea9a877	1411	FMC_SDCR1_SDCLK \| FMC_SDCR1_RBURST \| FMC_SDCR1_RPIPE));
ganlikun	0:13413ea9a877	1412
ganlikun	0:13413ea9a877	1413	tmpr2 \|= (uint32_t)(Init->ColumnBitsNumber \|\
ganlikun	0:13413ea9a877	1414	Init->RowBitsNumber \|\
ganlikun	0:13413ea9a877	1415	Init->MemoryDataWidth \|\
ganlikun	0:13413ea9a877	1416	Init->InternalBankNumber \|\
ganlikun	0:13413ea9a877	1417	Init->CASLatency \|\
ganlikun	0:13413ea9a877	1418	Init->WriteProtection);
ganlikun	0:13413ea9a877	1419
ganlikun	0:13413ea9a877	1420	Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
ganlikun	0:13413ea9a877	1421	Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
ganlikun	0:13413ea9a877	1422	}
ganlikun	0:13413ea9a877	1423
ganlikun	0:13413ea9a877	1424	return HAL_OK;
ganlikun	0:13413ea9a877	1425	}
ganlikun	0:13413ea9a877	1426
ganlikun	0:13413ea9a877	1427	/**
ganlikun	0:13413ea9a877	1428	* @brief Initializes the FMC_SDRAM device timing according to the specified
ganlikun	0:13413ea9a877	1429	* parameters in the FMC_SDRAM_TimingTypeDef
ganlikun	0:13413ea9a877	1430	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1431	* @param Timing: Pointer to SDRAM Timing structure
ganlikun	0:13413ea9a877	1432	* @param Bank: SDRAM bank number
ganlikun	0:13413ea9a877	1433	* @retval HAL status
ganlikun	0:13413ea9a877	1434	*/
ganlikun	0:13413ea9a877	1435	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank)
ganlikun	0:13413ea9a877	1436	{
ganlikun	0:13413ea9a877	1437	uint32_t tmpr1 = 0U;
ganlikun	0:13413ea9a877	1438	uint32_t tmpr2 = 0U;
ganlikun	0:13413ea9a877	1439
ganlikun	0:13413ea9a877	1440	/* Check the parameters */
ganlikun	0:13413ea9a877	1441	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1442	assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
ganlikun	0:13413ea9a877	1443	assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
ganlikun	0:13413ea9a877	1444	assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
ganlikun	0:13413ea9a877	1445	assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
ganlikun	0:13413ea9a877	1446	assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
ganlikun	0:13413ea9a877	1447	assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
ganlikun	0:13413ea9a877	1448	assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
ganlikun	0:13413ea9a877	1449	assert_param(IS_FMC_SDRAM_BANK(Bank));
ganlikun	0:13413ea9a877	1450
ganlikun	0:13413ea9a877	1451	/* Set SDRAM device timing parameters */
ganlikun	0:13413ea9a877	1452	if (Bank != FMC_SDRAM_BANK2)
ganlikun	0:13413ea9a877	1453	{
ganlikun	0:13413ea9a877	1454	tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
ganlikun	0:13413ea9a877	1455
ganlikun	0:13413ea9a877	1456	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
ganlikun	0:13413ea9a877	1457	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
ganlikun	0:13413ea9a877	1458	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
ganlikun	0:13413ea9a877	1459	FMC_SDTR1_TRCD));
ganlikun	0:13413ea9a877	1460
ganlikun	0:13413ea9a877	1461	tmpr1 \|= (uint32_t)(((Timing->LoadToActiveDelay)-1U) \|\
ganlikun	0:13413ea9a877	1462	(((Timing->ExitSelfRefreshDelay)-1U) << 4U) \|\
ganlikun	0:13413ea9a877	1463	(((Timing->SelfRefreshTime)-1U) << 8U) \|\
ganlikun	0:13413ea9a877	1464	(((Timing->RowCycleDelay)-1U) << 12U) \|\
ganlikun	0:13413ea9a877	1465	(((Timing->WriteRecoveryTime)-1U) <<16U) \|\
ganlikun	0:13413ea9a877	1466	(((Timing->RPDelay)-1U) << 20U) \|\
ganlikun	0:13413ea9a877	1467	(((Timing->RCDDelay)-1U) << 24U));
ganlikun	0:13413ea9a877	1468	Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
ganlikun	0:13413ea9a877	1469	}
ganlikun	0:13413ea9a877	1470	else /* FMC_Bank2_SDRAM */
ganlikun	0:13413ea9a877	1471	{
ganlikun	0:13413ea9a877	1472	tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
ganlikun	0:13413ea9a877	1473
ganlikun	0:13413ea9a877	1474	/* Clear TRC and TRP bits */
ganlikun	0:13413ea9a877	1475	tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC \| FMC_SDTR1_TRP));
ganlikun	0:13413ea9a877	1476
ganlikun	0:13413ea9a877	1477	tmpr1 \|= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) \|\
ganlikun	0:13413ea9a877	1478	(((Timing->RPDelay)-1U) << 20U));
ganlikun	0:13413ea9a877	1479
ganlikun	0:13413ea9a877	1480	tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
ganlikun	0:13413ea9a877	1481
ganlikun	0:13413ea9a877	1482	/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
ganlikun	0:13413ea9a877	1483	tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD \| FMC_SDTR1_TXSR \| FMC_SDTR1_TRAS \| \
ganlikun	0:13413ea9a877	1484	FMC_SDTR1_TRC \| FMC_SDTR1_TWR \| FMC_SDTR1_TRP \| \
ganlikun	0:13413ea9a877	1485	FMC_SDTR1_TRCD));
ganlikun	0:13413ea9a877	1486
ganlikun	0:13413ea9a877	1487	tmpr2 \|= (uint32_t)((((Timing->LoadToActiveDelay)-1U) \|\
ganlikun	0:13413ea9a877	1488	(((Timing->ExitSelfRefreshDelay)-1U) << 4U) \|\
ganlikun	0:13413ea9a877	1489	(((Timing->SelfRefreshTime)-1U) << 8U) \|\
ganlikun	0:13413ea9a877	1490	(((Timing->WriteRecoveryTime)-1U) <<16U) \|\
ganlikun	0:13413ea9a877	1491	(((Timing->RCDDelay)-1U) << 24U)));
ganlikun	0:13413ea9a877	1492
ganlikun	0:13413ea9a877	1493	Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
ganlikun	0:13413ea9a877	1494	Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
ganlikun	0:13413ea9a877	1495	}
ganlikun	0:13413ea9a877	1496	return HAL_OK;
ganlikun	0:13413ea9a877	1497	}
ganlikun	0:13413ea9a877	1498
ganlikun	0:13413ea9a877	1499	/**
ganlikun	0:13413ea9a877	1500	* @brief DeInitializes the FMC_SDRAM peripheral
ganlikun	0:13413ea9a877	1501	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1502	* @retval HAL status
ganlikun	0:13413ea9a877	1503	*/
ganlikun	0:13413ea9a877	1504	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	1505	{
ganlikun	0:13413ea9a877	1506	/* Check the parameters */
ganlikun	0:13413ea9a877	1507	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1508	assert_param(IS_FMC_SDRAM_BANK(Bank));
ganlikun	0:13413ea9a877	1509
ganlikun	0:13413ea9a877	1510	/* De-initialize the SDRAM device */
ganlikun	0:13413ea9a877	1511	Device->SDCR[Bank] = 0x000002D0U;
ganlikun	0:13413ea9a877	1512	Device->SDTR[Bank] = 0x0FFFFFFFU;
ganlikun	0:13413ea9a877	1513	Device->SDCMR = 0x00000000U;
ganlikun	0:13413ea9a877	1514	Device->SDRTR = 0x00000000U;
ganlikun	0:13413ea9a877	1515	Device->SDSR = 0x00000000U;
ganlikun	0:13413ea9a877	1516
ganlikun	0:13413ea9a877	1517	return HAL_OK;
ganlikun	0:13413ea9a877	1518	}
ganlikun	0:13413ea9a877	1519
ganlikun	0:13413ea9a877	1520	/**
ganlikun	0:13413ea9a877	1521	* @}
ganlikun	0:13413ea9a877	1522	*/
ganlikun	0:13413ea9a877	1523
ganlikun	0:13413ea9a877	1524	/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
ganlikun	0:13413ea9a877	1525	* @brief management functions
ganlikun	0:13413ea9a877	1526	*
ganlikun	0:13413ea9a877	1527	@verbatim
ganlikun	0:13413ea9a877	1528	==============================================================================
ganlikun	0:13413ea9a877	1529	##### FMC_SDRAM Control functions #####
ganlikun	0:13413ea9a877	1530	==============================================================================
ganlikun	0:13413ea9a877	1531	[..]
ganlikun	0:13413ea9a877	1532	This subsection provides a set of functions allowing to control dynamically
ganlikun	0:13413ea9a877	1533	the FMC SDRAM interface.
ganlikun	0:13413ea9a877	1534
ganlikun	0:13413ea9a877	1535	@endverbatim
ganlikun	0:13413ea9a877	1536	* @{
ganlikun	0:13413ea9a877	1537	*/
ganlikun	0:13413ea9a877	1538	/**
ganlikun	0:13413ea9a877	1539	* @brief Enables dynamically FMC_SDRAM write protection.
ganlikun	0:13413ea9a877	1540	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1541	* @param Bank: SDRAM bank number
ganlikun	0:13413ea9a877	1542	* @retval HAL status
ganlikun	0:13413ea9a877	1543	*/
ganlikun	0:13413ea9a877	1544	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	1545	{
ganlikun	0:13413ea9a877	1546	/* Check the parameters */
ganlikun	0:13413ea9a877	1547	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1548	assert_param(IS_FMC_SDRAM_BANK(Bank));
ganlikun	0:13413ea9a877	1549
ganlikun	0:13413ea9a877	1550	/* Enable write protection */
ganlikun	0:13413ea9a877	1551	Device->SDCR[Bank] \|= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
ganlikun	0:13413ea9a877	1552
ganlikun	0:13413ea9a877	1553	return HAL_OK;
ganlikun	0:13413ea9a877	1554	}
ganlikun	0:13413ea9a877	1555
ganlikun	0:13413ea9a877	1556	/**
ganlikun	0:13413ea9a877	1557	* @brief Disables dynamically FMC_SDRAM write protection.
ganlikun	0:13413ea9a877	1558	* @param hsdram: FMC_SDRAM handle
ganlikun	0:13413ea9a877	1559	* @retval HAL status
ganlikun	0:13413ea9a877	1560	*/
ganlikun	0:13413ea9a877	1561	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	1562	{
ganlikun	0:13413ea9a877	1563	/* Check the parameters */
ganlikun	0:13413ea9a877	1564	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1565	assert_param(IS_FMC_SDRAM_BANK(Bank));
ganlikun	0:13413ea9a877	1566
ganlikun	0:13413ea9a877	1567	/* Disable write protection */
ganlikun	0:13413ea9a877	1568	Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
ganlikun	0:13413ea9a877	1569
ganlikun	0:13413ea9a877	1570	return HAL_OK;
ganlikun	0:13413ea9a877	1571	}
ganlikun	0:13413ea9a877	1572
ganlikun	0:13413ea9a877	1573	/**
ganlikun	0:13413ea9a877	1574	* @brief Send Command to the FMC SDRAM bank
ganlikun	0:13413ea9a877	1575	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1576	* @param Command: Pointer to SDRAM command structure
ganlikun	0:13413ea9a877	1577	* @param Timing: Pointer to SDRAM Timing structure
ganlikun	0:13413ea9a877	1578	* @param Timeout: Timeout wait value
ganlikun	0:13413ea9a877	1579	* @retval HAL state
ganlikun	0:13413ea9a877	1580	*/
ganlikun	0:13413ea9a877	1581	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout)
ganlikun	0:13413ea9a877	1582	{
ganlikun	0:13413ea9a877	1583	__IO uint32_t tmpr = 0U;
ganlikun	0:13413ea9a877	1584	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	1585
ganlikun	0:13413ea9a877	1586	/* Check the parameters */
ganlikun	0:13413ea9a877	1587	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1588	assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
ganlikun	0:13413ea9a877	1589	assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
ganlikun	0:13413ea9a877	1590	assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
ganlikun	0:13413ea9a877	1591	assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
ganlikun	0:13413ea9a877	1592
ganlikun	0:13413ea9a877	1593	/* Set command register */
ganlikun	0:13413ea9a877	1594	tmpr = (uint32_t)((Command->CommandMode) \|\
ganlikun	0:13413ea9a877	1595	(Command->CommandTarget) \|\
ganlikun	0:13413ea9a877	1596	(((Command->AutoRefreshNumber)-1U) << 5U) \|\
ganlikun	0:13413ea9a877	1597	((Command->ModeRegisterDefinition) << 9U)
ganlikun	0:13413ea9a877	1598	);
ganlikun	0:13413ea9a877	1599
ganlikun	0:13413ea9a877	1600	Device->SDCMR = tmpr;
ganlikun	0:13413ea9a877	1601
ganlikun	0:13413ea9a877	1602	/* Get tick */
ganlikun	0:13413ea9a877	1603	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	1604
ganlikun	0:13413ea9a877	1605	/* Wait until command is send */
ganlikun	0:13413ea9a877	1606	while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
ganlikun	0:13413ea9a877	1607	{
ganlikun	0:13413ea9a877	1608	/* Check for the Timeout */
ganlikun	0:13413ea9a877	1609	if(Timeout != HAL_MAX_DELAY)
ganlikun	0:13413ea9a877	1610	{
ganlikun	0:13413ea9a877	1611	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
ganlikun	0:13413ea9a877	1612	{
ganlikun	0:13413ea9a877	1613	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	1614	}
ganlikun	0:13413ea9a877	1615	}
ganlikun	0:13413ea9a877	1616	}
ganlikun	0:13413ea9a877	1617
ganlikun	0:13413ea9a877	1618	return HAL_OK;
ganlikun	0:13413ea9a877	1619	}
ganlikun	0:13413ea9a877	1620
ganlikun	0:13413ea9a877	1621	/**
ganlikun	0:13413ea9a877	1622	* @brief Program the SDRAM Memory Refresh rate.
ganlikun	0:13413ea9a877	1623	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1624	* @param RefreshRate: The SDRAM refresh rate value.
ganlikun	0:13413ea9a877	1625	* @retval HAL state
ganlikun	0:13413ea9a877	1626	*/
ganlikun	0:13413ea9a877	1627	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
ganlikun	0:13413ea9a877	1628	{
ganlikun	0:13413ea9a877	1629	/* Check the parameters */
ganlikun	0:13413ea9a877	1630	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1631	assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
ganlikun	0:13413ea9a877	1632
ganlikun	0:13413ea9a877	1633	/* Set the refresh rate in command register */
ganlikun	0:13413ea9a877	1634	Device->SDRTR \|= (RefreshRate<<1U);
ganlikun	0:13413ea9a877	1635
ganlikun	0:13413ea9a877	1636	return HAL_OK;
ganlikun	0:13413ea9a877	1637	}
ganlikun	0:13413ea9a877	1638
ganlikun	0:13413ea9a877	1639	/**
ganlikun	0:13413ea9a877	1640	* @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
ganlikun	0:13413ea9a877	1641	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1642	* @param AutoRefreshNumber: Specifies the auto Refresh number.
ganlikun	0:13413ea9a877	1643	* @retval None
ganlikun	0:13413ea9a877	1644	*/
ganlikun	0:13413ea9a877	1645	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
ganlikun	0:13413ea9a877	1646	{
ganlikun	0:13413ea9a877	1647	/* Check the parameters */
ganlikun	0:13413ea9a877	1648	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1649	assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
ganlikun	0:13413ea9a877	1650
ganlikun	0:13413ea9a877	1651	/* Set the Auto-refresh number in command register */
ganlikun	0:13413ea9a877	1652	Device->SDCMR \|= (AutoRefreshNumber << 5U);
ganlikun	0:13413ea9a877	1653
ganlikun	0:13413ea9a877	1654	return HAL_OK;
ganlikun	0:13413ea9a877	1655	}
ganlikun	0:13413ea9a877	1656
ganlikun	0:13413ea9a877	1657	/**
ganlikun	0:13413ea9a877	1658	* @brief Returns the indicated FMC SDRAM bank mode status.
ganlikun	0:13413ea9a877	1659	* @param Device: Pointer to SDRAM device instance
ganlikun	0:13413ea9a877	1660	* @param Bank: Defines the FMC SDRAM bank. This parameter can be
ganlikun	0:13413ea9a877	1661	* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
ganlikun	0:13413ea9a877	1662	* @retval The FMC SDRAM bank mode status, could be on of the following values:
ganlikun	0:13413ea9a877	1663	* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
ganlikun	0:13413ea9a877	1664	* FMC_SDRAM_POWER_DOWN_MODE.
ganlikun	0:13413ea9a877	1665	*/
ganlikun	0:13413ea9a877	1666	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
ganlikun	0:13413ea9a877	1667	{
ganlikun	0:13413ea9a877	1668	uint32_t tmpreg = 0U;
ganlikun	0:13413ea9a877	1669
ganlikun	0:13413ea9a877	1670	/* Check the parameters */
ganlikun	0:13413ea9a877	1671	assert_param(IS_FMC_SDRAM_DEVICE(Device));
ganlikun	0:13413ea9a877	1672	assert_param(IS_FMC_SDRAM_BANK(Bank));
ganlikun	0:13413ea9a877	1673
ganlikun	0:13413ea9a877	1674	/* Get the corresponding bank mode */
ganlikun	0:13413ea9a877	1675	if(Bank == FMC_SDRAM_BANK1)
ganlikun	0:13413ea9a877	1676	{
ganlikun	0:13413ea9a877	1677	tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
ganlikun	0:13413ea9a877	1678	}
ganlikun	0:13413ea9a877	1679	else
ganlikun	0:13413ea9a877	1680	{
ganlikun	0:13413ea9a877	1681	tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
ganlikun	0:13413ea9a877	1682	}
ganlikun	0:13413ea9a877	1683
ganlikun	0:13413ea9a877	1684	/* Return the mode status */
ganlikun	0:13413ea9a877	1685	return tmpreg;
ganlikun	0:13413ea9a877	1686	}
ganlikun	0:13413ea9a877	1687
ganlikun	0:13413ea9a877	1688	/**
ganlikun	0:13413ea9a877	1689	* @}
ganlikun	0:13413ea9a877	1690	*/
ganlikun	0:13413ea9a877	1691
ganlikun	0:13413ea9a877	1692	/**
ganlikun	0:13413ea9a877	1693	* @}
ganlikun	0:13413ea9a877	1694	*/
ganlikun	0:13413ea9a877	1695
ganlikun	0:13413ea9a877	1696	/**
ganlikun	0:13413ea9a877	1697	* @}
ganlikun	0:13413ea9a877	1698	*/
ganlikun	0:13413ea9a877	1699	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1700	#endif /* HAL_SRAM_MODULE_ENABLED \|\| HAL_NOR_MODULE_ENABLED \|\| HAL_NAND_MODULE_ENABLED \|\| HAL_PCCARD_MODULE_ENABLED \|\| HAL_SDRAM_MODULE_ENABLED */
ganlikun	0:13413ea9a877	1701
ganlikun	0:13413ea9a877	1702	/**
ganlikun	0:13413ea9a877	1703	* @}
ganlikun	0:13413ea9a877	1704	*/
ganlikun	0:13413ea9a877	1705
ganlikun	0:13413ea9a877	1706	/**
ganlikun	0:13413ea9a877	1707	* @}
ganlikun	0:13413ea9a877	1708	*/
ganlikun	0:13413ea9a877	1709
ganlikun	0:13413ea9a877	1710	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1711

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Type:	Library
Created:	05 Jul 2022
Imports:	1
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Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c@0:13413ea9a877, 2022-06-12 (annotated)

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