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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_bus.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of BUS LL module.
ganlikun	0:13413ea9a877	8
ganlikun	0:13413ea9a877	9	@verbatim
ganlikun	0:13413ea9a877	10	##### RCC Limitations #####
ganlikun	0:13413ea9a877	11	==============================================================================
ganlikun	0:13413ea9a877	12	[..]
ganlikun	0:13413ea9a877	13	A delay between an RCC peripheral clock enable and the effective peripheral
ganlikun	0:13413ea9a877	14	enabling should be taken into account in order to manage the peripheral read/write
ganlikun	0:13413ea9a877	15	from/to registers.
ganlikun	0:13413ea9a877	16	(+) This delay depends on the peripheral mapping.
ganlikun	0:13413ea9a877	17	(++) AHB & APB peripherals, 1 dummy read is necessary
ganlikun	0:13413ea9a877	18
ganlikun	0:13413ea9a877	19	[..]
ganlikun	0:13413ea9a877	20	Workarounds:
ganlikun	0:13413ea9a877	21	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
ganlikun	0:13413ea9a877	22	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
ganlikun	0:13413ea9a877	23
ganlikun	0:13413ea9a877	24	@endverbatim
ganlikun	0:13413ea9a877	25	******************************************************************************
ganlikun	0:13413ea9a877	26	* @attention
ganlikun	0:13413ea9a877	27	*
ganlikun	0:13413ea9a877	28	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	29	*
ganlikun	0:13413ea9a877	30	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	31	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	32	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	33	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	34	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	35	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	36	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	37	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	38	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	39	* without specific prior written permission.
ganlikun	0:13413ea9a877	40	*
ganlikun	0:13413ea9a877	41	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	42	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	43	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	44	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	45	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	46	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	47	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	48	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	49	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	50	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	51	*
ganlikun	0:13413ea9a877	52	******************************************************************************
ganlikun	0:13413ea9a877	53	*/
ganlikun	0:13413ea9a877	54
ganlikun	0:13413ea9a877	55	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	56	#ifndef __STM32F4xx_LL_BUS_H
ganlikun	0:13413ea9a877	57	#define __STM32F4xx_LL_BUS_H
ganlikun	0:13413ea9a877	58
ganlikun	0:13413ea9a877	59	#ifdef __cplusplus
ganlikun	0:13413ea9a877	60	extern "C" {
ganlikun	0:13413ea9a877	61	#endif
ganlikun	0:13413ea9a877	62
ganlikun	0:13413ea9a877	63	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	64	#include "stm32f4xx.h"
ganlikun	0:13413ea9a877	65
ganlikun	0:13413ea9a877	66	/** @addtogroup STM32F4xx_LL_Driver
ganlikun	0:13413ea9a877	67	* @{
ganlikun	0:13413ea9a877	68	*/
ganlikun	0:13413ea9a877	69
ganlikun	0:13413ea9a877	70	#if defined(RCC)
ganlikun	0:13413ea9a877	71
ganlikun	0:13413ea9a877	72	/** @defgroup BUS_LL BUS
ganlikun	0:13413ea9a877	73	* @{
ganlikun	0:13413ea9a877	74	*/
ganlikun	0:13413ea9a877	75
ganlikun	0:13413ea9a877	76	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	77	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	78	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	79	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	80	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	81	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	82	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
ganlikun	0:13413ea9a877	83	* @{
ganlikun	0:13413ea9a877	84	*/
ganlikun	0:13413ea9a877	85
ganlikun	0:13413ea9a877	86	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
ganlikun	0:13413ea9a877	87	* @{
ganlikun	0:13413ea9a877	88	*/
ganlikun	0:13413ea9a877	89	#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
ganlikun	0:13413ea9a877	90	#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
ganlikun	0:13413ea9a877	91	#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
ganlikun	0:13413ea9a877	92	#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
ganlikun	0:13413ea9a877	93	#if defined(GPIOD)
ganlikun	0:13413ea9a877	94	#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
ganlikun	0:13413ea9a877	95	#endif /* GPIOD */
ganlikun	0:13413ea9a877	96	#if defined(GPIOE)
ganlikun	0:13413ea9a877	97	#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
ganlikun	0:13413ea9a877	98	#endif /* GPIOE */
ganlikun	0:13413ea9a877	99	#if defined(GPIOF)
ganlikun	0:13413ea9a877	100	#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
ganlikun	0:13413ea9a877	101	#endif /* GPIOF */
ganlikun	0:13413ea9a877	102	#if defined(GPIOG)
ganlikun	0:13413ea9a877	103	#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
ganlikun	0:13413ea9a877	104	#endif /* GPIOG */
ganlikun	0:13413ea9a877	105	#if defined(GPIOH)
ganlikun	0:13413ea9a877	106	#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
ganlikun	0:13413ea9a877	107	#endif /* GPIOH */
ganlikun	0:13413ea9a877	108	#if defined(GPIOI)
ganlikun	0:13413ea9a877	109	#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
ganlikun	0:13413ea9a877	110	#endif /* GPIOI */
ganlikun	0:13413ea9a877	111	#if defined(GPIOJ)
ganlikun	0:13413ea9a877	112	#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
ganlikun	0:13413ea9a877	113	#endif /* GPIOJ */
ganlikun	0:13413ea9a877	114	#if defined(GPIOK)
ganlikun	0:13413ea9a877	115	#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
ganlikun	0:13413ea9a877	116	#endif /* GPIOK */
ganlikun	0:13413ea9a877	117	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
ganlikun	0:13413ea9a877	118	#if defined(RCC_AHB1ENR_BKPSRAMEN)
ganlikun	0:13413ea9a877	119	#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
ganlikun	0:13413ea9a877	120	#endif /* RCC_AHB1ENR_BKPSRAMEN */
ganlikun	0:13413ea9a877	121	#if defined(RCC_AHB1ENR_CCMDATARAMEN)
ganlikun	0:13413ea9a877	122	#define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
ganlikun	0:13413ea9a877	123	#endif /* RCC_AHB1ENR_CCMDATARAMEN */
ganlikun	0:13413ea9a877	124	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
ganlikun	0:13413ea9a877	125	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
ganlikun	0:13413ea9a877	126	#if defined(RCC_AHB1ENR_RNGEN)
ganlikun	0:13413ea9a877	127	#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN
ganlikun	0:13413ea9a877	128	#endif /* RCC_AHB1ENR_RNGEN */
ganlikun	0:13413ea9a877	129	#if defined(DMA2D)
ganlikun	0:13413ea9a877	130	#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
ganlikun	0:13413ea9a877	131	#endif /* DMA2D */
ganlikun	0:13413ea9a877	132	#if defined(ETH)
ganlikun	0:13413ea9a877	133	#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
ganlikun	0:13413ea9a877	134	#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
ganlikun	0:13413ea9a877	135	#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
ganlikun	0:13413ea9a877	136	#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
ganlikun	0:13413ea9a877	137	#endif /* ETH */
ganlikun	0:13413ea9a877	138	#if defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	139	#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
ganlikun	0:13413ea9a877	140	#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
ganlikun	0:13413ea9a877	141	#endif /* USB_OTG_HS */
ganlikun	0:13413ea9a877	142	#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
ganlikun	0:13413ea9a877	143	#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
ganlikun	0:13413ea9a877	144	#if defined(RCC_AHB1LPENR_SRAM2LPEN)
ganlikun	0:13413ea9a877	145	#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
ganlikun	0:13413ea9a877	146	#endif /* RCC_AHB1LPENR_SRAM2LPEN */
ganlikun	0:13413ea9a877	147	#if defined(RCC_AHB1LPENR_SRAM3LPEN)
ganlikun	0:13413ea9a877	148	#define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
ganlikun	0:13413ea9a877	149	#endif /* RCC_AHB1LPENR_SRAM3LPEN */
ganlikun	0:13413ea9a877	150	/**
ganlikun	0:13413ea9a877	151	* @}
ganlikun	0:13413ea9a877	152	*/
ganlikun	0:13413ea9a877	153
ganlikun	0:13413ea9a877	154	#if defined(RCC_AHB2_SUPPORT)
ganlikun	0:13413ea9a877	155	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
ganlikun	0:13413ea9a877	156	* @{
ganlikun	0:13413ea9a877	157	*/
ganlikun	0:13413ea9a877	158	#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
ganlikun	0:13413ea9a877	159	#if defined(DCMI)
ganlikun	0:13413ea9a877	160	#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
ganlikun	0:13413ea9a877	161	#endif /* DCMI */
ganlikun	0:13413ea9a877	162	#if defined(CRYP)
ganlikun	0:13413ea9a877	163	#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
ganlikun	0:13413ea9a877	164	#endif /* CRYP */
ganlikun	0:13413ea9a877	165	#if defined(AES)
ganlikun	0:13413ea9a877	166	#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
ganlikun	0:13413ea9a877	167	#endif /* AES */
ganlikun	0:13413ea9a877	168	#if defined(HASH)
ganlikun	0:13413ea9a877	169	#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
ganlikun	0:13413ea9a877	170	#endif /* HASH */
ganlikun	0:13413ea9a877	171	#if defined(RCC_AHB2ENR_RNGEN)
ganlikun	0:13413ea9a877	172	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
ganlikun	0:13413ea9a877	173	#endif /* RCC_AHB2ENR_RNGEN */
ganlikun	0:13413ea9a877	174	#if defined(USB_OTG_FS)
ganlikun	0:13413ea9a877	175	#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
ganlikun	0:13413ea9a877	176	#endif /* USB_OTG_FS */
ganlikun	0:13413ea9a877	177	/**
ganlikun	0:13413ea9a877	178	* @}
ganlikun	0:13413ea9a877	179	*/
ganlikun	0:13413ea9a877	180	#endif /* RCC_AHB2_SUPPORT */
ganlikun	0:13413ea9a877	181
ganlikun	0:13413ea9a877	182	#if defined(RCC_AHB3_SUPPORT)
ganlikun	0:13413ea9a877	183	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
ganlikun	0:13413ea9a877	184	* @{
ganlikun	0:13413ea9a877	185	*/
ganlikun	0:13413ea9a877	186	#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
ganlikun	0:13413ea9a877	187	#if defined(FSMC_Bank1)
ganlikun	0:13413ea9a877	188	#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
ganlikun	0:13413ea9a877	189	#endif /* FSMC_Bank1 */
ganlikun	0:13413ea9a877	190	#if defined(FMC_Bank1)
ganlikun	0:13413ea9a877	191	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
ganlikun	0:13413ea9a877	192	#endif /* FMC_Bank1 */
ganlikun	0:13413ea9a877	193	#if defined(QUADSPI)
ganlikun	0:13413ea9a877	194	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
ganlikun	0:13413ea9a877	195	#endif /* QUADSPI */
ganlikun	0:13413ea9a877	196	/**
ganlikun	0:13413ea9a877	197	* @}
ganlikun	0:13413ea9a877	198	*/
ganlikun	0:13413ea9a877	199	#endif /* RCC_AHB3_SUPPORT */
ganlikun	0:13413ea9a877	200
ganlikun	0:13413ea9a877	201	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
ganlikun	0:13413ea9a877	202	* @{
ganlikun	0:13413ea9a877	203	*/
ganlikun	0:13413ea9a877	204	#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
ganlikun	0:13413ea9a877	205	#if defined(TIM2)
ganlikun	0:13413ea9a877	206	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
ganlikun	0:13413ea9a877	207	#endif /* TIM2 */
ganlikun	0:13413ea9a877	208	#if defined(TIM3)
ganlikun	0:13413ea9a877	209	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
ganlikun	0:13413ea9a877	210	#endif /* TIM3 */
ganlikun	0:13413ea9a877	211	#if defined(TIM4)
ganlikun	0:13413ea9a877	212	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
ganlikun	0:13413ea9a877	213	#endif /* TIM4 */
ganlikun	0:13413ea9a877	214	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
ganlikun	0:13413ea9a877	215	#if defined(TIM6)
ganlikun	0:13413ea9a877	216	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
ganlikun	0:13413ea9a877	217	#endif /* TIM6 */
ganlikun	0:13413ea9a877	218	#if defined(TIM7)
ganlikun	0:13413ea9a877	219	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
ganlikun	0:13413ea9a877	220	#endif /* TIM7 */
ganlikun	0:13413ea9a877	221	#if defined(TIM12)
ganlikun	0:13413ea9a877	222	#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
ganlikun	0:13413ea9a877	223	#endif /* TIM12 */
ganlikun	0:13413ea9a877	224	#if defined(TIM13)
ganlikun	0:13413ea9a877	225	#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
ganlikun	0:13413ea9a877	226	#endif /* TIM13 */
ganlikun	0:13413ea9a877	227	#if defined(TIM14)
ganlikun	0:13413ea9a877	228	#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
ganlikun	0:13413ea9a877	229	#endif /* TIM14 */
ganlikun	0:13413ea9a877	230	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	231	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
ganlikun	0:13413ea9a877	232	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	233	#if defined(RCC_APB1ENR_RTCAPBEN)
ganlikun	0:13413ea9a877	234	#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN
ganlikun	0:13413ea9a877	235	#endif /* RCC_APB1ENR_RTCAPBEN */
ganlikun	0:13413ea9a877	236	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
ganlikun	0:13413ea9a877	237	#if defined(SPI2)
ganlikun	0:13413ea9a877	238	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
ganlikun	0:13413ea9a877	239	#endif /* SPI2 */
ganlikun	0:13413ea9a877	240	#if defined(SPI3)
ganlikun	0:13413ea9a877	241	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
ganlikun	0:13413ea9a877	242	#endif /* SPI3 */
ganlikun	0:13413ea9a877	243	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	244	#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
ganlikun	0:13413ea9a877	245	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	246	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
ganlikun	0:13413ea9a877	247	#if defined(USART3)
ganlikun	0:13413ea9a877	248	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
ganlikun	0:13413ea9a877	249	#endif /* USART3 */
ganlikun	0:13413ea9a877	250	#if defined(UART4)
ganlikun	0:13413ea9a877	251	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
ganlikun	0:13413ea9a877	252	#endif /* UART4 */
ganlikun	0:13413ea9a877	253	#if defined(UART5)
ganlikun	0:13413ea9a877	254	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
ganlikun	0:13413ea9a877	255	#endif /* UART5 */
ganlikun	0:13413ea9a877	256	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
ganlikun	0:13413ea9a877	257	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
ganlikun	0:13413ea9a877	258	#if defined(I2C3)
ganlikun	0:13413ea9a877	259	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
ganlikun	0:13413ea9a877	260	#endif /* I2C3 */
ganlikun	0:13413ea9a877	261	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	262	#define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN
ganlikun	0:13413ea9a877	263	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	264	#if defined(CAN1)
ganlikun	0:13413ea9a877	265	#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
ganlikun	0:13413ea9a877	266	#endif /* CAN1 */
ganlikun	0:13413ea9a877	267	#if defined(CAN2)
ganlikun	0:13413ea9a877	268	#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
ganlikun	0:13413ea9a877	269	#endif /* CAN2 */
ganlikun	0:13413ea9a877	270	#if defined(CAN3)
ganlikun	0:13413ea9a877	271	#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
ganlikun	0:13413ea9a877	272	#endif /* CAN3 */
ganlikun	0:13413ea9a877	273	#if defined(CEC)
ganlikun	0:13413ea9a877	274	#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
ganlikun	0:13413ea9a877	275	#endif /* CEC */
ganlikun	0:13413ea9a877	276	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
ganlikun	0:13413ea9a877	277	#if defined(DAC1)
ganlikun	0:13413ea9a877	278	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
ganlikun	0:13413ea9a877	279	#endif /* DAC1 */
ganlikun	0:13413ea9a877	280	#if defined(UART7)
ganlikun	0:13413ea9a877	281	#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
ganlikun	0:13413ea9a877	282	#endif /* UART7 */
ganlikun	0:13413ea9a877	283	#if defined(UART8)
ganlikun	0:13413ea9a877	284	#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
ganlikun	0:13413ea9a877	285	#endif /* UART8 */
ganlikun	0:13413ea9a877	286	/**
ganlikun	0:13413ea9a877	287	* @}
ganlikun	0:13413ea9a877	288	*/
ganlikun	0:13413ea9a877	289
ganlikun	0:13413ea9a877	290	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
ganlikun	0:13413ea9a877	291	* @{
ganlikun	0:13413ea9a877	292	*/
ganlikun	0:13413ea9a877	293	#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
ganlikun	0:13413ea9a877	294	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
ganlikun	0:13413ea9a877	295	#if defined(TIM8)
ganlikun	0:13413ea9a877	296	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
ganlikun	0:13413ea9a877	297	#endif /* TIM8 */
ganlikun	0:13413ea9a877	298	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
ganlikun	0:13413ea9a877	299	#if defined(USART6)
ganlikun	0:13413ea9a877	300	#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
ganlikun	0:13413ea9a877	301	#endif /* USART6 */
ganlikun	0:13413ea9a877	302	#if defined(UART9)
ganlikun	0:13413ea9a877	303	#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
ganlikun	0:13413ea9a877	304	#endif /* UART9 */
ganlikun	0:13413ea9a877	305	#if defined(UART10)
ganlikun	0:13413ea9a877	306	#define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN
ganlikun	0:13413ea9a877	307	#endif /* UART10 */
ganlikun	0:13413ea9a877	308	#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
ganlikun	0:13413ea9a877	309	#if defined(ADC2)
ganlikun	0:13413ea9a877	310	#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
ganlikun	0:13413ea9a877	311	#endif /* ADC2 */
ganlikun	0:13413ea9a877	312	#if defined(ADC3)
ganlikun	0:13413ea9a877	313	#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
ganlikun	0:13413ea9a877	314	#endif /* ADC3 */
ganlikun	0:13413ea9a877	315	#if defined(SDIO)
ganlikun	0:13413ea9a877	316	#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
ganlikun	0:13413ea9a877	317	#endif /* SDIO */
ganlikun	0:13413ea9a877	318	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
ganlikun	0:13413ea9a877	319	#if defined(SPI4)
ganlikun	0:13413ea9a877	320	#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
ganlikun	0:13413ea9a877	321	#endif /* SPI4 */
ganlikun	0:13413ea9a877	322	#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
ganlikun	0:13413ea9a877	323	#if defined(RCC_APB2ENR_EXTITEN)
ganlikun	0:13413ea9a877	324	#define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN
ganlikun	0:13413ea9a877	325	#endif /* RCC_APB2ENR_EXTITEN */
ganlikun	0:13413ea9a877	326	#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
ganlikun	0:13413ea9a877	327	#if defined(TIM10)
ganlikun	0:13413ea9a877	328	#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
ganlikun	0:13413ea9a877	329	#endif /* TIM10 */
ganlikun	0:13413ea9a877	330	#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
ganlikun	0:13413ea9a877	331	#if defined(SPI5)
ganlikun	0:13413ea9a877	332	#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
ganlikun	0:13413ea9a877	333	#endif /* SPI5 */
ganlikun	0:13413ea9a877	334	#if defined(SPI6)
ganlikun	0:13413ea9a877	335	#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
ganlikun	0:13413ea9a877	336	#endif /* SPI6 */
ganlikun	0:13413ea9a877	337	#if defined(SAI1)
ganlikun	0:13413ea9a877	338	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
ganlikun	0:13413ea9a877	339	#endif /* SAI1 */
ganlikun	0:13413ea9a877	340	#if defined(SAI2)
ganlikun	0:13413ea9a877	341	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
ganlikun	0:13413ea9a877	342	#endif /* SAI2 */
ganlikun	0:13413ea9a877	343	#if defined(LTDC)
ganlikun	0:13413ea9a877	344	#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
ganlikun	0:13413ea9a877	345	#endif /* LTDC */
ganlikun	0:13413ea9a877	346	#if defined(DSI)
ganlikun	0:13413ea9a877	347	#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
ganlikun	0:13413ea9a877	348	#endif /* DSI */
ganlikun	0:13413ea9a877	349	#if defined(DFSDM1_Channel0)
ganlikun	0:13413ea9a877	350	#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
ganlikun	0:13413ea9a877	351	#endif /* DFSDM1_Channel0 */
ganlikun	0:13413ea9a877	352	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	353	#define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN
ganlikun	0:13413ea9a877	354	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	355	#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
ganlikun	0:13413ea9a877	356	/**
ganlikun	0:13413ea9a877	357	* @}
ganlikun	0:13413ea9a877	358	*/
ganlikun	0:13413ea9a877	359
ganlikun	0:13413ea9a877	360	/**
ganlikun	0:13413ea9a877	361	* @}
ganlikun	0:13413ea9a877	362	*/
ganlikun	0:13413ea9a877	363
ganlikun	0:13413ea9a877	364	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	365	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	366	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
ganlikun	0:13413ea9a877	367	* @{
ganlikun	0:13413ea9a877	368	*/
ganlikun	0:13413ea9a877	369
ganlikun	0:13413ea9a877	370	/** @defgroup BUS_LL_EF_AHB1 AHB1
ganlikun	0:13413ea9a877	371	* @{
ganlikun	0:13413ea9a877	372	*/
ganlikun	0:13413ea9a877	373
ganlikun	0:13413ea9a877	374	/**
ganlikun	0:13413ea9a877	375	* @brief Enable AHB1 peripherals clock.
ganlikun	0:13413ea9a877	376	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	377	* AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	378	* AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	379	* AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	380	* AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	381	* AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	382	* AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	383	* AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	384	* AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	385	* AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	386	* AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	387	* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	388	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	389	* AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	390	* AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	391	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	392	* AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	393	* AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	394	* AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	395	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	396	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	397	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	398	* AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	399	* AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
ganlikun	0:13413ea9a877	400	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	401	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
ganlikun	0:13413ea9a877	402	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
ganlikun	0:13413ea9a877	403	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
ganlikun	0:13413ea9a877	404	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
ganlikun	0:13413ea9a877	405	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
ganlikun	0:13413ea9a877	406	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
ganlikun	0:13413ea9a877	407	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
ganlikun	0:13413ea9a877	408	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
ganlikun	0:13413ea9a877	409	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
ganlikun	0:13413ea9a877	410	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
ganlikun	0:13413ea9a877	411	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
ganlikun	0:13413ea9a877	412	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
ganlikun	0:13413ea9a877	413	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
ganlikun	0:13413ea9a877	414	* @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
ganlikun	0:13413ea9a877	415	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
ganlikun	0:13413ea9a877	416	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
ganlikun	0:13413ea9a877	417	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	418	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
ganlikun	0:13413ea9a877	419	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
ganlikun	0:13413ea9a877	420	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
ganlikun	0:13413ea9a877	421	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
ganlikun	0:13413ea9a877	422	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
ganlikun	0:13413ea9a877	423	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
ganlikun	0:13413ea9a877	424	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
ganlikun	0:13413ea9a877	425	*
ganlikun	0:13413ea9a877	426	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	427	* @retval None
ganlikun	0:13413ea9a877	428	*/
ganlikun	0:13413ea9a877	429	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	430	{
ganlikun	0:13413ea9a877	431	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	432	SET_BIT(RCC->AHB1ENR, Periphs);
ganlikun	0:13413ea9a877	433	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	434	tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
ganlikun	0:13413ea9a877	435	(void)tmpreg;
ganlikun	0:13413ea9a877	436	}
ganlikun	0:13413ea9a877	437
ganlikun	0:13413ea9a877	438	/**
ganlikun	0:13413ea9a877	439	* @brief Check if AHB1 peripheral clock is enabled or not
ganlikun	0:13413ea9a877	440	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	441	* AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	442	* AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	443	* AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	444	* AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	445	* AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	446	* AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	447	* AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	448	* AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	449	* AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	450	* AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	451	* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	452	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	453	* AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	454	* AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	455	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	456	* AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	457	* AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	458	* AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	459	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	460	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	461	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	462	* AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	463	* AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
ganlikun	0:13413ea9a877	464	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	465	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
ganlikun	0:13413ea9a877	466	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
ganlikun	0:13413ea9a877	467	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
ganlikun	0:13413ea9a877	468	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
ganlikun	0:13413ea9a877	469	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
ganlikun	0:13413ea9a877	470	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
ganlikun	0:13413ea9a877	471	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
ganlikun	0:13413ea9a877	472	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
ganlikun	0:13413ea9a877	473	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
ganlikun	0:13413ea9a877	474	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
ganlikun	0:13413ea9a877	475	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
ganlikun	0:13413ea9a877	476	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
ganlikun	0:13413ea9a877	477	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
ganlikun	0:13413ea9a877	478	* @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
ganlikun	0:13413ea9a877	479	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
ganlikun	0:13413ea9a877	480	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
ganlikun	0:13413ea9a877	481	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	482	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
ganlikun	0:13413ea9a877	483	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
ganlikun	0:13413ea9a877	484	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
ganlikun	0:13413ea9a877	485	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
ganlikun	0:13413ea9a877	486	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
ganlikun	0:13413ea9a877	487	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
ganlikun	0:13413ea9a877	488	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
ganlikun	0:13413ea9a877	489	*
ganlikun	0:13413ea9a877	490	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	491	* @retval State of Periphs (1 or 0).
ganlikun	0:13413ea9a877	492	*/
ganlikun	0:13413ea9a877	493	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	494	{
ganlikun	0:13413ea9a877	495	return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
ganlikun	0:13413ea9a877	496	}
ganlikun	0:13413ea9a877	497
ganlikun	0:13413ea9a877	498	/**
ganlikun	0:13413ea9a877	499	* @brief Disable AHB1 peripherals clock.
ganlikun	0:13413ea9a877	500	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	501	* AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	502	* AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	503	* AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	504	* AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	505	* AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	506	* AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	507	* AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	508	* AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	509	* AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	510	* AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	511	* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	512	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	513	* AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	514	* AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	515	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	516	* AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	517	* AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	518	* AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	519	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	520	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	521	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	522	* AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	523	* AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
ganlikun	0:13413ea9a877	524	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	525	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
ganlikun	0:13413ea9a877	526	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
ganlikun	0:13413ea9a877	527	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
ganlikun	0:13413ea9a877	528	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
ganlikun	0:13413ea9a877	529	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
ganlikun	0:13413ea9a877	530	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
ganlikun	0:13413ea9a877	531	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
ganlikun	0:13413ea9a877	532	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
ganlikun	0:13413ea9a877	533	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
ganlikun	0:13413ea9a877	534	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
ganlikun	0:13413ea9a877	535	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
ganlikun	0:13413ea9a877	536	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
ganlikun	0:13413ea9a877	537	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
ganlikun	0:13413ea9a877	538	* @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
ganlikun	0:13413ea9a877	539	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
ganlikun	0:13413ea9a877	540	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
ganlikun	0:13413ea9a877	541	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	542	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
ganlikun	0:13413ea9a877	543	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
ganlikun	0:13413ea9a877	544	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
ganlikun	0:13413ea9a877	545	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
ganlikun	0:13413ea9a877	546	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
ganlikun	0:13413ea9a877	547	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
ganlikun	0:13413ea9a877	548	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
ganlikun	0:13413ea9a877	549	*
ganlikun	0:13413ea9a877	550	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	551	* @retval None
ganlikun	0:13413ea9a877	552	*/
ganlikun	0:13413ea9a877	553	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	554	{
ganlikun	0:13413ea9a877	555	CLEAR_BIT(RCC->AHB1ENR, Periphs);
ganlikun	0:13413ea9a877	556	}
ganlikun	0:13413ea9a877	557
ganlikun	0:13413ea9a877	558	/**
ganlikun	0:13413ea9a877	559	* @brief Force AHB1 peripherals reset.
ganlikun	0:13413ea9a877	560	* @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	561	* AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	562	* AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	563	* AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	564	* AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	565	* AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	566	* AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	567	* AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	568	* AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	569	* AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	570	* AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	571	* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	572	* AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	573	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	574	* AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	575	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	576	* AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	577	* AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
ganlikun	0:13413ea9a877	578	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	579	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	580	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
ganlikun	0:13413ea9a877	581	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
ganlikun	0:13413ea9a877	582	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
ganlikun	0:13413ea9a877	583	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
ganlikun	0:13413ea9a877	584	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
ganlikun	0:13413ea9a877	585	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
ganlikun	0:13413ea9a877	586	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
ganlikun	0:13413ea9a877	587	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
ganlikun	0:13413ea9a877	588	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
ganlikun	0:13413ea9a877	589	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
ganlikun	0:13413ea9a877	590	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
ganlikun	0:13413ea9a877	591	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
ganlikun	0:13413ea9a877	592	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
ganlikun	0:13413ea9a877	593	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
ganlikun	0:13413ea9a877	594	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	595	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
ganlikun	0:13413ea9a877	596	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
ganlikun	0:13413ea9a877	597	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
ganlikun	0:13413ea9a877	598	*
ganlikun	0:13413ea9a877	599	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	600	* @retval None
ganlikun	0:13413ea9a877	601	*/
ganlikun	0:13413ea9a877	602	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	603	{
ganlikun	0:13413ea9a877	604	SET_BIT(RCC->AHB1RSTR, Periphs);
ganlikun	0:13413ea9a877	605	}
ganlikun	0:13413ea9a877	606
ganlikun	0:13413ea9a877	607	/**
ganlikun	0:13413ea9a877	608	* @brief Release AHB1 peripherals reset.
ganlikun	0:13413ea9a877	609	* @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	610	* AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	611	* AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	612	* AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	613	* AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	614	* AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	615	* AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	616	* AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	617	* AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	618	* AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	619	* AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	620	* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	621	* AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	622	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	623	* AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	624	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	625	* AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	626	* AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
ganlikun	0:13413ea9a877	627	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	628	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	629	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
ganlikun	0:13413ea9a877	630	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
ganlikun	0:13413ea9a877	631	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
ganlikun	0:13413ea9a877	632	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
ganlikun	0:13413ea9a877	633	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
ganlikun	0:13413ea9a877	634	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
ganlikun	0:13413ea9a877	635	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
ganlikun	0:13413ea9a877	636	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
ganlikun	0:13413ea9a877	637	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
ganlikun	0:13413ea9a877	638	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
ganlikun	0:13413ea9a877	639	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
ganlikun	0:13413ea9a877	640	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
ganlikun	0:13413ea9a877	641	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
ganlikun	0:13413ea9a877	642	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
ganlikun	0:13413ea9a877	643	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	644	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
ganlikun	0:13413ea9a877	645	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
ganlikun	0:13413ea9a877	646	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
ganlikun	0:13413ea9a877	647	*
ganlikun	0:13413ea9a877	648	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	649	* @retval None
ganlikun	0:13413ea9a877	650	*/
ganlikun	0:13413ea9a877	651	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	652	{
ganlikun	0:13413ea9a877	653	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
ganlikun	0:13413ea9a877	654	}
ganlikun	0:13413ea9a877	655
ganlikun	0:13413ea9a877	656	/**
ganlikun	0:13413ea9a877	657	* @brief Enable AHB1 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	658	* @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	659	* AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	660	* AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	661	* AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	662	* AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	663	* AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	664	* AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	665	* AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	666	* AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	667	* AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	668	* AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	669	* AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	670	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	671	* AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	672	* AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	673	* AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	674	* AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	675	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	676	* AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	677	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	678	* AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	679	* AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	680	* AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	681	* AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	682	* AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	683	* AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	684	* AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	685	* AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
ganlikun	0:13413ea9a877	686	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	687	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
ganlikun	0:13413ea9a877	688	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
ganlikun	0:13413ea9a877	689	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
ganlikun	0:13413ea9a877	690	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
ganlikun	0:13413ea9a877	691	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
ganlikun	0:13413ea9a877	692	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
ganlikun	0:13413ea9a877	693	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
ganlikun	0:13413ea9a877	694	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
ganlikun	0:13413ea9a877	695	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
ganlikun	0:13413ea9a877	696	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
ganlikun	0:13413ea9a877	697	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
ganlikun	0:13413ea9a877	698	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
ganlikun	0:13413ea9a877	699	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
ganlikun	0:13413ea9a877	700	* @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
ganlikun	0:13413ea9a877	701	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
ganlikun	0:13413ea9a877	702	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
ganlikun	0:13413ea9a877	703	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
ganlikun	0:13413ea9a877	704	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
ganlikun	0:13413ea9a877	705	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
ganlikun	0:13413ea9a877	706	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	707	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
ganlikun	0:13413ea9a877	708	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
ganlikun	0:13413ea9a877	709	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
ganlikun	0:13413ea9a877	710	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
ganlikun	0:13413ea9a877	711	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
ganlikun	0:13413ea9a877	712	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
ganlikun	0:13413ea9a877	713	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
ganlikun	0:13413ea9a877	714	*
ganlikun	0:13413ea9a877	715	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	716	* @retval None
ganlikun	0:13413ea9a877	717	*/
ganlikun	0:13413ea9a877	718	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	719	{
ganlikun	0:13413ea9a877	720	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	721	SET_BIT(RCC->AHB1LPENR, Periphs);
ganlikun	0:13413ea9a877	722	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	723	tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
ganlikun	0:13413ea9a877	724	(void)tmpreg;
ganlikun	0:13413ea9a877	725	}
ganlikun	0:13413ea9a877	726
ganlikun	0:13413ea9a877	727	/**
ganlikun	0:13413ea9a877	728	* @brief Disable AHB1 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	729	* @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	730	* AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	731	* AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	732	* AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	733	* AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	734	* AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	735	* AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	736	* AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	737	* AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	738	* AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	739	* AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	740	* AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	741	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	742	* AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	743	* AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	744	* AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	745	* AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	746	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	747	* AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	748	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	749	* AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	750	* AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	751	* AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	752	* AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	753	* AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	754	* AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	755	* AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	756	* AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
ganlikun	0:13413ea9a877	757	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	758	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
ganlikun	0:13413ea9a877	759	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
ganlikun	0:13413ea9a877	760	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
ganlikun	0:13413ea9a877	761	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
ganlikun	0:13413ea9a877	762	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
ganlikun	0:13413ea9a877	763	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
ganlikun	0:13413ea9a877	764	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
ganlikun	0:13413ea9a877	765	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
ganlikun	0:13413ea9a877	766	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
ganlikun	0:13413ea9a877	767	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
ganlikun	0:13413ea9a877	768	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
ganlikun	0:13413ea9a877	769	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
ganlikun	0:13413ea9a877	770	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
ganlikun	0:13413ea9a877	771	* @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
ganlikun	0:13413ea9a877	772	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
ganlikun	0:13413ea9a877	773	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
ganlikun	0:13413ea9a877	774	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
ganlikun	0:13413ea9a877	775	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
ganlikun	0:13413ea9a877	776	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
ganlikun	0:13413ea9a877	777	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	778	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
ganlikun	0:13413ea9a877	779	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
ganlikun	0:13413ea9a877	780	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
ganlikun	0:13413ea9a877	781	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
ganlikun	0:13413ea9a877	782	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
ganlikun	0:13413ea9a877	783	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
ganlikun	0:13413ea9a877	784	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
ganlikun	0:13413ea9a877	785	*
ganlikun	0:13413ea9a877	786	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	787	* @retval None
ganlikun	0:13413ea9a877	788	*/
ganlikun	0:13413ea9a877	789	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	790	{
ganlikun	0:13413ea9a877	791	CLEAR_BIT(RCC->AHB1LPENR, Periphs);
ganlikun	0:13413ea9a877	792	}
ganlikun	0:13413ea9a877	793
ganlikun	0:13413ea9a877	794	/**
ganlikun	0:13413ea9a877	795	* @}
ganlikun	0:13413ea9a877	796	*/
ganlikun	0:13413ea9a877	797
ganlikun	0:13413ea9a877	798	#if defined(RCC_AHB2_SUPPORT)
ganlikun	0:13413ea9a877	799	/** @defgroup BUS_LL_EF_AHB2 AHB2
ganlikun	0:13413ea9a877	800	* @{
ganlikun	0:13413ea9a877	801	*/
ganlikun	0:13413ea9a877	802
ganlikun	0:13413ea9a877	803	/**
ganlikun	0:13413ea9a877	804	* @brief Enable AHB2 peripherals clock.
ganlikun	0:13413ea9a877	805	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	806	* AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	807	* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	808	* AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	809	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	810	* AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
ganlikun	0:13413ea9a877	811	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	812	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
ganlikun	0:13413ea9a877	813	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
ganlikun	0:13413ea9a877	814	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
ganlikun	0:13413ea9a877	815	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
ganlikun	0:13413ea9a877	816	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	817	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
ganlikun	0:13413ea9a877	818	*
ganlikun	0:13413ea9a877	819	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	820	* @retval None
ganlikun	0:13413ea9a877	821	*/
ganlikun	0:13413ea9a877	822	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	823	{
ganlikun	0:13413ea9a877	824	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	825	SET_BIT(RCC->AHB2ENR, Periphs);
ganlikun	0:13413ea9a877	826	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	827	tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
ganlikun	0:13413ea9a877	828	(void)tmpreg;
ganlikun	0:13413ea9a877	829	}
ganlikun	0:13413ea9a877	830
ganlikun	0:13413ea9a877	831	/**
ganlikun	0:13413ea9a877	832	* @brief Check if AHB2 peripheral clock is enabled or not
ganlikun	0:13413ea9a877	833	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	834	* AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	835	* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	836	* AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	837	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	838	* AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
ganlikun	0:13413ea9a877	839	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	840	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
ganlikun	0:13413ea9a877	841	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
ganlikun	0:13413ea9a877	842	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
ganlikun	0:13413ea9a877	843	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
ganlikun	0:13413ea9a877	844	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	845	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
ganlikun	0:13413ea9a877	846	*
ganlikun	0:13413ea9a877	847	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	848	* @retval State of Periphs (1 or 0).
ganlikun	0:13413ea9a877	849	*/
ganlikun	0:13413ea9a877	850	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	851	{
ganlikun	0:13413ea9a877	852	return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
ganlikun	0:13413ea9a877	853	}
ganlikun	0:13413ea9a877	854
ganlikun	0:13413ea9a877	855	/**
ganlikun	0:13413ea9a877	856	* @brief Disable AHB2 peripherals clock.
ganlikun	0:13413ea9a877	857	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	858	* AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	859	* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	860	* AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	861	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	862	* AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
ganlikun	0:13413ea9a877	863	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	864	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
ganlikun	0:13413ea9a877	865	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
ganlikun	0:13413ea9a877	866	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
ganlikun	0:13413ea9a877	867	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
ganlikun	0:13413ea9a877	868	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	869	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
ganlikun	0:13413ea9a877	870	*
ganlikun	0:13413ea9a877	871	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	872	* @retval None
ganlikun	0:13413ea9a877	873	*/
ganlikun	0:13413ea9a877	874	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	875	{
ganlikun	0:13413ea9a877	876	CLEAR_BIT(RCC->AHB2ENR, Periphs);
ganlikun	0:13413ea9a877	877	}
ganlikun	0:13413ea9a877	878
ganlikun	0:13413ea9a877	879	/**
ganlikun	0:13413ea9a877	880	* @brief Force AHB2 peripherals reset.
ganlikun	0:13413ea9a877	881	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	882	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	883	* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	884	* AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	885	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	886	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
ganlikun	0:13413ea9a877	887	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	888	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	889	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
ganlikun	0:13413ea9a877	890	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
ganlikun	0:13413ea9a877	891	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
ganlikun	0:13413ea9a877	892	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
ganlikun	0:13413ea9a877	893	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	894	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
ganlikun	0:13413ea9a877	895	*
ganlikun	0:13413ea9a877	896	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	897	* @retval None
ganlikun	0:13413ea9a877	898	*/
ganlikun	0:13413ea9a877	899	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	900	{
ganlikun	0:13413ea9a877	901	SET_BIT(RCC->AHB2RSTR, Periphs);
ganlikun	0:13413ea9a877	902	}
ganlikun	0:13413ea9a877	903
ganlikun	0:13413ea9a877	904	/**
ganlikun	0:13413ea9a877	905	* @brief Release AHB2 peripherals reset.
ganlikun	0:13413ea9a877	906	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	907	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	908	* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	909	* AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	910	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	911	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
ganlikun	0:13413ea9a877	912	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	913	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	914	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
ganlikun	0:13413ea9a877	915	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
ganlikun	0:13413ea9a877	916	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
ganlikun	0:13413ea9a877	917	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
ganlikun	0:13413ea9a877	918	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	919	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
ganlikun	0:13413ea9a877	920	*
ganlikun	0:13413ea9a877	921	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	922	* @retval None
ganlikun	0:13413ea9a877	923	*/
ganlikun	0:13413ea9a877	924	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	925	{
ganlikun	0:13413ea9a877	926	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
ganlikun	0:13413ea9a877	927	}
ganlikun	0:13413ea9a877	928
ganlikun	0:13413ea9a877	929	/**
ganlikun	0:13413ea9a877	930	* @brief Enable AHB2 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	931	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	932	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	933	* AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	934	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	935	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	936	* AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
ganlikun	0:13413ea9a877	937	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	938	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
ganlikun	0:13413ea9a877	939	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
ganlikun	0:13413ea9a877	940	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
ganlikun	0:13413ea9a877	941	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
ganlikun	0:13413ea9a877	942	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	943	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
ganlikun	0:13413ea9a877	944	*
ganlikun	0:13413ea9a877	945	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	946	* @retval None
ganlikun	0:13413ea9a877	947	*/
ganlikun	0:13413ea9a877	948	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	949	{
ganlikun	0:13413ea9a877	950	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	951	SET_BIT(RCC->AHB2LPENR, Periphs);
ganlikun	0:13413ea9a877	952	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	953	tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
ganlikun	0:13413ea9a877	954	(void)tmpreg;
ganlikun	0:13413ea9a877	955	}
ganlikun	0:13413ea9a877	956
ganlikun	0:13413ea9a877	957	/**
ganlikun	0:13413ea9a877	958	* @brief Disable AHB2 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	959	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	960	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	961	* AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	962	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	963	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	964	* AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
ganlikun	0:13413ea9a877	965	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	966	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
ganlikun	0:13413ea9a877	967	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
ganlikun	0:13413ea9a877	968	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
ganlikun	0:13413ea9a877	969	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
ganlikun	0:13413ea9a877	970	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
ganlikun	0:13413ea9a877	971	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
ganlikun	0:13413ea9a877	972	*
ganlikun	0:13413ea9a877	973	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	974	* @retval None
ganlikun	0:13413ea9a877	975	*/
ganlikun	0:13413ea9a877	976	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	977	{
ganlikun	0:13413ea9a877	978	CLEAR_BIT(RCC->AHB2LPENR, Periphs);
ganlikun	0:13413ea9a877	979	}
ganlikun	0:13413ea9a877	980
ganlikun	0:13413ea9a877	981	/**
ganlikun	0:13413ea9a877	982	* @}
ganlikun	0:13413ea9a877	983	*/
ganlikun	0:13413ea9a877	984	#endif /* RCC_AHB2_SUPPORT */
ganlikun	0:13413ea9a877	985
ganlikun	0:13413ea9a877	986	#if defined(RCC_AHB3_SUPPORT)
ganlikun	0:13413ea9a877	987	/** @defgroup BUS_LL_EF_AHB3 AHB3
ganlikun	0:13413ea9a877	988	* @{
ganlikun	0:13413ea9a877	989	*/
ganlikun	0:13413ea9a877	990
ganlikun	0:13413ea9a877	991	/**
ganlikun	0:13413ea9a877	992	* @brief Enable AHB3 peripherals clock.
ganlikun	0:13413ea9a877	993	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	994	* AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	995	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
ganlikun	0:13413ea9a877	996	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	997	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
ganlikun	0:13413ea9a877	998	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
ganlikun	0:13413ea9a877	999	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
ganlikun	0:13413ea9a877	1000	*
ganlikun	0:13413ea9a877	1001	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1002	* @retval None
ganlikun	0:13413ea9a877	1003	*/
ganlikun	0:13413ea9a877	1004	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1005	{
ganlikun	0:13413ea9a877	1006	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1007	SET_BIT(RCC->AHB3ENR, Periphs);
ganlikun	0:13413ea9a877	1008	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	1009	tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
ganlikun	0:13413ea9a877	1010	(void)tmpreg;
ganlikun	0:13413ea9a877	1011	}
ganlikun	0:13413ea9a877	1012
ganlikun	0:13413ea9a877	1013	/**
ganlikun	0:13413ea9a877	1014	* @brief Check if AHB3 peripheral clock is enabled or not
ganlikun	0:13413ea9a877	1015	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1016	* AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1017	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
ganlikun	0:13413ea9a877	1018	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1019	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
ganlikun	0:13413ea9a877	1020	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
ganlikun	0:13413ea9a877	1021	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
ganlikun	0:13413ea9a877	1022	*
ganlikun	0:13413ea9a877	1023	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1024	* @retval State of Periphs (1 or 0).
ganlikun	0:13413ea9a877	1025	*/
ganlikun	0:13413ea9a877	1026	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1027	{
ganlikun	0:13413ea9a877	1028	return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
ganlikun	0:13413ea9a877	1029	}
ganlikun	0:13413ea9a877	1030
ganlikun	0:13413ea9a877	1031	/**
ganlikun	0:13413ea9a877	1032	* @brief Disable AHB3 peripherals clock.
ganlikun	0:13413ea9a877	1033	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1034	* AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1035	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
ganlikun	0:13413ea9a877	1036	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1037	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
ganlikun	0:13413ea9a877	1038	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
ganlikun	0:13413ea9a877	1039	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
ganlikun	0:13413ea9a877	1040	*
ganlikun	0:13413ea9a877	1041	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1042	* @retval None
ganlikun	0:13413ea9a877	1043	*/
ganlikun	0:13413ea9a877	1044	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1045	{
ganlikun	0:13413ea9a877	1046	CLEAR_BIT(RCC->AHB3ENR, Periphs);
ganlikun	0:13413ea9a877	1047	}
ganlikun	0:13413ea9a877	1048
ganlikun	0:13413ea9a877	1049	/**
ganlikun	0:13413ea9a877	1050	* @brief Force AHB3 peripherals reset.
ganlikun	0:13413ea9a877	1051	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1052	* AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1053	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
ganlikun	0:13413ea9a877	1054	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1055	* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	1056	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
ganlikun	0:13413ea9a877	1057	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
ganlikun	0:13413ea9a877	1058	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
ganlikun	0:13413ea9a877	1059	*
ganlikun	0:13413ea9a877	1060	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1061	* @retval None
ganlikun	0:13413ea9a877	1062	*/
ganlikun	0:13413ea9a877	1063	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	1064	{
ganlikun	0:13413ea9a877	1065	SET_BIT(RCC->AHB3RSTR, Periphs);
ganlikun	0:13413ea9a877	1066	}
ganlikun	0:13413ea9a877	1067
ganlikun	0:13413ea9a877	1068	/**
ganlikun	0:13413ea9a877	1069	* @brief Release AHB3 peripherals reset.
ganlikun	0:13413ea9a877	1070	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1071	* AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1072	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
ganlikun	0:13413ea9a877	1073	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1074	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	1075	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
ganlikun	0:13413ea9a877	1076	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
ganlikun	0:13413ea9a877	1077	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
ganlikun	0:13413ea9a877	1078	*
ganlikun	0:13413ea9a877	1079	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1080	* @retval None
ganlikun	0:13413ea9a877	1081	*/
ganlikun	0:13413ea9a877	1082	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	1083	{
ganlikun	0:13413ea9a877	1084	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
ganlikun	0:13413ea9a877	1085	}
ganlikun	0:13413ea9a877	1086
ganlikun	0:13413ea9a877	1087	/**
ganlikun	0:13413ea9a877	1088	* @brief Enable AHB3 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	1089	* @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1090	* AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1091	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
ganlikun	0:13413ea9a877	1092	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1093	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
ganlikun	0:13413ea9a877	1094	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
ganlikun	0:13413ea9a877	1095	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
ganlikun	0:13413ea9a877	1096	*
ganlikun	0:13413ea9a877	1097	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1098	* @retval None
ganlikun	0:13413ea9a877	1099	*/
ganlikun	0:13413ea9a877	1100	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	1101	{
ganlikun	0:13413ea9a877	1102	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1103	SET_BIT(RCC->AHB3LPENR, Periphs);
ganlikun	0:13413ea9a877	1104	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	1105	tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
ganlikun	0:13413ea9a877	1106	(void)tmpreg;
ganlikun	0:13413ea9a877	1107	}
ganlikun	0:13413ea9a877	1108
ganlikun	0:13413ea9a877	1109	/**
ganlikun	0:13413ea9a877	1110	* @brief Disable AHB3 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	1111	* @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1112	* AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1113	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
ganlikun	0:13413ea9a877	1114	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1115	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
ganlikun	0:13413ea9a877	1116	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
ganlikun	0:13413ea9a877	1117	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
ganlikun	0:13413ea9a877	1118	*
ganlikun	0:13413ea9a877	1119	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1120	* @retval None
ganlikun	0:13413ea9a877	1121	*/
ganlikun	0:13413ea9a877	1122	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	1123	{
ganlikun	0:13413ea9a877	1124	CLEAR_BIT(RCC->AHB3LPENR, Periphs);
ganlikun	0:13413ea9a877	1125	}
ganlikun	0:13413ea9a877	1126
ganlikun	0:13413ea9a877	1127	/**
ganlikun	0:13413ea9a877	1128	* @}
ganlikun	0:13413ea9a877	1129	*/
ganlikun	0:13413ea9a877	1130	#endif /* RCC_AHB3_SUPPORT */
ganlikun	0:13413ea9a877	1131
ganlikun	0:13413ea9a877	1132	/** @defgroup BUS_LL_EF_APB1 APB1
ganlikun	0:13413ea9a877	1133	* @{
ganlikun	0:13413ea9a877	1134	*/
ganlikun	0:13413ea9a877	1135
ganlikun	0:13413ea9a877	1136	/**
ganlikun	0:13413ea9a877	1137	* @brief Enable APB1 peripherals clock.
ganlikun	0:13413ea9a877	1138	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1139	* APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1140	* APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1141	* APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1142	* APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1143	* APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1144	* APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1145	* APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1146	* APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1147	* APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1148	* APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1149	* APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1150	* APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1151	* APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1152	* APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1153	* APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1154	* APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1155	* APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1156	* APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1157	* APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1158	* APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1159	* APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1160	* APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1161	* APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1162	* APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1163	* APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1164	* APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1165	* APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1166	* APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1167	* APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1168	* APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock
ganlikun	0:13413ea9a877	1169	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1170	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
ganlikun	0:13413ea9a877	1171	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
ganlikun	0:13413ea9a877	1172	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
ganlikun	0:13413ea9a877	1173	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
ganlikun	0:13413ea9a877	1174	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
ganlikun	0:13413ea9a877	1175	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
ganlikun	0:13413ea9a877	1176	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
ganlikun	0:13413ea9a877	1177	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
ganlikun	0:13413ea9a877	1178	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
ganlikun	0:13413ea9a877	1179	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
ganlikun	0:13413ea9a877	1180	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
ganlikun	0:13413ea9a877	1181	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
ganlikun	0:13413ea9a877	1182	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
ganlikun	0:13413ea9a877	1183	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
ganlikun	0:13413ea9a877	1184	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
ganlikun	0:13413ea9a877	1185	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
ganlikun	0:13413ea9a877	1186	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
ganlikun	0:13413ea9a877	1187	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
ganlikun	0:13413ea9a877	1188	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
ganlikun	0:13413ea9a877	1189	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
ganlikun	0:13413ea9a877	1190	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
ganlikun	0:13413ea9a877	1191	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
ganlikun	0:13413ea9a877	1192	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
ganlikun	0:13413ea9a877	1193	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
ganlikun	0:13413ea9a877	1194	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
ganlikun	0:13413ea9a877	1195	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
ganlikun	0:13413ea9a877	1196	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
ganlikun	0:13413ea9a877	1197	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
ganlikun	0:13413ea9a877	1198	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
ganlikun	0:13413ea9a877	1199	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
ganlikun	0:13413ea9a877	1200	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
ganlikun	0:13413ea9a877	1201	*
ganlikun	0:13413ea9a877	1202	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1203	* @retval None
ganlikun	0:13413ea9a877	1204	*/
ganlikun	0:13413ea9a877	1205	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1206	{
ganlikun	0:13413ea9a877	1207	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1208	SET_BIT(RCC->APB1ENR, Periphs);
ganlikun	0:13413ea9a877	1209	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	1210	tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
ganlikun	0:13413ea9a877	1211	(void)tmpreg;
ganlikun	0:13413ea9a877	1212	}
ganlikun	0:13413ea9a877	1213
ganlikun	0:13413ea9a877	1214	/**
ganlikun	0:13413ea9a877	1215	* @brief Check if APB1 peripheral clock is enabled or not
ganlikun	0:13413ea9a877	1216	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1217	* APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1218	* APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1219	* APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1220	* APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1221	* APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1222	* APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1223	* APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1224	* APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1225	* APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1226	* APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1227	* APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1228	* APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1229	* APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1230	* APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1231	* APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1232	* APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1233	* APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1234	* APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1235	* APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1236	* APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1237	* APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1238	* APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1239	* APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1240	* APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1241	* APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1242	* APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1243	* APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1244	* APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1245	* APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1246	* APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock
ganlikun	0:13413ea9a877	1247	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1248	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
ganlikun	0:13413ea9a877	1249	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
ganlikun	0:13413ea9a877	1250	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
ganlikun	0:13413ea9a877	1251	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
ganlikun	0:13413ea9a877	1252	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
ganlikun	0:13413ea9a877	1253	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
ganlikun	0:13413ea9a877	1254	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
ganlikun	0:13413ea9a877	1255	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
ganlikun	0:13413ea9a877	1256	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
ganlikun	0:13413ea9a877	1257	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
ganlikun	0:13413ea9a877	1258	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
ganlikun	0:13413ea9a877	1259	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
ganlikun	0:13413ea9a877	1260	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
ganlikun	0:13413ea9a877	1261	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
ganlikun	0:13413ea9a877	1262	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
ganlikun	0:13413ea9a877	1263	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
ganlikun	0:13413ea9a877	1264	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
ganlikun	0:13413ea9a877	1265	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
ganlikun	0:13413ea9a877	1266	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
ganlikun	0:13413ea9a877	1267	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
ganlikun	0:13413ea9a877	1268	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
ganlikun	0:13413ea9a877	1269	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
ganlikun	0:13413ea9a877	1270	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
ganlikun	0:13413ea9a877	1271	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
ganlikun	0:13413ea9a877	1272	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
ganlikun	0:13413ea9a877	1273	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
ganlikun	0:13413ea9a877	1274	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
ganlikun	0:13413ea9a877	1275	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
ganlikun	0:13413ea9a877	1276	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
ganlikun	0:13413ea9a877	1277	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
ganlikun	0:13413ea9a877	1278	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
ganlikun	0:13413ea9a877	1279	*
ganlikun	0:13413ea9a877	1280	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1281	* @retval State of Periphs (1 or 0).
ganlikun	0:13413ea9a877	1282	*/
ganlikun	0:13413ea9a877	1283	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1284	{
ganlikun	0:13413ea9a877	1285	return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
ganlikun	0:13413ea9a877	1286	}
ganlikun	0:13413ea9a877	1287
ganlikun	0:13413ea9a877	1288	/**
ganlikun	0:13413ea9a877	1289	* @brief Disable APB1 peripherals clock.
ganlikun	0:13413ea9a877	1290	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1291	* APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1292	* APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1293	* APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1294	* APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1295	* APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1296	* APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1297	* APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1298	* APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1299	* APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1300	* APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1301	* APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1302	* APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1303	* APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1304	* APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1305	* APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1306	* APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1307	* APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1308	* APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1309	* APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1310	* APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1311	* APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1312	* APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1313	* APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1314	* APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1315	* APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1316	* APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1317	* APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1318	* APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1319	* APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1320	* APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock
ganlikun	0:13413ea9a877	1321	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1322	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
ganlikun	0:13413ea9a877	1323	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
ganlikun	0:13413ea9a877	1324	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
ganlikun	0:13413ea9a877	1325	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
ganlikun	0:13413ea9a877	1326	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
ganlikun	0:13413ea9a877	1327	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
ganlikun	0:13413ea9a877	1328	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
ganlikun	0:13413ea9a877	1329	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
ganlikun	0:13413ea9a877	1330	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
ganlikun	0:13413ea9a877	1331	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
ganlikun	0:13413ea9a877	1332	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
ganlikun	0:13413ea9a877	1333	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
ganlikun	0:13413ea9a877	1334	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
ganlikun	0:13413ea9a877	1335	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
ganlikun	0:13413ea9a877	1336	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
ganlikun	0:13413ea9a877	1337	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
ganlikun	0:13413ea9a877	1338	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
ganlikun	0:13413ea9a877	1339	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
ganlikun	0:13413ea9a877	1340	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
ganlikun	0:13413ea9a877	1341	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
ganlikun	0:13413ea9a877	1342	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
ganlikun	0:13413ea9a877	1343	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
ganlikun	0:13413ea9a877	1344	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
ganlikun	0:13413ea9a877	1345	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
ganlikun	0:13413ea9a877	1346	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
ganlikun	0:13413ea9a877	1347	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
ganlikun	0:13413ea9a877	1348	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
ganlikun	0:13413ea9a877	1349	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
ganlikun	0:13413ea9a877	1350	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
ganlikun	0:13413ea9a877	1351	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
ganlikun	0:13413ea9a877	1352	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
ganlikun	0:13413ea9a877	1353	*
ganlikun	0:13413ea9a877	1354	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1355	* @retval None
ganlikun	0:13413ea9a877	1356	*/
ganlikun	0:13413ea9a877	1357	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1358	{
ganlikun	0:13413ea9a877	1359	CLEAR_BIT(RCC->APB1ENR, Periphs);
ganlikun	0:13413ea9a877	1360	}
ganlikun	0:13413ea9a877	1361
ganlikun	0:13413ea9a877	1362	/**
ganlikun	0:13413ea9a877	1363	* @brief Force APB1 peripherals reset.
ganlikun	0:13413ea9a877	1364	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1365	* APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1366	* APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1367	* APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1368	* APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1369	* APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1370	* APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1371	* APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1372	* APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1373	* APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1374	* APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1375	* APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1376	* APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1377	* APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1378	* APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1379	* APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1380	* APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1381	* APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1382	* APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1383	* APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1384	* APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1385	* APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1386	* APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1387	* APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1388	* APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1389	* APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1390	* APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1391	* APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1392	* APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1393	* APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
ganlikun	0:13413ea9a877	1394	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1395	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
ganlikun	0:13413ea9a877	1396	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
ganlikun	0:13413ea9a877	1397	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
ganlikun	0:13413ea9a877	1398	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
ganlikun	0:13413ea9a877	1399	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
ganlikun	0:13413ea9a877	1400	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
ganlikun	0:13413ea9a877	1401	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
ganlikun	0:13413ea9a877	1402	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
ganlikun	0:13413ea9a877	1403	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
ganlikun	0:13413ea9a877	1404	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
ganlikun	0:13413ea9a877	1405	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
ganlikun	0:13413ea9a877	1406	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
ganlikun	0:13413ea9a877	1407	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
ganlikun	0:13413ea9a877	1408	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
ganlikun	0:13413ea9a877	1409	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
ganlikun	0:13413ea9a877	1410	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
ganlikun	0:13413ea9a877	1411	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
ganlikun	0:13413ea9a877	1412	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
ganlikun	0:13413ea9a877	1413	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
ganlikun	0:13413ea9a877	1414	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
ganlikun	0:13413ea9a877	1415	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
ganlikun	0:13413ea9a877	1416	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
ganlikun	0:13413ea9a877	1417	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
ganlikun	0:13413ea9a877	1418	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
ganlikun	0:13413ea9a877	1419	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
ganlikun	0:13413ea9a877	1420	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
ganlikun	0:13413ea9a877	1421	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
ganlikun	0:13413ea9a877	1422	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
ganlikun	0:13413ea9a877	1423	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
ganlikun	0:13413ea9a877	1424	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
ganlikun	0:13413ea9a877	1425	*
ganlikun	0:13413ea9a877	1426	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1427	* @retval None
ganlikun	0:13413ea9a877	1428	*/
ganlikun	0:13413ea9a877	1429	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	1430	{
ganlikun	0:13413ea9a877	1431	SET_BIT(RCC->APB1RSTR, Periphs);
ganlikun	0:13413ea9a877	1432	}
ganlikun	0:13413ea9a877	1433
ganlikun	0:13413ea9a877	1434	/**
ganlikun	0:13413ea9a877	1435	* @brief Release APB1 peripherals reset.
ganlikun	0:13413ea9a877	1436	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1437	* APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1438	* APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1439	* APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1440	* APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1441	* APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1442	* APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1443	* APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1444	* APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1445	* APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1446	* APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1447	* APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1448	* APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1449	* APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1450	* APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1451	* APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1452	* APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1453	* APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1454	* APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1455	* APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1456	* APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1457	* APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1458	* APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1459	* APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1460	* APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1461	* APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1462	* APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1463	* APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1464	* APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1465	* APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
ganlikun	0:13413ea9a877	1466	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1467	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
ganlikun	0:13413ea9a877	1468	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
ganlikun	0:13413ea9a877	1469	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
ganlikun	0:13413ea9a877	1470	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
ganlikun	0:13413ea9a877	1471	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
ganlikun	0:13413ea9a877	1472	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
ganlikun	0:13413ea9a877	1473	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
ganlikun	0:13413ea9a877	1474	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
ganlikun	0:13413ea9a877	1475	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
ganlikun	0:13413ea9a877	1476	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
ganlikun	0:13413ea9a877	1477	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
ganlikun	0:13413ea9a877	1478	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
ganlikun	0:13413ea9a877	1479	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
ganlikun	0:13413ea9a877	1480	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
ganlikun	0:13413ea9a877	1481	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
ganlikun	0:13413ea9a877	1482	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
ganlikun	0:13413ea9a877	1483	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
ganlikun	0:13413ea9a877	1484	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
ganlikun	0:13413ea9a877	1485	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
ganlikun	0:13413ea9a877	1486	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
ganlikun	0:13413ea9a877	1487	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
ganlikun	0:13413ea9a877	1488	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
ganlikun	0:13413ea9a877	1489	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
ganlikun	0:13413ea9a877	1490	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
ganlikun	0:13413ea9a877	1491	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
ganlikun	0:13413ea9a877	1492	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
ganlikun	0:13413ea9a877	1493	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
ganlikun	0:13413ea9a877	1494	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
ganlikun	0:13413ea9a877	1495	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
ganlikun	0:13413ea9a877	1496	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
ganlikun	0:13413ea9a877	1497	*
ganlikun	0:13413ea9a877	1498	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1499	* @retval None
ganlikun	0:13413ea9a877	1500	*/
ganlikun	0:13413ea9a877	1501	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	1502	{
ganlikun	0:13413ea9a877	1503	CLEAR_BIT(RCC->APB1RSTR, Periphs);
ganlikun	0:13413ea9a877	1504	}
ganlikun	0:13413ea9a877	1505
ganlikun	0:13413ea9a877	1506	/**
ganlikun	0:13413ea9a877	1507	* @brief Enable APB1 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	1508	* @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1509	* APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1510	* APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1511	* APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1512	* APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1513	* APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1514	* APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1515	* APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1516	* APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1517	* APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1518	* APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1519	* APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1520	* APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1521	* APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1522	* APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1523	* APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1524	* APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1525	* APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1526	* APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1527	* APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1528	* APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1529	* APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1530	* APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1531	* APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1532	* APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1533	* APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1534	* APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1535	* APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1536	* APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1537	* APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1538	* APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower
ganlikun	0:13413ea9a877	1539	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1540	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
ganlikun	0:13413ea9a877	1541	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
ganlikun	0:13413ea9a877	1542	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
ganlikun	0:13413ea9a877	1543	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
ganlikun	0:13413ea9a877	1544	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
ganlikun	0:13413ea9a877	1545	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
ganlikun	0:13413ea9a877	1546	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
ganlikun	0:13413ea9a877	1547	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
ganlikun	0:13413ea9a877	1548	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
ganlikun	0:13413ea9a877	1549	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
ganlikun	0:13413ea9a877	1550	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
ganlikun	0:13413ea9a877	1551	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
ganlikun	0:13413ea9a877	1552	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
ganlikun	0:13413ea9a877	1553	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
ganlikun	0:13413ea9a877	1554	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
ganlikun	0:13413ea9a877	1555	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
ganlikun	0:13413ea9a877	1556	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
ganlikun	0:13413ea9a877	1557	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
ganlikun	0:13413ea9a877	1558	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
ganlikun	0:13413ea9a877	1559	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
ganlikun	0:13413ea9a877	1560	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
ganlikun	0:13413ea9a877	1561	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
ganlikun	0:13413ea9a877	1562	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
ganlikun	0:13413ea9a877	1563	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
ganlikun	0:13413ea9a877	1564	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
ganlikun	0:13413ea9a877	1565	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
ganlikun	0:13413ea9a877	1566	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
ganlikun	0:13413ea9a877	1567	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
ganlikun	0:13413ea9a877	1568	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
ganlikun	0:13413ea9a877	1569	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
ganlikun	0:13413ea9a877	1570	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
ganlikun	0:13413ea9a877	1571	*
ganlikun	0:13413ea9a877	1572	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1573	* @retval None
ganlikun	0:13413ea9a877	1574	*/
ganlikun	0:13413ea9a877	1575	__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	1576	{
ganlikun	0:13413ea9a877	1577	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1578	SET_BIT(RCC->APB1LPENR, Periphs);
ganlikun	0:13413ea9a877	1579	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	1580	tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
ganlikun	0:13413ea9a877	1581	(void)tmpreg;
ganlikun	0:13413ea9a877	1582	}
ganlikun	0:13413ea9a877	1583
ganlikun	0:13413ea9a877	1584	/**
ganlikun	0:13413ea9a877	1585	* @brief Disable APB1 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	1586	* @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1587	* APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1588	* APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1589	* APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1590	* APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1591	* APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1592	* APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1593	* APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1594	* APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1595	* APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1596	* APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1597	* APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1598	* APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1599	* APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1600	* APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1601	* APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1602	* APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1603	* APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1604	* APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1605	* APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1606	* APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1607	* APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1608	* APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1609	* APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1610	* APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1611	* APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1612	* APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1613	* APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1614	* APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1615	* APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	1616	* APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower
ganlikun	0:13413ea9a877	1617	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1618	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
ganlikun	0:13413ea9a877	1619	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
ganlikun	0:13413ea9a877	1620	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
ganlikun	0:13413ea9a877	1621	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
ganlikun	0:13413ea9a877	1622	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
ganlikun	0:13413ea9a877	1623	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
ganlikun	0:13413ea9a877	1624	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
ganlikun	0:13413ea9a877	1625	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
ganlikun	0:13413ea9a877	1626	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
ganlikun	0:13413ea9a877	1627	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
ganlikun	0:13413ea9a877	1628	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
ganlikun	0:13413ea9a877	1629	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
ganlikun	0:13413ea9a877	1630	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
ganlikun	0:13413ea9a877	1631	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
ganlikun	0:13413ea9a877	1632	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
ganlikun	0:13413ea9a877	1633	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
ganlikun	0:13413ea9a877	1634	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
ganlikun	0:13413ea9a877	1635	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
ganlikun	0:13413ea9a877	1636	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
ganlikun	0:13413ea9a877	1637	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
ganlikun	0:13413ea9a877	1638	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
ganlikun	0:13413ea9a877	1639	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
ganlikun	0:13413ea9a877	1640	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
ganlikun	0:13413ea9a877	1641	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
ganlikun	0:13413ea9a877	1642	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
ganlikun	0:13413ea9a877	1643	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
ganlikun	0:13413ea9a877	1644	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
ganlikun	0:13413ea9a877	1645	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
ganlikun	0:13413ea9a877	1646	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
ganlikun	0:13413ea9a877	1647	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
ganlikun	0:13413ea9a877	1648	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
ganlikun	0:13413ea9a877	1649	*
ganlikun	0:13413ea9a877	1650	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1651	* @retval None
ganlikun	0:13413ea9a877	1652	*/
ganlikun	0:13413ea9a877	1653	__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	1654	{
ganlikun	0:13413ea9a877	1655	CLEAR_BIT(RCC->APB1LPENR, Periphs);
ganlikun	0:13413ea9a877	1656	}
ganlikun	0:13413ea9a877	1657
ganlikun	0:13413ea9a877	1658	/**
ganlikun	0:13413ea9a877	1659	* @}
ganlikun	0:13413ea9a877	1660	*/
ganlikun	0:13413ea9a877	1661
ganlikun	0:13413ea9a877	1662	/** @defgroup BUS_LL_EF_APB2 APB2
ganlikun	0:13413ea9a877	1663	* @{
ganlikun	0:13413ea9a877	1664	*/
ganlikun	0:13413ea9a877	1665
ganlikun	0:13413ea9a877	1666	/**
ganlikun	0:13413ea9a877	1667	* @brief Enable APB2 peripherals clock.
ganlikun	0:13413ea9a877	1668	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1669	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1670	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1671	* APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1672	* APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1673	* APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1674	* APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1675	* APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1676	* APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1677	* APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1678	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1679	* APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1680	* APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1681	* APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1682	* APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1683	* APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1684	* APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1685	* APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1686	* APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1687	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1688	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1689	* APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1690	* APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1691	* APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
ganlikun	0:13413ea9a877	1692	* APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock
ganlikun	0:13413ea9a877	1693	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1694	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
ganlikun	0:13413ea9a877	1695	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
ganlikun	0:13413ea9a877	1696	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
ganlikun	0:13413ea9a877	1697	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
ganlikun	0:13413ea9a877	1698	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
ganlikun	0:13413ea9a877	1699	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
ganlikun	0:13413ea9a877	1700	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
ganlikun	0:13413ea9a877	1701	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
ganlikun	0:13413ea9a877	1702	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
ganlikun	0:13413ea9a877	1703	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
ganlikun	0:13413ea9a877	1704	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
ganlikun	0:13413ea9a877	1705	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
ganlikun	0:13413ea9a877	1706	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
ganlikun	0:13413ea9a877	1707	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
ganlikun	0:13413ea9a877	1708	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
ganlikun	0:13413ea9a877	1709	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
ganlikun	0:13413ea9a877	1710	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
ganlikun	0:13413ea9a877	1711	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
ganlikun	0:13413ea9a877	1712	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
ganlikun	0:13413ea9a877	1713	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
ganlikun	0:13413ea9a877	1714	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
ganlikun	0:13413ea9a877	1715	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
ganlikun	0:13413ea9a877	1716	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
ganlikun	0:13413ea9a877	1717	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
ganlikun	0:13413ea9a877	1718	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
ganlikun	0:13413ea9a877	1719
ganlikun	0:13413ea9a877	1720	*
ganlikun	0:13413ea9a877	1721	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1722	* @retval None
ganlikun	0:13413ea9a877	1723	*/
ganlikun	0:13413ea9a877	1724	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1725	{
ganlikun	0:13413ea9a877	1726	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1727	SET_BIT(RCC->APB2ENR, Periphs);
ganlikun	0:13413ea9a877	1728	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	1729	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
ganlikun	0:13413ea9a877	1730	(void)tmpreg;
ganlikun	0:13413ea9a877	1731	}
ganlikun	0:13413ea9a877	1732
ganlikun	0:13413ea9a877	1733	/**
ganlikun	0:13413ea9a877	1734	* @brief Check if APB2 peripheral clock is enabled or not
ganlikun	0:13413ea9a877	1735	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1736	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1737	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1738	* APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1739	* APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1740	* APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1741	* APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1742	* APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1743	* APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1744	* APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1745	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1746	* APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1747	* APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1748	* APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1749	* APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1750	* APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1751	* APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1752	* APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1753	* APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1754	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1755	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1756	* APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1757	* APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1758	* APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
ganlikun	0:13413ea9a877	1759	* APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock
ganlikun	0:13413ea9a877	1760	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1761	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
ganlikun	0:13413ea9a877	1762	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
ganlikun	0:13413ea9a877	1763	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
ganlikun	0:13413ea9a877	1764	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
ganlikun	0:13413ea9a877	1765	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
ganlikun	0:13413ea9a877	1766	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
ganlikun	0:13413ea9a877	1767	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
ganlikun	0:13413ea9a877	1768	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
ganlikun	0:13413ea9a877	1769	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
ganlikun	0:13413ea9a877	1770	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
ganlikun	0:13413ea9a877	1771	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
ganlikun	0:13413ea9a877	1772	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
ganlikun	0:13413ea9a877	1773	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
ganlikun	0:13413ea9a877	1774	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
ganlikun	0:13413ea9a877	1775	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
ganlikun	0:13413ea9a877	1776	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
ganlikun	0:13413ea9a877	1777	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
ganlikun	0:13413ea9a877	1778	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
ganlikun	0:13413ea9a877	1779	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
ganlikun	0:13413ea9a877	1780	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
ganlikun	0:13413ea9a877	1781	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
ganlikun	0:13413ea9a877	1782	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
ganlikun	0:13413ea9a877	1783	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
ganlikun	0:13413ea9a877	1784	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
ganlikun	0:13413ea9a877	1785	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
ganlikun	0:13413ea9a877	1786	*
ganlikun	0:13413ea9a877	1787	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1788	* @retval State of Periphs (1 or 0).
ganlikun	0:13413ea9a877	1789	*/
ganlikun	0:13413ea9a877	1790	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1791	{
ganlikun	0:13413ea9a877	1792	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
ganlikun	0:13413ea9a877	1793	}
ganlikun	0:13413ea9a877	1794
ganlikun	0:13413ea9a877	1795	/**
ganlikun	0:13413ea9a877	1796	* @brief Disable APB2 peripherals clock.
ganlikun	0:13413ea9a877	1797	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1798	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1799	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1800	* APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1801	* APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1802	* APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1803	* APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1804	* APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1805	* APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1806	* APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1807	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1808	* APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1809	* APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1810	* APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1811	* APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1812	* APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1813	* APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1814	* APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1815	* APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1816	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1817	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1818	* APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1819	* APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1820	* APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
ganlikun	0:13413ea9a877	1821	* APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock
ganlikun	0:13413ea9a877	1822	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1823	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
ganlikun	0:13413ea9a877	1824	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
ganlikun	0:13413ea9a877	1825	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
ganlikun	0:13413ea9a877	1826	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
ganlikun	0:13413ea9a877	1827	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
ganlikun	0:13413ea9a877	1828	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
ganlikun	0:13413ea9a877	1829	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
ganlikun	0:13413ea9a877	1830	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
ganlikun	0:13413ea9a877	1831	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
ganlikun	0:13413ea9a877	1832	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
ganlikun	0:13413ea9a877	1833	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
ganlikun	0:13413ea9a877	1834	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
ganlikun	0:13413ea9a877	1835	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
ganlikun	0:13413ea9a877	1836	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
ganlikun	0:13413ea9a877	1837	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
ganlikun	0:13413ea9a877	1838	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
ganlikun	0:13413ea9a877	1839	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
ganlikun	0:13413ea9a877	1840	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
ganlikun	0:13413ea9a877	1841	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
ganlikun	0:13413ea9a877	1842	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
ganlikun	0:13413ea9a877	1843	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
ganlikun	0:13413ea9a877	1844	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
ganlikun	0:13413ea9a877	1845	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
ganlikun	0:13413ea9a877	1846	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
ganlikun	0:13413ea9a877	1847	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
ganlikun	0:13413ea9a877	1848	*
ganlikun	0:13413ea9a877	1849	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1850	* @retval None
ganlikun	0:13413ea9a877	1851	*/
ganlikun	0:13413ea9a877	1852	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
ganlikun	0:13413ea9a877	1853	{
ganlikun	0:13413ea9a877	1854	CLEAR_BIT(RCC->APB2ENR, Periphs);
ganlikun	0:13413ea9a877	1855	}
ganlikun	0:13413ea9a877	1856
ganlikun	0:13413ea9a877	1857	/**
ganlikun	0:13413ea9a877	1858	* @brief Force APB2 peripherals reset.
ganlikun	0:13413ea9a877	1859	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1860	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1861	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1862	* APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1863	* APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1864	* APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1865	* APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1866	* APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1867	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1868	* APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1869	* APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1870	* APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1871	* APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1872	* APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1873	* APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1874	* APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1875	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1876	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1877	* APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1878	* APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1879	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
ganlikun	0:13413ea9a877	1880	* APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset
ganlikun	0:13413ea9a877	1881	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1882	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	1883	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
ganlikun	0:13413ea9a877	1884	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
ganlikun	0:13413ea9a877	1885	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
ganlikun	0:13413ea9a877	1886	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
ganlikun	0:13413ea9a877	1887	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
ganlikun	0:13413ea9a877	1888	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
ganlikun	0:13413ea9a877	1889	* @arg @ref LL_APB2_GRP1_PERIPH_ADC
ganlikun	0:13413ea9a877	1890	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
ganlikun	0:13413ea9a877	1891	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
ganlikun	0:13413ea9a877	1892	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
ganlikun	0:13413ea9a877	1893	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
ganlikun	0:13413ea9a877	1894	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
ganlikun	0:13413ea9a877	1895	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
ganlikun	0:13413ea9a877	1896	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
ganlikun	0:13413ea9a877	1897	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
ganlikun	0:13413ea9a877	1898	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
ganlikun	0:13413ea9a877	1899	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
ganlikun	0:13413ea9a877	1900	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
ganlikun	0:13413ea9a877	1901	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
ganlikun	0:13413ea9a877	1902	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
ganlikun	0:13413ea9a877	1903	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
ganlikun	0:13413ea9a877	1904	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
ganlikun	0:13413ea9a877	1905	*
ganlikun	0:13413ea9a877	1906	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1907	* @retval None
ganlikun	0:13413ea9a877	1908	*/
ganlikun	0:13413ea9a877	1909	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	1910	{
ganlikun	0:13413ea9a877	1911	SET_BIT(RCC->APB2RSTR, Periphs);
ganlikun	0:13413ea9a877	1912	}
ganlikun	0:13413ea9a877	1913
ganlikun	0:13413ea9a877	1914	/**
ganlikun	0:13413ea9a877	1915	* @brief Release APB2 peripherals reset.
ganlikun	0:13413ea9a877	1916	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1917	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1918	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1919	* APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1920	* APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1921	* APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1922	* APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1923	* APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1924	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1925	* APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1926	* APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1927	* APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1928	* APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1929	* APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1930	* APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1931	* APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1932	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1933	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1934	* APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1935	* APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1936	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
ganlikun	0:13413ea9a877	1937	* APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset
ganlikun	0:13413ea9a877	1938	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1939	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
ganlikun	0:13413ea9a877	1940	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
ganlikun	0:13413ea9a877	1941	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
ganlikun	0:13413ea9a877	1942	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
ganlikun	0:13413ea9a877	1943	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
ganlikun	0:13413ea9a877	1944	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
ganlikun	0:13413ea9a877	1945	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
ganlikun	0:13413ea9a877	1946	* @arg @ref LL_APB2_GRP1_PERIPH_ADC
ganlikun	0:13413ea9a877	1947	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
ganlikun	0:13413ea9a877	1948	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
ganlikun	0:13413ea9a877	1949	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
ganlikun	0:13413ea9a877	1950	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
ganlikun	0:13413ea9a877	1951	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
ganlikun	0:13413ea9a877	1952	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
ganlikun	0:13413ea9a877	1953	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
ganlikun	0:13413ea9a877	1954	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
ganlikun	0:13413ea9a877	1955	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
ganlikun	0:13413ea9a877	1956	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
ganlikun	0:13413ea9a877	1957	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
ganlikun	0:13413ea9a877	1958	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
ganlikun	0:13413ea9a877	1959	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
ganlikun	0:13413ea9a877	1960	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
ganlikun	0:13413ea9a877	1961	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
ganlikun	0:13413ea9a877	1962	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
ganlikun	0:13413ea9a877	1963	*
ganlikun	0:13413ea9a877	1964	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1965	* @retval None
ganlikun	0:13413ea9a877	1966	*/
ganlikun	0:13413ea9a877	1967	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
ganlikun	0:13413ea9a877	1968	{
ganlikun	0:13413ea9a877	1969	CLEAR_BIT(RCC->APB2RSTR, Periphs);
ganlikun	0:13413ea9a877	1970	}
ganlikun	0:13413ea9a877	1971
ganlikun	0:13413ea9a877	1972	/**
ganlikun	0:13413ea9a877	1973	* @brief Enable APB2 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	1974	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1975	* APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1976	* APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1977	* APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1978	* APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1979	* APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1980	* APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1981	* APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1982	* APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1983	* APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1984	* APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1985	* APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1986	* APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1987	* APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1988	* APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1989	* APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1990	* APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1991	* APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1992	* APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1993	* APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1994	* APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1995	* APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1996	* APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1997	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1998	* APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
ganlikun	0:13413ea9a877	1999	* APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower
ganlikun	0:13413ea9a877	2000	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	2001	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
ganlikun	0:13413ea9a877	2002	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
ganlikun	0:13413ea9a877	2003	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
ganlikun	0:13413ea9a877	2004	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
ganlikun	0:13413ea9a877	2005	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
ganlikun	0:13413ea9a877	2006	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
ganlikun	0:13413ea9a877	2007	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
ganlikun	0:13413ea9a877	2008	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
ganlikun	0:13413ea9a877	2009	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
ganlikun	0:13413ea9a877	2010	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
ganlikun	0:13413ea9a877	2011	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
ganlikun	0:13413ea9a877	2012	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
ganlikun	0:13413ea9a877	2013	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
ganlikun	0:13413ea9a877	2014	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
ganlikun	0:13413ea9a877	2015	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
ganlikun	0:13413ea9a877	2016	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
ganlikun	0:13413ea9a877	2017	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
ganlikun	0:13413ea9a877	2018	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
ganlikun	0:13413ea9a877	2019	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
ganlikun	0:13413ea9a877	2020	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
ganlikun	0:13413ea9a877	2021	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
ganlikun	0:13413ea9a877	2022	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
ganlikun	0:13413ea9a877	2023	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
ganlikun	0:13413ea9a877	2024	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
ganlikun	0:13413ea9a877	2025	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
ganlikun	0:13413ea9a877	2026	*
ganlikun	0:13413ea9a877	2027	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2028	* @retval None
ganlikun	0:13413ea9a877	2029	*/
ganlikun	0:13413ea9a877	2030	__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	2031	{
ganlikun	0:13413ea9a877	2032	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	2033	SET_BIT(RCC->APB2LPENR, Periphs);
ganlikun	0:13413ea9a877	2034	/* Delay after an RCC peripheral clock enabling */
ganlikun	0:13413ea9a877	2035	tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
ganlikun	0:13413ea9a877	2036	(void)tmpreg;
ganlikun	0:13413ea9a877	2037	}
ganlikun	0:13413ea9a877	2038
ganlikun	0:13413ea9a877	2039	/**
ganlikun	0:13413ea9a877	2040	* @brief Disable APB2 peripheral clocks in low-power mode
ganlikun	0:13413ea9a877	2041	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2042	* APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2043	* APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2044	* APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2045	* APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2046	* APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2047	* APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2048	* APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2049	* APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2050	* APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2051	* APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2052	* APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2053	* APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2054	* APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2055	* APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2056	* APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2057	* APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2058	* APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2059	* APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2060	* APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2061	* APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2062	* APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2063	* APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2064	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2065	* APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
ganlikun	0:13413ea9a877	2066	* APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower
ganlikun	0:13413ea9a877	2067	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	2068	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
ganlikun	0:13413ea9a877	2069	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
ganlikun	0:13413ea9a877	2070	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
ganlikun	0:13413ea9a877	2071	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
ganlikun	0:13413ea9a877	2072	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
ganlikun	0:13413ea9a877	2073	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
ganlikun	0:13413ea9a877	2074	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
ganlikun	0:13413ea9a877	2075	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
ganlikun	0:13413ea9a877	2076	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
ganlikun	0:13413ea9a877	2077	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
ganlikun	0:13413ea9a877	2078	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
ganlikun	0:13413ea9a877	2079	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
ganlikun	0:13413ea9a877	2080	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
ganlikun	0:13413ea9a877	2081	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
ganlikun	0:13413ea9a877	2082	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
ganlikun	0:13413ea9a877	2083	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
ganlikun	0:13413ea9a877	2084	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
ganlikun	0:13413ea9a877	2085	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
ganlikun	0:13413ea9a877	2086	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
ganlikun	0:13413ea9a877	2087	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
ganlikun	0:13413ea9a877	2088	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
ganlikun	0:13413ea9a877	2089	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
ganlikun	0:13413ea9a877	2090	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
ganlikun	0:13413ea9a877	2091	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
ganlikun	0:13413ea9a877	2092	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
ganlikun	0:13413ea9a877	2093	*
ganlikun	0:13413ea9a877	2094	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2095	* @retval None
ganlikun	0:13413ea9a877	2096	*/
ganlikun	0:13413ea9a877	2097	__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
ganlikun	0:13413ea9a877	2098	{
ganlikun	0:13413ea9a877	2099	CLEAR_BIT(RCC->APB2LPENR, Periphs);
ganlikun	0:13413ea9a877	2100	}
ganlikun	0:13413ea9a877	2101
ganlikun	0:13413ea9a877	2102	/**
ganlikun	0:13413ea9a877	2103	* @}
ganlikun	0:13413ea9a877	2104	*/
ganlikun	0:13413ea9a877	2105
ganlikun	0:13413ea9a877	2106	/**
ganlikun	0:13413ea9a877	2107	* @}
ganlikun	0:13413ea9a877	2108	*/
ganlikun	0:13413ea9a877	2109
ganlikun	0:13413ea9a877	2110	/**
ganlikun	0:13413ea9a877	2111	* @}
ganlikun	0:13413ea9a877	2112	*/
ganlikun	0:13413ea9a877	2113
ganlikun	0:13413ea9a877	2114	#endif /* defined(RCC) */
ganlikun	0:13413ea9a877	2115
ganlikun	0:13413ea9a877	2116	/**
ganlikun	0:13413ea9a877	2117	* @}
ganlikun	0:13413ea9a877	2118	*/
ganlikun	0:13413ea9a877	2119
ganlikun	0:13413ea9a877	2120	#ifdef __cplusplus
ganlikun	0:13413ea9a877	2121	}
ganlikun	0:13413ea9a877	2122	#endif
ganlikun	0:13413ea9a877	2123
ganlikun	0:13413ea9a877	2124	#endif /* __STM32F4xx_LL_BUS_H */
ganlikun	0:13413ea9a877	2125
ganlikun	0:13413ea9a877	2126	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	2127

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h@0:13413ea9a877, 2022-06-12 (annotated)

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