Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

Who changed what in which revision?

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ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_ll_adc.c
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief ADC LL module driver
ganlikun 0:13413ea9a877 8 ******************************************************************************
ganlikun 0:13413ea9a877 9 * @attention
ganlikun 0:13413ea9a877 10 *
ganlikun 0:13413ea9a877 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 12 *
ganlikun 0:13413ea9a877 13 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 14 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 15 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 16 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 18 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 19 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 21 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 22 * without specific prior written permission.
ganlikun 0:13413ea9a877 23 *
ganlikun 0:13413ea9a877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 34 *
ganlikun 0:13413ea9a877 35 ******************************************************************************
ganlikun 0:13413ea9a877 36 */
ganlikun 0:13413ea9a877 37 #if defined(USE_FULL_LL_DRIVER)
ganlikun 0:13413ea9a877 38
ganlikun 0:13413ea9a877 39 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 40 #include "stm32f4xx_ll_adc.h"
ganlikun 0:13413ea9a877 41 #include "stm32f4xx_ll_bus.h"
ganlikun 0:13413ea9a877 42
ganlikun 0:13413ea9a877 43 #ifdef USE_FULL_ASSERT
ganlikun 0:13413ea9a877 44 #include "stm32_assert.h"
ganlikun 0:13413ea9a877 45 #else
ganlikun 0:13413ea9a877 46 #define assert_param(expr) ((void)0U)
ganlikun 0:13413ea9a877 47 #endif
ganlikun 0:13413ea9a877 48
ganlikun 0:13413ea9a877 49 /** @addtogroup STM32F4xx_LL_Driver
ganlikun 0:13413ea9a877 50 * @{
ganlikun 0:13413ea9a877 51 */
ganlikun 0:13413ea9a877 52
ganlikun 0:13413ea9a877 53 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
ganlikun 0:13413ea9a877 54
ganlikun 0:13413ea9a877 55 /** @addtogroup ADC_LL ADC
ganlikun 0:13413ea9a877 56 * @{
ganlikun 0:13413ea9a877 57 */
ganlikun 0:13413ea9a877 58
ganlikun 0:13413ea9a877 59 /* Private types -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 60 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 61 /* Private constants ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 62 /* Private macros ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 63
ganlikun 0:13413ea9a877 64 /** @addtogroup ADC_LL_Private_Macros
ganlikun 0:13413ea9a877 65 * @{
ganlikun 0:13413ea9a877 66 */
ganlikun 0:13413ea9a877 67
ganlikun 0:13413ea9a877 68 /* Check of parameters for configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 69 /* common to several ADC instances. */
ganlikun 0:13413ea9a877 70 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
ganlikun 0:13413ea9a877 71 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
ganlikun 0:13413ea9a877 72 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
ganlikun 0:13413ea9a877 73 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
ganlikun 0:13413ea9a877 74 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
ganlikun 0:13413ea9a877 75 )
ganlikun 0:13413ea9a877 76
ganlikun 0:13413ea9a877 77 /* Check of parameters for configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 78 /* ADC instance. */
ganlikun 0:13413ea9a877 79 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
ganlikun 0:13413ea9a877 80 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
ganlikun 0:13413ea9a877 81 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
ganlikun 0:13413ea9a877 82 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
ganlikun 0:13413ea9a877 83 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
ganlikun 0:13413ea9a877 84 )
ganlikun 0:13413ea9a877 85
ganlikun 0:13413ea9a877 86 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
ganlikun 0:13413ea9a877 87 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
ganlikun 0:13413ea9a877 88 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
ganlikun 0:13413ea9a877 89 )
ganlikun 0:13413ea9a877 90
ganlikun 0:13413ea9a877 91 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
ganlikun 0:13413ea9a877 92 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
ganlikun 0:13413ea9a877 93 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
ganlikun 0:13413ea9a877 94 )
ganlikun 0:13413ea9a877 95
ganlikun 0:13413ea9a877 96 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
ganlikun 0:13413ea9a877 97 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
ganlikun 0:13413ea9a877 98 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
ganlikun 0:13413ea9a877 99 )
ganlikun 0:13413ea9a877 100
ganlikun 0:13413ea9a877 101 /* Check of parameters for configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 102 /* ADC group regular */
ganlikun 0:13413ea9a877 103 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
ganlikun 0:13413ea9a877 104 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
ganlikun 0:13413ea9a877 105 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
ganlikun 0:13413ea9a877 106 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
ganlikun 0:13413ea9a877 107 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
ganlikun 0:13413ea9a877 108 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
ganlikun 0:13413ea9a877 109 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
ganlikun 0:13413ea9a877 110 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
ganlikun 0:13413ea9a877 111 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
ganlikun 0:13413ea9a877 112 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
ganlikun 0:13413ea9a877 113 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
ganlikun 0:13413ea9a877 114 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
ganlikun 0:13413ea9a877 115 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
ganlikun 0:13413ea9a877 116 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
ganlikun 0:13413ea9a877 117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
ganlikun 0:13413ea9a877 118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
ganlikun 0:13413ea9a877 119 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
ganlikun 0:13413ea9a877 120 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
ganlikun 0:13413ea9a877 121 )
ganlikun 0:13413ea9a877 122 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
ganlikun 0:13413ea9a877 123 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
ganlikun 0:13413ea9a877 124 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
ganlikun 0:13413ea9a877 125 )
ganlikun 0:13413ea9a877 126
ganlikun 0:13413ea9a877 127 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
ganlikun 0:13413ea9a877 128 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
ganlikun 0:13413ea9a877 129 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
ganlikun 0:13413ea9a877 130 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
ganlikun 0:13413ea9a877 131 )
ganlikun 0:13413ea9a877 132
ganlikun 0:13413ea9a877 133 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
ganlikun 0:13413ea9a877 134 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
ganlikun 0:13413ea9a877 135 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
ganlikun 0:13413ea9a877 136 )
ganlikun 0:13413ea9a877 137
ganlikun 0:13413ea9a877 138 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
ganlikun 0:13413ea9a877 139 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
ganlikun 0:13413ea9a877 140 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
ganlikun 0:13413ea9a877 141 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
ganlikun 0:13413ea9a877 142 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
ganlikun 0:13413ea9a877 143 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
ganlikun 0:13413ea9a877 144 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
ganlikun 0:13413ea9a877 145 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
ganlikun 0:13413ea9a877 146 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
ganlikun 0:13413ea9a877 147 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
ganlikun 0:13413ea9a877 148 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
ganlikun 0:13413ea9a877 149 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
ganlikun 0:13413ea9a877 150 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
ganlikun 0:13413ea9a877 151 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
ganlikun 0:13413ea9a877 152 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
ganlikun 0:13413ea9a877 153 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
ganlikun 0:13413ea9a877 154 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
ganlikun 0:13413ea9a877 155 )
ganlikun 0:13413ea9a877 156
ganlikun 0:13413ea9a877 157 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
ganlikun 0:13413ea9a877 158 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
ganlikun 0:13413ea9a877 159 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
ganlikun 0:13413ea9a877 160 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
ganlikun 0:13413ea9a877 161 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
ganlikun 0:13413ea9a877 162 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
ganlikun 0:13413ea9a877 163 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
ganlikun 0:13413ea9a877 164 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
ganlikun 0:13413ea9a877 165 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
ganlikun 0:13413ea9a877 166 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
ganlikun 0:13413ea9a877 167 )
ganlikun 0:13413ea9a877 168
ganlikun 0:13413ea9a877 169 /* Check of parameters for configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 170 /* ADC group injected */
ganlikun 0:13413ea9a877 171 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
ganlikun 0:13413ea9a877 172 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
ganlikun 0:13413ea9a877 173 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
ganlikun 0:13413ea9a877 174 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
ganlikun 0:13413ea9a877 175 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
ganlikun 0:13413ea9a877 176 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
ganlikun 0:13413ea9a877 177 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
ganlikun 0:13413ea9a877 178 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
ganlikun 0:13413ea9a877 179 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
ganlikun 0:13413ea9a877 180 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
ganlikun 0:13413ea9a877 181 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
ganlikun 0:13413ea9a877 182 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
ganlikun 0:13413ea9a877 183 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
ganlikun 0:13413ea9a877 184 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
ganlikun 0:13413ea9a877 185 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
ganlikun 0:13413ea9a877 186 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
ganlikun 0:13413ea9a877 187 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
ganlikun 0:13413ea9a877 188 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
ganlikun 0:13413ea9a877 189 )
ganlikun 0:13413ea9a877 190
ganlikun 0:13413ea9a877 191 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
ganlikun 0:13413ea9a877 192 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
ganlikun 0:13413ea9a877 193 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
ganlikun 0:13413ea9a877 194 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
ganlikun 0:13413ea9a877 195 )
ganlikun 0:13413ea9a877 196
ganlikun 0:13413ea9a877 197 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
ganlikun 0:13413ea9a877 198 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
ganlikun 0:13413ea9a877 199 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
ganlikun 0:13413ea9a877 200 )
ganlikun 0:13413ea9a877 201
ganlikun 0:13413ea9a877 202 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
ganlikun 0:13413ea9a877 203 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
ganlikun 0:13413ea9a877 204 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
ganlikun 0:13413ea9a877 205 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
ganlikun 0:13413ea9a877 206 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
ganlikun 0:13413ea9a877 207 )
ganlikun 0:13413ea9a877 208
ganlikun 0:13413ea9a877 209 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
ganlikun 0:13413ea9a877 210 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
ganlikun 0:13413ea9a877 211 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
ganlikun 0:13413ea9a877 212 )
ganlikun 0:13413ea9a877 213
ganlikun 0:13413ea9a877 214 #if defined(ADC_MULTIMODE_SUPPORT)
ganlikun 0:13413ea9a877 215 /* Check of parameters for configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 216 /* multimode. */
ganlikun 0:13413ea9a877 217 #if defined(ADC3)
ganlikun 0:13413ea9a877 218 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
ganlikun 0:13413ea9a877 219 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
ganlikun 0:13413ea9a877 220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
ganlikun 0:13413ea9a877 221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
ganlikun 0:13413ea9a877 222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
ganlikun 0:13413ea9a877 223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
ganlikun 0:13413ea9a877 224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
ganlikun 0:13413ea9a877 225 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
ganlikun 0:13413ea9a877 226 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
ganlikun 0:13413ea9a877 227 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
ganlikun 0:13413ea9a877 228 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
ganlikun 0:13413ea9a877 229 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
ganlikun 0:13413ea9a877 230 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
ganlikun 0:13413ea9a877 231 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
ganlikun 0:13413ea9a877 232 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
ganlikun 0:13413ea9a877 233 )
ganlikun 0:13413ea9a877 234 #else
ganlikun 0:13413ea9a877 235 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
ganlikun 0:13413ea9a877 236 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
ganlikun 0:13413ea9a877 237 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
ganlikun 0:13413ea9a877 238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
ganlikun 0:13413ea9a877 239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
ganlikun 0:13413ea9a877 240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
ganlikun 0:13413ea9a877 241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
ganlikun 0:13413ea9a877 242 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
ganlikun 0:13413ea9a877 243 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
ganlikun 0:13413ea9a877 244 )
ganlikun 0:13413ea9a877 245 #endif
ganlikun 0:13413ea9a877 246
ganlikun 0:13413ea9a877 247 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
ganlikun 0:13413ea9a877 248 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
ganlikun 0:13413ea9a877 249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
ganlikun 0:13413ea9a877 250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
ganlikun 0:13413ea9a877 251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
ganlikun 0:13413ea9a877 252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
ganlikun 0:13413ea9a877 253 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
ganlikun 0:13413ea9a877 254 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
ganlikun 0:13413ea9a877 255 )
ganlikun 0:13413ea9a877 256
ganlikun 0:13413ea9a877 257 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
ganlikun 0:13413ea9a877 258 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
ganlikun 0:13413ea9a877 259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
ganlikun 0:13413ea9a877 260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
ganlikun 0:13413ea9a877 261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
ganlikun 0:13413ea9a877 262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
ganlikun 0:13413ea9a877 263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
ganlikun 0:13413ea9a877 264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
ganlikun 0:13413ea9a877 265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
ganlikun 0:13413ea9a877 266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
ganlikun 0:13413ea9a877 267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
ganlikun 0:13413ea9a877 268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
ganlikun 0:13413ea9a877 269 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
ganlikun 0:13413ea9a877 270 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
ganlikun 0:13413ea9a877 271 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
ganlikun 0:13413ea9a877 272 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
ganlikun 0:13413ea9a877 273 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
ganlikun 0:13413ea9a877 274 )
ganlikun 0:13413ea9a877 275
ganlikun 0:13413ea9a877 276 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
ganlikun 0:13413ea9a877 277 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
ganlikun 0:13413ea9a877 278 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
ganlikun 0:13413ea9a877 279 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
ganlikun 0:13413ea9a877 280 )
ganlikun 0:13413ea9a877 281
ganlikun 0:13413ea9a877 282 #endif /* ADC_MULTIMODE_SUPPORT */
ganlikun 0:13413ea9a877 283 /**
ganlikun 0:13413ea9a877 284 * @}
ganlikun 0:13413ea9a877 285 */
ganlikun 0:13413ea9a877 286
ganlikun 0:13413ea9a877 287
ganlikun 0:13413ea9a877 288 /* Private function prototypes -----------------------------------------------*/
ganlikun 0:13413ea9a877 289
ganlikun 0:13413ea9a877 290 /* Exported functions --------------------------------------------------------*/
ganlikun 0:13413ea9a877 291 /** @addtogroup ADC_LL_Exported_Functions
ganlikun 0:13413ea9a877 292 * @{
ganlikun 0:13413ea9a877 293 */
ganlikun 0:13413ea9a877 294
ganlikun 0:13413ea9a877 295 /** @addtogroup ADC_LL_EF_Init
ganlikun 0:13413ea9a877 296 * @{
ganlikun 0:13413ea9a877 297 */
ganlikun 0:13413ea9a877 298
ganlikun 0:13413ea9a877 299 /**
ganlikun 0:13413ea9a877 300 * @brief De-initialize registers of all ADC instances belonging to
ganlikun 0:13413ea9a877 301 * the same ADC common instance to their default reset values.
ganlikun 0:13413ea9a877 302 * @param ADCxy_COMMON ADC common instance
ganlikun 0:13413ea9a877 303 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
ganlikun 0:13413ea9a877 304 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 305 * - SUCCESS: ADC common registers are de-initialized
ganlikun 0:13413ea9a877 306 * - ERROR: not applicable
ganlikun 0:13413ea9a877 307 */
ganlikun 0:13413ea9a877 308 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
ganlikun 0:13413ea9a877 309 {
ganlikun 0:13413ea9a877 310 /* Check the parameters */
ganlikun 0:13413ea9a877 311 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
ganlikun 0:13413ea9a877 312
ganlikun 0:13413ea9a877 313
ganlikun 0:13413ea9a877 314 /* Force reset of ADC clock (core clock) */
ganlikun 0:13413ea9a877 315 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
ganlikun 0:13413ea9a877 316
ganlikun 0:13413ea9a877 317 /* Release reset of ADC clock (core clock) */
ganlikun 0:13413ea9a877 318 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
ganlikun 0:13413ea9a877 319
ganlikun 0:13413ea9a877 320 return SUCCESS;
ganlikun 0:13413ea9a877 321 }
ganlikun 0:13413ea9a877 322
ganlikun 0:13413ea9a877 323 /**
ganlikun 0:13413ea9a877 324 * @brief Initialize some features of ADC common parameters
ganlikun 0:13413ea9a877 325 * (all ADC instances belonging to the same ADC common instance)
ganlikun 0:13413ea9a877 326 * and multimode (for devices with several ADC instances available).
ganlikun 0:13413ea9a877 327 * @note The setting of ADC common parameters is conditioned to
ganlikun 0:13413ea9a877 328 * ADC instances state:
ganlikun 0:13413ea9a877 329 * All ADC instances belonging to the same ADC common instance
ganlikun 0:13413ea9a877 330 * must be disabled.
ganlikun 0:13413ea9a877 331 * @param ADCxy_COMMON ADC common instance
ganlikun 0:13413ea9a877 332 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
ganlikun 0:13413ea9a877 333 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
ganlikun 0:13413ea9a877 334 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 335 * - SUCCESS: ADC common registers are initialized
ganlikun 0:13413ea9a877 336 * - ERROR: ADC common registers are not initialized
ganlikun 0:13413ea9a877 337 */
ganlikun 0:13413ea9a877 338 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
ganlikun 0:13413ea9a877 339 {
ganlikun 0:13413ea9a877 340 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 341
ganlikun 0:13413ea9a877 342 /* Check the parameters */
ganlikun 0:13413ea9a877 343 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
ganlikun 0:13413ea9a877 344 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
ganlikun 0:13413ea9a877 345
ganlikun 0:13413ea9a877 346 #if defined(ADC_MULTIMODE_SUPPORT)
ganlikun 0:13413ea9a877 347 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
ganlikun 0:13413ea9a877 348 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
ganlikun 0:13413ea9a877 349 {
ganlikun 0:13413ea9a877 350 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
ganlikun 0:13413ea9a877 351 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
ganlikun 0:13413ea9a877 352 }
ganlikun 0:13413ea9a877 353 #endif /* ADC_MULTIMODE_SUPPORT */
ganlikun 0:13413ea9a877 354
ganlikun 0:13413ea9a877 355 /* Note: Hardware constraint (refer to description of functions */
ganlikun 0:13413ea9a877 356 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
ganlikun 0:13413ea9a877 357 /* On this STM32 serie, setting of these features is conditioned to */
ganlikun 0:13413ea9a877 358 /* ADC state: */
ganlikun 0:13413ea9a877 359 /* All ADC instances of the ADC common group must be disabled. */
ganlikun 0:13413ea9a877 360 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
ganlikun 0:13413ea9a877 361 {
ganlikun 0:13413ea9a877 362 /* Configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 363 /* - common to several ADC */
ganlikun 0:13413ea9a877 364 /* (all ADC instances belonging to the same ADC common instance) */
ganlikun 0:13413ea9a877 365 /* - Set ADC clock (conversion clock) */
ganlikun 0:13413ea9a877 366 /* - multimode (if several ADC instances available on the */
ganlikun 0:13413ea9a877 367 /* selected device) */
ganlikun 0:13413ea9a877 368 /* - Set ADC multimode configuration */
ganlikun 0:13413ea9a877 369 /* - Set ADC multimode DMA transfer */
ganlikun 0:13413ea9a877 370 /* - Set ADC multimode: delay between 2 sampling phases */
ganlikun 0:13413ea9a877 371 #if defined(ADC_MULTIMODE_SUPPORT)
ganlikun 0:13413ea9a877 372 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
ganlikun 0:13413ea9a877 373 {
ganlikun 0:13413ea9a877 374 MODIFY_REG(ADCxy_COMMON->CCR,
ganlikun 0:13413ea9a877 375 ADC_CCR_ADCPRE
ganlikun 0:13413ea9a877 376 | ADC_CCR_MULTI
ganlikun 0:13413ea9a877 377 | ADC_CCR_DMA
ganlikun 0:13413ea9a877 378 | ADC_CCR_DDS
ganlikun 0:13413ea9a877 379 | ADC_CCR_DELAY
ganlikun 0:13413ea9a877 380 ,
ganlikun 0:13413ea9a877 381 ADC_CommonInitStruct->CommonClock
ganlikun 0:13413ea9a877 382 | ADC_CommonInitStruct->Multimode
ganlikun 0:13413ea9a877 383 | ADC_CommonInitStruct->MultiDMATransfer
ganlikun 0:13413ea9a877 384 | ADC_CommonInitStruct->MultiTwoSamplingDelay
ganlikun 0:13413ea9a877 385 );
ganlikun 0:13413ea9a877 386 }
ganlikun 0:13413ea9a877 387 else
ganlikun 0:13413ea9a877 388 {
ganlikun 0:13413ea9a877 389 MODIFY_REG(ADCxy_COMMON->CCR,
ganlikun 0:13413ea9a877 390 ADC_CCR_ADCPRE
ganlikun 0:13413ea9a877 391 | ADC_CCR_MULTI
ganlikun 0:13413ea9a877 392 | ADC_CCR_DMA
ganlikun 0:13413ea9a877 393 | ADC_CCR_DDS
ganlikun 0:13413ea9a877 394 | ADC_CCR_DELAY
ganlikun 0:13413ea9a877 395 ,
ganlikun 0:13413ea9a877 396 ADC_CommonInitStruct->CommonClock
ganlikun 0:13413ea9a877 397 | LL_ADC_MULTI_INDEPENDENT
ganlikun 0:13413ea9a877 398 );
ganlikun 0:13413ea9a877 399 }
ganlikun 0:13413ea9a877 400 #else
ganlikun 0:13413ea9a877 401 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
ganlikun 0:13413ea9a877 402 #endif
ganlikun 0:13413ea9a877 403 }
ganlikun 0:13413ea9a877 404 else
ganlikun 0:13413ea9a877 405 {
ganlikun 0:13413ea9a877 406 /* Initialization error: One or several ADC instances belonging to */
ganlikun 0:13413ea9a877 407 /* the same ADC common instance are not disabled. */
ganlikun 0:13413ea9a877 408 status = ERROR;
ganlikun 0:13413ea9a877 409 }
ganlikun 0:13413ea9a877 410
ganlikun 0:13413ea9a877 411 return status;
ganlikun 0:13413ea9a877 412 }
ganlikun 0:13413ea9a877 413
ganlikun 0:13413ea9a877 414 /**
ganlikun 0:13413ea9a877 415 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
ganlikun 0:13413ea9a877 416 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
ganlikun 0:13413ea9a877 417 * whose fields will be set to default values.
ganlikun 0:13413ea9a877 418 * @retval None
ganlikun 0:13413ea9a877 419 */
ganlikun 0:13413ea9a877 420 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
ganlikun 0:13413ea9a877 421 {
ganlikun 0:13413ea9a877 422 /* Set ADC_CommonInitStruct fields to default values */
ganlikun 0:13413ea9a877 423 /* Set fields of ADC common */
ganlikun 0:13413ea9a877 424 /* (all ADC instances belonging to the same ADC common instance) */
ganlikun 0:13413ea9a877 425 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
ganlikun 0:13413ea9a877 426
ganlikun 0:13413ea9a877 427 #if defined(ADC_MULTIMODE_SUPPORT)
ganlikun 0:13413ea9a877 428 /* Set fields of ADC multimode */
ganlikun 0:13413ea9a877 429 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
ganlikun 0:13413ea9a877 430 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
ganlikun 0:13413ea9a877 431 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
ganlikun 0:13413ea9a877 432 #endif /* ADC_MULTIMODE_SUPPORT */
ganlikun 0:13413ea9a877 433 }
ganlikun 0:13413ea9a877 434
ganlikun 0:13413ea9a877 435 /**
ganlikun 0:13413ea9a877 436 * @brief De-initialize registers of the selected ADC instance
ganlikun 0:13413ea9a877 437 * to their default reset values.
ganlikun 0:13413ea9a877 438 * @note To reset all ADC instances quickly (perform a hard reset),
ganlikun 0:13413ea9a877 439 * use function @ref LL_ADC_CommonDeInit().
ganlikun 0:13413ea9a877 440 * @param ADCx ADC instance
ganlikun 0:13413ea9a877 441 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 442 * - SUCCESS: ADC registers are de-initialized
ganlikun 0:13413ea9a877 443 * - ERROR: ADC registers are not de-initialized
ganlikun 0:13413ea9a877 444 */
ganlikun 0:13413ea9a877 445 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
ganlikun 0:13413ea9a877 446 {
ganlikun 0:13413ea9a877 447 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 448
ganlikun 0:13413ea9a877 449 /* Check the parameters */
ganlikun 0:13413ea9a877 450 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
ganlikun 0:13413ea9a877 451
ganlikun 0:13413ea9a877 452 /* Disable ADC instance if not already disabled. */
ganlikun 0:13413ea9a877 453 if(LL_ADC_IsEnabled(ADCx) == 1U)
ganlikun 0:13413ea9a877 454 {
ganlikun 0:13413ea9a877 455 /* Set ADC group regular trigger source to SW start to ensure to not */
ganlikun 0:13413ea9a877 456 /* have an external trigger event occurring during the conversion stop */
ganlikun 0:13413ea9a877 457 /* ADC disable process. */
ganlikun 0:13413ea9a877 458 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
ganlikun 0:13413ea9a877 459
ganlikun 0:13413ea9a877 460 /* Set ADC group injected trigger source to SW start to ensure to not */
ganlikun 0:13413ea9a877 461 /* have an external trigger event occurring during the conversion stop */
ganlikun 0:13413ea9a877 462 /* ADC disable process. */
ganlikun 0:13413ea9a877 463 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
ganlikun 0:13413ea9a877 464
ganlikun 0:13413ea9a877 465 /* Disable the ADC instance */
ganlikun 0:13413ea9a877 466 LL_ADC_Disable(ADCx);
ganlikun 0:13413ea9a877 467 }
ganlikun 0:13413ea9a877 468
ganlikun 0:13413ea9a877 469 /* Check whether ADC state is compliant with expected state */
ganlikun 0:13413ea9a877 470 /* (hardware requirements of bits state to reset registers below) */
ganlikun 0:13413ea9a877 471 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
ganlikun 0:13413ea9a877 472 {
ganlikun 0:13413ea9a877 473 /* ========== Reset ADC registers ========== */
ganlikun 0:13413ea9a877 474 /* Reset register SR */
ganlikun 0:13413ea9a877 475 CLEAR_BIT(ADCx->SR,
ganlikun 0:13413ea9a877 476 ( LL_ADC_FLAG_STRT
ganlikun 0:13413ea9a877 477 | LL_ADC_FLAG_JSTRT
ganlikun 0:13413ea9a877 478 | LL_ADC_FLAG_EOCS
ganlikun 0:13413ea9a877 479 | LL_ADC_FLAG_OVR
ganlikun 0:13413ea9a877 480 | LL_ADC_FLAG_JEOS
ganlikun 0:13413ea9a877 481 | LL_ADC_FLAG_AWD1 )
ganlikun 0:13413ea9a877 482 );
ganlikun 0:13413ea9a877 483
ganlikun 0:13413ea9a877 484 /* Reset register CR1 */
ganlikun 0:13413ea9a877 485 CLEAR_BIT(ADCx->CR1,
ganlikun 0:13413ea9a877 486 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
ganlikun 0:13413ea9a877 487 | ADC_CR1_JAWDEN
ganlikun 0:13413ea9a877 488 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
ganlikun 0:13413ea9a877 489 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
ganlikun 0:13413ea9a877 490 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
ganlikun 0:13413ea9a877 491 | ADC_CR1_AWDCH )
ganlikun 0:13413ea9a877 492 );
ganlikun 0:13413ea9a877 493
ganlikun 0:13413ea9a877 494 /* Reset register CR2 */
ganlikun 0:13413ea9a877 495 CLEAR_BIT(ADCx->CR2,
ganlikun 0:13413ea9a877 496 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
ganlikun 0:13413ea9a877 497 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
ganlikun 0:13413ea9a877 498 | ADC_CR2_ALIGN | ADC_CR2_EOCS
ganlikun 0:13413ea9a877 499 | ADC_CR2_DDS | ADC_CR2_DMA
ganlikun 0:13413ea9a877 500 | ADC_CR2_CONT | ADC_CR2_ADON )
ganlikun 0:13413ea9a877 501 );
ganlikun 0:13413ea9a877 502
ganlikun 0:13413ea9a877 503 /* Reset register SMPR1 */
ganlikun 0:13413ea9a877 504 CLEAR_BIT(ADCx->SMPR1,
ganlikun 0:13413ea9a877 505 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
ganlikun 0:13413ea9a877 506 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
ganlikun 0:13413ea9a877 507 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
ganlikun 0:13413ea9a877 508 );
ganlikun 0:13413ea9a877 509
ganlikun 0:13413ea9a877 510 /* Reset register SMPR2 */
ganlikun 0:13413ea9a877 511 CLEAR_BIT(ADCx->SMPR2,
ganlikun 0:13413ea9a877 512 ( ADC_SMPR2_SMP9
ganlikun 0:13413ea9a877 513 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
ganlikun 0:13413ea9a877 514 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
ganlikun 0:13413ea9a877 515 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
ganlikun 0:13413ea9a877 516 );
ganlikun 0:13413ea9a877 517
ganlikun 0:13413ea9a877 518 /* Reset register JOFR1 */
ganlikun 0:13413ea9a877 519 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
ganlikun 0:13413ea9a877 520 /* Reset register JOFR2 */
ganlikun 0:13413ea9a877 521 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
ganlikun 0:13413ea9a877 522 /* Reset register JOFR3 */
ganlikun 0:13413ea9a877 523 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
ganlikun 0:13413ea9a877 524 /* Reset register JOFR4 */
ganlikun 0:13413ea9a877 525 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
ganlikun 0:13413ea9a877 526
ganlikun 0:13413ea9a877 527 /* Reset register HTR */
ganlikun 0:13413ea9a877 528 SET_BIT(ADCx->HTR, ADC_HTR_HT);
ganlikun 0:13413ea9a877 529 /* Reset register LTR */
ganlikun 0:13413ea9a877 530 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
ganlikun 0:13413ea9a877 531
ganlikun 0:13413ea9a877 532 /* Reset register SQR1 */
ganlikun 0:13413ea9a877 533 CLEAR_BIT(ADCx->SQR1,
ganlikun 0:13413ea9a877 534 ( ADC_SQR1_L
ganlikun 0:13413ea9a877 535 | ADC_SQR1_SQ16
ganlikun 0:13413ea9a877 536 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
ganlikun 0:13413ea9a877 537 );
ganlikun 0:13413ea9a877 538
ganlikun 0:13413ea9a877 539 /* Reset register SQR2 */
ganlikun 0:13413ea9a877 540 CLEAR_BIT(ADCx->SQR2,
ganlikun 0:13413ea9a877 541 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
ganlikun 0:13413ea9a877 542 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
ganlikun 0:13413ea9a877 543 );
ganlikun 0:13413ea9a877 544
ganlikun 0:13413ea9a877 545
ganlikun 0:13413ea9a877 546 /* Reset register JSQR */
ganlikun 0:13413ea9a877 547 CLEAR_BIT(ADCx->JSQR,
ganlikun 0:13413ea9a877 548 ( ADC_JSQR_JL
ganlikun 0:13413ea9a877 549 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
ganlikun 0:13413ea9a877 550 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
ganlikun 0:13413ea9a877 551 );
ganlikun 0:13413ea9a877 552
ganlikun 0:13413ea9a877 553 /* Reset register DR */
ganlikun 0:13413ea9a877 554 /* bits in access mode read only, no direct reset applicable */
ganlikun 0:13413ea9a877 555
ganlikun 0:13413ea9a877 556 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
ganlikun 0:13413ea9a877 557 /* bits in access mode read only, no direct reset applicable */
ganlikun 0:13413ea9a877 558
ganlikun 0:13413ea9a877 559 /* Reset register CCR */
ganlikun 0:13413ea9a877 560 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
ganlikun 0:13413ea9a877 561 }
ganlikun 0:13413ea9a877 562
ganlikun 0:13413ea9a877 563 return status;
ganlikun 0:13413ea9a877 564 }
ganlikun 0:13413ea9a877 565
ganlikun 0:13413ea9a877 566 /**
ganlikun 0:13413ea9a877 567 * @brief Initialize some features of ADC instance.
ganlikun 0:13413ea9a877 568 * @note These parameters have an impact on ADC scope: ADC instance.
ganlikun 0:13413ea9a877 569 * Affects both group regular and group injected (availability
ganlikun 0:13413ea9a877 570 * of ADC group injected depends on STM32 families).
ganlikun 0:13413ea9a877 571 * Refer to corresponding unitary functions into
ganlikun 0:13413ea9a877 572 * @ref ADC_LL_EF_Configuration_ADC_Instance .
ganlikun 0:13413ea9a877 573 * @note The setting of these parameters by function @ref LL_ADC_Init()
ganlikun 0:13413ea9a877 574 * is conditioned to ADC state:
ganlikun 0:13413ea9a877 575 * ADC instance must be disabled.
ganlikun 0:13413ea9a877 576 * This condition is applied to all ADC features, for efficiency
ganlikun 0:13413ea9a877 577 * and compatibility over all STM32 families. However, the different
ganlikun 0:13413ea9a877 578 * features can be set under different ADC state conditions
ganlikun 0:13413ea9a877 579 * (setting possible with ADC enabled without conversion on going,
ganlikun 0:13413ea9a877 580 * ADC enabled with conversion on going, ...)
ganlikun 0:13413ea9a877 581 * Each feature can be updated afterwards with a unitary function
ganlikun 0:13413ea9a877 582 * and potentially with ADC in a different state than disabled,
ganlikun 0:13413ea9a877 583 * refer to description of each function for setting
ganlikun 0:13413ea9a877 584 * conditioned to ADC state.
ganlikun 0:13413ea9a877 585 * @note After using this function, some other features must be configured
ganlikun 0:13413ea9a877 586 * using LL unitary functions.
ganlikun 0:13413ea9a877 587 * The minimum configuration remaining to be done is:
ganlikun 0:13413ea9a877 588 * - Set ADC group regular or group injected sequencer:
ganlikun 0:13413ea9a877 589 * map channel on the selected sequencer rank.
ganlikun 0:13413ea9a877 590 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
ganlikun 0:13413ea9a877 591 * - Set ADC channel sampling time
ganlikun 0:13413ea9a877 592 * Refer to function LL_ADC_SetChannelSamplingTime();
ganlikun 0:13413ea9a877 593 * @param ADCx ADC instance
ganlikun 0:13413ea9a877 594 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
ganlikun 0:13413ea9a877 595 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 596 * - SUCCESS: ADC registers are initialized
ganlikun 0:13413ea9a877 597 * - ERROR: ADC registers are not initialized
ganlikun 0:13413ea9a877 598 */
ganlikun 0:13413ea9a877 599 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
ganlikun 0:13413ea9a877 600 {
ganlikun 0:13413ea9a877 601 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 602
ganlikun 0:13413ea9a877 603 /* Check the parameters */
ganlikun 0:13413ea9a877 604 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
ganlikun 0:13413ea9a877 605
ganlikun 0:13413ea9a877 606 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
ganlikun 0:13413ea9a877 607 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
ganlikun 0:13413ea9a877 608 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
ganlikun 0:13413ea9a877 609
ganlikun 0:13413ea9a877 610 /* Note: Hardware constraint (refer to description of this function): */
ganlikun 0:13413ea9a877 611 /* ADC instance must be disabled. */
ganlikun 0:13413ea9a877 612 if(LL_ADC_IsEnabled(ADCx) == 0U)
ganlikun 0:13413ea9a877 613 {
ganlikun 0:13413ea9a877 614 /* Configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 615 /* - ADC instance */
ganlikun 0:13413ea9a877 616 /* - Set ADC data resolution */
ganlikun 0:13413ea9a877 617 /* - Set ADC conversion data alignment */
ganlikun 0:13413ea9a877 618 MODIFY_REG(ADCx->CR1,
ganlikun 0:13413ea9a877 619 ADC_CR1_RES
ganlikun 0:13413ea9a877 620 | ADC_CR1_SCAN
ganlikun 0:13413ea9a877 621 ,
ganlikun 0:13413ea9a877 622 ADC_InitStruct->Resolution
ganlikun 0:13413ea9a877 623 | ADC_InitStruct->SequencersScanMode
ganlikun 0:13413ea9a877 624 );
ganlikun 0:13413ea9a877 625
ganlikun 0:13413ea9a877 626 MODIFY_REG(ADCx->CR2,
ganlikun 0:13413ea9a877 627 ADC_CR2_ALIGN
ganlikun 0:13413ea9a877 628 ,
ganlikun 0:13413ea9a877 629 ADC_InitStruct->DataAlignment
ganlikun 0:13413ea9a877 630 );
ganlikun 0:13413ea9a877 631
ganlikun 0:13413ea9a877 632 }
ganlikun 0:13413ea9a877 633 else
ganlikun 0:13413ea9a877 634 {
ganlikun 0:13413ea9a877 635 /* Initialization error: ADC instance is not disabled. */
ganlikun 0:13413ea9a877 636 status = ERROR;
ganlikun 0:13413ea9a877 637 }
ganlikun 0:13413ea9a877 638 return status;
ganlikun 0:13413ea9a877 639 }
ganlikun 0:13413ea9a877 640
ganlikun 0:13413ea9a877 641 /**
ganlikun 0:13413ea9a877 642 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
ganlikun 0:13413ea9a877 643 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
ganlikun 0:13413ea9a877 644 * whose fields will be set to default values.
ganlikun 0:13413ea9a877 645 * @retval None
ganlikun 0:13413ea9a877 646 */
ganlikun 0:13413ea9a877 647 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
ganlikun 0:13413ea9a877 648 {
ganlikun 0:13413ea9a877 649 /* Set ADC_InitStruct fields to default values */
ganlikun 0:13413ea9a877 650 /* Set fields of ADC instance */
ganlikun 0:13413ea9a877 651 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
ganlikun 0:13413ea9a877 652 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
ganlikun 0:13413ea9a877 653
ganlikun 0:13413ea9a877 654 /* Enable scan mode to have a generic behavior with ADC of other */
ganlikun 0:13413ea9a877 655 /* STM32 families, without this setting available: */
ganlikun 0:13413ea9a877 656 /* ADC group regular sequencer and ADC group injected sequencer depend */
ganlikun 0:13413ea9a877 657 /* only of their own configuration. */
ganlikun 0:13413ea9a877 658 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
ganlikun 0:13413ea9a877 659
ganlikun 0:13413ea9a877 660 }
ganlikun 0:13413ea9a877 661
ganlikun 0:13413ea9a877 662 /**
ganlikun 0:13413ea9a877 663 * @brief Initialize some features of ADC group regular.
ganlikun 0:13413ea9a877 664 * @note These parameters have an impact on ADC scope: ADC group regular.
ganlikun 0:13413ea9a877 665 * Refer to corresponding unitary functions into
ganlikun 0:13413ea9a877 666 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
ganlikun 0:13413ea9a877 667 * (functions with prefix "REG").
ganlikun 0:13413ea9a877 668 * @note The setting of these parameters by function @ref LL_ADC_Init()
ganlikun 0:13413ea9a877 669 * is conditioned to ADC state:
ganlikun 0:13413ea9a877 670 * ADC instance must be disabled.
ganlikun 0:13413ea9a877 671 * This condition is applied to all ADC features, for efficiency
ganlikun 0:13413ea9a877 672 * and compatibility over all STM32 families. However, the different
ganlikun 0:13413ea9a877 673 * features can be set under different ADC state conditions
ganlikun 0:13413ea9a877 674 * (setting possible with ADC enabled without conversion on going,
ganlikun 0:13413ea9a877 675 * ADC enabled with conversion on going, ...)
ganlikun 0:13413ea9a877 676 * Each feature can be updated afterwards with a unitary function
ganlikun 0:13413ea9a877 677 * and potentially with ADC in a different state than disabled,
ganlikun 0:13413ea9a877 678 * refer to description of each function for setting
ganlikun 0:13413ea9a877 679 * conditioned to ADC state.
ganlikun 0:13413ea9a877 680 * @note After using this function, other features must be configured
ganlikun 0:13413ea9a877 681 * using LL unitary functions.
ganlikun 0:13413ea9a877 682 * The minimum configuration remaining to be done is:
ganlikun 0:13413ea9a877 683 * - Set ADC group regular or group injected sequencer:
ganlikun 0:13413ea9a877 684 * map channel on the selected sequencer rank.
ganlikun 0:13413ea9a877 685 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
ganlikun 0:13413ea9a877 686 * - Set ADC channel sampling time
ganlikun 0:13413ea9a877 687 * Refer to function LL_ADC_SetChannelSamplingTime();
ganlikun 0:13413ea9a877 688 * @param ADCx ADC instance
ganlikun 0:13413ea9a877 689 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
ganlikun 0:13413ea9a877 690 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 691 * - SUCCESS: ADC registers are initialized
ganlikun 0:13413ea9a877 692 * - ERROR: ADC registers are not initialized
ganlikun 0:13413ea9a877 693 */
ganlikun 0:13413ea9a877 694 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
ganlikun 0:13413ea9a877 695 {
ganlikun 0:13413ea9a877 696 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 697
ganlikun 0:13413ea9a877 698 /* Check the parameters */
ganlikun 0:13413ea9a877 699 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
ganlikun 0:13413ea9a877 700 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
ganlikun 0:13413ea9a877 701 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
ganlikun 0:13413ea9a877 702 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
ganlikun 0:13413ea9a877 703 {
ganlikun 0:13413ea9a877 704 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
ganlikun 0:13413ea9a877 705 }
ganlikun 0:13413ea9a877 706 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
ganlikun 0:13413ea9a877 707 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
ganlikun 0:13413ea9a877 708
ganlikun 0:13413ea9a877 709 /* Note: Hardware constraint (refer to description of this function): */
ganlikun 0:13413ea9a877 710 /* ADC instance must be disabled. */
ganlikun 0:13413ea9a877 711 if(LL_ADC_IsEnabled(ADCx) == 0U)
ganlikun 0:13413ea9a877 712 {
ganlikun 0:13413ea9a877 713 /* Configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 714 /* - ADC group regular */
ganlikun 0:13413ea9a877 715 /* - Set ADC group regular trigger source */
ganlikun 0:13413ea9a877 716 /* - Set ADC group regular sequencer length */
ganlikun 0:13413ea9a877 717 /* - Set ADC group regular sequencer discontinuous mode */
ganlikun 0:13413ea9a877 718 /* - Set ADC group regular continuous mode */
ganlikun 0:13413ea9a877 719 /* - Set ADC group regular conversion data transfer: no transfer or */
ganlikun 0:13413ea9a877 720 /* transfer by DMA, and DMA requests mode */
ganlikun 0:13413ea9a877 721 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
ganlikun 0:13413ea9a877 722 /* ADC conversion. */
ganlikun 0:13413ea9a877 723 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
ganlikun 0:13413ea9a877 724 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
ganlikun 0:13413ea9a877 725 {
ganlikun 0:13413ea9a877 726 MODIFY_REG(ADCx->CR1,
ganlikun 0:13413ea9a877 727 ADC_CR1_DISCEN
ganlikun 0:13413ea9a877 728 | ADC_CR1_DISCNUM
ganlikun 0:13413ea9a877 729 ,
ganlikun 0:13413ea9a877 730 ADC_REG_InitStruct->SequencerLength
ganlikun 0:13413ea9a877 731 | ADC_REG_InitStruct->SequencerDiscont
ganlikun 0:13413ea9a877 732 );
ganlikun 0:13413ea9a877 733 }
ganlikun 0:13413ea9a877 734 else
ganlikun 0:13413ea9a877 735 {
ganlikun 0:13413ea9a877 736 MODIFY_REG(ADCx->CR1,
ganlikun 0:13413ea9a877 737 ADC_CR1_DISCEN
ganlikun 0:13413ea9a877 738 | ADC_CR1_DISCNUM
ganlikun 0:13413ea9a877 739 ,
ganlikun 0:13413ea9a877 740 ADC_REG_InitStruct->SequencerLength
ganlikun 0:13413ea9a877 741 | LL_ADC_REG_SEQ_DISCONT_DISABLE
ganlikun 0:13413ea9a877 742 );
ganlikun 0:13413ea9a877 743 }
ganlikun 0:13413ea9a877 744
ganlikun 0:13413ea9a877 745 MODIFY_REG(ADCx->CR2,
ganlikun 0:13413ea9a877 746 ADC_CR2_EXTSEL
ganlikun 0:13413ea9a877 747 | ADC_CR2_EXTEN
ganlikun 0:13413ea9a877 748 | ADC_CR2_CONT
ganlikun 0:13413ea9a877 749 | ADC_CR2_DMA
ganlikun 0:13413ea9a877 750 | ADC_CR2_DDS
ganlikun 0:13413ea9a877 751 ,
ganlikun 0:13413ea9a877 752 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
ganlikun 0:13413ea9a877 753 | ADC_REG_InitStruct->ContinuousMode
ganlikun 0:13413ea9a877 754 | ADC_REG_InitStruct->DMATransfer
ganlikun 0:13413ea9a877 755 );
ganlikun 0:13413ea9a877 756
ganlikun 0:13413ea9a877 757 /* Set ADC group regular sequencer length and scan direction */
ganlikun 0:13413ea9a877 758 /* Note: Hardware constraint (refer to description of this function): */
ganlikun 0:13413ea9a877 759 /* Note: If ADC instance feature scan mode is disabled */
ganlikun 0:13413ea9a877 760 /* (refer to ADC instance initialization structure */
ganlikun 0:13413ea9a877 761 /* parameter @ref SequencersScanMode */
ganlikun 0:13413ea9a877 762 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
ganlikun 0:13413ea9a877 763 /* this parameter is discarded. */
ganlikun 0:13413ea9a877 764 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
ganlikun 0:13413ea9a877 765 }
ganlikun 0:13413ea9a877 766 else
ganlikun 0:13413ea9a877 767 {
ganlikun 0:13413ea9a877 768 /* Initialization error: ADC instance is not disabled. */
ganlikun 0:13413ea9a877 769 status = ERROR;
ganlikun 0:13413ea9a877 770 }
ganlikun 0:13413ea9a877 771 return status;
ganlikun 0:13413ea9a877 772 }
ganlikun 0:13413ea9a877 773
ganlikun 0:13413ea9a877 774 /**
ganlikun 0:13413ea9a877 775 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
ganlikun 0:13413ea9a877 776 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
ganlikun 0:13413ea9a877 777 * whose fields will be set to default values.
ganlikun 0:13413ea9a877 778 * @retval None
ganlikun 0:13413ea9a877 779 */
ganlikun 0:13413ea9a877 780 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
ganlikun 0:13413ea9a877 781 {
ganlikun 0:13413ea9a877 782 /* Set ADC_REG_InitStruct fields to default values */
ganlikun 0:13413ea9a877 783 /* Set fields of ADC group regular */
ganlikun 0:13413ea9a877 784 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
ganlikun 0:13413ea9a877 785 /* ADC conversion. */
ganlikun 0:13413ea9a877 786 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
ganlikun 0:13413ea9a877 787 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ganlikun 0:13413ea9a877 788 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
ganlikun 0:13413ea9a877 789 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
ganlikun 0:13413ea9a877 790 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
ganlikun 0:13413ea9a877 791 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
ganlikun 0:13413ea9a877 792 }
ganlikun 0:13413ea9a877 793
ganlikun 0:13413ea9a877 794 /**
ganlikun 0:13413ea9a877 795 * @brief Initialize some features of ADC group injected.
ganlikun 0:13413ea9a877 796 * @note These parameters have an impact on ADC scope: ADC group injected.
ganlikun 0:13413ea9a877 797 * Refer to corresponding unitary functions into
ganlikun 0:13413ea9a877 798 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
ganlikun 0:13413ea9a877 799 * (functions with prefix "INJ").
ganlikun 0:13413ea9a877 800 * @note The setting of these parameters by function @ref LL_ADC_Init()
ganlikun 0:13413ea9a877 801 * is conditioned to ADC state:
ganlikun 0:13413ea9a877 802 * ADC instance must be disabled.
ganlikun 0:13413ea9a877 803 * This condition is applied to all ADC features, for efficiency
ganlikun 0:13413ea9a877 804 * and compatibility over all STM32 families. However, the different
ganlikun 0:13413ea9a877 805 * features can be set under different ADC state conditions
ganlikun 0:13413ea9a877 806 * (setting possible with ADC enabled without conversion on going,
ganlikun 0:13413ea9a877 807 * ADC enabled with conversion on going, ...)
ganlikun 0:13413ea9a877 808 * Each feature can be updated afterwards with a unitary function
ganlikun 0:13413ea9a877 809 * and potentially with ADC in a different state than disabled,
ganlikun 0:13413ea9a877 810 * refer to description of each function for setting
ganlikun 0:13413ea9a877 811 * conditioned to ADC state.
ganlikun 0:13413ea9a877 812 * @note After using this function, other features must be configured
ganlikun 0:13413ea9a877 813 * using LL unitary functions.
ganlikun 0:13413ea9a877 814 * The minimum configuration remaining to be done is:
ganlikun 0:13413ea9a877 815 * - Set ADC group injected sequencer:
ganlikun 0:13413ea9a877 816 * map channel on the selected sequencer rank.
ganlikun 0:13413ea9a877 817 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
ganlikun 0:13413ea9a877 818 * - Set ADC channel sampling time
ganlikun 0:13413ea9a877 819 * Refer to function LL_ADC_SetChannelSamplingTime();
ganlikun 0:13413ea9a877 820 * @param ADCx ADC instance
ganlikun 0:13413ea9a877 821 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
ganlikun 0:13413ea9a877 822 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 823 * - SUCCESS: ADC registers are initialized
ganlikun 0:13413ea9a877 824 * - ERROR: ADC registers are not initialized
ganlikun 0:13413ea9a877 825 */
ganlikun 0:13413ea9a877 826 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
ganlikun 0:13413ea9a877 827 {
ganlikun 0:13413ea9a877 828 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 829
ganlikun 0:13413ea9a877 830 /* Check the parameters */
ganlikun 0:13413ea9a877 831 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
ganlikun 0:13413ea9a877 832 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
ganlikun 0:13413ea9a877 833 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
ganlikun 0:13413ea9a877 834 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
ganlikun 0:13413ea9a877 835 {
ganlikun 0:13413ea9a877 836 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
ganlikun 0:13413ea9a877 837 }
ganlikun 0:13413ea9a877 838 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
ganlikun 0:13413ea9a877 839
ganlikun 0:13413ea9a877 840 /* Note: Hardware constraint (refer to description of this function): */
ganlikun 0:13413ea9a877 841 /* ADC instance must be disabled. */
ganlikun 0:13413ea9a877 842 if(LL_ADC_IsEnabled(ADCx) == 0U)
ganlikun 0:13413ea9a877 843 {
ganlikun 0:13413ea9a877 844 /* Configuration of ADC hierarchical scope: */
ganlikun 0:13413ea9a877 845 /* - ADC group injected */
ganlikun 0:13413ea9a877 846 /* - Set ADC group injected trigger source */
ganlikun 0:13413ea9a877 847 /* - Set ADC group injected sequencer length */
ganlikun 0:13413ea9a877 848 /* - Set ADC group injected sequencer discontinuous mode */
ganlikun 0:13413ea9a877 849 /* - Set ADC group injected conversion trigger: independent or */
ganlikun 0:13413ea9a877 850 /* from ADC group regular */
ganlikun 0:13413ea9a877 851 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
ganlikun 0:13413ea9a877 852 /* ADC conversion. */
ganlikun 0:13413ea9a877 853 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
ganlikun 0:13413ea9a877 854 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
ganlikun 0:13413ea9a877 855 {
ganlikun 0:13413ea9a877 856 MODIFY_REG(ADCx->CR1,
ganlikun 0:13413ea9a877 857 ADC_CR1_JDISCEN
ganlikun 0:13413ea9a877 858 | ADC_CR1_JAUTO
ganlikun 0:13413ea9a877 859 ,
ganlikun 0:13413ea9a877 860 ADC_INJ_InitStruct->SequencerDiscont
ganlikun 0:13413ea9a877 861 | ADC_INJ_InitStruct->TrigAuto
ganlikun 0:13413ea9a877 862 );
ganlikun 0:13413ea9a877 863 }
ganlikun 0:13413ea9a877 864 else
ganlikun 0:13413ea9a877 865 {
ganlikun 0:13413ea9a877 866 MODIFY_REG(ADCx->CR1,
ganlikun 0:13413ea9a877 867 ADC_CR1_JDISCEN
ganlikun 0:13413ea9a877 868 | ADC_CR1_JAUTO
ganlikun 0:13413ea9a877 869 ,
ganlikun 0:13413ea9a877 870 LL_ADC_REG_SEQ_DISCONT_DISABLE
ganlikun 0:13413ea9a877 871 | ADC_INJ_InitStruct->TrigAuto
ganlikun 0:13413ea9a877 872 );
ganlikun 0:13413ea9a877 873 }
ganlikun 0:13413ea9a877 874
ganlikun 0:13413ea9a877 875 MODIFY_REG(ADCx->CR2,
ganlikun 0:13413ea9a877 876 ADC_CR2_JEXTSEL
ganlikun 0:13413ea9a877 877 | ADC_CR2_JEXTEN
ganlikun 0:13413ea9a877 878 ,
ganlikun 0:13413ea9a877 879 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
ganlikun 0:13413ea9a877 880 );
ganlikun 0:13413ea9a877 881
ganlikun 0:13413ea9a877 882 /* Note: Hardware constraint (refer to description of this function): */
ganlikun 0:13413ea9a877 883 /* Note: If ADC instance feature scan mode is disabled */
ganlikun 0:13413ea9a877 884 /* (refer to ADC instance initialization structure */
ganlikun 0:13413ea9a877 885 /* parameter @ref SequencersScanMode */
ganlikun 0:13413ea9a877 886 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
ganlikun 0:13413ea9a877 887 /* this parameter is discarded. */
ganlikun 0:13413ea9a877 888 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
ganlikun 0:13413ea9a877 889 }
ganlikun 0:13413ea9a877 890 else
ganlikun 0:13413ea9a877 891 {
ganlikun 0:13413ea9a877 892 /* Initialization error: ADC instance is not disabled. */
ganlikun 0:13413ea9a877 893 status = ERROR;
ganlikun 0:13413ea9a877 894 }
ganlikun 0:13413ea9a877 895 return status;
ganlikun 0:13413ea9a877 896 }
ganlikun 0:13413ea9a877 897
ganlikun 0:13413ea9a877 898 /**
ganlikun 0:13413ea9a877 899 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
ganlikun 0:13413ea9a877 900 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
ganlikun 0:13413ea9a877 901 * whose fields will be set to default values.
ganlikun 0:13413ea9a877 902 * @retval None
ganlikun 0:13413ea9a877 903 */
ganlikun 0:13413ea9a877 904 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
ganlikun 0:13413ea9a877 905 {
ganlikun 0:13413ea9a877 906 /* Set ADC_INJ_InitStruct fields to default values */
ganlikun 0:13413ea9a877 907 /* Set fields of ADC group injected */
ganlikun 0:13413ea9a877 908 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
ganlikun 0:13413ea9a877 909 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
ganlikun 0:13413ea9a877 910 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
ganlikun 0:13413ea9a877 911 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
ganlikun 0:13413ea9a877 912 }
ganlikun 0:13413ea9a877 913
ganlikun 0:13413ea9a877 914 /**
ganlikun 0:13413ea9a877 915 * @}
ganlikun 0:13413ea9a877 916 */
ganlikun 0:13413ea9a877 917
ganlikun 0:13413ea9a877 918 /**
ganlikun 0:13413ea9a877 919 * @}
ganlikun 0:13413ea9a877 920 */
ganlikun 0:13413ea9a877 921
ganlikun 0:13413ea9a877 922 /**
ganlikun 0:13413ea9a877 923 * @}
ganlikun 0:13413ea9a877 924 */
ganlikun 0:13413ea9a877 925
ganlikun 0:13413ea9a877 926 #endif /* ADC1 || ADC2 || ADC3 */
ganlikun 0:13413ea9a877 927
ganlikun 0:13413ea9a877 928 /**
ganlikun 0:13413ea9a877 929 * @}
ganlikun 0:13413ea9a877 930 */
ganlikun 0:13413ea9a877 931
ganlikun 0:13413ea9a877 932 #endif /* USE_FULL_LL_DRIVER */
ganlikun 0:13413ea9a877 933
ganlikun 0:13413ea9a877 934 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 935