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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_hal_rcc_ex.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of RCC HAL Extension module.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37
ganlikun	0:13413ea9a877	38	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
ganlikun	0:13413ea9a877	40	#define __STM32F4xx_HAL_RCC_EX_H
ganlikun	0:13413ea9a877	41
ganlikun	0:13413ea9a877	42	#ifdef __cplusplus
ganlikun	0:13413ea9a877	43	extern "C" {
ganlikun	0:13413ea9a877	44	#endif
ganlikun	0:13413ea9a877	45
ganlikun	0:13413ea9a877	46	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	47	#include "stm32f4xx_hal_def.h"
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	/** @addtogroup STM32F4xx_HAL_Driver
ganlikun	0:13413ea9a877	50	* @{
ganlikun	0:13413ea9a877	51	*/
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	/** @addtogroup RCCEx
ganlikun	0:13413ea9a877	54	* @{
ganlikun	0:13413ea9a877	55	*/
ganlikun	0:13413ea9a877	56
ganlikun	0:13413ea9a877	57	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
ganlikun	0:13413ea9a877	59	* @{
ganlikun	0:13413ea9a877	60	*/
ganlikun	0:13413ea9a877	61
ganlikun	0:13413ea9a877	62	/**
ganlikun	0:13413ea9a877	63	* @brief RCC PLL configuration structure definition
ganlikun	0:13413ea9a877	64	*/
ganlikun	0:13413ea9a877	65	typedef struct
ganlikun	0:13413ea9a877	66	{
ganlikun	0:13413ea9a877	67	uint32_t PLLState; /*!< The new state of the PLL.
ganlikun	0:13413ea9a877	68	This parameter can be a value of @ref RCC_PLL_Config */
ganlikun	0:13413ea9a877	69
ganlikun	0:13413ea9a877	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
ganlikun	0:13413ea9a877	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
ganlikun	0:13413ea9a877	72
ganlikun	0:13413ea9a877	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
ganlikun	0:13413ea9a877	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
ganlikun	0:13413ea9a877	75
ganlikun	0:13413ea9a877	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
ganlikun	0:13413ea9a877	77	This parameter must be a number between Min_Data = 50 and Max_Data = 432
ganlikun	0:13413ea9a877	78	except for STM32F411xE devices where the Min_Data = 192 */
ganlikun	0:13413ea9a877	79
ganlikun	0:13413ea9a877	80	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
ganlikun	0:13413ea9a877	81	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
ganlikun	0:13413ea9a877	82
ganlikun	0:13413ea9a877	83	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
ganlikun	0:13413ea9a877	84	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
ganlikun	0:13413ea9a877	85	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
ganlikun	0:13413ea9a877	86	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
ganlikun	0:13413ea9a877	87	defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	88	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
ganlikun	0:13413ea9a877	89	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
ganlikun	0:13413ea9a877	90	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
ganlikun	0:13413ea9a877	91	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
ganlikun	0:13413ea9a877	92	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	93	}RCC_PLLInitTypeDef;
ganlikun	0:13413ea9a877	94
ganlikun	0:13413ea9a877	95	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	96	/**
ganlikun	0:13413ea9a877	97	* @brief PLLI2S Clock structure definition
ganlikun	0:13413ea9a877	98	*/
ganlikun	0:13413ea9a877	99	typedef struct
ganlikun	0:13413ea9a877	100	{
ganlikun	0:13413ea9a877	101	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
ganlikun	0:13413ea9a877	102	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
ganlikun	0:13413ea9a877	103
ganlikun	0:13413ea9a877	104	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
ganlikun	0:13413ea9a877	105	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
ganlikun	0:13413ea9a877	106
ganlikun	0:13413ea9a877	107	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
ganlikun	0:13413ea9a877	108	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
ganlikun	0:13413ea9a877	109
ganlikun	0:13413ea9a877	110	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
ganlikun	0:13413ea9a877	111	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	112	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	113
ganlikun	0:13413ea9a877	114	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
ganlikun	0:13413ea9a877	115	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	116	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
ganlikun	0:13413ea9a877	117	}RCC_PLLI2SInitTypeDef;
ganlikun	0:13413ea9a877	118
ganlikun	0:13413ea9a877	119	/**
ganlikun	0:13413ea9a877	120	* @brief PLLSAI Clock structure definition
ganlikun	0:13413ea9a877	121	*/
ganlikun	0:13413ea9a877	122	typedef struct
ganlikun	0:13413ea9a877	123	{
ganlikun	0:13413ea9a877	124	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
ganlikun	0:13413ea9a877	125	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
ganlikun	0:13413ea9a877	126
ganlikun	0:13413ea9a877	127	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
ganlikun	0:13413ea9a877	128	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
ganlikun	0:13413ea9a877	129
ganlikun	0:13413ea9a877	130	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
ganlikun	0:13413ea9a877	131	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
ganlikun	0:13413ea9a877	132
ganlikun	0:13413ea9a877	133	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
ganlikun	0:13413ea9a877	134	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	135	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	136	}RCC_PLLSAIInitTypeDef;
ganlikun	0:13413ea9a877	137
ganlikun	0:13413ea9a877	138	/**
ganlikun	0:13413ea9a877	139	* @brief RCC extended clocks structure definition
ganlikun	0:13413ea9a877	140	*/
ganlikun	0:13413ea9a877	141	typedef struct
ganlikun	0:13413ea9a877	142	{
ganlikun	0:13413ea9a877	143	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
ganlikun	0:13413ea9a877	144	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
ganlikun	0:13413ea9a877	145
ganlikun	0:13413ea9a877	146	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
ganlikun	0:13413ea9a877	147	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
ganlikun	0:13413ea9a877	148
ganlikun	0:13413ea9a877	149	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
ganlikun	0:13413ea9a877	150	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
ganlikun	0:13413ea9a877	151
ganlikun	0:13413ea9a877	152	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
ganlikun	0:13413ea9a877	153	This parameter must be a number between Min_Data = 1 and Max_Data = 32
ganlikun	0:13413ea9a877	154	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	155
ganlikun	0:13413ea9a877	156	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
ganlikun	0:13413ea9a877	157	This parameter must be a number between Min_Data = 1 and Max_Data = 32
ganlikun	0:13413ea9a877	158	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	159
ganlikun	0:13413ea9a877	160	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
ganlikun	0:13413ea9a877	161	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
ganlikun	0:13413ea9a877	162
ganlikun	0:13413ea9a877	163	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
ganlikun	0:13413ea9a877	164	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
ganlikun	0:13413ea9a877	165
ganlikun	0:13413ea9a877	166	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
ganlikun	0:13413ea9a877	167	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
ganlikun	0:13413ea9a877	168
ganlikun	0:13413ea9a877	169	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
ganlikun	0:13413ea9a877	170	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
ganlikun	0:13413ea9a877	171
ganlikun	0:13413ea9a877	172	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
ganlikun	0:13413ea9a877	173	This parameter can be a value of @ref RCC_RTC_Clock_Source */
ganlikun	0:13413ea9a877	174
ganlikun	0:13413ea9a877	175	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
ganlikun	0:13413ea9a877	176	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
ganlikun	0:13413ea9a877	177
ganlikun	0:13413ea9a877	178	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
ganlikun	0:13413ea9a877	179	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
ganlikun	0:13413ea9a877	180
ganlikun	0:13413ea9a877	181	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
ganlikun	0:13413ea9a877	182	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
ganlikun	0:13413ea9a877	183
ganlikun	0:13413ea9a877	184	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
ganlikun	0:13413ea9a877	185	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
ganlikun	0:13413ea9a877	186
ganlikun	0:13413ea9a877	187	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
ganlikun	0:13413ea9a877	188	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
ganlikun	0:13413ea9a877	189
ganlikun	0:13413ea9a877	190	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
ganlikun	0:13413ea9a877	191	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
ganlikun	0:13413ea9a877	192	}RCC_PeriphCLKInitTypeDef;
ganlikun	0:13413ea9a877	193	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	194
ganlikun	0:13413ea9a877	195	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	196	/**
ganlikun	0:13413ea9a877	197	* @brief RCC extended clocks structure definition
ganlikun	0:13413ea9a877	198	*/
ganlikun	0:13413ea9a877	199	typedef struct
ganlikun	0:13413ea9a877	200	{
ganlikun	0:13413ea9a877	201	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
ganlikun	0:13413ea9a877	202	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
ganlikun	0:13413ea9a877	203
ganlikun	0:13413ea9a877	204	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
ganlikun	0:13413ea9a877	205	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
ganlikun	0:13413ea9a877	206
ganlikun	0:13413ea9a877	207	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
ganlikun	0:13413ea9a877	208	This parameter can be a value of @ref RCC_RTC_Clock_Source */
ganlikun	0:13413ea9a877	209
ganlikun	0:13413ea9a877	210	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
ganlikun	0:13413ea9a877	211	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
ganlikun	0:13413ea9a877	212
ganlikun	0:13413ea9a877	213	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
ganlikun	0:13413ea9a877	214	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
ganlikun	0:13413ea9a877	215
ganlikun	0:13413ea9a877	216	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
ganlikun	0:13413ea9a877	217	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
ganlikun	0:13413ea9a877	218	}RCC_PeriphCLKInitTypeDef;
ganlikun	0:13413ea9a877	219	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	220
ganlikun	0:13413ea9a877	221	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	222	/**
ganlikun	0:13413ea9a877	223	* @brief PLLI2S Clock structure definition
ganlikun	0:13413ea9a877	224	*/
ganlikun	0:13413ea9a877	225	typedef struct
ganlikun	0:13413ea9a877	226	{
ganlikun	0:13413ea9a877	227	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
ganlikun	0:13413ea9a877	228	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
ganlikun	0:13413ea9a877	229
ganlikun	0:13413ea9a877	230	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
ganlikun	0:13413ea9a877	231	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
ganlikun	0:13413ea9a877	232
ganlikun	0:13413ea9a877	233	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
ganlikun	0:13413ea9a877	234	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	235	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	236
ganlikun	0:13413ea9a877	237	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
ganlikun	0:13413ea9a877	238	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	239	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
ganlikun	0:13413ea9a877	240	}RCC_PLLI2SInitTypeDef;
ganlikun	0:13413ea9a877	241
ganlikun	0:13413ea9a877	242	/**
ganlikun	0:13413ea9a877	243	* @brief RCC extended clocks structure definition
ganlikun	0:13413ea9a877	244	*/
ganlikun	0:13413ea9a877	245	typedef struct
ganlikun	0:13413ea9a877	246	{
ganlikun	0:13413ea9a877	247	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
ganlikun	0:13413ea9a877	248	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
ganlikun	0:13413ea9a877	249
ganlikun	0:13413ea9a877	250	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
ganlikun	0:13413ea9a877	251	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
ganlikun	0:13413ea9a877	252
ganlikun	0:13413ea9a877	253	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	254	uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
ganlikun	0:13413ea9a877	255	This parameter must be a number between Min_Data = 1 and Max_Data = 32
ganlikun	0:13413ea9a877	256	This parameter will be used only when PLL is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	257
ganlikun	0:13413ea9a877	258	uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
ganlikun	0:13413ea9a877	259	This parameter must be a number between Min_Data = 1 and Max_Data = 32
ganlikun	0:13413ea9a877	260	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	261	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	262
ganlikun	0:13413ea9a877	263	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
ganlikun	0:13413ea9a877	264	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
ganlikun	0:13413ea9a877	265
ganlikun	0:13413ea9a877	266	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
ganlikun	0:13413ea9a877	267	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
ganlikun	0:13413ea9a877	268
ganlikun	0:13413ea9a877	269	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
ganlikun	0:13413ea9a877	270	This parameter can be a value of @ref RCC_RTC_Clock_Source */
ganlikun	0:13413ea9a877	271
ganlikun	0:13413ea9a877	272	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
ganlikun	0:13413ea9a877	273	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
ganlikun	0:13413ea9a877	274
ganlikun	0:13413ea9a877	275	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
ganlikun	0:13413ea9a877	276	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
ganlikun	0:13413ea9a877	277
ganlikun	0:13413ea9a877	278	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
ganlikun	0:13413ea9a877	279	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
ganlikun	0:13413ea9a877	280
ganlikun	0:13413ea9a877	281	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
ganlikun	0:13413ea9a877	282	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
ganlikun	0:13413ea9a877	283
ganlikun	0:13413ea9a877	284	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
ganlikun	0:13413ea9a877	285	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
ganlikun	0:13413ea9a877	286
ganlikun	0:13413ea9a877	287	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	288	uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
ganlikun	0:13413ea9a877	289	This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
ganlikun	0:13413ea9a877	290
ganlikun	0:13413ea9a877	291	uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
ganlikun	0:13413ea9a877	292	This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
ganlikun	0:13413ea9a877	293
ganlikun	0:13413ea9a877	294	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
ganlikun	0:13413ea9a877	295	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
ganlikun	0:13413ea9a877	296
ganlikun	0:13413ea9a877	297	uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
ganlikun	0:13413ea9a877	298	This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
ganlikun	0:13413ea9a877	299
ganlikun	0:13413ea9a877	300	uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
ganlikun	0:13413ea9a877	301	This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
ganlikun	0:13413ea9a877	302	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	303
ganlikun	0:13413ea9a877	304	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
ganlikun	0:13413ea9a877	305	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
ganlikun	0:13413ea9a877	306
ganlikun	0:13413ea9a877	307	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
ganlikun	0:13413ea9a877	308	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
ganlikun	0:13413ea9a877	309	}RCC_PeriphCLKInitTypeDef;
ganlikun	0:13413ea9a877	310	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	311
ganlikun	0:13413ea9a877	312	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	313	/**
ganlikun	0:13413ea9a877	314	* @brief PLLI2S Clock structure definition
ganlikun	0:13413ea9a877	315	*/
ganlikun	0:13413ea9a877	316	typedef struct
ganlikun	0:13413ea9a877	317	{
ganlikun	0:13413ea9a877	318	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
ganlikun	0:13413ea9a877	319	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	320	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
ganlikun	0:13413ea9a877	321
ganlikun	0:13413ea9a877	322	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
ganlikun	0:13413ea9a877	323	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	324	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
ganlikun	0:13413ea9a877	325
ganlikun	0:13413ea9a877	326	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
ganlikun	0:13413ea9a877	327	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	328	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	329	}RCC_PLLI2SInitTypeDef;
ganlikun	0:13413ea9a877	330
ganlikun	0:13413ea9a877	331	/**
ganlikun	0:13413ea9a877	332	* @brief PLLSAI Clock structure definition
ganlikun	0:13413ea9a877	333	*/
ganlikun	0:13413ea9a877	334	typedef struct
ganlikun	0:13413ea9a877	335	{
ganlikun	0:13413ea9a877	336	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
ganlikun	0:13413ea9a877	337	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	338	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
ganlikun	0:13413ea9a877	339	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	340	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
ganlikun	0:13413ea9a877	341	This parameter is only available in STM32F469xx/STM32F479xx devices.
ganlikun	0:13413ea9a877	342	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
ganlikun	0:13413ea9a877	343	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	344
ganlikun	0:13413ea9a877	345	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
ganlikun	0:13413ea9a877	346	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	347	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
ganlikun	0:13413ea9a877	348
ganlikun	0:13413ea9a877	349	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
ganlikun	0:13413ea9a877	350	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	351	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
ganlikun	0:13413ea9a877	352
ganlikun	0:13413ea9a877	353	}RCC_PLLSAIInitTypeDef;
ganlikun	0:13413ea9a877	354
ganlikun	0:13413ea9a877	355	/**
ganlikun	0:13413ea9a877	356	* @brief RCC extended clocks structure definition
ganlikun	0:13413ea9a877	357	*/
ganlikun	0:13413ea9a877	358	typedef struct
ganlikun	0:13413ea9a877	359	{
ganlikun	0:13413ea9a877	360	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
ganlikun	0:13413ea9a877	361	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
ganlikun	0:13413ea9a877	362
ganlikun	0:13413ea9a877	363	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
ganlikun	0:13413ea9a877	364	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
ganlikun	0:13413ea9a877	365
ganlikun	0:13413ea9a877	366	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
ganlikun	0:13413ea9a877	367	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
ganlikun	0:13413ea9a877	368
ganlikun	0:13413ea9a877	369	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
ganlikun	0:13413ea9a877	370	This parameter must be a number between Min_Data = 1 and Max_Data = 32
ganlikun	0:13413ea9a877	371	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	372
ganlikun	0:13413ea9a877	373	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
ganlikun	0:13413ea9a877	374	This parameter must be a number between Min_Data = 1 and Max_Data = 32
ganlikun	0:13413ea9a877	375	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
ganlikun	0:13413ea9a877	376
ganlikun	0:13413ea9a877	377	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
ganlikun	0:13413ea9a877	378	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
ganlikun	0:13413ea9a877	379
ganlikun	0:13413ea9a877	380	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
ganlikun	0:13413ea9a877	381	This parameter can be a value of @ref RCC_RTC_Clock_Source */
ganlikun	0:13413ea9a877	382
ganlikun	0:13413ea9a877	383	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
ganlikun	0:13413ea9a877	384	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
ganlikun	0:13413ea9a877	385	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	386	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
ganlikun	0:13413ea9a877	387	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
ganlikun	0:13413ea9a877	388
ganlikun	0:13413ea9a877	389	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
ganlikun	0:13413ea9a877	390	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
ganlikun	0:13413ea9a877	391	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	392	}RCC_PeriphCLKInitTypeDef;
ganlikun	0:13413ea9a877	393
ganlikun	0:13413ea9a877	394	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	395
ganlikun	0:13413ea9a877	396	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
ganlikun	0:13413ea9a877	397	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
ganlikun	0:13413ea9a877	398	/**
ganlikun	0:13413ea9a877	399	* @brief PLLI2S Clock structure definition
ganlikun	0:13413ea9a877	400	*/
ganlikun	0:13413ea9a877	401	typedef struct
ganlikun	0:13413ea9a877	402	{
ganlikun	0:13413ea9a877	403	#if defined(STM32F411xE)
ganlikun	0:13413ea9a877	404	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
ganlikun	0:13413ea9a877	405	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
ganlikun	0:13413ea9a877	406	#endif /* STM32F411xE */
ganlikun	0:13413ea9a877	407
ganlikun	0:13413ea9a877	408	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
ganlikun	0:13413ea9a877	409	This parameter must be a number between Min_Data = 50 and Max_Data = 432
ganlikun	0:13413ea9a877	410	Except for STM32F411xE devices where the Min_Data = 192.
ganlikun	0:13413ea9a877	411	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
ganlikun	0:13413ea9a877	412
ganlikun	0:13413ea9a877	413	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
ganlikun	0:13413ea9a877	414	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	415	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
ganlikun	0:13413ea9a877	416
ganlikun	0:13413ea9a877	417	}RCC_PLLI2SInitTypeDef;
ganlikun	0:13413ea9a877	418
ganlikun	0:13413ea9a877	419	/**
ganlikun	0:13413ea9a877	420	* @brief RCC extended clocks structure definition
ganlikun	0:13413ea9a877	421	*/
ganlikun	0:13413ea9a877	422	typedef struct
ganlikun	0:13413ea9a877	423	{
ganlikun	0:13413ea9a877	424	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
ganlikun	0:13413ea9a877	425	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
ganlikun	0:13413ea9a877	426
ganlikun	0:13413ea9a877	427	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
ganlikun	0:13413ea9a877	428	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
ganlikun	0:13413ea9a877	429
ganlikun	0:13413ea9a877	430	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
ganlikun	0:13413ea9a877	431	This parameter can be a value of @ref RCC_RTC_Clock_Source */
ganlikun	0:13413ea9a877	432	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
ganlikun	0:13413ea9a877	433	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
ganlikun	0:13413ea9a877	434	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
ganlikun	0:13413ea9a877	435	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
ganlikun	0:13413ea9a877	436	}RCC_PeriphCLKInitTypeDef;
ganlikun	0:13413ea9a877	437	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
ganlikun	0:13413ea9a877	438	/**
ganlikun	0:13413ea9a877	439	* @}
ganlikun	0:13413ea9a877	440	*/
ganlikun	0:13413ea9a877	441
ganlikun	0:13413ea9a877	442	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	443	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
ganlikun	0:13413ea9a877	444	* @{
ganlikun	0:13413ea9a877	445	*/
ganlikun	0:13413ea9a877	446
ganlikun	0:13413ea9a877	447	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
ganlikun	0:13413ea9a877	448	* @{
ganlikun	0:13413ea9a877	449	*/
ganlikun	0:13413ea9a877	450	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
ganlikun	0:13413ea9a877	451	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
ganlikun	0:13413ea9a877	452	defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	453	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
ganlikun	0:13413ea9a877	454	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
ganlikun	0:13413ea9a877	455	#define RCC_PERIPHCLK_TIM 0x00000004U
ganlikun	0:13413ea9a877	456	#define RCC_PERIPHCLK_RTC 0x00000008U
ganlikun	0:13413ea9a877	457	#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
ganlikun	0:13413ea9a877	458	#define RCC_PERIPHCLK_CLK48 0x00000020U
ganlikun	0:13413ea9a877	459	#define RCC_PERIPHCLK_SDIO 0x00000040U
ganlikun	0:13413ea9a877	460	#define RCC_PERIPHCLK_PLLI2S 0x00000080U
ganlikun	0:13413ea9a877	461	#define RCC_PERIPHCLK_DFSDM1 0x00000100U
ganlikun	0:13413ea9a877	462	#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
ganlikun	0:13413ea9a877	463	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
ganlikun	0:13413ea9a877	464	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	465	#define RCC_PERIPHCLK_DFSDM2 0x00000400U
ganlikun	0:13413ea9a877	466	#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
ganlikun	0:13413ea9a877	467	#define RCC_PERIPHCLK_LPTIM1 0x00001000U
ganlikun	0:13413ea9a877	468	#define RCC_PERIPHCLK_SAIA 0x00002000U
ganlikun	0:13413ea9a877	469	#define RCC_PERIPHCLK_SAIB 0x00004000U
ganlikun	0:13413ea9a877	470	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	471	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	472
ganlikun	0:13413ea9a877	473	/------------------- Peripheral Clock source for STM32F410xx ----------------/
ganlikun	0:13413ea9a877	474	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	475	#define RCC_PERIPHCLK_I2S 0x00000001U
ganlikun	0:13413ea9a877	476	#define RCC_PERIPHCLK_TIM 0x00000002U
ganlikun	0:13413ea9a877	477	#define RCC_PERIPHCLK_RTC 0x00000004U
ganlikun	0:13413ea9a877	478	#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
ganlikun	0:13413ea9a877	479	#define RCC_PERIPHCLK_LPTIM1 0x00000010U
ganlikun	0:13413ea9a877	480	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	481	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	482
ganlikun	0:13413ea9a877	483	/------------------- Peripheral Clock source for STM32F446xx ----------------/
ganlikun	0:13413ea9a877	484	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	485	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
ganlikun	0:13413ea9a877	486	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
ganlikun	0:13413ea9a877	487	#define RCC_PERIPHCLK_SAI1 0x00000004U
ganlikun	0:13413ea9a877	488	#define RCC_PERIPHCLK_SAI2 0x00000008U
ganlikun	0:13413ea9a877	489	#define RCC_PERIPHCLK_TIM 0x00000010U
ganlikun	0:13413ea9a877	490	#define RCC_PERIPHCLK_RTC 0x00000020U
ganlikun	0:13413ea9a877	491	#define RCC_PERIPHCLK_CEC 0x00000040U
ganlikun	0:13413ea9a877	492	#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
ganlikun	0:13413ea9a877	493	#define RCC_PERIPHCLK_CLK48 0x00000100U
ganlikun	0:13413ea9a877	494	#define RCC_PERIPHCLK_SDIO 0x00000200U
ganlikun	0:13413ea9a877	495	#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
ganlikun	0:13413ea9a877	496	#define RCC_PERIPHCLK_PLLI2S 0x00000800U
ganlikun	0:13413ea9a877	497	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	498	/-----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	499
ganlikun	0:13413ea9a877	500	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
ganlikun	0:13413ea9a877	501	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	502	#define RCC_PERIPHCLK_I2S 0x00000001U
ganlikun	0:13413ea9a877	503	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
ganlikun	0:13413ea9a877	504	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
ganlikun	0:13413ea9a877	505	#define RCC_PERIPHCLK_LTDC 0x00000008U
ganlikun	0:13413ea9a877	506	#define RCC_PERIPHCLK_TIM 0x00000010U
ganlikun	0:13413ea9a877	507	#define RCC_PERIPHCLK_RTC 0x00000020U
ganlikun	0:13413ea9a877	508	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
ganlikun	0:13413ea9a877	509	#define RCC_PERIPHCLK_CLK48 0x00000080U
ganlikun	0:13413ea9a877	510	#define RCC_PERIPHCLK_SDIO 0x00000100U
ganlikun	0:13413ea9a877	511	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	512	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	513
ganlikun	0:13413ea9a877	514	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
ganlikun	0:13413ea9a877	515	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	516	#define RCC_PERIPHCLK_I2S 0x00000001U
ganlikun	0:13413ea9a877	517	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
ganlikun	0:13413ea9a877	518	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
ganlikun	0:13413ea9a877	519	#define RCC_PERIPHCLK_LTDC 0x00000008U
ganlikun	0:13413ea9a877	520	#define RCC_PERIPHCLK_TIM 0x00000010U
ganlikun	0:13413ea9a877	521	#define RCC_PERIPHCLK_RTC 0x00000020U
ganlikun	0:13413ea9a877	522	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
ganlikun	0:13413ea9a877	523	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	524	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	525
ganlikun	0:13413ea9a877	526	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
ganlikun	0:13413ea9a877	527	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
ganlikun	0:13413ea9a877	528	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
ganlikun	0:13413ea9a877	529	#define RCC_PERIPHCLK_I2S 0x00000001U
ganlikun	0:13413ea9a877	530	#define RCC_PERIPHCLK_RTC 0x00000002U
ganlikun	0:13413ea9a877	531	#define RCC_PERIPHCLK_PLLI2S 0x00000004U
ganlikun	0:13413ea9a877	532	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
ganlikun	0:13413ea9a877	533	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
ganlikun	0:13413ea9a877	534	#define RCC_PERIPHCLK_TIM 0x00000008U
ganlikun	0:13413ea9a877	535	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
ganlikun	0:13413ea9a877	536	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	537	/**
ganlikun	0:13413ea9a877	538	* @}
ganlikun	0:13413ea9a877	539	*/
ganlikun	0:13413ea9a877	540	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
ganlikun	0:13413ea9a877	541	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
ganlikun	0:13413ea9a877	542	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\| \
ganlikun	0:13413ea9a877	543	defined(STM32F479xx)
ganlikun	0:13413ea9a877	544	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
ganlikun	0:13413ea9a877	545	* @{
ganlikun	0:13413ea9a877	546	*/
ganlikun	0:13413ea9a877	547	#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
ganlikun	0:13413ea9a877	548	#define RCC_I2SCLKSOURCE_EXT 0x00000001U
ganlikun	0:13413ea9a877	549	/**
ganlikun	0:13413ea9a877	550	* @}
ganlikun	0:13413ea9a877	551	*/
ganlikun	0:13413ea9a877	552	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
ganlikun	0:13413ea9a877	553	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	554
ganlikun	0:13413ea9a877	555	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
ganlikun	0:13413ea9a877	556	* @{
ganlikun	0:13413ea9a877	557	*/
ganlikun	0:13413ea9a877	558	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
ganlikun	0:13413ea9a877	559	defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	560	#define RCC_PLLSAIDIVR_2 0x00000000U
ganlikun	0:13413ea9a877	561	#define RCC_PLLSAIDIVR_4 0x00010000U
ganlikun	0:13413ea9a877	562	#define RCC_PLLSAIDIVR_8 0x00020000U
ganlikun	0:13413ea9a877	563	#define RCC_PLLSAIDIVR_16 0x00030000U
ganlikun	0:13413ea9a877	564	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	565	/**
ganlikun	0:13413ea9a877	566	* @}
ganlikun	0:13413ea9a877	567	*/
ganlikun	0:13413ea9a877	568
ganlikun	0:13413ea9a877	569	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
ganlikun	0:13413ea9a877	570	* @{
ganlikun	0:13413ea9a877	571	*/
ganlikun	0:13413ea9a877	572	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	573	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
ganlikun	0:13413ea9a877	574	#define RCC_PLLI2SP_DIV2 0x00000002U
ganlikun	0:13413ea9a877	575	#define RCC_PLLI2SP_DIV4 0x00000004U
ganlikun	0:13413ea9a877	576	#define RCC_PLLI2SP_DIV6 0x00000006U
ganlikun	0:13413ea9a877	577	#define RCC_PLLI2SP_DIV8 0x00000008U
ganlikun	0:13413ea9a877	578	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
ganlikun	0:13413ea9a877	579	/**
ganlikun	0:13413ea9a877	580	* @}
ganlikun	0:13413ea9a877	581	*/
ganlikun	0:13413ea9a877	582
ganlikun	0:13413ea9a877	583	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
ganlikun	0:13413ea9a877	584	* @{
ganlikun	0:13413ea9a877	585	*/
ganlikun	0:13413ea9a877	586	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	587	#define RCC_PLLSAIP_DIV2 0x00000002U
ganlikun	0:13413ea9a877	588	#define RCC_PLLSAIP_DIV4 0x00000004U
ganlikun	0:13413ea9a877	589	#define RCC_PLLSAIP_DIV6 0x00000006U
ganlikun	0:13413ea9a877	590	#define RCC_PLLSAIP_DIV8 0x00000008U
ganlikun	0:13413ea9a877	591	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	592	/**
ganlikun	0:13413ea9a877	593	* @}
ganlikun	0:13413ea9a877	594	*/
ganlikun	0:13413ea9a877	595
ganlikun	0:13413ea9a877	596	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	597	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
ganlikun	0:13413ea9a877	598	* @{
ganlikun	0:13413ea9a877	599	*/
ganlikun	0:13413ea9a877	600	#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
ganlikun	0:13413ea9a877	601	#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
ganlikun	0:13413ea9a877	602	#define RCC_SAIACLKSOURCE_EXT 0x00200000U
ganlikun	0:13413ea9a877	603	/**
ganlikun	0:13413ea9a877	604	* @}
ganlikun	0:13413ea9a877	605	*/
ganlikun	0:13413ea9a877	606
ganlikun	0:13413ea9a877	607	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
ganlikun	0:13413ea9a877	608	* @{
ganlikun	0:13413ea9a877	609	*/
ganlikun	0:13413ea9a877	610	#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
ganlikun	0:13413ea9a877	611	#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
ganlikun	0:13413ea9a877	612	#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
ganlikun	0:13413ea9a877	613	/**
ganlikun	0:13413ea9a877	614	* @}
ganlikun	0:13413ea9a877	615	*/
ganlikun	0:13413ea9a877	616	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	617
ganlikun	0:13413ea9a877	618	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	619	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
ganlikun	0:13413ea9a877	620	* @{
ganlikun	0:13413ea9a877	621	*/
ganlikun	0:13413ea9a877	622	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
ganlikun	0:13413ea9a877	623	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	624	/**
ganlikun	0:13413ea9a877	625	* @}
ganlikun	0:13413ea9a877	626	*/
ganlikun	0:13413ea9a877	627
ganlikun	0:13413ea9a877	628	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
ganlikun	0:13413ea9a877	629	* @{
ganlikun	0:13413ea9a877	630	*/
ganlikun	0:13413ea9a877	631	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
ganlikun	0:13413ea9a877	632	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
ganlikun	0:13413ea9a877	633	/**
ganlikun	0:13413ea9a877	634	* @}
ganlikun	0:13413ea9a877	635	*/
ganlikun	0:13413ea9a877	636
ganlikun	0:13413ea9a877	637	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
ganlikun	0:13413ea9a877	638	* @{
ganlikun	0:13413ea9a877	639	*/
ganlikun	0:13413ea9a877	640	#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
ganlikun	0:13413ea9a877	641	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
ganlikun	0:13413ea9a877	642	/**
ganlikun	0:13413ea9a877	643	* @}
ganlikun	0:13413ea9a877	644	*/
ganlikun	0:13413ea9a877	645	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	646
ganlikun	0:13413ea9a877	647	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	648	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
ganlikun	0:13413ea9a877	649	* @{
ganlikun	0:13413ea9a877	650	*/
ganlikun	0:13413ea9a877	651	#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
ganlikun	0:13413ea9a877	652	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
ganlikun	0:13413ea9a877	653	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
ganlikun	0:13413ea9a877	654	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
ganlikun	0:13413ea9a877	655	/**
ganlikun	0:13413ea9a877	656	* @}
ganlikun	0:13413ea9a877	657	*/
ganlikun	0:13413ea9a877	658
ganlikun	0:13413ea9a877	659	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
ganlikun	0:13413ea9a877	660	* @{
ganlikun	0:13413ea9a877	661	*/
ganlikun	0:13413ea9a877	662	#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
ganlikun	0:13413ea9a877	663	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
ganlikun	0:13413ea9a877	664	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
ganlikun	0:13413ea9a877	665	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
ganlikun	0:13413ea9a877	666	/**
ganlikun	0:13413ea9a877	667	* @}
ganlikun	0:13413ea9a877	668	*/
ganlikun	0:13413ea9a877	669
ganlikun	0:13413ea9a877	670	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
ganlikun	0:13413ea9a877	671	* @{
ganlikun	0:13413ea9a877	672	*/
ganlikun	0:13413ea9a877	673	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
ganlikun	0:13413ea9a877	674	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
ganlikun	0:13413ea9a877	675	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
ganlikun	0:13413ea9a877	676	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
ganlikun	0:13413ea9a877	677	/**
ganlikun	0:13413ea9a877	678	* @}
ganlikun	0:13413ea9a877	679	*/
ganlikun	0:13413ea9a877	680
ganlikun	0:13413ea9a877	681	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
ganlikun	0:13413ea9a877	682	* @{
ganlikun	0:13413ea9a877	683	*/
ganlikun	0:13413ea9a877	684	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
ganlikun	0:13413ea9a877	685	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
ganlikun	0:13413ea9a877	686	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
ganlikun	0:13413ea9a877	687	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
ganlikun	0:13413ea9a877	688	/**
ganlikun	0:13413ea9a877	689	* @}
ganlikun	0:13413ea9a877	690	*/
ganlikun	0:13413ea9a877	691
ganlikun	0:13413ea9a877	692	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
ganlikun	0:13413ea9a877	693	* @{
ganlikun	0:13413ea9a877	694	*/
ganlikun	0:13413ea9a877	695	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
ganlikun	0:13413ea9a877	696	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
ganlikun	0:13413ea9a877	697	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
ganlikun	0:13413ea9a877	698	/**
ganlikun	0:13413ea9a877	699	* @}
ganlikun	0:13413ea9a877	700	*/
ganlikun	0:13413ea9a877	701
ganlikun	0:13413ea9a877	702	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
ganlikun	0:13413ea9a877	703	* @{
ganlikun	0:13413ea9a877	704	*/
ganlikun	0:13413ea9a877	705	#define RCC_CECCLKSOURCE_HSI 0x00000000U
ganlikun	0:13413ea9a877	706	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
ganlikun	0:13413ea9a877	707	/**
ganlikun	0:13413ea9a877	708	* @}
ganlikun	0:13413ea9a877	709	*/
ganlikun	0:13413ea9a877	710
ganlikun	0:13413ea9a877	711	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
ganlikun	0:13413ea9a877	712	* @{
ganlikun	0:13413ea9a877	713	*/
ganlikun	0:13413ea9a877	714	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
ganlikun	0:13413ea9a877	715	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	716	/**
ganlikun	0:13413ea9a877	717	* @}
ganlikun	0:13413ea9a877	718	*/
ganlikun	0:13413ea9a877	719
ganlikun	0:13413ea9a877	720	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
ganlikun	0:13413ea9a877	721	* @{
ganlikun	0:13413ea9a877	722	*/
ganlikun	0:13413ea9a877	723	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
ganlikun	0:13413ea9a877	724	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
ganlikun	0:13413ea9a877	725	/**
ganlikun	0:13413ea9a877	726	* @}
ganlikun	0:13413ea9a877	727	*/
ganlikun	0:13413ea9a877	728
ganlikun	0:13413ea9a877	729	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
ganlikun	0:13413ea9a877	730	* @{
ganlikun	0:13413ea9a877	731	*/
ganlikun	0:13413ea9a877	732	#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
ganlikun	0:13413ea9a877	733	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
ganlikun	0:13413ea9a877	734	/**
ganlikun	0:13413ea9a877	735	* @}
ganlikun	0:13413ea9a877	736	*/
ganlikun	0:13413ea9a877	737	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	738
ganlikun	0:13413ea9a877	739	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	740	/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
ganlikun	0:13413ea9a877	741	* @{
ganlikun	0:13413ea9a877	742	*/
ganlikun	0:13413ea9a877	743	#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
ganlikun	0:13413ea9a877	744	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
ganlikun	0:13413ea9a877	745	#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
ganlikun	0:13413ea9a877	746	#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 \| RCC_DCKCFGR_SAI1ASRC_1)
ganlikun	0:13413ea9a877	747	/**
ganlikun	0:13413ea9a877	748	* @}
ganlikun	0:13413ea9a877	749	*/
ganlikun	0:13413ea9a877	750
ganlikun	0:13413ea9a877	751	/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
ganlikun	0:13413ea9a877	752	* @{
ganlikun	0:13413ea9a877	753	*/
ganlikun	0:13413ea9a877	754	#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
ganlikun	0:13413ea9a877	755	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
ganlikun	0:13413ea9a877	756	#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
ganlikun	0:13413ea9a877	757	#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 \| RCC_DCKCFGR_SAI1BSRC_1)
ganlikun	0:13413ea9a877	758	/**
ganlikun	0:13413ea9a877	759	* @}
ganlikun	0:13413ea9a877	760	*/
ganlikun	0:13413ea9a877	761
ganlikun	0:13413ea9a877	762	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
ganlikun	0:13413ea9a877	763	* @{
ganlikun	0:13413ea9a877	764	*/
ganlikun	0:13413ea9a877	765	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
ganlikun	0:13413ea9a877	766	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
ganlikun	0:13413ea9a877	767	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
ganlikun	0:13413ea9a877	768	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
ganlikun	0:13413ea9a877	769	/**
ganlikun	0:13413ea9a877	770	* @}
ganlikun	0:13413ea9a877	771	*/
ganlikun	0:13413ea9a877	772
ganlikun	0:13413ea9a877	773
ganlikun	0:13413ea9a877	774	/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
ganlikun	0:13413ea9a877	775	* @{
ganlikun	0:13413ea9a877	776	*/
ganlikun	0:13413ea9a877	777	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
ganlikun	0:13413ea9a877	778	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
ganlikun	0:13413ea9a877	779	/**
ganlikun	0:13413ea9a877	780	* @}
ganlikun	0:13413ea9a877	781	*/
ganlikun	0:13413ea9a877	782
ganlikun	0:13413ea9a877	783	/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
ganlikun	0:13413ea9a877	784	* @{
ganlikun	0:13413ea9a877	785	*/
ganlikun	0:13413ea9a877	786	#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
ganlikun	0:13413ea9a877	787	#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
ganlikun	0:13413ea9a877	788	/**
ganlikun	0:13413ea9a877	789	* @}
ganlikun	0:13413ea9a877	790	*/
ganlikun	0:13413ea9a877	791
ganlikun	0:13413ea9a877	792	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	793
ganlikun	0:13413ea9a877	794	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	795	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
ganlikun	0:13413ea9a877	796	* @{
ganlikun	0:13413ea9a877	797	*/
ganlikun	0:13413ea9a877	798	#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
ganlikun	0:13413ea9a877	799	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
ganlikun	0:13413ea9a877	800	/**
ganlikun	0:13413ea9a877	801	* @}
ganlikun	0:13413ea9a877	802	*/
ganlikun	0:13413ea9a877	803
ganlikun	0:13413ea9a877	804	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
ganlikun	0:13413ea9a877	805	* @{
ganlikun	0:13413ea9a877	806	*/
ganlikun	0:13413ea9a877	807	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
ganlikun	0:13413ea9a877	808	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
ganlikun	0:13413ea9a877	809	/**
ganlikun	0:13413ea9a877	810	* @}
ganlikun	0:13413ea9a877	811	*/
ganlikun	0:13413ea9a877	812
ganlikun	0:13413ea9a877	813	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
ganlikun	0:13413ea9a877	814	* @{
ganlikun	0:13413ea9a877	815	*/
ganlikun	0:13413ea9a877	816	#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
ganlikun	0:13413ea9a877	817	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
ganlikun	0:13413ea9a877	818	/**
ganlikun	0:13413ea9a877	819	* @}
ganlikun	0:13413ea9a877	820	*/
ganlikun	0:13413ea9a877	821
ganlikun	0:13413ea9a877	822	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
ganlikun	0:13413ea9a877	823	* @{
ganlikun	0:13413ea9a877	824	*/
ganlikun	0:13413ea9a877	825	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
ganlikun	0:13413ea9a877	826	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
ganlikun	0:13413ea9a877	827	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
ganlikun	0:13413ea9a877	828	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
ganlikun	0:13413ea9a877	829	/**
ganlikun	0:13413ea9a877	830	* @}
ganlikun	0:13413ea9a877	831	*/
ganlikun	0:13413ea9a877	832
ganlikun	0:13413ea9a877	833	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
ganlikun	0:13413ea9a877	834	* @{
ganlikun	0:13413ea9a877	835	*/
ganlikun	0:13413ea9a877	836	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
ganlikun	0:13413ea9a877	837	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
ganlikun	0:13413ea9a877	838	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
ganlikun	0:13413ea9a877	839	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
ganlikun	0:13413ea9a877	840	/**
ganlikun	0:13413ea9a877	841	* @}
ganlikun	0:13413ea9a877	842	*/
ganlikun	0:13413ea9a877	843
ganlikun	0:13413ea9a877	844	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
ganlikun	0:13413ea9a877	845	* @{
ganlikun	0:13413ea9a877	846	*/
ganlikun	0:13413ea9a877	847	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
ganlikun	0:13413ea9a877	848	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
ganlikun	0:13413ea9a877	849	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
ganlikun	0:13413ea9a877	850	/**
ganlikun	0:13413ea9a877	851	* @}
ganlikun	0:13413ea9a877	852	*/
ganlikun	0:13413ea9a877	853
ganlikun	0:13413ea9a877	854	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
ganlikun	0:13413ea9a877	855	* @{
ganlikun	0:13413ea9a877	856	*/
ganlikun	0:13413ea9a877	857	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
ganlikun	0:13413ea9a877	858	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	859	/**
ganlikun	0:13413ea9a877	860	* @}
ganlikun	0:13413ea9a877	861	*/
ganlikun	0:13413ea9a877	862
ganlikun	0:13413ea9a877	863	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
ganlikun	0:13413ea9a877	864	* @{
ganlikun	0:13413ea9a877	865	*/
ganlikun	0:13413ea9a877	866	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
ganlikun	0:13413ea9a877	867	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
ganlikun	0:13413ea9a877	868	/**
ganlikun	0:13413ea9a877	869	* @}
ganlikun	0:13413ea9a877	870	*/
ganlikun	0:13413ea9a877	871	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	872
ganlikun	0:13413ea9a877	873	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	874	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
ganlikun	0:13413ea9a877	875	* @{
ganlikun	0:13413ea9a877	876	*/
ganlikun	0:13413ea9a877	877	#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
ganlikun	0:13413ea9a877	878	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
ganlikun	0:13413ea9a877	879	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
ganlikun	0:13413ea9a877	880	/**
ganlikun	0:13413ea9a877	881	* @}
ganlikun	0:13413ea9a877	882	*/
ganlikun	0:13413ea9a877	883
ganlikun	0:13413ea9a877	884	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
ganlikun	0:13413ea9a877	885	* @{
ganlikun	0:13413ea9a877	886	*/
ganlikun	0:13413ea9a877	887	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
ganlikun	0:13413ea9a877	888	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
ganlikun	0:13413ea9a877	889	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
ganlikun	0:13413ea9a877	890	/**
ganlikun	0:13413ea9a877	891	* @}
ganlikun	0:13413ea9a877	892	*/
ganlikun	0:13413ea9a877	893
ganlikun	0:13413ea9a877	894	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
ganlikun	0:13413ea9a877	895	* @{
ganlikun	0:13413ea9a877	896	*/
ganlikun	0:13413ea9a877	897	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
ganlikun	0:13413ea9a877	898	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
ganlikun	0:13413ea9a877	899	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
ganlikun	0:13413ea9a877	900	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
ganlikun	0:13413ea9a877	901	/**
ganlikun	0:13413ea9a877	902	* @}
ganlikun	0:13413ea9a877	903	*/
ganlikun	0:13413ea9a877	904	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	905
ganlikun	0:13413ea9a877	906	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	907	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
ganlikun	0:13413ea9a877	908	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
ganlikun	0:13413ea9a877	909	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
ganlikun	0:13413ea9a877	910	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	911	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
ganlikun	0:13413ea9a877	912	* @{
ganlikun	0:13413ea9a877	913	*/
ganlikun	0:13413ea9a877	914	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
ganlikun	0:13413ea9a877	915	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
ganlikun	0:13413ea9a877	916	/**
ganlikun	0:13413ea9a877	917	* @}
ganlikun	0:13413ea9a877	918	*/
ganlikun	0:13413ea9a877	919	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
ganlikun	0:13413ea9a877	920	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
ganlikun	0:13413ea9a877	921	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	922
ganlikun	0:13413ea9a877	923	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
ganlikun	0:13413ea9a877	924	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
ganlikun	0:13413ea9a877	925	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
ganlikun	0:13413ea9a877	926	defined(STM32F423xx)
ganlikun	0:13413ea9a877	927	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
ganlikun	0:13413ea9a877	928	* @{
ganlikun	0:13413ea9a877	929	*/
ganlikun	0:13413ea9a877	930	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
ganlikun	0:13413ea9a877	931	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
ganlikun	0:13413ea9a877	932	/**
ganlikun	0:13413ea9a877	933	* @}
ganlikun	0:13413ea9a877	934	*/
ganlikun	0:13413ea9a877	935	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
ganlikun	0:13413ea9a877	936	STM32F412Rx \|\| STM32F412Cx */
ganlikun	0:13413ea9a877	937
ganlikun	0:13413ea9a877	938	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
ganlikun	0:13413ea9a877	939	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
ganlikun	0:13413ea9a877	940	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
ganlikun	0:13413ea9a877	941	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	942	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	943	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
ganlikun	0:13413ea9a877	944	* @{
ganlikun	0:13413ea9a877	945	*/
ganlikun	0:13413ea9a877	946	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
ganlikun	0:13413ea9a877	947	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
ganlikun	0:13413ea9a877	948	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
ganlikun	0:13413ea9a877	949	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
ganlikun	0:13413ea9a877	950	/**
ganlikun	0:13413ea9a877	951	* @}
ganlikun	0:13413ea9a877	952	*/
ganlikun	0:13413ea9a877	953	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
ganlikun	0:13413ea9a877	954	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
ganlikun	0:13413ea9a877	955	STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
ganlikun	0:13413ea9a877	956
ganlikun	0:13413ea9a877	957	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	958	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
ganlikun	0:13413ea9a877	959	* @{
ganlikun	0:13413ea9a877	960	*/
ganlikun	0:13413ea9a877	961	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
ganlikun	0:13413ea9a877	962	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
ganlikun	0:13413ea9a877	963	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
ganlikun	0:13413ea9a877	964	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
ganlikun	0:13413ea9a877	965	/**
ganlikun	0:13413ea9a877	966	* @}
ganlikun	0:13413ea9a877	967	*/
ganlikun	0:13413ea9a877	968	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	969
ganlikun	0:13413ea9a877	970	/**
ganlikun	0:13413ea9a877	971	* @}
ganlikun	0:13413ea9a877	972	*/
ganlikun	0:13413ea9a877	973
ganlikun	0:13413ea9a877	974	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	975	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
ganlikun	0:13413ea9a877	976	* @{
ganlikun	0:13413ea9a877	977	*/
ganlikun	0:13413ea9a877	978	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
ganlikun	0:13413ea9a877	979	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	980	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	981	* @brief Enables or disables the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	982	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	983	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	984	* using it.
ganlikun	0:13413ea9a877	985	* @{
ganlikun	0:13413ea9a877	986	*/
ganlikun	0:13413ea9a877	987	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	988	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	989	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
ganlikun	0:13413ea9a877	990	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	991	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
ganlikun	0:13413ea9a877	992	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	993	} while(0U)
ganlikun	0:13413ea9a877	994	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	995	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	996	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	997	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	998	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	999	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1000	} while(0U)
ganlikun	0:13413ea9a877	1001	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1002	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1003	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	1004	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1005	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	1006	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1007	} while(0U)
ganlikun	0:13413ea9a877	1008	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1009	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1010	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	1011	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1012	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	1013	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1014	} while(0U)
ganlikun	0:13413ea9a877	1015	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1016	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1017	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	1018	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1019	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	1020	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1021	} while(0U)
ganlikun	0:13413ea9a877	1022	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1023	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1024	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
ganlikun	0:13413ea9a877	1025	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1026	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
ganlikun	0:13413ea9a877	1027	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1028	} while(0U)
ganlikun	0:13413ea9a877	1029	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1030	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1031	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	1032	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1033	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	1034	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1035	} while(0U)
ganlikun	0:13413ea9a877	1036	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1037	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1038	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	1039	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1040	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	1041	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1042	} while(0U)
ganlikun	0:13413ea9a877	1043	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1044	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1045	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
ganlikun	0:13413ea9a877	1046	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1047	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
ganlikun	0:13413ea9a877	1048	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1049	} while(0U)
ganlikun	0:13413ea9a877	1050	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1051	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1052	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
ganlikun	0:13413ea9a877	1053	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1054	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
ganlikun	0:13413ea9a877	1055	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1056	} while(0U)
ganlikun	0:13413ea9a877	1057	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1058	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1059	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
ganlikun	0:13413ea9a877	1060	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1061	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
ganlikun	0:13413ea9a877	1062	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1063	} while(0U)
ganlikun	0:13413ea9a877	1064	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1065	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1066	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
ganlikun	0:13413ea9a877	1067	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1068	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
ganlikun	0:13413ea9a877	1069	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1070	} while(0U)
ganlikun	0:13413ea9a877	1071	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1072	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1073	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
ganlikun	0:13413ea9a877	1074	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1075	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
ganlikun	0:13413ea9a877	1076	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1077	} while(0U)
ganlikun	0:13413ea9a877	1078	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1079	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1080	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
ganlikun	0:13413ea9a877	1081	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1082	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
ganlikun	0:13413ea9a877	1083	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1084	} while(0U)
ganlikun	0:13413ea9a877	1085	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1086	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1087	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
ganlikun	0:13413ea9a877	1088	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1089	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
ganlikun	0:13413ea9a877	1090	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1091	} while(0U)
ganlikun	0:13413ea9a877	1092	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1093	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1094	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
ganlikun	0:13413ea9a877	1095	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1096	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
ganlikun	0:13413ea9a877	1097	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1098	} while(0U)
ganlikun	0:13413ea9a877	1099	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1100	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1101	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
ganlikun	0:13413ea9a877	1102	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1103	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
ganlikun	0:13413ea9a877	1104	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1105	} while(0U)
ganlikun	0:13413ea9a877	1106	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
ganlikun	0:13413ea9a877	1107	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
ganlikun	0:13413ea9a877	1108	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
ganlikun	0:13413ea9a877	1109	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
ganlikun	0:13413ea9a877	1110	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
ganlikun	0:13413ea9a877	1111	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
ganlikun	0:13413ea9a877	1112	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
ganlikun	0:13413ea9a877	1113	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
ganlikun	0:13413ea9a877	1114	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
ganlikun	0:13413ea9a877	1115	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
ganlikun	0:13413ea9a877	1116	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
ganlikun	0:13413ea9a877	1117	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
ganlikun	0:13413ea9a877	1118	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
ganlikun	0:13413ea9a877	1119	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
ganlikun	0:13413ea9a877	1120	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
ganlikun	0:13413ea9a877	1121	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
ganlikun	0:13413ea9a877	1122	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
ganlikun	0:13413ea9a877	1123
ganlikun	0:13413ea9a877	1124	/**
ganlikun	0:13413ea9a877	1125	* @brief Enable ETHERNET clock.
ganlikun	0:13413ea9a877	1126	*/
ganlikun	0:13413ea9a877	1127	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1128	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
ganlikun	0:13413ea9a877	1129	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
ganlikun	0:13413ea9a877	1130	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
ganlikun	0:13413ea9a877	1131	} while(0U)
ganlikun	0:13413ea9a877	1132	/**
ganlikun	0:13413ea9a877	1133	* @brief Disable ETHERNET clock.
ganlikun	0:13413ea9a877	1134	*/
ganlikun	0:13413ea9a877	1135	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
ganlikun	0:13413ea9a877	1136	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
ganlikun	0:13413ea9a877	1137	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
ganlikun	0:13413ea9a877	1138	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
ganlikun	0:13413ea9a877	1139	} while(0U)
ganlikun	0:13413ea9a877	1140	/**
ganlikun	0:13413ea9a877	1141	* @}
ganlikun	0:13413ea9a877	1142	*/
ganlikun	0:13413ea9a877	1143
ganlikun	0:13413ea9a877	1144	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	1145	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	1146	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1147	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1148	* using it.
ganlikun	0:13413ea9a877	1149	* @{
ganlikun	0:13413ea9a877	1150	*/
ganlikun	0:13413ea9a877	1151	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
ganlikun	0:13413ea9a877	1152	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
ganlikun	0:13413ea9a877	1153	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
ganlikun	0:13413ea9a877	1154	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
ganlikun	0:13413ea9a877	1155	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
ganlikun	0:13413ea9a877	1156	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
ganlikun	0:13413ea9a877	1157	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
ganlikun	0:13413ea9a877	1158	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
ganlikun	0:13413ea9a877	1159	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
ganlikun	0:13413ea9a877	1160	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
ganlikun	0:13413ea9a877	1161	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
ganlikun	0:13413ea9a877	1162	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
ganlikun	0:13413ea9a877	1163	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
ganlikun	0:13413ea9a877	1164	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
ganlikun	0:13413ea9a877	1165	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
ganlikun	0:13413ea9a877	1166	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
ganlikun	0:13413ea9a877	1167	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
ganlikun	0:13413ea9a877	1168	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
ganlikun	0:13413ea9a877	1169	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
ganlikun	0:13413ea9a877	1170	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
ganlikun	0:13413ea9a877	1171
ganlikun	0:13413ea9a877	1172	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
ganlikun	0:13413ea9a877	1173	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
ganlikun	0:13413ea9a877	1174	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
ganlikun	0:13413ea9a877	1175	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
ganlikun	0:13413ea9a877	1176	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
ganlikun	0:13413ea9a877	1177	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
ganlikun	0:13413ea9a877	1178	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
ganlikun	0:13413ea9a877	1179	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
ganlikun	0:13413ea9a877	1180	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
ganlikun	0:13413ea9a877	1181	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
ganlikun	0:13413ea9a877	1182	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
ganlikun	0:13413ea9a877	1183	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
ganlikun	0:13413ea9a877	1184	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
ganlikun	0:13413ea9a877	1185	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
ganlikun	0:13413ea9a877	1186	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
ganlikun	0:13413ea9a877	1187	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
ganlikun	0:13413ea9a877	1188	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
ganlikun	0:13413ea9a877	1189	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
ganlikun	0:13413ea9a877	1190	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
ganlikun	0:13413ea9a877	1191	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
ganlikun	0:13413ea9a877	1192	/**
ganlikun	0:13413ea9a877	1193	* @}
ganlikun	0:13413ea9a877	1194	*/
ganlikun	0:13413ea9a877	1195
ganlikun	0:13413ea9a877	1196	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	1197	* @brief Enable or disable the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	1198	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1199	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1200	* using it.
ganlikun	0:13413ea9a877	1201	* @{
ganlikun	0:13413ea9a877	1202	*/
ganlikun	0:13413ea9a877	1203	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1204	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1205	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
ganlikun	0:13413ea9a877	1206	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1207	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
ganlikun	0:13413ea9a877	1208	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1209	} while(0U)
ganlikun	0:13413ea9a877	1210	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
ganlikun	0:13413ea9a877	1211
ganlikun	0:13413ea9a877	1212	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1213	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1214	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1215	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
ganlikun	0:13413ea9a877	1216	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1217	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
ganlikun	0:13413ea9a877	1218	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1219	} while(0U)
ganlikun	0:13413ea9a877	1220	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1221	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1222	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
ganlikun	0:13413ea9a877	1223	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1224	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
ganlikun	0:13413ea9a877	1225	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1226	} while(0U)
ganlikun	0:13413ea9a877	1227
ganlikun	0:13413ea9a877	1228	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
ganlikun	0:13413ea9a877	1229	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
ganlikun	0:13413ea9a877	1230	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1231
ganlikun	0:13413ea9a877	1232	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
ganlikun	0:13413ea9a877	1233	__HAL_RCC_SYSCFG_CLK_ENABLE();\
ganlikun	0:13413ea9a877	1234	}while(0U)
ganlikun	0:13413ea9a877	1235
ganlikun	0:13413ea9a877	1236	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
ganlikun	0:13413ea9a877	1237
ganlikun	0:13413ea9a877	1238	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1239	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1240	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	1241	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1242	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	1243	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1244	} while(0U)
ganlikun	0:13413ea9a877	1245	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
ganlikun	0:13413ea9a877	1246	/**
ganlikun	0:13413ea9a877	1247	* @}
ganlikun	0:13413ea9a877	1248	*/
ganlikun	0:13413ea9a877	1249
ganlikun	0:13413ea9a877	1250	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	1251	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	1252	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1253	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1254	* using it.
ganlikun	0:13413ea9a877	1255	* @{
ganlikun	0:13413ea9a877	1256	*/
ganlikun	0:13413ea9a877	1257	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
ganlikun	0:13413ea9a877	1258	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
ganlikun	0:13413ea9a877	1259
ganlikun	0:13413ea9a877	1260	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1261	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
ganlikun	0:13413ea9a877	1262	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
ganlikun	0:13413ea9a877	1263
ganlikun	0:13413ea9a877	1264	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
ganlikun	0:13413ea9a877	1265	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
ganlikun	0:13413ea9a877	1266	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1267
ganlikun	0:13413ea9a877	1268	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
ganlikun	0:13413ea9a877	1269	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
ganlikun	0:13413ea9a877	1270
ganlikun	0:13413ea9a877	1271	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
ganlikun	0:13413ea9a877	1272	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
ganlikun	0:13413ea9a877	1273	/**
ganlikun	0:13413ea9a877	1274	* @}
ganlikun	0:13413ea9a877	1275	*/
ganlikun	0:13413ea9a877	1276
ganlikun	0:13413ea9a877	1277	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	1278	* @brief Enables or disables the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	1279	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1280	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1281	* using it.
ganlikun	0:13413ea9a877	1282	* @{
ganlikun	0:13413ea9a877	1283	*/
ganlikun	0:13413ea9a877	1284	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1285	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1286	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
ganlikun	0:13413ea9a877	1287	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1288	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
ganlikun	0:13413ea9a877	1289	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1290	} while(0U)
ganlikun	0:13413ea9a877	1291	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
ganlikun	0:13413ea9a877	1292	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1293	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1294	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1295	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
ganlikun	0:13413ea9a877	1296	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1297	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
ganlikun	0:13413ea9a877	1298	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1299	} while(0U)
ganlikun	0:13413ea9a877	1300	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
ganlikun	0:13413ea9a877	1301	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1302	/**
ganlikun	0:13413ea9a877	1303	* @}
ganlikun	0:13413ea9a877	1304	*/
ganlikun	0:13413ea9a877	1305
ganlikun	0:13413ea9a877	1306
ganlikun	0:13413ea9a877	1307	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	1308	* @brief Get the enable or disable status of the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	1309	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1310	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1311	* using it.
ganlikun	0:13413ea9a877	1312	* @{
ganlikun	0:13413ea9a877	1313	*/
ganlikun	0:13413ea9a877	1314	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
ganlikun	0:13413ea9a877	1315	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
ganlikun	0:13413ea9a877	1316	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1317	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
ganlikun	0:13413ea9a877	1318	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
ganlikun	0:13413ea9a877	1319	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1320	/**
ganlikun	0:13413ea9a877	1321	* @}
ganlikun	0:13413ea9a877	1322	*/
ganlikun	0:13413ea9a877	1323
ganlikun	0:13413ea9a877	1324	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	1325	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	1326	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1327	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1328	* using it.
ganlikun	0:13413ea9a877	1329	* @{
ganlikun	0:13413ea9a877	1330	*/
ganlikun	0:13413ea9a877	1331	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1332	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1333	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	1334	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1335	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	1336	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1337	} while(0U)
ganlikun	0:13413ea9a877	1338	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1339	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1340	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	1341	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1342	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	1343	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1344	} while(0U)
ganlikun	0:13413ea9a877	1345	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1346	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1347	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	1348	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1349	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	1350	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1351	} while(0U)
ganlikun	0:13413ea9a877	1352	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1353	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1354	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	1355	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1356	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	1357	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1358	} while(0U)
ganlikun	0:13413ea9a877	1359	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1360	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1361	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	1362	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1363	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	1364	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1365	} while(0U)
ganlikun	0:13413ea9a877	1366	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1367	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1368	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	1369	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1370	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	1371	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1372	} while(0U)
ganlikun	0:13413ea9a877	1373	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1374	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1375	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	1376	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1377	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	1378	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1379	} while(0U)
ganlikun	0:13413ea9a877	1380	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1381	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1382	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	1383	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1384	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	1385	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1386	} while(0U)
ganlikun	0:13413ea9a877	1387	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1388	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1389	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	1390	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1391	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	1392	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1393	} while(0U)
ganlikun	0:13413ea9a877	1394	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1395	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1396	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	1397	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1398	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	1399	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1400	} while(0U)
ganlikun	0:13413ea9a877	1401	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1402	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1403	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	1404	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1405	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	1406	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1407	} while(0U)
ganlikun	0:13413ea9a877	1408	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1409	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1410	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	1411	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1412	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	1413	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1414	} while(0U)
ganlikun	0:13413ea9a877	1415	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1416	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1417	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
ganlikun	0:13413ea9a877	1418	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1419	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
ganlikun	0:13413ea9a877	1420	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1421	} while(0U)
ganlikun	0:13413ea9a877	1422	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1423	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1424	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
ganlikun	0:13413ea9a877	1425	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1426	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
ganlikun	0:13413ea9a877	1427	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1428	} while(0U)
ganlikun	0:13413ea9a877	1429	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1430	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1431	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	1432	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1433	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	1434	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1435	} while(0U)
ganlikun	0:13413ea9a877	1436	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1437	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1438	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	1439	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1440	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	1441	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1442	} while(0U)
ganlikun	0:13413ea9a877	1443	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1444	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1445	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	1446	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1447	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	1448	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1449	} while(0U)
ganlikun	0:13413ea9a877	1450	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1451	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1452	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	1453	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1454	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	1455	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1456	} while(0U)
ganlikun	0:13413ea9a877	1457	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1458	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1459	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	1460	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1461	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	1462	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1463	} while(0U)
ganlikun	0:13413ea9a877	1464	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
ganlikun	0:13413ea9a877	1465	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
ganlikun	0:13413ea9a877	1466	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
ganlikun	0:13413ea9a877	1467	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
ganlikun	0:13413ea9a877	1468	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
ganlikun	0:13413ea9a877	1469	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
ganlikun	0:13413ea9a877	1470	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
ganlikun	0:13413ea9a877	1471	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
ganlikun	0:13413ea9a877	1472	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
ganlikun	0:13413ea9a877	1473	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
ganlikun	0:13413ea9a877	1474	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
ganlikun	0:13413ea9a877	1475	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
ganlikun	0:13413ea9a877	1476	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
ganlikun	0:13413ea9a877	1477	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
ganlikun	0:13413ea9a877	1478	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
ganlikun	0:13413ea9a877	1479	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
ganlikun	0:13413ea9a877	1480	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
ganlikun	0:13413ea9a877	1481	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
ganlikun	0:13413ea9a877	1482	/**
ganlikun	0:13413ea9a877	1483	* @}
ganlikun	0:13413ea9a877	1484	*/
ganlikun	0:13413ea9a877	1485
ganlikun	0:13413ea9a877	1486	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	1487	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	1488	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1489	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1490	* using it.
ganlikun	0:13413ea9a877	1491	* @{
ganlikun	0:13413ea9a877	1492	*/
ganlikun	0:13413ea9a877	1493	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
ganlikun	0:13413ea9a877	1494	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
ganlikun	0:13413ea9a877	1495	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
ganlikun	0:13413ea9a877	1496	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
ganlikun	0:13413ea9a877	1497	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
ganlikun	0:13413ea9a877	1498	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
ganlikun	0:13413ea9a877	1499	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
ganlikun	0:13413ea9a877	1500	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
ganlikun	0:13413ea9a877	1501	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
ganlikun	0:13413ea9a877	1502	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
ganlikun	0:13413ea9a877	1503	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
ganlikun	0:13413ea9a877	1504	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
ganlikun	0:13413ea9a877	1505	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
ganlikun	0:13413ea9a877	1506	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
ganlikun	0:13413ea9a877	1507	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
ganlikun	0:13413ea9a877	1508	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
ganlikun	0:13413ea9a877	1509	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
ganlikun	0:13413ea9a877	1510	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
ganlikun	0:13413ea9a877	1511
ganlikun	0:13413ea9a877	1512	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
ganlikun	0:13413ea9a877	1513	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
ganlikun	0:13413ea9a877	1514	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
ganlikun	0:13413ea9a877	1515	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
ganlikun	0:13413ea9a877	1516	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
ganlikun	0:13413ea9a877	1517	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
ganlikun	0:13413ea9a877	1518	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
ganlikun	0:13413ea9a877	1519	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
ganlikun	0:13413ea9a877	1520	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
ganlikun	0:13413ea9a877	1521	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
ganlikun	0:13413ea9a877	1522	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
ganlikun	0:13413ea9a877	1523	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
ganlikun	0:13413ea9a877	1524	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
ganlikun	0:13413ea9a877	1525	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
ganlikun	0:13413ea9a877	1526	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
ganlikun	0:13413ea9a877	1527	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
ganlikun	0:13413ea9a877	1528	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
ganlikun	0:13413ea9a877	1529	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
ganlikun	0:13413ea9a877	1530	/**
ganlikun	0:13413ea9a877	1531	* @}
ganlikun	0:13413ea9a877	1532	*/
ganlikun	0:13413ea9a877	1533
ganlikun	0:13413ea9a877	1534	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	1535	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	1536	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1537	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1538	* using it.
ganlikun	0:13413ea9a877	1539	* @{
ganlikun	0:13413ea9a877	1540	*/
ganlikun	0:13413ea9a877	1541	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1542	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1543	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	1544	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1545	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	1546	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1547	} while(0U)
ganlikun	0:13413ea9a877	1548	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1549	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1550	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
ganlikun	0:13413ea9a877	1551	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1552	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
ganlikun	0:13413ea9a877	1553	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1554	} while(0U)
ganlikun	0:13413ea9a877	1555	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1556	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1557	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
ganlikun	0:13413ea9a877	1558	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1559	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
ganlikun	0:13413ea9a877	1560	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1561	} while(0U)
ganlikun	0:13413ea9a877	1562	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1563	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1564	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	1565	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1566	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	1567	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1568	} while(0U)
ganlikun	0:13413ea9a877	1569	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1570	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1571	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
ganlikun	0:13413ea9a877	1572	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1573	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
ganlikun	0:13413ea9a877	1574	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1575	} while(0U)
ganlikun	0:13413ea9a877	1576	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1577	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1578	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
ganlikun	0:13413ea9a877	1579	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1580	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
ganlikun	0:13413ea9a877	1581	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1582	} while(0U)
ganlikun	0:13413ea9a877	1583	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1584	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1585	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	1586	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1587	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	1588	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1589	} while(0U)
ganlikun	0:13413ea9a877	1590	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1591	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1592	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	1593	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1594	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	1595	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1596	} while(0U)
ganlikun	0:13413ea9a877	1597	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1598	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1599	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	1600	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1601	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	1602	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1603	} while(0U)
ganlikun	0:13413ea9a877	1604	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
ganlikun	0:13413ea9a877	1605	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
ganlikun	0:13413ea9a877	1606	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
ganlikun	0:13413ea9a877	1607	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
ganlikun	0:13413ea9a877	1608	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
ganlikun	0:13413ea9a877	1609	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
ganlikun	0:13413ea9a877	1610	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
ganlikun	0:13413ea9a877	1611	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
ganlikun	0:13413ea9a877	1612	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
ganlikun	0:13413ea9a877	1613
ganlikun	0:13413ea9a877	1614	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1615	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1616	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1617	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
ganlikun	0:13413ea9a877	1618	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1619	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
ganlikun	0:13413ea9a877	1620	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1621	} while(0U)
ganlikun	0:13413ea9a877	1622
ganlikun	0:13413ea9a877	1623	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
ganlikun	0:13413ea9a877	1624	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1625
ganlikun	0:13413ea9a877	1626	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1627	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	1628	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	1629	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
ganlikun	0:13413ea9a877	1630	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	1631	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
ganlikun	0:13413ea9a877	1632	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	1633	} while(0U)
ganlikun	0:13413ea9a877	1634
ganlikun	0:13413ea9a877	1635	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
ganlikun	0:13413ea9a877	1636	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1637	/**
ganlikun	0:13413ea9a877	1638	* @}
ganlikun	0:13413ea9a877	1639	*/
ganlikun	0:13413ea9a877	1640
ganlikun	0:13413ea9a877	1641	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	1642	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	1643	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	1644	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	1645	* using it.
ganlikun	0:13413ea9a877	1646	* @{
ganlikun	0:13413ea9a877	1647	*/
ganlikun	0:13413ea9a877	1648	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
ganlikun	0:13413ea9a877	1649	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
ganlikun	0:13413ea9a877	1650	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
ganlikun	0:13413ea9a877	1651	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
ganlikun	0:13413ea9a877	1652	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
ganlikun	0:13413ea9a877	1653	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
ganlikun	0:13413ea9a877	1654	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
ganlikun	0:13413ea9a877	1655	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
ganlikun	0:13413ea9a877	1656	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
ganlikun	0:13413ea9a877	1657
ganlikun	0:13413ea9a877	1658	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
ganlikun	0:13413ea9a877	1659	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
ganlikun	0:13413ea9a877	1660	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
ganlikun	0:13413ea9a877	1661	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
ganlikun	0:13413ea9a877	1662	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
ganlikun	0:13413ea9a877	1663	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
ganlikun	0:13413ea9a877	1664	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
ganlikun	0:13413ea9a877	1665	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
ganlikun	0:13413ea9a877	1666	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
ganlikun	0:13413ea9a877	1667
ganlikun	0:13413ea9a877	1668	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1669	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
ganlikun	0:13413ea9a877	1670	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
ganlikun	0:13413ea9a877	1671	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1672
ganlikun	0:13413ea9a877	1673	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1674	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
ganlikun	0:13413ea9a877	1675	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
ganlikun	0:13413ea9a877	1676	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1677	/**
ganlikun	0:13413ea9a877	1678	* @}
ganlikun	0:13413ea9a877	1679	*/
ganlikun	0:13413ea9a877	1680
ganlikun	0:13413ea9a877	1681	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	1682	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	1683	* @{
ganlikun	0:13413ea9a877	1684	*/
ganlikun	0:13413ea9a877	1685	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	1686	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	1687	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	1688	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	1689	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
ganlikun	0:13413ea9a877	1690	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
ganlikun	0:13413ea9a877	1691	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
ganlikun	0:13413ea9a877	1692	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
ganlikun	0:13413ea9a877	1693	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
ganlikun	0:13413ea9a877	1694	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
ganlikun	0:13413ea9a877	1695	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	1696
ganlikun	0:13413ea9a877	1697	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	1698	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	1699	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	1700	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	1701	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
ganlikun	0:13413ea9a877	1702	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
ganlikun	0:13413ea9a877	1703	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
ganlikun	0:13413ea9a877	1704	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
ganlikun	0:13413ea9a877	1705	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
ganlikun	0:13413ea9a877	1706	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
ganlikun	0:13413ea9a877	1707	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	1708	/**
ganlikun	0:13413ea9a877	1709	* @}
ganlikun	0:13413ea9a877	1710	*/
ganlikun	0:13413ea9a877	1711
ganlikun	0:13413ea9a877	1712	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
ganlikun	0:13413ea9a877	1713	* @brief Force or release AHB2 peripheral reset.
ganlikun	0:13413ea9a877	1714	* @{
ganlikun	0:13413ea9a877	1715	*/
ganlikun	0:13413ea9a877	1716	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	1717	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	1718	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	1719	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
ganlikun	0:13413ea9a877	1720
ganlikun	0:13413ea9a877	1721	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	1722	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	1723	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	1724	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
ganlikun	0:13413ea9a877	1725
ganlikun	0:13413ea9a877	1726	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1727	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
ganlikun	0:13413ea9a877	1728	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
ganlikun	0:13413ea9a877	1729
ganlikun	0:13413ea9a877	1730	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
ganlikun	0:13413ea9a877	1731	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
ganlikun	0:13413ea9a877	1732	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1733	/**
ganlikun	0:13413ea9a877	1734	* @}
ganlikun	0:13413ea9a877	1735	*/
ganlikun	0:13413ea9a877	1736
ganlikun	0:13413ea9a877	1737	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
ganlikun	0:13413ea9a877	1738	* @brief Force or release AHB3 peripheral reset.
ganlikun	0:13413ea9a877	1739	* @{
ganlikun	0:13413ea9a877	1740	*/
ganlikun	0:13413ea9a877	1741	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	1742	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
ganlikun	0:13413ea9a877	1743	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
ganlikun	0:13413ea9a877	1744	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
ganlikun	0:13413ea9a877	1745
ganlikun	0:13413ea9a877	1746	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1747	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
ganlikun	0:13413ea9a877	1748	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
ganlikun	0:13413ea9a877	1749	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1750	/**
ganlikun	0:13413ea9a877	1751	* @}
ganlikun	0:13413ea9a877	1752	*/
ganlikun	0:13413ea9a877	1753
ganlikun	0:13413ea9a877	1754	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	1755	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	1756	* @{
ganlikun	0:13413ea9a877	1757	*/
ganlikun	0:13413ea9a877	1758	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	1759	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	1760	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	1761	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	1762	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	1763	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	1764	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	1765	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	1766	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	1767	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	1768	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	1769	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
ganlikun	0:13413ea9a877	1770	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
ganlikun	0:13413ea9a877	1771	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	1772	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	1773	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	1774	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	1775	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	1776
ganlikun	0:13413ea9a877	1777	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	1778	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	1779	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	1780	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	1781	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	1782	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	1783	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	1784	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	1785	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	1786	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	1787	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	1788	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	1789	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	1790	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	1791	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	1792	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	1793	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
ganlikun	0:13413ea9a877	1794	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
ganlikun	0:13413ea9a877	1795	/**
ganlikun	0:13413ea9a877	1796	* @}
ganlikun	0:13413ea9a877	1797	*/
ganlikun	0:13413ea9a877	1798
ganlikun	0:13413ea9a877	1799	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	1800	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	1801	* @{
ganlikun	0:13413ea9a877	1802	*/
ganlikun	0:13413ea9a877	1803	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	1804	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	1805	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
ganlikun	0:13413ea9a877	1806	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
ganlikun	0:13413ea9a877	1807	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	1808	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	1809	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	1810
ganlikun	0:13413ea9a877	1811	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	1812	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	1813	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	1814	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	1815	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	1816	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
ganlikun	0:13413ea9a877	1817	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
ganlikun	0:13413ea9a877	1818
ganlikun	0:13413ea9a877	1819	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1820	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
ganlikun	0:13413ea9a877	1821	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
ganlikun	0:13413ea9a877	1822	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1823
ganlikun	0:13413ea9a877	1824	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1825	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
ganlikun	0:13413ea9a877	1826	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
ganlikun	0:13413ea9a877	1827	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1828	/**
ganlikun	0:13413ea9a877	1829	* @}
ganlikun	0:13413ea9a877	1830	*/
ganlikun	0:13413ea9a877	1831
ganlikun	0:13413ea9a877	1832	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	1833	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	1834	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	1835	* power consumption.
ganlikun	0:13413ea9a877	1836	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	1837	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	1838	* @{
ganlikun	0:13413ea9a877	1839	*/
ganlikun	0:13413ea9a877	1840	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	1841	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	1842	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	1843	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	1844	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
ganlikun	0:13413ea9a877	1845	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	1846	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
ganlikun	0:13413ea9a877	1847	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
ganlikun	0:13413ea9a877	1848	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
ganlikun	0:13413ea9a877	1849	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
ganlikun	0:13413ea9a877	1850	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
ganlikun	0:13413ea9a877	1851	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
ganlikun	0:13413ea9a877	1852	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
ganlikun	0:13413ea9a877	1853	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
ganlikun	0:13413ea9a877	1854	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
ganlikun	0:13413ea9a877	1855	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
ganlikun	0:13413ea9a877	1856	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	1857	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	1858	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	1859	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
ganlikun	0:13413ea9a877	1860
ganlikun	0:13413ea9a877	1861	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	1862	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	1863	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	1864	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	1865	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
ganlikun	0:13413ea9a877	1866	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	1867	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
ganlikun	0:13413ea9a877	1868	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
ganlikun	0:13413ea9a877	1869	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
ganlikun	0:13413ea9a877	1870	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
ganlikun	0:13413ea9a877	1871	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
ganlikun	0:13413ea9a877	1872	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
ganlikun	0:13413ea9a877	1873	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
ganlikun	0:13413ea9a877	1874	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
ganlikun	0:13413ea9a877	1875	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
ganlikun	0:13413ea9a877	1876	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	1877	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	1878	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	1879	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
ganlikun	0:13413ea9a877	1880	/**
ganlikun	0:13413ea9a877	1881	* @}
ganlikun	0:13413ea9a877	1882	*/
ganlikun	0:13413ea9a877	1883
ganlikun	0:13413ea9a877	1884	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	1885	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	1886	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	1887	* power consumption.
ganlikun	0:13413ea9a877	1888	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	1889	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	1890	* @{
ganlikun	0:13413ea9a877	1891	*/
ganlikun	0:13413ea9a877	1892	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	1893	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	1894
ganlikun	0:13413ea9a877	1895	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	1896	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	1897
ganlikun	0:13413ea9a877	1898	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
ganlikun	0:13413ea9a877	1899	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
ganlikun	0:13413ea9a877	1900
ganlikun	0:13413ea9a877	1901	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1902	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
ganlikun	0:13413ea9a877	1903	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
ganlikun	0:13413ea9a877	1904
ganlikun	0:13413ea9a877	1905	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
ganlikun	0:13413ea9a877	1906	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
ganlikun	0:13413ea9a877	1907	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1908	/**
ganlikun	0:13413ea9a877	1909	* @}
ganlikun	0:13413ea9a877	1910	*/
ganlikun	0:13413ea9a877	1911
ganlikun	0:13413ea9a877	1912	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	1913	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	1914	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	1915	* power consumption.
ganlikun	0:13413ea9a877	1916	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	1917	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	1918	* @{
ganlikun	0:13413ea9a877	1919	*/
ganlikun	0:13413ea9a877	1920	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
ganlikun	0:13413ea9a877	1921	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
ganlikun	0:13413ea9a877	1922
ganlikun	0:13413ea9a877	1923	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	1924	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
ganlikun	0:13413ea9a877	1925	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
ganlikun	0:13413ea9a877	1926	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1927	/**
ganlikun	0:13413ea9a877	1928	* @}
ganlikun	0:13413ea9a877	1929	*/
ganlikun	0:13413ea9a877	1930
ganlikun	0:13413ea9a877	1931	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	1932	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	1933	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	1934	* power consumption.
ganlikun	0:13413ea9a877	1935	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	1936	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	1937	* @{
ganlikun	0:13413ea9a877	1938	*/
ganlikun	0:13413ea9a877	1939	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	1940	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	1941	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	1942	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	1943	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	1944	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	1945	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	1946	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	1947	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	1948	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	1949	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	1950	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
ganlikun	0:13413ea9a877	1951	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
ganlikun	0:13413ea9a877	1952	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	1953	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	1954	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	1955	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	1956	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	1957
ganlikun	0:13413ea9a877	1958	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	1959	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	1960	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	1961	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	1962	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	1963	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	1964	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	1965	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	1966	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	1967	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	1968	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	1969	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	1970	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	1971	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	1972	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	1973	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	1974	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
ganlikun	0:13413ea9a877	1975	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
ganlikun	0:13413ea9a877	1976	/**
ganlikun	0:13413ea9a877	1977	* @}
ganlikun	0:13413ea9a877	1978	*/
ganlikun	0:13413ea9a877	1979
ganlikun	0:13413ea9a877	1980	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	1981	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	1982	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	1983	* power consumption.
ganlikun	0:13413ea9a877	1984	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	1985	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	1986	* @{
ganlikun	0:13413ea9a877	1987	*/
ganlikun	0:13413ea9a877	1988	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	1989	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
ganlikun	0:13413ea9a877	1990	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
ganlikun	0:13413ea9a877	1991	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	1992	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
ganlikun	0:13413ea9a877	1993	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
ganlikun	0:13413ea9a877	1994	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	1995	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	1996	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	1997
ganlikun	0:13413ea9a877	1998	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	1999	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	2000	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	2001	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	2002	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
ganlikun	0:13413ea9a877	2003	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
ganlikun	0:13413ea9a877	2004	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	2005	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
ganlikun	0:13413ea9a877	2006	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
ganlikun	0:13413ea9a877	2007
ganlikun	0:13413ea9a877	2008	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	2009	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
ganlikun	0:13413ea9a877	2010
ganlikun	0:13413ea9a877	2011	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
ganlikun	0:13413ea9a877	2012	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	2013
ganlikun	0:13413ea9a877	2014	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	2015	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
ganlikun	0:13413ea9a877	2016	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
ganlikun	0:13413ea9a877	2017	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	2018	/**
ganlikun	0:13413ea9a877	2019	* @}
ganlikun	0:13413ea9a877	2020	*/
ganlikun	0:13413ea9a877	2021	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	2022	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	2023
ganlikun	0:13413ea9a877	2024	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
ganlikun	0:13413ea9a877	2025	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2026	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2027	* @brief Enables or disables the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	2028	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2029	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2030	* using it.
ganlikun	0:13413ea9a877	2031	* @{
ganlikun	0:13413ea9a877	2032	*/
ganlikun	0:13413ea9a877	2033	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2034	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2035	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
ganlikun	0:13413ea9a877	2036	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2037	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
ganlikun	0:13413ea9a877	2038	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2039	} while(0U)
ganlikun	0:13413ea9a877	2040	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2041	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2042	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	2043	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2044	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	2045	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2046	} while(0U)
ganlikun	0:13413ea9a877	2047	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2048	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2049	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	2050	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2051	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	2052	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2053	} while(0U)
ganlikun	0:13413ea9a877	2054	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2055	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2056	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	2057	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2058	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	2059	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2060	} while(0U)
ganlikun	0:13413ea9a877	2061	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2062	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2063	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	2064	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2065	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	2066	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2067	} while(0U)
ganlikun	0:13413ea9a877	2068	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2069	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2070	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
ganlikun	0:13413ea9a877	2071	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2072	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
ganlikun	0:13413ea9a877	2073	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2074	} while(0U)
ganlikun	0:13413ea9a877	2075	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2076	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2077	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	2078	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2079	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	2080	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2081	} while(0U)
ganlikun	0:13413ea9a877	2082	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2083	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2084	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	2085	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2086	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	2087	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2088	} while(0U)
ganlikun	0:13413ea9a877	2089	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2090	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2091	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
ganlikun	0:13413ea9a877	2092	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2093	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
ganlikun	0:13413ea9a877	2094	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2095	} while(0U)
ganlikun	0:13413ea9a877	2096	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2097	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2098	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
ganlikun	0:13413ea9a877	2099	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2100	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
ganlikun	0:13413ea9a877	2101	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2102	} while(0U)
ganlikun	0:13413ea9a877	2103	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
ganlikun	0:13413ea9a877	2104	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
ganlikun	0:13413ea9a877	2105	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
ganlikun	0:13413ea9a877	2106	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
ganlikun	0:13413ea9a877	2107	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
ganlikun	0:13413ea9a877	2108	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
ganlikun	0:13413ea9a877	2109	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
ganlikun	0:13413ea9a877	2110	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
ganlikun	0:13413ea9a877	2111	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
ganlikun	0:13413ea9a877	2112	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
ganlikun	0:13413ea9a877	2113	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2114	/**
ganlikun	0:13413ea9a877	2115	* @brief Enable ETHERNET clock.
ganlikun	0:13413ea9a877	2116	*/
ganlikun	0:13413ea9a877	2117	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2118	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2119	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
ganlikun	0:13413ea9a877	2120	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2121	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
ganlikun	0:13413ea9a877	2122	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2123	} while(0U)
ganlikun	0:13413ea9a877	2124	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2125	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2126	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
ganlikun	0:13413ea9a877	2127	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2128	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
ganlikun	0:13413ea9a877	2129	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2130	} while(0U)
ganlikun	0:13413ea9a877	2131	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2132	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2133	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
ganlikun	0:13413ea9a877	2134	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2135	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
ganlikun	0:13413ea9a877	2136	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2137	} while(0U)
ganlikun	0:13413ea9a877	2138	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2139	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2140	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
ganlikun	0:13413ea9a877	2141	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2142	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
ganlikun	0:13413ea9a877	2143	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2144	} while(0U)
ganlikun	0:13413ea9a877	2145	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2146	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
ganlikun	0:13413ea9a877	2147	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
ganlikun	0:13413ea9a877	2148	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
ganlikun	0:13413ea9a877	2149	} while(0U)
ganlikun	0:13413ea9a877	2150
ganlikun	0:13413ea9a877	2151	/**
ganlikun	0:13413ea9a877	2152	* @brief Disable ETHERNET clock.
ganlikun	0:13413ea9a877	2153	*/
ganlikun	0:13413ea9a877	2154	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
ganlikun	0:13413ea9a877	2155	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
ganlikun	0:13413ea9a877	2156	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
ganlikun	0:13413ea9a877	2157	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
ganlikun	0:13413ea9a877	2158	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
ganlikun	0:13413ea9a877	2159	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
ganlikun	0:13413ea9a877	2160	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
ganlikun	0:13413ea9a877	2161	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
ganlikun	0:13413ea9a877	2162	} while(0U)
ganlikun	0:13413ea9a877	2163	#endif /* STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2164	/**
ganlikun	0:13413ea9a877	2165	* @}
ganlikun	0:13413ea9a877	2166	*/
ganlikun	0:13413ea9a877	2167
ganlikun	0:13413ea9a877	2168	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	2169	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	2170	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2171	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2172	* using it.
ganlikun	0:13413ea9a877	2173	* @{
ganlikun	0:13413ea9a877	2174	*/
ganlikun	0:13413ea9a877	2175	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
ganlikun	0:13413ea9a877	2176	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
ganlikun	0:13413ea9a877	2177	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
ganlikun	0:13413ea9a877	2178	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
ganlikun	0:13413ea9a877	2179	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
ganlikun	0:13413ea9a877	2180	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
ganlikun	0:13413ea9a877	2181	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
ganlikun	0:13413ea9a877	2182	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
ganlikun	0:13413ea9a877	2183	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
ganlikun	0:13413ea9a877	2184	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
ganlikun	0:13413ea9a877	2185
ganlikun	0:13413ea9a877	2186	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
ganlikun	0:13413ea9a877	2187	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
ganlikun	0:13413ea9a877	2188	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
ganlikun	0:13413ea9a877	2189	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
ganlikun	0:13413ea9a877	2190	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
ganlikun	0:13413ea9a877	2191	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
ganlikun	0:13413ea9a877	2192	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
ganlikun	0:13413ea9a877	2193	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
ganlikun	0:13413ea9a877	2194	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
ganlikun	0:13413ea9a877	2195	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
ganlikun	0:13413ea9a877	2196	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2197	/**
ganlikun	0:13413ea9a877	2198	* @brief Enable ETHERNET clock.
ganlikun	0:13413ea9a877	2199	*/
ganlikun	0:13413ea9a877	2200	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
ganlikun	0:13413ea9a877	2201	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
ganlikun	0:13413ea9a877	2202	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
ganlikun	0:13413ea9a877	2203	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
ganlikun	0:13413ea9a877	2204	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
ganlikun	0:13413ea9a877	2205	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
ganlikun	0:13413ea9a877	2206	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
ganlikun	0:13413ea9a877	2207	/**
ganlikun	0:13413ea9a877	2208	* @brief Disable ETHERNET clock.
ganlikun	0:13413ea9a877	2209	*/
ganlikun	0:13413ea9a877	2210	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
ganlikun	0:13413ea9a877	2211	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
ganlikun	0:13413ea9a877	2212	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
ganlikun	0:13413ea9a877	2213	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
ganlikun	0:13413ea9a877	2214	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
ganlikun	0:13413ea9a877	2215	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
ganlikun	0:13413ea9a877	2216	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
ganlikun	0:13413ea9a877	2217	#endif /* STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2218	/**
ganlikun	0:13413ea9a877	2219	* @}
ganlikun	0:13413ea9a877	2220	*/
ganlikun	0:13413ea9a877	2221
ganlikun	0:13413ea9a877	2222	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2223	* @brief Enable or disable the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	2224	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2225	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2226	* using it.
ganlikun	0:13413ea9a877	2227	* @{
ganlikun	0:13413ea9a877	2228	*/
ganlikun	0:13413ea9a877	2229	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
ganlikun	0:13413ea9a877	2230	__HAL_RCC_SYSCFG_CLK_ENABLE();\
ganlikun	0:13413ea9a877	2231	}while(0U)
ganlikun	0:13413ea9a877	2232
ganlikun	0:13413ea9a877	2233	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
ganlikun	0:13413ea9a877	2234
ganlikun	0:13413ea9a877	2235	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2236	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2237	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	2238	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2239	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	2240	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2241	} while(0U)
ganlikun	0:13413ea9a877	2242	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
ganlikun	0:13413ea9a877	2243
ganlikun	0:13413ea9a877	2244	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2245	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2246	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2247	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
ganlikun	0:13413ea9a877	2248	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2249	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
ganlikun	0:13413ea9a877	2250	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2251	} while(0U)
ganlikun	0:13413ea9a877	2252	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
ganlikun	0:13413ea9a877	2253	#endif /* STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2254
ganlikun	0:13413ea9a877	2255	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2256	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2257	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2258	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
ganlikun	0:13413ea9a877	2259	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2260	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
ganlikun	0:13413ea9a877	2261	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2262	} while(0U)
ganlikun	0:13413ea9a877	2263	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2264	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2265	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
ganlikun	0:13413ea9a877	2266	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2267	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
ganlikun	0:13413ea9a877	2268	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2269	} while(0U)
ganlikun	0:13413ea9a877	2270	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
ganlikun	0:13413ea9a877	2271	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
ganlikun	0:13413ea9a877	2272	#endif /* STM32F415xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2273	/**
ganlikun	0:13413ea9a877	2274	* @}
ganlikun	0:13413ea9a877	2275	*/
ganlikun	0:13413ea9a877	2276
ganlikun	0:13413ea9a877	2277
ganlikun	0:13413ea9a877	2278	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	2279	* @brief Get the enable or disable status of the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	2280	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2281	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2282	* using it.
ganlikun	0:13413ea9a877	2283	* @{
ganlikun	0:13413ea9a877	2284	*/
ganlikun	0:13413ea9a877	2285	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
ganlikun	0:13413ea9a877	2286	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
ganlikun	0:13413ea9a877	2287
ganlikun	0:13413ea9a877	2288	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
ganlikun	0:13413ea9a877	2289	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
ganlikun	0:13413ea9a877	2290
ganlikun	0:13413ea9a877	2291	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2292	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
ganlikun	0:13413ea9a877	2293	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
ganlikun	0:13413ea9a877	2294	#endif /* STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2295
ganlikun	0:13413ea9a877	2296	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2297	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
ganlikun	0:13413ea9a877	2298	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
ganlikun	0:13413ea9a877	2299
ganlikun	0:13413ea9a877	2300	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
ganlikun	0:13413ea9a877	2301	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
ganlikun	0:13413ea9a877	2302	#endif /* STM32F415xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2303	/**
ganlikun	0:13413ea9a877	2304	* @}
ganlikun	0:13413ea9a877	2305	*/
ganlikun	0:13413ea9a877	2306
ganlikun	0:13413ea9a877	2307	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2308	* @brief Enables or disables the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	2309	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2310	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2311	* using it.
ganlikun	0:13413ea9a877	2312	* @{
ganlikun	0:13413ea9a877	2313	*/
ganlikun	0:13413ea9a877	2314	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2315	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2316	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
ganlikun	0:13413ea9a877	2317	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2318	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
ganlikun	0:13413ea9a877	2319	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2320	} while(0U)
ganlikun	0:13413ea9a877	2321	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
ganlikun	0:13413ea9a877	2322	/**
ganlikun	0:13413ea9a877	2323	* @}
ganlikun	0:13413ea9a877	2324	*/
ganlikun	0:13413ea9a877	2325
ganlikun	0:13413ea9a877	2326	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	2327	* @brief Get the enable or disable status of the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	2328	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2329	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2330	* using it.
ganlikun	0:13413ea9a877	2331	* @{
ganlikun	0:13413ea9a877	2332	*/
ganlikun	0:13413ea9a877	2333	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
ganlikun	0:13413ea9a877	2334	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
ganlikun	0:13413ea9a877	2335	/**
ganlikun	0:13413ea9a877	2336	* @}
ganlikun	0:13413ea9a877	2337	*/
ganlikun	0:13413ea9a877	2338
ganlikun	0:13413ea9a877	2339	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2340	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	2341	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2342	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2343	* using it.
ganlikun	0:13413ea9a877	2344	* @{
ganlikun	0:13413ea9a877	2345	*/
ganlikun	0:13413ea9a877	2346	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2347	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	2349	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	2351	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2352	} while(0U)
ganlikun	0:13413ea9a877	2353	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2354	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	2356	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	2358	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2359	} while(0U)
ganlikun	0:13413ea9a877	2360	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2361	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	2363	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	2365	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2366	} while(0U)
ganlikun	0:13413ea9a877	2367	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2368	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	2370	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	2372	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2373	} while(0U)
ganlikun	0:13413ea9a877	2374	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2375	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	2377	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	2379	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2380	} while(0U)
ganlikun	0:13413ea9a877	2381	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2382	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	2384	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	2386	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2387	} while(0U)
ganlikun	0:13413ea9a877	2388	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2389	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2390	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	2391	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2392	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	2393	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2394	} while(0U)
ganlikun	0:13413ea9a877	2395	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2396	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2397	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	2398	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2399	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	2400	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2401	} while(0U)
ganlikun	0:13413ea9a877	2402	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2403	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2404	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	2405	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2406	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	2407	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2408	} while(0U)
ganlikun	0:13413ea9a877	2409	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2410	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2411	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	2412	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2413	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	2414	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2415	} while(0U)
ganlikun	0:13413ea9a877	2416	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2417	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2418	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	2419	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2420	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	2421	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2422	} while(0U)
ganlikun	0:13413ea9a877	2423	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2424	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2425	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	2426	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2427	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	2428	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2429	} while(0U)
ganlikun	0:13413ea9a877	2430	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2431	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2432	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	2433	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2434	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	2435	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2436	} while(0U)
ganlikun	0:13413ea9a877	2437	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2438	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2439	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	2440	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2441	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	2442	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2443	} while(0U)
ganlikun	0:13413ea9a877	2444	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2445	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2446	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	2447	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2448	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	2449	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2450	} while(0U)
ganlikun	0:13413ea9a877	2451	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2452	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2453	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	2454	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2455	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	2456	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2457	} while(0U)
ganlikun	0:13413ea9a877	2458	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
ganlikun	0:13413ea9a877	2459	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
ganlikun	0:13413ea9a877	2460	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
ganlikun	0:13413ea9a877	2461	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
ganlikun	0:13413ea9a877	2462	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
ganlikun	0:13413ea9a877	2463	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
ganlikun	0:13413ea9a877	2464	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
ganlikun	0:13413ea9a877	2465	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
ganlikun	0:13413ea9a877	2466	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
ganlikun	0:13413ea9a877	2467	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
ganlikun	0:13413ea9a877	2468	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
ganlikun	0:13413ea9a877	2469	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
ganlikun	0:13413ea9a877	2470	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
ganlikun	0:13413ea9a877	2471	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
ganlikun	0:13413ea9a877	2472	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
ganlikun	0:13413ea9a877	2473	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
ganlikun	0:13413ea9a877	2474	/**
ganlikun	0:13413ea9a877	2475	* @}
ganlikun	0:13413ea9a877	2476	*/
ganlikun	0:13413ea9a877	2477
ganlikun	0:13413ea9a877	2478	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	2479	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	2480	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2481	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2482	* using it.
ganlikun	0:13413ea9a877	2483	* @{
ganlikun	0:13413ea9a877	2484	*/
ganlikun	0:13413ea9a877	2485	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
ganlikun	0:13413ea9a877	2486	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
ganlikun	0:13413ea9a877	2487	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
ganlikun	0:13413ea9a877	2488	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
ganlikun	0:13413ea9a877	2489	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
ganlikun	0:13413ea9a877	2490	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
ganlikun	0:13413ea9a877	2491	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
ganlikun	0:13413ea9a877	2492	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
ganlikun	0:13413ea9a877	2493	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
ganlikun	0:13413ea9a877	2494	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
ganlikun	0:13413ea9a877	2495	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
ganlikun	0:13413ea9a877	2496	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
ganlikun	0:13413ea9a877	2497	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
ganlikun	0:13413ea9a877	2498	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
ganlikun	0:13413ea9a877	2499	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
ganlikun	0:13413ea9a877	2500	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
ganlikun	0:13413ea9a877	2501
ganlikun	0:13413ea9a877	2502	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
ganlikun	0:13413ea9a877	2503	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
ganlikun	0:13413ea9a877	2504	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
ganlikun	0:13413ea9a877	2505	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
ganlikun	0:13413ea9a877	2506	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
ganlikun	0:13413ea9a877	2507	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
ganlikun	0:13413ea9a877	2508	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
ganlikun	0:13413ea9a877	2509	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
ganlikun	0:13413ea9a877	2510	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
ganlikun	0:13413ea9a877	2511	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
ganlikun	0:13413ea9a877	2512	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
ganlikun	0:13413ea9a877	2513	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
ganlikun	0:13413ea9a877	2514	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
ganlikun	0:13413ea9a877	2515	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
ganlikun	0:13413ea9a877	2516	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
ganlikun	0:13413ea9a877	2517	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
ganlikun	0:13413ea9a877	2518	/**
ganlikun	0:13413ea9a877	2519	* @}
ganlikun	0:13413ea9a877	2520	*/
ganlikun	0:13413ea9a877	2521
ganlikun	0:13413ea9a877	2522	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2523	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	2524	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2525	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2526	* using it.
ganlikun	0:13413ea9a877	2527	* @{
ganlikun	0:13413ea9a877	2528	*/
ganlikun	0:13413ea9a877	2529	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2530	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2531	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	2532	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2533	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	2534	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2535	} while(0U)
ganlikun	0:13413ea9a877	2536	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2537	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2538	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
ganlikun	0:13413ea9a877	2539	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2540	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
ganlikun	0:13413ea9a877	2541	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2542	} while(0U)
ganlikun	0:13413ea9a877	2543	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2544	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2545	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
ganlikun	0:13413ea9a877	2546	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2547	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
ganlikun	0:13413ea9a877	2548	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2549	} while(0U)
ganlikun	0:13413ea9a877	2550	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2551	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2552	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	2553	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2554	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	2555	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2556	} while(0U)
ganlikun	0:13413ea9a877	2557	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2558	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2559	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	2560	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2561	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	2562	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2563	} while(0U)
ganlikun	0:13413ea9a877	2564	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2565	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2566	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	2567	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2568	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	2569	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2570	} while(0U)
ganlikun	0:13413ea9a877	2571
ganlikun	0:13413ea9a877	2572	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
ganlikun	0:13413ea9a877	2573	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
ganlikun	0:13413ea9a877	2574	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
ganlikun	0:13413ea9a877	2575	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
ganlikun	0:13413ea9a877	2576	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
ganlikun	0:13413ea9a877	2577	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
ganlikun	0:13413ea9a877	2578	/**
ganlikun	0:13413ea9a877	2579	* @}
ganlikun	0:13413ea9a877	2580	*/
ganlikun	0:13413ea9a877	2581
ganlikun	0:13413ea9a877	2582	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	2583	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	2584	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2585	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2586	* using it.
ganlikun	0:13413ea9a877	2587	* @{
ganlikun	0:13413ea9a877	2588	*/
ganlikun	0:13413ea9a877	2589	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
ganlikun	0:13413ea9a877	2590	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
ganlikun	0:13413ea9a877	2591	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
ganlikun	0:13413ea9a877	2592	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
ganlikun	0:13413ea9a877	2593	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
ganlikun	0:13413ea9a877	2594	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
ganlikun	0:13413ea9a877	2595
ganlikun	0:13413ea9a877	2596	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
ganlikun	0:13413ea9a877	2597	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
ganlikun	0:13413ea9a877	2598	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
ganlikun	0:13413ea9a877	2599	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
ganlikun	0:13413ea9a877	2600	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
ganlikun	0:13413ea9a877	2601	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
ganlikun	0:13413ea9a877	2602	/**
ganlikun	0:13413ea9a877	2603	* @}
ganlikun	0:13413ea9a877	2604	*/
ganlikun	0:13413ea9a877	2605
ganlikun	0:13413ea9a877	2606	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	2607	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	2608	* @{
ganlikun	0:13413ea9a877	2609	*/
ganlikun	0:13413ea9a877	2610	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	2611	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	2612	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	2613	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	2614	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
ganlikun	0:13413ea9a877	2615	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
ganlikun	0:13413ea9a877	2616	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
ganlikun	0:13413ea9a877	2617	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	2618
ganlikun	0:13413ea9a877	2619	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	2620	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	2621	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	2622	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	2623	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
ganlikun	0:13413ea9a877	2624	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
ganlikun	0:13413ea9a877	2625	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
ganlikun	0:13413ea9a877	2626	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	2627	/**
ganlikun	0:13413ea9a877	2628	* @}
ganlikun	0:13413ea9a877	2629	*/
ganlikun	0:13413ea9a877	2630
ganlikun	0:13413ea9a877	2631	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
ganlikun	0:13413ea9a877	2632	* @brief Force or release AHB2 peripheral reset.
ganlikun	0:13413ea9a877	2633	* @{
ganlikun	0:13413ea9a877	2634	*/
ganlikun	0:13413ea9a877	2635	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	2636	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	2637
ganlikun	0:13413ea9a877	2638	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2639	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
ganlikun	0:13413ea9a877	2640	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
ganlikun	0:13413ea9a877	2641	#endif /* STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2642
ganlikun	0:13413ea9a877	2643	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2644	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
ganlikun	0:13413ea9a877	2645	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
ganlikun	0:13413ea9a877	2646
ganlikun	0:13413ea9a877	2647	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
ganlikun	0:13413ea9a877	2648	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
ganlikun	0:13413ea9a877	2649	#endif /* STM32F415xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2650
ganlikun	0:13413ea9a877	2651	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	2652	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	2653
ganlikun	0:13413ea9a877	2654	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	2655	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	2656	/**
ganlikun	0:13413ea9a877	2657	* @}
ganlikun	0:13413ea9a877	2658	*/
ganlikun	0:13413ea9a877	2659
ganlikun	0:13413ea9a877	2660	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
ganlikun	0:13413ea9a877	2661	* @brief Force or release AHB3 peripheral reset.
ganlikun	0:13413ea9a877	2662	* @{
ganlikun	0:13413ea9a877	2663	*/
ganlikun	0:13413ea9a877	2664	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	2665	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
ganlikun	0:13413ea9a877	2666
ganlikun	0:13413ea9a877	2667	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
ganlikun	0:13413ea9a877	2668	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
ganlikun	0:13413ea9a877	2669	/**
ganlikun	0:13413ea9a877	2670	* @}
ganlikun	0:13413ea9a877	2671	*/
ganlikun	0:13413ea9a877	2672
ganlikun	0:13413ea9a877	2673	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	2674	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	2675	* @{
ganlikun	0:13413ea9a877	2676	*/
ganlikun	0:13413ea9a877	2677	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	2678	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	2679	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	2680	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	2681	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	2682	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	2683	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	2684	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	2685	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	2686	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	2687	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	2688	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	2689	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	2690	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	2691	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	2692	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	2693
ganlikun	0:13413ea9a877	2694	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	2695	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	2696	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	2697	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	2698	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	2699	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	2700	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	2701	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	2702	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	2703	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	2704	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	2705	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	2706	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	2707	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	2708	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	2709	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	2710	/**
ganlikun	0:13413ea9a877	2711	* @}
ganlikun	0:13413ea9a877	2712	*/
ganlikun	0:13413ea9a877	2713
ganlikun	0:13413ea9a877	2714	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	2715	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	2716	* @{
ganlikun	0:13413ea9a877	2717	*/
ganlikun	0:13413ea9a877	2718	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	2719	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	2720	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	2721	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	2722
ganlikun	0:13413ea9a877	2723	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	2724	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	2725	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	2726	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	2727	/**
ganlikun	0:13413ea9a877	2728	* @}
ganlikun	0:13413ea9a877	2729	*/
ganlikun	0:13413ea9a877	2730
ganlikun	0:13413ea9a877	2731	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	2732	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	2733	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	2734	* power consumption.
ganlikun	0:13413ea9a877	2735	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	2736	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	2737	* @{
ganlikun	0:13413ea9a877	2738	*/
ganlikun	0:13413ea9a877	2739	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	2740	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	2741	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	2742	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	2743	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
ganlikun	0:13413ea9a877	2744	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	2745	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
ganlikun	0:13413ea9a877	2746	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
ganlikun	0:13413ea9a877	2747	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
ganlikun	0:13413ea9a877	2748	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
ganlikun	0:13413ea9a877	2749	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
ganlikun	0:13413ea9a877	2750	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
ganlikun	0:13413ea9a877	2751	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	2752	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	2753	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	2754	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
ganlikun	0:13413ea9a877	2755
ganlikun	0:13413ea9a877	2756	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	2757	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	2758	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	2759	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	2760	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
ganlikun	0:13413ea9a877	2761	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	2762	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
ganlikun	0:13413ea9a877	2763	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
ganlikun	0:13413ea9a877	2764	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
ganlikun	0:13413ea9a877	2765	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
ganlikun	0:13413ea9a877	2766	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
ganlikun	0:13413ea9a877	2767	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
ganlikun	0:13413ea9a877	2768	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	2769	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	2770	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	2771	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
ganlikun	0:13413ea9a877	2772	/**
ganlikun	0:13413ea9a877	2773	* @}
ganlikun	0:13413ea9a877	2774	*/
ganlikun	0:13413ea9a877	2775
ganlikun	0:13413ea9a877	2776	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	2777	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	2778	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	2779	* power consumption.
ganlikun	0:13413ea9a877	2780	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	2781	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	2782	* @{
ganlikun	0:13413ea9a877	2783	*/
ganlikun	0:13413ea9a877	2784	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	2785	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	2786
ganlikun	0:13413ea9a877	2787	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	2788	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	2789
ganlikun	0:13413ea9a877	2790	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2791	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
ganlikun	0:13413ea9a877	2792	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
ganlikun	0:13413ea9a877	2793	#endif /* STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2794
ganlikun	0:13413ea9a877	2795	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	2796	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
ganlikun	0:13413ea9a877	2797	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
ganlikun	0:13413ea9a877	2798
ganlikun	0:13413ea9a877	2799	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
ganlikun	0:13413ea9a877	2800	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
ganlikun	0:13413ea9a877	2801	#endif /* STM32F415xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2802	/**
ganlikun	0:13413ea9a877	2803	* @}
ganlikun	0:13413ea9a877	2804	*/
ganlikun	0:13413ea9a877	2805
ganlikun	0:13413ea9a877	2806	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	2807	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	2808	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	2809	* power consumption.
ganlikun	0:13413ea9a877	2810	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	2811	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	2812	* @{
ganlikun	0:13413ea9a877	2813	*/
ganlikun	0:13413ea9a877	2814	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
ganlikun	0:13413ea9a877	2815	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
ganlikun	0:13413ea9a877	2816	/**
ganlikun	0:13413ea9a877	2817	* @}
ganlikun	0:13413ea9a877	2818	*/
ganlikun	0:13413ea9a877	2819
ganlikun	0:13413ea9a877	2820	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	2821	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	2822	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	2823	* power consumption.
ganlikun	0:13413ea9a877	2824	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	2825	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	2826	* @{
ganlikun	0:13413ea9a877	2827	*/
ganlikun	0:13413ea9a877	2828	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	2829	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	2830	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	2831	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	2832	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	2833	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	2834	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	2835	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	2836	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	2837	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	2838	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	2839	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	2840	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	2841	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	2842	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	2843	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	2844
ganlikun	0:13413ea9a877	2845	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	2846	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	2847	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	2848	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	2849	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	2850	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	2851	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	2852	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	2853	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	2854	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	2855	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	2856	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	2857	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	2858	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	2859	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	2860	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	2861	/**
ganlikun	0:13413ea9a877	2862	* @}
ganlikun	0:13413ea9a877	2863	*/
ganlikun	0:13413ea9a877	2864
ganlikun	0:13413ea9a877	2865	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	2866	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	2867	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	2868	* power consumption.
ganlikun	0:13413ea9a877	2869	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	2870	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	2871	* @{
ganlikun	0:13413ea9a877	2872	*/
ganlikun	0:13413ea9a877	2873	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	2874	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
ganlikun	0:13413ea9a877	2875	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
ganlikun	0:13413ea9a877	2876	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	2877	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	2878	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	2879
ganlikun	0:13413ea9a877	2880	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	2881	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	2882	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	2883	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	2884	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
ganlikun	0:13413ea9a877	2885	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
ganlikun	0:13413ea9a877	2886	/**
ganlikun	0:13413ea9a877	2887	* @}
ganlikun	0:13413ea9a877	2888	*/
ganlikun	0:13413ea9a877	2889	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	2890	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	2891
ganlikun	0:13413ea9a877	2892	/------------------------- STM32F401xE/STM32F401xC --------------------------/
ganlikun	0:13413ea9a877	2893	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
ganlikun	0:13413ea9a877	2894	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2895	* @brief Enable or disable the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	2896	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2897	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2898	* using it.
ganlikun	0:13413ea9a877	2899	* @{
ganlikun	0:13413ea9a877	2900	*/
ganlikun	0:13413ea9a877	2901	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2902	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2903	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	2904	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2905	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	2906	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2907	} while(0U)
ganlikun	0:13413ea9a877	2908	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2909	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2910	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	2911	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2912	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	2913	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2914	} while(0U)
ganlikun	0:13413ea9a877	2915	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2916	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2917	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	2918	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2919	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	2920	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2921	} while(0U)
ganlikun	0:13413ea9a877	2922	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2923	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2924	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	2925	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2926	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	2927	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	2928	} while(0U)
ganlikun	0:13413ea9a877	2929
ganlikun	0:13413ea9a877	2930	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
ganlikun	0:13413ea9a877	2931	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
ganlikun	0:13413ea9a877	2932	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
ganlikun	0:13413ea9a877	2933	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
ganlikun	0:13413ea9a877	2934	/**
ganlikun	0:13413ea9a877	2935	* @}
ganlikun	0:13413ea9a877	2936	*/
ganlikun	0:13413ea9a877	2937
ganlikun	0:13413ea9a877	2938	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	2939	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	2940	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2941	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2942	* using it.
ganlikun	0:13413ea9a877	2943	* @{
ganlikun	0:13413ea9a877	2944	*/
ganlikun	0:13413ea9a877	2945	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
ganlikun	0:13413ea9a877	2946	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
ganlikun	0:13413ea9a877	2947	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
ganlikun	0:13413ea9a877	2948	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
ganlikun	0:13413ea9a877	2949
ganlikun	0:13413ea9a877	2950	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
ganlikun	0:13413ea9a877	2951	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
ganlikun	0:13413ea9a877	2952	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
ganlikun	0:13413ea9a877	2953	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
ganlikun	0:13413ea9a877	2954	/**
ganlikun	0:13413ea9a877	2955	* @}
ganlikun	0:13413ea9a877	2956	*/
ganlikun	0:13413ea9a877	2957
ganlikun	0:13413ea9a877	2958	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2959	* @brief Enable or disable the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	2960	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2961	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2962	* using it.
ganlikun	0:13413ea9a877	2963	* @{
ganlikun	0:13413ea9a877	2964	*/
ganlikun	0:13413ea9a877	2965	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
ganlikun	0:13413ea9a877	2966	__HAL_RCC_SYSCFG_CLK_ENABLE();\
ganlikun	0:13413ea9a877	2967	}while(0U)
ganlikun	0:13413ea9a877	2968
ganlikun	0:13413ea9a877	2969	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
ganlikun	0:13413ea9a877	2970	/**
ganlikun	0:13413ea9a877	2971	* @}
ganlikun	0:13413ea9a877	2972	*/
ganlikun	0:13413ea9a877	2973
ganlikun	0:13413ea9a877	2974	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	2975	* @brief Get the enable or disable status of the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	2976	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2977	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2978	* using it.
ganlikun	0:13413ea9a877	2979	* @{
ganlikun	0:13413ea9a877	2980	*/
ganlikun	0:13413ea9a877	2981	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
ganlikun	0:13413ea9a877	2982	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
ganlikun	0:13413ea9a877	2983	/**
ganlikun	0:13413ea9a877	2984	* @}
ganlikun	0:13413ea9a877	2985	*/
ganlikun	0:13413ea9a877	2986
ganlikun	0:13413ea9a877	2987	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	2988	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	2989	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	2990	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	2991	* using it.
ganlikun	0:13413ea9a877	2992	* @{
ganlikun	0:13413ea9a877	2993	*/
ganlikun	0:13413ea9a877	2994	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	2995	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	2996	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	2997	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	2998	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	2999	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3000	} while(0U)
ganlikun	0:13413ea9a877	3001	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3002	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3003	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	3004	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3005	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	3006	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3007	} while(0U)
ganlikun	0:13413ea9a877	3008	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3009	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3010	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	3011	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3012	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	3013	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3014	} while(0U)
ganlikun	0:13413ea9a877	3015	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3016	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3017	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	3018	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3019	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	3020	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3021	} while(0U)
ganlikun	0:13413ea9a877	3022	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3023	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3024	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	3025	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3026	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	3027	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3028	} while(0U)
ganlikun	0:13413ea9a877	3029	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
ganlikun	0:13413ea9a877	3030	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
ganlikun	0:13413ea9a877	3031	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
ganlikun	0:13413ea9a877	3032	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
ganlikun	0:13413ea9a877	3033	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
ganlikun	0:13413ea9a877	3034	/**
ganlikun	0:13413ea9a877	3035	* @}
ganlikun	0:13413ea9a877	3036	*/
ganlikun	0:13413ea9a877	3037
ganlikun	0:13413ea9a877	3038	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3039	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	3040	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3041	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3042	* using it.
ganlikun	0:13413ea9a877	3043	* @{
ganlikun	0:13413ea9a877	3044	*/
ganlikun	0:13413ea9a877	3045	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
ganlikun	0:13413ea9a877	3046	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
ganlikun	0:13413ea9a877	3047	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
ganlikun	0:13413ea9a877	3048	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
ganlikun	0:13413ea9a877	3049	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
ganlikun	0:13413ea9a877	3050
ganlikun	0:13413ea9a877	3051	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
ganlikun	0:13413ea9a877	3052	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
ganlikun	0:13413ea9a877	3053	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
ganlikun	0:13413ea9a877	3054	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
ganlikun	0:13413ea9a877	3055	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
ganlikun	0:13413ea9a877	3056	/**
ganlikun	0:13413ea9a877	3057	* @}
ganlikun	0:13413ea9a877	3058	*/
ganlikun	0:13413ea9a877	3059
ganlikun	0:13413ea9a877	3060	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3061	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	3062	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3063	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3064	* using it.
ganlikun	0:13413ea9a877	3065	* @{
ganlikun	0:13413ea9a877	3066	*/
ganlikun	0:13413ea9a877	3067	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3068	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3069	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	3070	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3071	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	3072	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3073	} while(0U)
ganlikun	0:13413ea9a877	3074	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3075	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3076	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	3077	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3078	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	3079	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3080	} while(0U)
ganlikun	0:13413ea9a877	3081	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3082	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3083	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	3084	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3085	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	3086	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3087	} while(0U)
ganlikun	0:13413ea9a877	3088
ganlikun	0:13413ea9a877	3089	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
ganlikun	0:13413ea9a877	3090	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
ganlikun	0:13413ea9a877	3091	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
ganlikun	0:13413ea9a877	3092	/**
ganlikun	0:13413ea9a877	3093	* @}
ganlikun	0:13413ea9a877	3094	*/
ganlikun	0:13413ea9a877	3095
ganlikun	0:13413ea9a877	3096	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3097	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	3098	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3099	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3100	* using it.
ganlikun	0:13413ea9a877	3101	* @{
ganlikun	0:13413ea9a877	3102	*/
ganlikun	0:13413ea9a877	3103	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
ganlikun	0:13413ea9a877	3104	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
ganlikun	0:13413ea9a877	3105	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
ganlikun	0:13413ea9a877	3106
ganlikun	0:13413ea9a877	3107	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
ganlikun	0:13413ea9a877	3108	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
ganlikun	0:13413ea9a877	3109	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
ganlikun	0:13413ea9a877	3110	/**
ganlikun	0:13413ea9a877	3111	* @}
ganlikun	0:13413ea9a877	3112	*/
ganlikun	0:13413ea9a877	3113	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	3114	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	3115	* @{
ganlikun	0:13413ea9a877	3116	*/
ganlikun	0:13413ea9a877	3117	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	3118	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	3119	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	3120	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	3121
ganlikun	0:13413ea9a877	3122	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
ganlikun	0:13413ea9a877	3123	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	3124	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	3125	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	3126	/**
ganlikun	0:13413ea9a877	3127	* @}
ganlikun	0:13413ea9a877	3128	*/
ganlikun	0:13413ea9a877	3129
ganlikun	0:13413ea9a877	3130	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
ganlikun	0:13413ea9a877	3131	* @brief Force or release AHB2 peripheral reset.
ganlikun	0:13413ea9a877	3132	* @{
ganlikun	0:13413ea9a877	3133	*/
ganlikun	0:13413ea9a877	3134	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	3135	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	3136
ganlikun	0:13413ea9a877	3137	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	3138	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	3139	/**
ganlikun	0:13413ea9a877	3140	* @}
ganlikun	0:13413ea9a877	3141	*/
ganlikun	0:13413ea9a877	3142
ganlikun	0:13413ea9a877	3143	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	3144	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	3145	* @{
ganlikun	0:13413ea9a877	3146	*/
ganlikun	0:13413ea9a877	3147	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	3148	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	3149	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	3150	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	3151	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	3152	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	3153
ganlikun	0:13413ea9a877	3154	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
ganlikun	0:13413ea9a877	3155	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	3156	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	3157	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	3158	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	3159	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	3160	/**
ganlikun	0:13413ea9a877	3161	* @}
ganlikun	0:13413ea9a877	3162	*/
ganlikun	0:13413ea9a877	3163
ganlikun	0:13413ea9a877	3164	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	3165	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	3166	* @{
ganlikun	0:13413ea9a877	3167	*/
ganlikun	0:13413ea9a877	3168	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	3169	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	3170	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	3171	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	3172
ganlikun	0:13413ea9a877	3173	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	3174	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	3175	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	3176	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	3177	/**
ganlikun	0:13413ea9a877	3178	* @}
ganlikun	0:13413ea9a877	3179	*/
ganlikun	0:13413ea9a877	3180
ganlikun	0:13413ea9a877	3181	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
ganlikun	0:13413ea9a877	3182	* @brief Force or release AHB3 peripheral reset.
ganlikun	0:13413ea9a877	3183	* @{
ganlikun	0:13413ea9a877	3184	*/
ganlikun	0:13413ea9a877	3185	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	3186	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
ganlikun	0:13413ea9a877	3187	/**
ganlikun	0:13413ea9a877	3188	* @}
ganlikun	0:13413ea9a877	3189	*/
ganlikun	0:13413ea9a877	3190
ganlikun	0:13413ea9a877	3191	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3192	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3193	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	3194	* power consumption.
ganlikun	0:13413ea9a877	3195	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	3196	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	3197	* @{
ganlikun	0:13413ea9a877	3198	*/
ganlikun	0:13413ea9a877	3199	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	3200	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	3201	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	3202	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	3203	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	3204
ganlikun	0:13413ea9a877	3205	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	3206	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	3207	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	3208	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	3209	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	3210	/**
ganlikun	0:13413ea9a877	3211	* @}
ganlikun	0:13413ea9a877	3212	*/
ganlikun	0:13413ea9a877	3213
ganlikun	0:13413ea9a877	3214	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3215	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3216	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	3217	* power consumption.
ganlikun	0:13413ea9a877	3218	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	3219	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	3220	* @{
ganlikun	0:13413ea9a877	3221	*/
ganlikun	0:13413ea9a877	3222	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	3223
ganlikun	0:13413ea9a877	3224	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	3225	/**
ganlikun	0:13413ea9a877	3226	* @}
ganlikun	0:13413ea9a877	3227	*/
ganlikun	0:13413ea9a877	3228
ganlikun	0:13413ea9a877	3229	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3230	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3231	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	3232	* power consumption.
ganlikun	0:13413ea9a877	3233	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	3234	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	3235	* @{
ganlikun	0:13413ea9a877	3236	*/
ganlikun	0:13413ea9a877	3237	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	3238	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	3239	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	3240	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	3241	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	3242
ganlikun	0:13413ea9a877	3243	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	3244	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	3245	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	3246	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	3247	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	3248	/**
ganlikun	0:13413ea9a877	3249	* @}
ganlikun	0:13413ea9a877	3250	*/
ganlikun	0:13413ea9a877	3251
ganlikun	0:13413ea9a877	3252	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3253	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3254	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	3255	* power consumption.
ganlikun	0:13413ea9a877	3256	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	3257	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	3258	* @{
ganlikun	0:13413ea9a877	3259	*/
ganlikun	0:13413ea9a877	3260	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	3261	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	3262	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	3263
ganlikun	0:13413ea9a877	3264	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	3265	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	3266	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	3267	/**
ganlikun	0:13413ea9a877	3268	* @}
ganlikun	0:13413ea9a877	3269	*/
ganlikun	0:13413ea9a877	3270	#endif /* STM32F401xC \|\| STM32F401xE*/
ganlikun	0:13413ea9a877	3271	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	3272
ganlikun	0:13413ea9a877	3273	/-------------------------------- STM32F410xx -------------------------------/
ganlikun	0:13413ea9a877	3274	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	3275	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3276	* @brief Enables or disables the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	3277	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3278	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3279	* using it.
ganlikun	0:13413ea9a877	3280	* @{
ganlikun	0:13413ea9a877	3281	*/
ganlikun	0:13413ea9a877	3282	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3283	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3284	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	3285	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3286	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	3287	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3288	} while(0U)
ganlikun	0:13413ea9a877	3289	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3290	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3291	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
ganlikun	0:13413ea9a877	3292	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3293	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
ganlikun	0:13413ea9a877	3294	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3295	} while(0U)
ganlikun	0:13413ea9a877	3296	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
ganlikun	0:13413ea9a877	3297	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
ganlikun	0:13413ea9a877	3298	/**
ganlikun	0:13413ea9a877	3299	* @}
ganlikun	0:13413ea9a877	3300	*/
ganlikun	0:13413ea9a877	3301
ganlikun	0:13413ea9a877	3302	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3303	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	3304	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3305	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3306	* using it.
ganlikun	0:13413ea9a877	3307	* @{
ganlikun	0:13413ea9a877	3308	*/
ganlikun	0:13413ea9a877	3309	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
ganlikun	0:13413ea9a877	3310	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
ganlikun	0:13413ea9a877	3311
ganlikun	0:13413ea9a877	3312	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
ganlikun	0:13413ea9a877	3313	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
ganlikun	0:13413ea9a877	3314	/**
ganlikun	0:13413ea9a877	3315	* @}
ganlikun	0:13413ea9a877	3316	*/
ganlikun	0:13413ea9a877	3317
ganlikun	0:13413ea9a877	3318	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3319	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	3320	* @{
ganlikun	0:13413ea9a877	3321	*/
ganlikun	0:13413ea9a877	3322	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3323	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3324	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	3325	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3326	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	3327	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3328	} while(0U)
ganlikun	0:13413ea9a877	3329	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3330	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3331	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
ganlikun	0:13413ea9a877	3332	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3333	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
ganlikun	0:13413ea9a877	3334	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3335	} while(0U)
ganlikun	0:13413ea9a877	3336	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3337	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3338	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
ganlikun	0:13413ea9a877	3339	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3340	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
ganlikun	0:13413ea9a877	3341	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3342	} while(0U)
ganlikun	0:13413ea9a877	3343	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3344	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3345	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
ganlikun	0:13413ea9a877	3346	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3347	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
ganlikun	0:13413ea9a877	3348	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3349	} while(0U)
ganlikun	0:13413ea9a877	3350	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3351	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3352	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	3353	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3354	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	3355	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3356	} while(0U)
ganlikun	0:13413ea9a877	3357
ganlikun	0:13413ea9a877	3358	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
ganlikun	0:13413ea9a877	3359	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
ganlikun	0:13413ea9a877	3360	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
ganlikun	0:13413ea9a877	3361	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
ganlikun	0:13413ea9a877	3362	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
ganlikun	0:13413ea9a877	3363	/**
ganlikun	0:13413ea9a877	3364	* @}
ganlikun	0:13413ea9a877	3365	*/
ganlikun	0:13413ea9a877	3366
ganlikun	0:13413ea9a877	3367	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3368	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	3369	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3370	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3371	* using it.
ganlikun	0:13413ea9a877	3372	* @{
ganlikun	0:13413ea9a877	3373	*/
ganlikun	0:13413ea9a877	3374	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
ganlikun	0:13413ea9a877	3375	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
ganlikun	0:13413ea9a877	3376	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
ganlikun	0:13413ea9a877	3377	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
ganlikun	0:13413ea9a877	3378	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
ganlikun	0:13413ea9a877	3379
ganlikun	0:13413ea9a877	3380	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
ganlikun	0:13413ea9a877	3381	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
ganlikun	0:13413ea9a877	3382	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
ganlikun	0:13413ea9a877	3383	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
ganlikun	0:13413ea9a877	3384	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
ganlikun	0:13413ea9a877	3385	/**
ganlikun	0:13413ea9a877	3386	* @}
ganlikun	0:13413ea9a877	3387	*/
ganlikun	0:13413ea9a877	3388
ganlikun	0:13413ea9a877	3389	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3390	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	3391	* @{
ganlikun	0:13413ea9a877	3392	*/
ganlikun	0:13413ea9a877	3393	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3394	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3395	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	3396	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3397	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	3398	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3399	} while(0U)
ganlikun	0:13413ea9a877	3400	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3401	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3402	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
ganlikun	0:13413ea9a877	3403	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3404	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
ganlikun	0:13413ea9a877	3405	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3406	} while(0U)
ganlikun	0:13413ea9a877	3407	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
ganlikun	0:13413ea9a877	3408	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
ganlikun	0:13413ea9a877	3409	/**
ganlikun	0:13413ea9a877	3410	* @}
ganlikun	0:13413ea9a877	3411	*/
ganlikun	0:13413ea9a877	3412
ganlikun	0:13413ea9a877	3413	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3414	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	3415	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3416	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3417	* using it.
ganlikun	0:13413ea9a877	3418	* @{
ganlikun	0:13413ea9a877	3419	*/
ganlikun	0:13413ea9a877	3420	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
ganlikun	0:13413ea9a877	3421	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
ganlikun	0:13413ea9a877	3422
ganlikun	0:13413ea9a877	3423	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
ganlikun	0:13413ea9a877	3424	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
ganlikun	0:13413ea9a877	3425	/**
ganlikun	0:13413ea9a877	3426	* @}
ganlikun	0:13413ea9a877	3427	*/
ganlikun	0:13413ea9a877	3428
ganlikun	0:13413ea9a877	3429	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	3430	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	3431	* @{
ganlikun	0:13413ea9a877	3432	*/
ganlikun	0:13413ea9a877	3433	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	3434	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
ganlikun	0:13413ea9a877	3435	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	3436	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
ganlikun	0:13413ea9a877	3437	/**
ganlikun	0:13413ea9a877	3438	* @}
ganlikun	0:13413ea9a877	3439	*/
ganlikun	0:13413ea9a877	3440
ganlikun	0:13413ea9a877	3441	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
ganlikun	0:13413ea9a877	3442	* @brief Force or release AHB2 peripheral reset.
ganlikun	0:13413ea9a877	3443	* @{
ganlikun	0:13413ea9a877	3444	*/
ganlikun	0:13413ea9a877	3445	#define __HAL_RCC_AHB2_FORCE_RESET()
ganlikun	0:13413ea9a877	3446	#define __HAL_RCC_AHB2_RELEASE_RESET()
ganlikun	0:13413ea9a877	3447	/**
ganlikun	0:13413ea9a877	3448	* @}
ganlikun	0:13413ea9a877	3449	*/
ganlikun	0:13413ea9a877	3450
ganlikun	0:13413ea9a877	3451	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
ganlikun	0:13413ea9a877	3452	* @brief Force or release AHB3 peripheral reset.
ganlikun	0:13413ea9a877	3453	* @{
ganlikun	0:13413ea9a877	3454	*/
ganlikun	0:13413ea9a877	3455	#define __HAL_RCC_AHB3_FORCE_RESET()
ganlikun	0:13413ea9a877	3456	#define __HAL_RCC_AHB3_RELEASE_RESET()
ganlikun	0:13413ea9a877	3457	/**
ganlikun	0:13413ea9a877	3458	* @}
ganlikun	0:13413ea9a877	3459	*/
ganlikun	0:13413ea9a877	3460
ganlikun	0:13413ea9a877	3461	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	3462	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	3463	* @{
ganlikun	0:13413ea9a877	3464	*/
ganlikun	0:13413ea9a877	3465	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	3466	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
ganlikun	0:13413ea9a877	3467	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
ganlikun	0:13413ea9a877	3468	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	3469
ganlikun	0:13413ea9a877	3470	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	3471	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
ganlikun	0:13413ea9a877	3472	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
ganlikun	0:13413ea9a877	3473	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	3474	/**
ganlikun	0:13413ea9a877	3475	* @}
ganlikun	0:13413ea9a877	3476	*/
ganlikun	0:13413ea9a877	3477
ganlikun	0:13413ea9a877	3478	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	3479	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	3480	* @{
ganlikun	0:13413ea9a877	3481	*/
ganlikun	0:13413ea9a877	3482	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	3483	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	3484	/**
ganlikun	0:13413ea9a877	3485	* @}
ganlikun	0:13413ea9a877	3486	*/
ganlikun	0:13413ea9a877	3487
ganlikun	0:13413ea9a877	3488	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3489	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3490	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	3491	* power consumption.
ganlikun	0:13413ea9a877	3492	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	3493	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	3494	* @{
ganlikun	0:13413ea9a877	3495	*/
ganlikun	0:13413ea9a877	3496	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	3497	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	3498	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	3499	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	3500
ganlikun	0:13413ea9a877	3501	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	3502	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	3503	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	3504	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	3505	/**
ganlikun	0:13413ea9a877	3506	* @}
ganlikun	0:13413ea9a877	3507	*/
ganlikun	0:13413ea9a877	3508
ganlikun	0:13413ea9a877	3509	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3510	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3511	* @{
ganlikun	0:13413ea9a877	3512	*/
ganlikun	0:13413ea9a877	3513	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	3514	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
ganlikun	0:13413ea9a877	3515	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
ganlikun	0:13413ea9a877	3516	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
ganlikun	0:13413ea9a877	3517	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	3518
ganlikun	0:13413ea9a877	3519	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	3520	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
ganlikun	0:13413ea9a877	3521	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
ganlikun	0:13413ea9a877	3522	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
ganlikun	0:13413ea9a877	3523	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	3524	/**
ganlikun	0:13413ea9a877	3525	* @}
ganlikun	0:13413ea9a877	3526	*/
ganlikun	0:13413ea9a877	3527
ganlikun	0:13413ea9a877	3528	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3529	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3530	* @{
ganlikun	0:13413ea9a877	3531	*/
ganlikun	0:13413ea9a877	3532	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	3533	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
ganlikun	0:13413ea9a877	3534	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	3535	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
ganlikun	0:13413ea9a877	3536	/**
ganlikun	0:13413ea9a877	3537	* @}
ganlikun	0:13413ea9a877	3538	*/
ganlikun	0:13413ea9a877	3539
ganlikun	0:13413ea9a877	3540	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	3541	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	3542
ganlikun	0:13413ea9a877	3543	/-------------------------------- STM32F411xx -------------------------------/
ganlikun	0:13413ea9a877	3544	#if defined(STM32F411xE)
ganlikun	0:13413ea9a877	3545	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3546	* @brief Enables or disables the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	3547	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3548	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3549	* using it.
ganlikun	0:13413ea9a877	3550	* @{
ganlikun	0:13413ea9a877	3551	*/
ganlikun	0:13413ea9a877	3552	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3553	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3554	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	3555	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3556	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	3557	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3558	} while(0U)
ganlikun	0:13413ea9a877	3559	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3560	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3561	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	3562	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3563	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	3564	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3565	} while(0U)
ganlikun	0:13413ea9a877	3566	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3567	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3568	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	3569	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3570	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	3571	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3572	} while(0U)
ganlikun	0:13413ea9a877	3573	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3574	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3575	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	3576	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3577	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	3578	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3579	} while(0U)
ganlikun	0:13413ea9a877	3580	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
ganlikun	0:13413ea9a877	3581	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
ganlikun	0:13413ea9a877	3582	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
ganlikun	0:13413ea9a877	3583	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
ganlikun	0:13413ea9a877	3584	/**
ganlikun	0:13413ea9a877	3585	* @}
ganlikun	0:13413ea9a877	3586	*/
ganlikun	0:13413ea9a877	3587
ganlikun	0:13413ea9a877	3588	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3589	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	3590	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3591	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3592	* using it.
ganlikun	0:13413ea9a877	3593	* @{
ganlikun	0:13413ea9a877	3594	*/
ganlikun	0:13413ea9a877	3595	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
ganlikun	0:13413ea9a877	3596	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
ganlikun	0:13413ea9a877	3597	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
ganlikun	0:13413ea9a877	3598	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
ganlikun	0:13413ea9a877	3599
ganlikun	0:13413ea9a877	3600	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
ganlikun	0:13413ea9a877	3601	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
ganlikun	0:13413ea9a877	3602	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
ganlikun	0:13413ea9a877	3603	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
ganlikun	0:13413ea9a877	3604	/**
ganlikun	0:13413ea9a877	3605	* @}
ganlikun	0:13413ea9a877	3606	*/
ganlikun	0:13413ea9a877	3607
ganlikun	0:13413ea9a877	3608	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3609	* @brief Enable or disable the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	3610	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3611	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3612	* using it.
ganlikun	0:13413ea9a877	3613	* @{
ganlikun	0:13413ea9a877	3614	*/
ganlikun	0:13413ea9a877	3615	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
ganlikun	0:13413ea9a877	3616	__HAL_RCC_SYSCFG_CLK_ENABLE();\
ganlikun	0:13413ea9a877	3617	}while(0U)
ganlikun	0:13413ea9a877	3618
ganlikun	0:13413ea9a877	3619	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
ganlikun	0:13413ea9a877	3620	/**
ganlikun	0:13413ea9a877	3621	* @}
ganlikun	0:13413ea9a877	3622	*/
ganlikun	0:13413ea9a877	3623
ganlikun	0:13413ea9a877	3624	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3625	* @brief Get the enable or disable status of the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	3626	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3627	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3628	* using it.
ganlikun	0:13413ea9a877	3629	* @{
ganlikun	0:13413ea9a877	3630	*/
ganlikun	0:13413ea9a877	3631	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
ganlikun	0:13413ea9a877	3632	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
ganlikun	0:13413ea9a877	3633	/**
ganlikun	0:13413ea9a877	3634	* @}
ganlikun	0:13413ea9a877	3635	*/
ganlikun	0:13413ea9a877	3636
ganlikun	0:13413ea9a877	3637	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3638	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	3639	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3640	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3641	* using it.
ganlikun	0:13413ea9a877	3642	* @{
ganlikun	0:13413ea9a877	3643	*/
ganlikun	0:13413ea9a877	3644	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3645	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3646	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	3647	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3648	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	3649	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3650	} while(0U)
ganlikun	0:13413ea9a877	3651	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3652	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3653	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	3654	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3655	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	3656	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3657	} while(0U)
ganlikun	0:13413ea9a877	3658	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3659	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3660	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	3661	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3662	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	3663	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3664	} while(0U)
ganlikun	0:13413ea9a877	3665	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3666	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3667	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	3668	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3669	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	3670	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3671	} while(0U)
ganlikun	0:13413ea9a877	3672	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3673	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	3675	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	3677	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3678	} while(0U)
ganlikun	0:13413ea9a877	3679	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
ganlikun	0:13413ea9a877	3680	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
ganlikun	0:13413ea9a877	3681	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
ganlikun	0:13413ea9a877	3682	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
ganlikun	0:13413ea9a877	3683	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
ganlikun	0:13413ea9a877	3684	/**
ganlikun	0:13413ea9a877	3685	* @}
ganlikun	0:13413ea9a877	3686	*/
ganlikun	0:13413ea9a877	3687
ganlikun	0:13413ea9a877	3688	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3689	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	3690	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3691	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3692	* using it.
ganlikun	0:13413ea9a877	3693	* @{
ganlikun	0:13413ea9a877	3694	*/
ganlikun	0:13413ea9a877	3695	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
ganlikun	0:13413ea9a877	3696	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
ganlikun	0:13413ea9a877	3697	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
ganlikun	0:13413ea9a877	3698	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
ganlikun	0:13413ea9a877	3699	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
ganlikun	0:13413ea9a877	3700
ganlikun	0:13413ea9a877	3701	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
ganlikun	0:13413ea9a877	3702	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
ganlikun	0:13413ea9a877	3703	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
ganlikun	0:13413ea9a877	3704	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
ganlikun	0:13413ea9a877	3705	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
ganlikun	0:13413ea9a877	3706	/**
ganlikun	0:13413ea9a877	3707	* @}
ganlikun	0:13413ea9a877	3708	*/
ganlikun	0:13413ea9a877	3709
ganlikun	0:13413ea9a877	3710	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3711	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	3712	* @{
ganlikun	0:13413ea9a877	3713	*/
ganlikun	0:13413ea9a877	3714	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3715	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	3717	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	3719	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3720	} while(0U)
ganlikun	0:13413ea9a877	3721	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3722	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3723	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	3724	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3725	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	3726	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3727	} while(0U)
ganlikun	0:13413ea9a877	3728	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3729	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3730	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	3731	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3732	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	3733	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3734	} while(0U)
ganlikun	0:13413ea9a877	3735	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3736	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3737	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	3738	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3739	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	3740	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3741	} while(0U)
ganlikun	0:13413ea9a877	3742	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
ganlikun	0:13413ea9a877	3743	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
ganlikun	0:13413ea9a877	3744	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
ganlikun	0:13413ea9a877	3745	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
ganlikun	0:13413ea9a877	3746	/**
ganlikun	0:13413ea9a877	3747	* @}
ganlikun	0:13413ea9a877	3748	*/
ganlikun	0:13413ea9a877	3749
ganlikun	0:13413ea9a877	3750	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	3751	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	3752	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3753	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3754	* using it.
ganlikun	0:13413ea9a877	3755	* @{
ganlikun	0:13413ea9a877	3756	*/
ganlikun	0:13413ea9a877	3757	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
ganlikun	0:13413ea9a877	3758	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
ganlikun	0:13413ea9a877	3759	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
ganlikun	0:13413ea9a877	3760	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
ganlikun	0:13413ea9a877	3761
ganlikun	0:13413ea9a877	3762	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
ganlikun	0:13413ea9a877	3763	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
ganlikun	0:13413ea9a877	3764	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
ganlikun	0:13413ea9a877	3765	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
ganlikun	0:13413ea9a877	3766	/**
ganlikun	0:13413ea9a877	3767	* @}
ganlikun	0:13413ea9a877	3768	*/
ganlikun	0:13413ea9a877	3769
ganlikun	0:13413ea9a877	3770	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	3771	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	3772	* @{
ganlikun	0:13413ea9a877	3773	*/
ganlikun	0:13413ea9a877	3774	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	3775	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	3776	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	3777
ganlikun	0:13413ea9a877	3778	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	3779	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	3780	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	3781	/**
ganlikun	0:13413ea9a877	3782	* @}
ganlikun	0:13413ea9a877	3783	*/
ganlikun	0:13413ea9a877	3784
ganlikun	0:13413ea9a877	3785	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
ganlikun	0:13413ea9a877	3786	* @brief Force or release AHB2 peripheral reset.
ganlikun	0:13413ea9a877	3787	* @{
ganlikun	0:13413ea9a877	3788	*/
ganlikun	0:13413ea9a877	3789	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	3790	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	3791
ganlikun	0:13413ea9a877	3792	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	3793	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	3794	/**
ganlikun	0:13413ea9a877	3795	* @}
ganlikun	0:13413ea9a877	3796	*/
ganlikun	0:13413ea9a877	3797
ganlikun	0:13413ea9a877	3798	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
ganlikun	0:13413ea9a877	3799	* @brief Force or release AHB3 peripheral reset.
ganlikun	0:13413ea9a877	3800	* @{
ganlikun	0:13413ea9a877	3801	*/
ganlikun	0:13413ea9a877	3802	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	3803	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
ganlikun	0:13413ea9a877	3804	/**
ganlikun	0:13413ea9a877	3805	* @}
ganlikun	0:13413ea9a877	3806	*/
ganlikun	0:13413ea9a877	3807
ganlikun	0:13413ea9a877	3808	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	3809	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	3810	* @{
ganlikun	0:13413ea9a877	3811	*/
ganlikun	0:13413ea9a877	3812	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	3813	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	3814	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	3815	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	3816	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	3817
ganlikun	0:13413ea9a877	3818	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	3819	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	3820	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	3821	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	3822	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	3823	/**
ganlikun	0:13413ea9a877	3824	* @}
ganlikun	0:13413ea9a877	3825	*/
ganlikun	0:13413ea9a877	3826
ganlikun	0:13413ea9a877	3827	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	3828	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	3829	* @{
ganlikun	0:13413ea9a877	3830	*/
ganlikun	0:13413ea9a877	3831	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	3832	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	3833	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	3834	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	3835
ganlikun	0:13413ea9a877	3836	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	3837	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	3838	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	3839	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	3840	/**
ganlikun	0:13413ea9a877	3841	* @}
ganlikun	0:13413ea9a877	3842	*/
ganlikun	0:13413ea9a877	3843
ganlikun	0:13413ea9a877	3844	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3845	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3846	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	3847	* power consumption.
ganlikun	0:13413ea9a877	3848	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	3849	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	3850	* @{
ganlikun	0:13413ea9a877	3851	*/
ganlikun	0:13413ea9a877	3852	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	3853	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	3854	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	3855	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	3856	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	3857
ganlikun	0:13413ea9a877	3858	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	3859	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	3860	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	3861	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	3862	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	3863	/**
ganlikun	0:13413ea9a877	3864	* @}
ganlikun	0:13413ea9a877	3865	*/
ganlikun	0:13413ea9a877	3866
ganlikun	0:13413ea9a877	3867	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3868	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3869	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	3870	* power consumption.
ganlikun	0:13413ea9a877	3871	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	3872	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	3873	* @{
ganlikun	0:13413ea9a877	3874	*/
ganlikun	0:13413ea9a877	3875	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	3876	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	3877	/**
ganlikun	0:13413ea9a877	3878	* @}
ganlikun	0:13413ea9a877	3879	*/
ganlikun	0:13413ea9a877	3880
ganlikun	0:13413ea9a877	3881	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3882	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3883	* @{
ganlikun	0:13413ea9a877	3884	*/
ganlikun	0:13413ea9a877	3885	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	3886	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	3887	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	3888	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	3889	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	3890
ganlikun	0:13413ea9a877	3891	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	3892	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	3893	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	3894	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	3895	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	3896	/**
ganlikun	0:13413ea9a877	3897	* @}
ganlikun	0:13413ea9a877	3898	*/
ganlikun	0:13413ea9a877	3899
ganlikun	0:13413ea9a877	3900	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	3901	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	3902	* @{
ganlikun	0:13413ea9a877	3903	*/
ganlikun	0:13413ea9a877	3904	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	3905	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	3906	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	3907	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	3908
ganlikun	0:13413ea9a877	3909	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	3910	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	3911	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	3912	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	3913	/**
ganlikun	0:13413ea9a877	3914	* @}
ganlikun	0:13413ea9a877	3915	*/
ganlikun	0:13413ea9a877	3916	#endif /* STM32F411xE */
ganlikun	0:13413ea9a877	3917	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	3918
ganlikun	0:13413ea9a877	3919	/---------------------------------- STM32F446xx -----------------------------/
ganlikun	0:13413ea9a877	3920	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	3921	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	3922	* @brief Enables or disables the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	3923	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	3924	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	3925	* using it.
ganlikun	0:13413ea9a877	3926	* @{
ganlikun	0:13413ea9a877	3927	*/
ganlikun	0:13413ea9a877	3928	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3929	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3930	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
ganlikun	0:13413ea9a877	3931	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3932	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
ganlikun	0:13413ea9a877	3933	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3934	} while(0U)
ganlikun	0:13413ea9a877	3935	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3936	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3937	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	3938	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3939	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
ganlikun	0:13413ea9a877	3940	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3941	} while(0U)
ganlikun	0:13413ea9a877	3942	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3943	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3944	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	3945	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3946	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	3947	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3948	} while(0U)
ganlikun	0:13413ea9a877	3949	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3950	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3951	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	3952	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3953	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	3954	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3955	} while(0U)
ganlikun	0:13413ea9a877	3956	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3957	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3958	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	3959	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3960	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	3961	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3962	} while(0U)
ganlikun	0:13413ea9a877	3963	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3964	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3965	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	3966	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3967	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	3968	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3969	} while(0U)
ganlikun	0:13413ea9a877	3970	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3971	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3972	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	3973	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3974	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	3975	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3976	} while(0U)
ganlikun	0:13413ea9a877	3977	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3978	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3979	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
ganlikun	0:13413ea9a877	3980	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3981	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
ganlikun	0:13413ea9a877	3982	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3983	} while(0U)
ganlikun	0:13413ea9a877	3984	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	3985	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	3986	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
ganlikun	0:13413ea9a877	3987	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	3988	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
ganlikun	0:13413ea9a877	3989	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	3990	} while(0U)
ganlikun	0:13413ea9a877	3991	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
ganlikun	0:13413ea9a877	3992	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
ganlikun	0:13413ea9a877	3993	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
ganlikun	0:13413ea9a877	3994	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
ganlikun	0:13413ea9a877	3995	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
ganlikun	0:13413ea9a877	3996	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
ganlikun	0:13413ea9a877	3997	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
ganlikun	0:13413ea9a877	3998	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
ganlikun	0:13413ea9a877	3999	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
ganlikun	0:13413ea9a877	4000	/**
ganlikun	0:13413ea9a877	4001	* @}
ganlikun	0:13413ea9a877	4002	*/
ganlikun	0:13413ea9a877	4003
ganlikun	0:13413ea9a877	4004	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4005	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	4006	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4007	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4008	* using it.
ganlikun	0:13413ea9a877	4009	* @{
ganlikun	0:13413ea9a877	4010	*/
ganlikun	0:13413ea9a877	4011	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
ganlikun	0:13413ea9a877	4012	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
ganlikun	0:13413ea9a877	4013	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
ganlikun	0:13413ea9a877	4014	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
ganlikun	0:13413ea9a877	4015	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
ganlikun	0:13413ea9a877	4016	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
ganlikun	0:13413ea9a877	4017	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
ganlikun	0:13413ea9a877	4018	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
ganlikun	0:13413ea9a877	4019	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
ganlikun	0:13413ea9a877	4020
ganlikun	0:13413ea9a877	4021	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
ganlikun	0:13413ea9a877	4022	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
ganlikun	0:13413ea9a877	4023	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
ganlikun	0:13413ea9a877	4024	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
ganlikun	0:13413ea9a877	4025	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
ganlikun	0:13413ea9a877	4026	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
ganlikun	0:13413ea9a877	4027	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
ganlikun	0:13413ea9a877	4028	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
ganlikun	0:13413ea9a877	4029	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
ganlikun	0:13413ea9a877	4030	/**
ganlikun	0:13413ea9a877	4031	* @}
ganlikun	0:13413ea9a877	4032	*/
ganlikun	0:13413ea9a877	4033
ganlikun	0:13413ea9a877	4034	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4035	* @brief Enable or disable the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	4036	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4037	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4038	* using it.
ganlikun	0:13413ea9a877	4039	* @{
ganlikun	0:13413ea9a877	4040	*/
ganlikun	0:13413ea9a877	4041	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4042	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4043	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
ganlikun	0:13413ea9a877	4044	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4045	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
ganlikun	0:13413ea9a877	4046	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4047	} while(0U)
ganlikun	0:13413ea9a877	4048	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
ganlikun	0:13413ea9a877	4049	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
ganlikun	0:13413ea9a877	4050	__HAL_RCC_SYSCFG_CLK_ENABLE();\
ganlikun	0:13413ea9a877	4051	}while(0U)
ganlikun	0:13413ea9a877	4052
ganlikun	0:13413ea9a877	4053	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
ganlikun	0:13413ea9a877	4054
ganlikun	0:13413ea9a877	4055	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4056	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4057	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	4058	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4059	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	4060	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4061	} while(0U)
ganlikun	0:13413ea9a877	4062	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
ganlikun	0:13413ea9a877	4063	/**
ganlikun	0:13413ea9a877	4064	* @}
ganlikun	0:13413ea9a877	4065	*/
ganlikun	0:13413ea9a877	4066
ganlikun	0:13413ea9a877	4067	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4068	* @brief Get the enable or disable status of the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	4069	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4070	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4071	* using it.
ganlikun	0:13413ea9a877	4072	* @{
ganlikun	0:13413ea9a877	4073	*/
ganlikun	0:13413ea9a877	4074	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
ganlikun	0:13413ea9a877	4075	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
ganlikun	0:13413ea9a877	4076
ganlikun	0:13413ea9a877	4077	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
ganlikun	0:13413ea9a877	4078	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
ganlikun	0:13413ea9a877	4079
ganlikun	0:13413ea9a877	4080	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
ganlikun	0:13413ea9a877	4081	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
ganlikun	0:13413ea9a877	4082	/**
ganlikun	0:13413ea9a877	4083	* @}
ganlikun	0:13413ea9a877	4084	*/
ganlikun	0:13413ea9a877	4085
ganlikun	0:13413ea9a877	4086	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4087	* @brief Enables or disables the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	4088	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4089	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4090	* using it.
ganlikun	0:13413ea9a877	4091	* @{
ganlikun	0:13413ea9a877	4092	*/
ganlikun	0:13413ea9a877	4093	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4094	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4095	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
ganlikun	0:13413ea9a877	4096	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4097	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
ganlikun	0:13413ea9a877	4098	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4099	} while(0U)
ganlikun	0:13413ea9a877	4100	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4101	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4102	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
ganlikun	0:13413ea9a877	4103	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4104	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
ganlikun	0:13413ea9a877	4105	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4106	} while(0U)
ganlikun	0:13413ea9a877	4107
ganlikun	0:13413ea9a877	4108	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
ganlikun	0:13413ea9a877	4109	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
ganlikun	0:13413ea9a877	4110	/**
ganlikun	0:13413ea9a877	4111	* @}
ganlikun	0:13413ea9a877	4112	*/
ganlikun	0:13413ea9a877	4113
ganlikun	0:13413ea9a877	4114	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4115	* @brief Get the enable or disable status of the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	4116	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4117	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4118	* using it.
ganlikun	0:13413ea9a877	4119	* @{
ganlikun	0:13413ea9a877	4120	*/
ganlikun	0:13413ea9a877	4121	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
ganlikun	0:13413ea9a877	4122	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
ganlikun	0:13413ea9a877	4123
ganlikun	0:13413ea9a877	4124	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
ganlikun	0:13413ea9a877	4125	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
ganlikun	0:13413ea9a877	4126	/**
ganlikun	0:13413ea9a877	4127	* @}
ganlikun	0:13413ea9a877	4128	*/
ganlikun	0:13413ea9a877	4129
ganlikun	0:13413ea9a877	4130	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4131	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	4132	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4133	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4134	* using it.
ganlikun	0:13413ea9a877	4135	* @{
ganlikun	0:13413ea9a877	4136	*/
ganlikun	0:13413ea9a877	4137	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4138	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4139	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	4140	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4141	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	4142	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4143	} while(0U)
ganlikun	0:13413ea9a877	4144	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4145	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4146	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	4147	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4148	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	4149	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4150	} while(0U)
ganlikun	0:13413ea9a877	4151	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4152	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4153	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	4154	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4155	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	4156	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4157	} while(0U)
ganlikun	0:13413ea9a877	4158	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4159	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4160	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	4161	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4162	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	4163	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4164	} while(0U)
ganlikun	0:13413ea9a877	4165	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4166	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4167	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	4168	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4169	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	4170	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4171	} while(0U)
ganlikun	0:13413ea9a877	4172	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4173	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4174	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
ganlikun	0:13413ea9a877	4175	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4176	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
ganlikun	0:13413ea9a877	4177	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4178	} while(0U)
ganlikun	0:13413ea9a877	4179	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4180	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4181	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	4182	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4183	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	4184	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4185	} while(0U)
ganlikun	0:13413ea9a877	4186	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4187	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4188	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	4189	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4190	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	4191	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4192	} while(0U)
ganlikun	0:13413ea9a877	4193	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4194	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4195	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	4196	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4197	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	4198	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4199	} while(0U)
ganlikun	0:13413ea9a877	4200	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4201	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4202	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
ganlikun	0:13413ea9a877	4203	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4204	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
ganlikun	0:13413ea9a877	4205	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4206	} while(0U)
ganlikun	0:13413ea9a877	4207	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4208	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4209	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	4210	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4211	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	4212	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4213	} while(0U)
ganlikun	0:13413ea9a877	4214	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4215	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4216	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	4217	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4218	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	4219	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4220	} while(0U)
ganlikun	0:13413ea9a877	4221	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4222	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4223	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
ganlikun	0:13413ea9a877	4224	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4225	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
ganlikun	0:13413ea9a877	4226	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4227	} while(0U)
ganlikun	0:13413ea9a877	4228	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4229	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4230	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	4231	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4232	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	4233	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4234	} while(0U)
ganlikun	0:13413ea9a877	4235	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4236	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4237	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	4238	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4239	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	4240	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4241	} while(0U)
ganlikun	0:13413ea9a877	4242	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4243	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4244	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	4245	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4246	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	4247	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4248	} while(0U)
ganlikun	0:13413ea9a877	4249	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4250	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4251	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	4252	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4253	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	4254	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4255	} while(0U)
ganlikun	0:13413ea9a877	4256	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4257	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4258	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	4259	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4260	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	4261	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4262	} while(0U)
ganlikun	0:13413ea9a877	4263	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4264	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	4266	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	4268	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4269	} while(0U)
ganlikun	0:13413ea9a877	4270	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
ganlikun	0:13413ea9a877	4271	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
ganlikun	0:13413ea9a877	4272	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
ganlikun	0:13413ea9a877	4273	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
ganlikun	0:13413ea9a877	4274	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
ganlikun	0:13413ea9a877	4275	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
ganlikun	0:13413ea9a877	4276	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
ganlikun	0:13413ea9a877	4277	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
ganlikun	0:13413ea9a877	4278	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
ganlikun	0:13413ea9a877	4279	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
ganlikun	0:13413ea9a877	4280	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
ganlikun	0:13413ea9a877	4281	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
ganlikun	0:13413ea9a877	4282	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
ganlikun	0:13413ea9a877	4283	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
ganlikun	0:13413ea9a877	4284	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
ganlikun	0:13413ea9a877	4285	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
ganlikun	0:13413ea9a877	4286	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
ganlikun	0:13413ea9a877	4287	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
ganlikun	0:13413ea9a877	4288	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
ganlikun	0:13413ea9a877	4289	/**
ganlikun	0:13413ea9a877	4290	* @}
ganlikun	0:13413ea9a877	4291	*/
ganlikun	0:13413ea9a877	4292
ganlikun	0:13413ea9a877	4293	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4294	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	4295	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4296	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4297	* using it.
ganlikun	0:13413ea9a877	4298	* @{
ganlikun	0:13413ea9a877	4299	*/
ganlikun	0:13413ea9a877	4300	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
ganlikun	0:13413ea9a877	4301	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
ganlikun	0:13413ea9a877	4302	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
ganlikun	0:13413ea9a877	4303	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
ganlikun	0:13413ea9a877	4304	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
ganlikun	0:13413ea9a877	4305	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
ganlikun	0:13413ea9a877	4306	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
ganlikun	0:13413ea9a877	4307	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
ganlikun	0:13413ea9a877	4308	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
ganlikun	0:13413ea9a877	4309	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
ganlikun	0:13413ea9a877	4310	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
ganlikun	0:13413ea9a877	4311	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
ganlikun	0:13413ea9a877	4312	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
ganlikun	0:13413ea9a877	4313	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
ganlikun	0:13413ea9a877	4314	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
ganlikun	0:13413ea9a877	4315	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
ganlikun	0:13413ea9a877	4316	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
ganlikun	0:13413ea9a877	4317	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
ganlikun	0:13413ea9a877	4318	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
ganlikun	0:13413ea9a877	4319
ganlikun	0:13413ea9a877	4320	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
ganlikun	0:13413ea9a877	4321	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
ganlikun	0:13413ea9a877	4322	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
ganlikun	0:13413ea9a877	4323	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
ganlikun	0:13413ea9a877	4324	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
ganlikun	0:13413ea9a877	4325	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
ganlikun	0:13413ea9a877	4326	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
ganlikun	0:13413ea9a877	4327	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
ganlikun	0:13413ea9a877	4328	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
ganlikun	0:13413ea9a877	4329	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
ganlikun	0:13413ea9a877	4330	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
ganlikun	0:13413ea9a877	4331	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
ganlikun	0:13413ea9a877	4332	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
ganlikun	0:13413ea9a877	4333	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
ganlikun	0:13413ea9a877	4334	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
ganlikun	0:13413ea9a877	4335	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
ganlikun	0:13413ea9a877	4336	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
ganlikun	0:13413ea9a877	4337	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
ganlikun	0:13413ea9a877	4338	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
ganlikun	0:13413ea9a877	4339	/**
ganlikun	0:13413ea9a877	4340	* @}
ganlikun	0:13413ea9a877	4341	*/
ganlikun	0:13413ea9a877	4342
ganlikun	0:13413ea9a877	4343	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4344	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	4345	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4346	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4347	* using it.
ganlikun	0:13413ea9a877	4348	* @{
ganlikun	0:13413ea9a877	4349	*/
ganlikun	0:13413ea9a877	4350	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4351	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4352	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	4353	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4354	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	4355	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4356	} while(0U)
ganlikun	0:13413ea9a877	4357	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4358	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4359	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
ganlikun	0:13413ea9a877	4360	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4361	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
ganlikun	0:13413ea9a877	4362	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4363	} while(0U)
ganlikun	0:13413ea9a877	4364	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4365	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4366	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
ganlikun	0:13413ea9a877	4367	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4368	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
ganlikun	0:13413ea9a877	4369	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4370	} while(0U)
ganlikun	0:13413ea9a877	4371	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4372	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4373	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
ganlikun	0:13413ea9a877	4374	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4375	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
ganlikun	0:13413ea9a877	4376	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4377	} while(0U)
ganlikun	0:13413ea9a877	4378	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4379	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4380	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
ganlikun	0:13413ea9a877	4381	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4382	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
ganlikun	0:13413ea9a877	4383	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4384	} while(0U)
ganlikun	0:13413ea9a877	4385	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4386	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4387	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	4388	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4389	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	4390	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4391	} while(0U)
ganlikun	0:13413ea9a877	4392	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4393	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4394	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	4395	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4396	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	4397	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4398	} while(0U)
ganlikun	0:13413ea9a877	4399	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4400	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4401	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	4402	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4403	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	4404	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4405	} while(0U)
ganlikun	0:13413ea9a877	4406	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
ganlikun	0:13413ea9a877	4407	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
ganlikun	0:13413ea9a877	4408	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
ganlikun	0:13413ea9a877	4409	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
ganlikun	0:13413ea9a877	4410	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
ganlikun	0:13413ea9a877	4411	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
ganlikun	0:13413ea9a877	4412	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
ganlikun	0:13413ea9a877	4413	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
ganlikun	0:13413ea9a877	4414	/**
ganlikun	0:13413ea9a877	4415	* @}
ganlikun	0:13413ea9a877	4416	*/
ganlikun	0:13413ea9a877	4417
ganlikun	0:13413ea9a877	4418	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4419	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	4420	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4421	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4422	* using it.
ganlikun	0:13413ea9a877	4423	* @{
ganlikun	0:13413ea9a877	4424	*/
ganlikun	0:13413ea9a877	4425	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
ganlikun	0:13413ea9a877	4426	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
ganlikun	0:13413ea9a877	4427	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
ganlikun	0:13413ea9a877	4428	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
ganlikun	0:13413ea9a877	4429	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
ganlikun	0:13413ea9a877	4430	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
ganlikun	0:13413ea9a877	4431	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
ganlikun	0:13413ea9a877	4432	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
ganlikun	0:13413ea9a877	4433
ganlikun	0:13413ea9a877	4434	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
ganlikun	0:13413ea9a877	4435	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
ganlikun	0:13413ea9a877	4436	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
ganlikun	0:13413ea9a877	4437	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
ganlikun	0:13413ea9a877	4438	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
ganlikun	0:13413ea9a877	4439	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
ganlikun	0:13413ea9a877	4440	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
ganlikun	0:13413ea9a877	4441	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
ganlikun	0:13413ea9a877	4442	/**
ganlikun	0:13413ea9a877	4443	* @}
ganlikun	0:13413ea9a877	4444	*/
ganlikun	0:13413ea9a877	4445
ganlikun	0:13413ea9a877	4446	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	4447	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	4448	* @{
ganlikun	0:13413ea9a877	4449	*/
ganlikun	0:13413ea9a877	4450	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	4451	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	4452	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	4453	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	4454	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
ganlikun	0:13413ea9a877	4455	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	4456
ganlikun	0:13413ea9a877	4457	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	4458	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	4459	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	4460	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	4461	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
ganlikun	0:13413ea9a877	4462	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	4463	/**
ganlikun	0:13413ea9a877	4464	* @}
ganlikun	0:13413ea9a877	4465	*/
ganlikun	0:13413ea9a877	4466
ganlikun	0:13413ea9a877	4467	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
ganlikun	0:13413ea9a877	4468	* @brief Force or release AHB2 peripheral reset.
ganlikun	0:13413ea9a877	4469	* @{
ganlikun	0:13413ea9a877	4470	*/
ganlikun	0:13413ea9a877	4471	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	4472	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	4473	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	4474	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
ganlikun	0:13413ea9a877	4475
ganlikun	0:13413ea9a877	4476	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	4477	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	4478	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	4479	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
ganlikun	0:13413ea9a877	4480	/**
ganlikun	0:13413ea9a877	4481	* @}
ganlikun	0:13413ea9a877	4482	*/
ganlikun	0:13413ea9a877	4483
ganlikun	0:13413ea9a877	4484	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
ganlikun	0:13413ea9a877	4485	* @brief Force or release AHB3 peripheral reset.
ganlikun	0:13413ea9a877	4486	* @{
ganlikun	0:13413ea9a877	4487	*/
ganlikun	0:13413ea9a877	4488	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	4489	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
ganlikun	0:13413ea9a877	4490
ganlikun	0:13413ea9a877	4491	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
ganlikun	0:13413ea9a877	4492	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
ganlikun	0:13413ea9a877	4493
ganlikun	0:13413ea9a877	4494	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
ganlikun	0:13413ea9a877	4495	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
ganlikun	0:13413ea9a877	4496	/**
ganlikun	0:13413ea9a877	4497	* @}
ganlikun	0:13413ea9a877	4498	*/
ganlikun	0:13413ea9a877	4499
ganlikun	0:13413ea9a877	4500	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	4501	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	4502	* @{
ganlikun	0:13413ea9a877	4503	*/
ganlikun	0:13413ea9a877	4504	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	4505	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	4506	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	4507	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	4508	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	4509	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
ganlikun	0:13413ea9a877	4510	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	4511	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	4512	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	4513	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
ganlikun	0:13413ea9a877	4514	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	4515	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	4516	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
ganlikun	0:13413ea9a877	4517	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	4518	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	4519	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	4520	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	4521	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	4522	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	4523
ganlikun	0:13413ea9a877	4524	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	4525	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	4526	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	4527	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	4528	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	4529	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	4530	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	4531	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	4532	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	4533	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	4534	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
ganlikun	0:13413ea9a877	4535	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	4536	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	4537	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	4538	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
ganlikun	0:13413ea9a877	4539	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	4540	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	4541	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
ganlikun	0:13413ea9a877	4542	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	4543	/**
ganlikun	0:13413ea9a877	4544	* @}
ganlikun	0:13413ea9a877	4545	*/
ganlikun	0:13413ea9a877	4546
ganlikun	0:13413ea9a877	4547	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	4548	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	4549	* @{
ganlikun	0:13413ea9a877	4550	*/
ganlikun	0:13413ea9a877	4551	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	4552	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
ganlikun	0:13413ea9a877	4553	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
ganlikun	0:13413ea9a877	4554	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	4555	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	4556	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	4557
ganlikun	0:13413ea9a877	4558	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	4559	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	4560	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	4561	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	4562	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
ganlikun	0:13413ea9a877	4563	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
ganlikun	0:13413ea9a877	4564	/**
ganlikun	0:13413ea9a877	4565	* @}
ganlikun	0:13413ea9a877	4566	*/
ganlikun	0:13413ea9a877	4567
ganlikun	0:13413ea9a877	4568	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	4569	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	4570	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	4571	* power consumption.
ganlikun	0:13413ea9a877	4572	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	4573	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	4574	* @{
ganlikun	0:13413ea9a877	4575	*/
ganlikun	0:13413ea9a877	4576	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	4577	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	4578	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	4579	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	4580	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	4581	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
ganlikun	0:13413ea9a877	4582	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
ganlikun	0:13413ea9a877	4583	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	4584	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	4585	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	4586	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
ganlikun	0:13413ea9a877	4587
ganlikun	0:13413ea9a877	4588	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	4589	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	4590	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	4591	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	4592	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	4593	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
ganlikun	0:13413ea9a877	4594	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
ganlikun	0:13413ea9a877	4595	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	4596	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	4597	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	4598	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
ganlikun	0:13413ea9a877	4599	/**
ganlikun	0:13413ea9a877	4600	* @}
ganlikun	0:13413ea9a877	4601	*/
ganlikun	0:13413ea9a877	4602
ganlikun	0:13413ea9a877	4603	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	4604	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	4605	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	4606	* power consumption.
ganlikun	0:13413ea9a877	4607	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	4608	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	4609	* @{
ganlikun	0:13413ea9a877	4610	*/
ganlikun	0:13413ea9a877	4611	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	4612	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	4613
ganlikun	0:13413ea9a877	4614	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	4615	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	4616
ganlikun	0:13413ea9a877	4617	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
ganlikun	0:13413ea9a877	4618	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
ganlikun	0:13413ea9a877	4619	/**
ganlikun	0:13413ea9a877	4620	* @}
ganlikun	0:13413ea9a877	4621	*/
ganlikun	0:13413ea9a877	4622
ganlikun	0:13413ea9a877	4623	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	4624	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	4625	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	4626	* power consumption.
ganlikun	0:13413ea9a877	4627	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	4628	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	4629	* @{
ganlikun	0:13413ea9a877	4630	*/
ganlikun	0:13413ea9a877	4631	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
ganlikun	0:13413ea9a877	4632	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
ganlikun	0:13413ea9a877	4633
ganlikun	0:13413ea9a877	4634	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
ganlikun	0:13413ea9a877	4635	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
ganlikun	0:13413ea9a877	4636	/**
ganlikun	0:13413ea9a877	4637	* @}
ganlikun	0:13413ea9a877	4638	*/
ganlikun	0:13413ea9a877	4639
ganlikun	0:13413ea9a877	4640	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	4641	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	4642	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	4643	* power consumption.
ganlikun	0:13413ea9a877	4644	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	4645	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	4646	* @{
ganlikun	0:13413ea9a877	4647	*/
ganlikun	0:13413ea9a877	4648	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	4649	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	4650	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	4651	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	4652	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	4653	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
ganlikun	0:13413ea9a877	4654	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	4655	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	4656	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	4657	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
ganlikun	0:13413ea9a877	4658	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	4659	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	4660	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
ganlikun	0:13413ea9a877	4661	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	4662	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	4663	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	4664	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	4665	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	4666	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	4667
ganlikun	0:13413ea9a877	4668	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	4669	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	4670	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	4671	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	4672	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	4673	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	4674	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	4675	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	4676	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	4677	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	4678	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
ganlikun	0:13413ea9a877	4679	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	4680	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	4681	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	4682	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
ganlikun	0:13413ea9a877	4683	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	4684	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	4685	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
ganlikun	0:13413ea9a877	4686	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	4687	/**
ganlikun	0:13413ea9a877	4688	* @}
ganlikun	0:13413ea9a877	4689	*/
ganlikun	0:13413ea9a877	4690
ganlikun	0:13413ea9a877	4691	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	4692	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	4693	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	4694	* power consumption.
ganlikun	0:13413ea9a877	4695	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	4696	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	4697	* @{
ganlikun	0:13413ea9a877	4698	*/
ganlikun	0:13413ea9a877	4699	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	4700	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
ganlikun	0:13413ea9a877	4701	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
ganlikun	0:13413ea9a877	4702	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
ganlikun	0:13413ea9a877	4703	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
ganlikun	0:13413ea9a877	4704	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	4705	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	4706	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	4707
ganlikun	0:13413ea9a877	4708	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	4709	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	4710	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	4711	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	4712	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
ganlikun	0:13413ea9a877	4713	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
ganlikun	0:13413ea9a877	4714	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
ganlikun	0:13413ea9a877	4715	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
ganlikun	0:13413ea9a877	4716	/**
ganlikun	0:13413ea9a877	4717	* @}
ganlikun	0:13413ea9a877	4718	*/
ganlikun	0:13413ea9a877	4719
ganlikun	0:13413ea9a877	4720	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	4721	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	4722
ganlikun	0:13413ea9a877	4723	/-------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx-------/
ganlikun	0:13413ea9a877	4724	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	4725	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4726	* @brief Enables or disables the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	4727	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4728	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4729	* using it.
ganlikun	0:13413ea9a877	4730	* @{
ganlikun	0:13413ea9a877	4731	*/
ganlikun	0:13413ea9a877	4732	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4733	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4734	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	4735	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4736	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
ganlikun	0:13413ea9a877	4737	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4738	} while(0U)
ganlikun	0:13413ea9a877	4739	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4740	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4741	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	4742	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4743	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
ganlikun	0:13413ea9a877	4744	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4745	} while(0U)
ganlikun	0:13413ea9a877	4746	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4747	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4748	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	4749	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4750	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
ganlikun	0:13413ea9a877	4751	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4752	} while(0U)
ganlikun	0:13413ea9a877	4753	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4754	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4755	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	4756	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4757	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
ganlikun	0:13413ea9a877	4758	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4759	} while(0U)
ganlikun	0:13413ea9a877	4760	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4761	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4762	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	4763	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4764	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
ganlikun	0:13413ea9a877	4765	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4766	} while(0U)
ganlikun	0:13413ea9a877	4767
ganlikun	0:13413ea9a877	4768	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
ganlikun	0:13413ea9a877	4769	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
ganlikun	0:13413ea9a877	4770	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
ganlikun	0:13413ea9a877	4771	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
ganlikun	0:13413ea9a877	4772	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
ganlikun	0:13413ea9a877	4773	/**
ganlikun	0:13413ea9a877	4774	* @}
ganlikun	0:13413ea9a877	4775	*/
ganlikun	0:13413ea9a877	4776
ganlikun	0:13413ea9a877	4777	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4778	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	4779	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4780	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4781	* using it.
ganlikun	0:13413ea9a877	4782	* @{
ganlikun	0:13413ea9a877	4783	*/
ganlikun	0:13413ea9a877	4784	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
ganlikun	0:13413ea9a877	4785	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
ganlikun	0:13413ea9a877	4786	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
ganlikun	0:13413ea9a877	4787	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
ganlikun	0:13413ea9a877	4788	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
ganlikun	0:13413ea9a877	4789
ganlikun	0:13413ea9a877	4790	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
ganlikun	0:13413ea9a877	4791	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
ganlikun	0:13413ea9a877	4792	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
ganlikun	0:13413ea9a877	4793	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
ganlikun	0:13413ea9a877	4794	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
ganlikun	0:13413ea9a877	4795	/**
ganlikun	0:13413ea9a877	4796	* @}
ganlikun	0:13413ea9a877	4797	*/
ganlikun	0:13413ea9a877	4798
ganlikun	0:13413ea9a877	4799	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4800	* @brief Enable or disable the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	4801	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4802	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4803	* using it.
ganlikun	0:13413ea9a877	4804	* @{
ganlikun	0:13413ea9a877	4805	*/
ganlikun	0:13413ea9a877	4806	#if defined(STM32F423xx)
ganlikun	0:13413ea9a877	4807	#define __HAL_RCC_AES_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4808	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4809	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
ganlikun	0:13413ea9a877	4810	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4811	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
ganlikun	0:13413ea9a877	4812	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4813	} while(0U)
ganlikun	0:13413ea9a877	4814
ganlikun	0:13413ea9a877	4815	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
ganlikun	0:13413ea9a877	4816	#endif /* STM32F423xx */
ganlikun	0:13413ea9a877	4817
ganlikun	0:13413ea9a877	4818	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4819	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4820	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	4821	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4822	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
ganlikun	0:13413ea9a877	4823	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4824	} while(0U)
ganlikun	0:13413ea9a877	4825	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
ganlikun	0:13413ea9a877	4826
ganlikun	0:13413ea9a877	4827	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
ganlikun	0:13413ea9a877	4828	__HAL_RCC_SYSCFG_CLK_ENABLE();\
ganlikun	0:13413ea9a877	4829	}while(0U)
ganlikun	0:13413ea9a877	4830
ganlikun	0:13413ea9a877	4831	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
ganlikun	0:13413ea9a877	4832	/**
ganlikun	0:13413ea9a877	4833	* @}
ganlikun	0:13413ea9a877	4834	*/
ganlikun	0:13413ea9a877	4835
ganlikun	0:13413ea9a877	4836	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4837	* @brief Get the enable or disable status of the AHB2 peripheral clock.
ganlikun	0:13413ea9a877	4838	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4839	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4840	* using it.
ganlikun	0:13413ea9a877	4841	* @{
ganlikun	0:13413ea9a877	4842	*/
ganlikun	0:13413ea9a877	4843	#if defined(STM32F423xx)
ganlikun	0:13413ea9a877	4844	#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
ganlikun	0:13413ea9a877	4845	#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
ganlikun	0:13413ea9a877	4846	#endif /* STM32F423xx */
ganlikun	0:13413ea9a877	4847
ganlikun	0:13413ea9a877	4848	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
ganlikun	0:13413ea9a877	4849	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
ganlikun	0:13413ea9a877	4850
ganlikun	0:13413ea9a877	4851	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
ganlikun	0:13413ea9a877	4852	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
ganlikun	0:13413ea9a877	4853	/**
ganlikun	0:13413ea9a877	4854	* @}
ganlikun	0:13413ea9a877	4855	*/
ganlikun	0:13413ea9a877	4856
ganlikun	0:13413ea9a877	4857	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4858	* @brief Enables or disables the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	4859	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4860	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4861	* using it.
ganlikun	0:13413ea9a877	4862	* @{
ganlikun	0:13413ea9a877	4863	*/
ganlikun	0:13413ea9a877	4864	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	4865	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4866	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4867	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
ganlikun	0:13413ea9a877	4868	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4869	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
ganlikun	0:13413ea9a877	4870	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4871	} while(0U)
ganlikun	0:13413ea9a877	4872	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4873	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4874	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
ganlikun	0:13413ea9a877	4875	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4876	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
ganlikun	0:13413ea9a877	4877	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4878	} while(0U)
ganlikun	0:13413ea9a877	4879
ganlikun	0:13413ea9a877	4880	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
ganlikun	0:13413ea9a877	4881	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
ganlikun	0:13413ea9a877	4882	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	4883	/**
ganlikun	0:13413ea9a877	4884	* @}
ganlikun	0:13413ea9a877	4885	*/
ganlikun	0:13413ea9a877	4886
ganlikun	0:13413ea9a877	4887	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	4888	* @brief Get the enable or disable status of the AHB3 peripheral clock.
ganlikun	0:13413ea9a877	4889	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4890	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4891	* using it.
ganlikun	0:13413ea9a877	4892	* @{
ganlikun	0:13413ea9a877	4893	*/
ganlikun	0:13413ea9a877	4894	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	4895	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
ganlikun	0:13413ea9a877	4896	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
ganlikun	0:13413ea9a877	4897
ganlikun	0:13413ea9a877	4898	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
ganlikun	0:13413ea9a877	4899	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
ganlikun	0:13413ea9a877	4900	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	4901
ganlikun	0:13413ea9a877	4902	/**
ganlikun	0:13413ea9a877	4903	* @}
ganlikun	0:13413ea9a877	4904	*/
ganlikun	0:13413ea9a877	4905
ganlikun	0:13413ea9a877	4906	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	4907	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	4908	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	4909	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	4910	* using it.
ganlikun	0:13413ea9a877	4911	* @{
ganlikun	0:13413ea9a877	4912	*/
ganlikun	0:13413ea9a877	4913	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4914	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4915	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	4916	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4917	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
ganlikun	0:13413ea9a877	4918	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4919	} while(0U)
ganlikun	0:13413ea9a877	4920	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4921	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4922	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	4923	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4924	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
ganlikun	0:13413ea9a877	4925	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4926	} while(0U)
ganlikun	0:13413ea9a877	4927	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4928	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4929	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	4930	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4931	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
ganlikun	0:13413ea9a877	4932	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4933	} while(0U)
ganlikun	0:13413ea9a877	4934	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4935	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4936	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	4937	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4938	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
ganlikun	0:13413ea9a877	4939	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4940	} while(0U)
ganlikun	0:13413ea9a877	4941	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4942	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4943	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	4944	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4945	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
ganlikun	0:13413ea9a877	4946	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4947	} while(0U)
ganlikun	0:13413ea9a877	4948	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	4949	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4950	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4951	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
ganlikun	0:13413ea9a877	4952	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4953	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
ganlikun	0:13413ea9a877	4954	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4955	} while(0U)
ganlikun	0:13413ea9a877	4956	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	4957	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4958	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4959	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
ganlikun	0:13413ea9a877	4960	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4961	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
ganlikun	0:13413ea9a877	4962	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4963	} while(0U)
ganlikun	0:13413ea9a877	4964	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	4965	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4966	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4967	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	4968	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4969	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
ganlikun	0:13413ea9a877	4970	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4971	} while(0U)
ganlikun	0:13413ea9a877	4972	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	4973
ganlikun	0:13413ea9a877	4974	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	4975	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4976	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4977	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	4978	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4979	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
ganlikun	0:13413ea9a877	4980	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4981	} while(0U)
ganlikun	0:13413ea9a877	4982	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4983	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4984	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	4985	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4986	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
ganlikun	0:13413ea9a877	4987	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4988	} while(0U)
ganlikun	0:13413ea9a877	4989	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	4990
ganlikun	0:13413ea9a877	4991	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4992	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	4993	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
ganlikun	0:13413ea9a877	4994	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	4995	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
ganlikun	0:13413ea9a877	4996	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	4997	} while(0U)
ganlikun	0:13413ea9a877	4998	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	4999	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5000	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	5001	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5002	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
ganlikun	0:13413ea9a877	5003	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5004	} while(0U)
ganlikun	0:13413ea9a877	5005	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5006	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5007	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	5008	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5009	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
ganlikun	0:13413ea9a877	5010	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5011	} while(0U)
ganlikun	0:13413ea9a877	5012	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5013	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5014	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5015	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
ganlikun	0:13413ea9a877	5016	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5017	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
ganlikun	0:13413ea9a877	5018	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5019	} while(0U)
ganlikun	0:13413ea9a877	5020	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5021	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5022	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5023	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	5024	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5025	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
ganlikun	0:13413ea9a877	5026	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5027	} while(0U)
ganlikun	0:13413ea9a877	5028	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5029	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5030	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	5031	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5032	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
ganlikun	0:13413ea9a877	5033	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5034	} while(0U)
ganlikun	0:13413ea9a877	5035	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5036	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5037	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	5038	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5039	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
ganlikun	0:13413ea9a877	5040	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5041	} while(0U)
ganlikun	0:13413ea9a877	5042	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5043	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5044	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	5045	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5046	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
ganlikun	0:13413ea9a877	5047	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5048	} while(0U)
ganlikun	0:13413ea9a877	5049	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5050	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5051	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	5052	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5053	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
ganlikun	0:13413ea9a877	5054	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5055	} while(0U)
ganlikun	0:13413ea9a877	5056	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5057	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5058	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5059	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	5060	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5061	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
ganlikun	0:13413ea9a877	5062	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5063	} while(0U)
ganlikun	0:13413ea9a877	5064	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5065	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5066	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
ganlikun	0:13413ea9a877	5067	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5068	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
ganlikun	0:13413ea9a877	5069	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5070	} while(0U)
ganlikun	0:13413ea9a877	5071	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5072	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5073	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
ganlikun	0:13413ea9a877	5074	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5075	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
ganlikun	0:13413ea9a877	5076	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5077	} while(0U)
ganlikun	0:13413ea9a877	5078	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5079
ganlikun	0:13413ea9a877	5080	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
ganlikun	0:13413ea9a877	5081	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
ganlikun	0:13413ea9a877	5082	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
ganlikun	0:13413ea9a877	5083	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
ganlikun	0:13413ea9a877	5084	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
ganlikun	0:13413ea9a877	5085	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
ganlikun	0:13413ea9a877	5086	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
ganlikun	0:13413ea9a877	5087	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
ganlikun	0:13413ea9a877	5088	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5089	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
ganlikun	0:13413ea9a877	5090	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5091	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
ganlikun	0:13413ea9a877	5092	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
ganlikun	0:13413ea9a877	5093	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5094	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
ganlikun	0:13413ea9a877	5095	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5096	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5097	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
ganlikun	0:13413ea9a877	5098	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
ganlikun	0:13413ea9a877	5099	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5100	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
ganlikun	0:13413ea9a877	5101	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
ganlikun	0:13413ea9a877	5102	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
ganlikun	0:13413ea9a877	5103	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
ganlikun	0:13413ea9a877	5104	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5105	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
ganlikun	0:13413ea9a877	5106	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
ganlikun	0:13413ea9a877	5107	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
ganlikun	0:13413ea9a877	5108	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
ganlikun	0:13413ea9a877	5109	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5110
ganlikun	0:13413ea9a877	5111	/**
ganlikun	0:13413ea9a877	5112	* @}
ganlikun	0:13413ea9a877	5113	*/
ganlikun	0:13413ea9a877	5114
ganlikun	0:13413ea9a877	5115	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	5116	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	5117	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	5118	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	5119	* using it.
ganlikun	0:13413ea9a877	5120	* @{
ganlikun	0:13413ea9a877	5121	*/
ganlikun	0:13413ea9a877	5122	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
ganlikun	0:13413ea9a877	5123	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
ganlikun	0:13413ea9a877	5124	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
ganlikun	0:13413ea9a877	5125	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
ganlikun	0:13413ea9a877	5126	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
ganlikun	0:13413ea9a877	5127	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
ganlikun	0:13413ea9a877	5128	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
ganlikun	0:13413ea9a877	5129	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
ganlikun	0:13413ea9a877	5130	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5131	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
ganlikun	0:13413ea9a877	5132	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5133	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
ganlikun	0:13413ea9a877	5134	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
ganlikun	0:13413ea9a877	5135	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5136	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
ganlikun	0:13413ea9a877	5137	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
ganlikun	0:13413ea9a877	5138	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5139	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
ganlikun	0:13413ea9a877	5140	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
ganlikun	0:13413ea9a877	5141	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5142	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
ganlikun	0:13413ea9a877	5143	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
ganlikun	0:13413ea9a877	5144	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
ganlikun	0:13413ea9a877	5145	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
ganlikun	0:13413ea9a877	5146	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5147	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
ganlikun	0:13413ea9a877	5148	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
ganlikun	0:13413ea9a877	5149	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
ganlikun	0:13413ea9a877	5150	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
ganlikun	0:13413ea9a877	5151	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5152
ganlikun	0:13413ea9a877	5153	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
ganlikun	0:13413ea9a877	5154	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
ganlikun	0:13413ea9a877	5155	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
ganlikun	0:13413ea9a877	5156	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
ganlikun	0:13413ea9a877	5157	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
ganlikun	0:13413ea9a877	5158	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
ganlikun	0:13413ea9a877	5159	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
ganlikun	0:13413ea9a877	5160	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
ganlikun	0:13413ea9a877	5161	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5162	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
ganlikun	0:13413ea9a877	5163	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5164	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
ganlikun	0:13413ea9a877	5165	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
ganlikun	0:13413ea9a877	5166	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5167	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
ganlikun	0:13413ea9a877	5168	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
ganlikun	0:13413ea9a877	5169	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5170	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
ganlikun	0:13413ea9a877	5171	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
ganlikun	0:13413ea9a877	5172	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5173	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
ganlikun	0:13413ea9a877	5174	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
ganlikun	0:13413ea9a877	5175	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
ganlikun	0:13413ea9a877	5176	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
ganlikun	0:13413ea9a877	5177	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5178	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
ganlikun	0:13413ea9a877	5179	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
ganlikun	0:13413ea9a877	5180	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
ganlikun	0:13413ea9a877	5181	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
ganlikun	0:13413ea9a877	5182	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5183	/**
ganlikun	0:13413ea9a877	5184	* @}
ganlikun	0:13413ea9a877	5185	*/
ganlikun	0:13413ea9a877	5186	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	5187	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	5188	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	5189	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	5190	* using it.
ganlikun	0:13413ea9a877	5191	* @{
ganlikun	0:13413ea9a877	5192	*/
ganlikun	0:13413ea9a877	5193	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5194	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5195	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	5196	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5197	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
ganlikun	0:13413ea9a877	5198	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5199	} while(0U)
ganlikun	0:13413ea9a877	5200	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5201	#define __HAL_RCC_UART9_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5202	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5203	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
ganlikun	0:13413ea9a877	5204	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5205	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
ganlikun	0:13413ea9a877	5206	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5207	} while(0U)
ganlikun	0:13413ea9a877	5208	#define __HAL_RCC_UART10_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5209	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5210	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
ganlikun	0:13413ea9a877	5211	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5212	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
ganlikun	0:13413ea9a877	5213	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5214	} while(0U)
ganlikun	0:13413ea9a877	5215	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5216	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5217	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5218	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	5219	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5220	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
ganlikun	0:13413ea9a877	5221	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5222	} while(0U)
ganlikun	0:13413ea9a877	5223	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5224	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5225	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	5226	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5227	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
ganlikun	0:13413ea9a877	5228	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5229	} while(0U)
ganlikun	0:13413ea9a877	5230	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5231	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5232	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
ganlikun	0:13413ea9a877	5233	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5234	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
ganlikun	0:13413ea9a877	5235	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5236	} while(0U)
ganlikun	0:13413ea9a877	5237	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5238	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5239	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	5240	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5241	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
ganlikun	0:13413ea9a877	5242	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5243	} while(0U)
ganlikun	0:13413ea9a877	5244	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5245	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5246	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	5247	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5248	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
ganlikun	0:13413ea9a877	5249	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5250	} while(0U)
ganlikun	0:13413ea9a877	5251	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5252	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5253	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5254	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
ganlikun	0:13413ea9a877	5255	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5256	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
ganlikun	0:13413ea9a877	5257	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5258	} while(0U)
ganlikun	0:13413ea9a877	5259	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5260	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5261	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5262	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
ganlikun	0:13413ea9a877	5263	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5264	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
ganlikun	0:13413ea9a877	5265	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5266	} while(0U)
ganlikun	0:13413ea9a877	5267	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5268	#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	5269	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	5270	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
ganlikun	0:13413ea9a877	5271	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	5272	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
ganlikun	0:13413ea9a877	5273	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	5274	} while(0U)
ganlikun	0:13413ea9a877	5275	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5276
ganlikun	0:13413ea9a877	5277	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
ganlikun	0:13413ea9a877	5278	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5279	#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
ganlikun	0:13413ea9a877	5280	#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
ganlikun	0:13413ea9a877	5281	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5282	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
ganlikun	0:13413ea9a877	5283	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
ganlikun	0:13413ea9a877	5284	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
ganlikun	0:13413ea9a877	5285	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
ganlikun	0:13413ea9a877	5286	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
ganlikun	0:13413ea9a877	5287	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5288	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
ganlikun	0:13413ea9a877	5289	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5290	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
ganlikun	0:13413ea9a877	5291	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5292	#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
ganlikun	0:13413ea9a877	5293	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5294	/**
ganlikun	0:13413ea9a877	5295	* @}
ganlikun	0:13413ea9a877	5296	*/
ganlikun	0:13413ea9a877	5297
ganlikun	0:13413ea9a877	5298	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	5299	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	5300	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	5301	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	5302	* using it.
ganlikun	0:13413ea9a877	5303	* @{
ganlikun	0:13413ea9a877	5304	*/
ganlikun	0:13413ea9a877	5305	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
ganlikun	0:13413ea9a877	5306	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5307	#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
ganlikun	0:13413ea9a877	5308	#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
ganlikun	0:13413ea9a877	5309	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5310	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
ganlikun	0:13413ea9a877	5311	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
ganlikun	0:13413ea9a877	5312	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
ganlikun	0:13413ea9a877	5313	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
ganlikun	0:13413ea9a877	5314	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
ganlikun	0:13413ea9a877	5315	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5316	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
ganlikun	0:13413ea9a877	5317	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5318	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
ganlikun	0:13413ea9a877	5319	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5320	#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
ganlikun	0:13413ea9a877	5321	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5322
ganlikun	0:13413ea9a877	5323	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
ganlikun	0:13413ea9a877	5324	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5325	#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
ganlikun	0:13413ea9a877	5326	#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
ganlikun	0:13413ea9a877	5327	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5328	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
ganlikun	0:13413ea9a877	5329	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
ganlikun	0:13413ea9a877	5330	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
ganlikun	0:13413ea9a877	5331	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
ganlikun	0:13413ea9a877	5332	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
ganlikun	0:13413ea9a877	5333	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5334	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
ganlikun	0:13413ea9a877	5335	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5336	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
ganlikun	0:13413ea9a877	5337	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5338	#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
ganlikun	0:13413ea9a877	5339	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5340	/**
ganlikun	0:13413ea9a877	5341	* @}
ganlikun	0:13413ea9a877	5342	*/
ganlikun	0:13413ea9a877	5343
ganlikun	0:13413ea9a877	5344	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	5345	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	5346	* @{
ganlikun	0:13413ea9a877	5347	*/
ganlikun	0:13413ea9a877	5348	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	5349	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	5350	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	5351	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	5352	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	5353
ganlikun	0:13413ea9a877	5354	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
ganlikun	0:13413ea9a877	5355	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
ganlikun	0:13413ea9a877	5356	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
ganlikun	0:13413ea9a877	5357	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
ganlikun	0:13413ea9a877	5358	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
ganlikun	0:13413ea9a877	5359	/**
ganlikun	0:13413ea9a877	5360	* @}
ganlikun	0:13413ea9a877	5361	*/
ganlikun	0:13413ea9a877	5362
ganlikun	0:13413ea9a877	5363	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
ganlikun	0:13413ea9a877	5364	* @brief Force or release AHB2 peripheral reset.
ganlikun	0:13413ea9a877	5365	* @{
ganlikun	0:13413ea9a877	5366	*/
ganlikun	0:13413ea9a877	5367	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	5368	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	5369
ganlikun	0:13413ea9a877	5370	#if defined(STM32F423xx)
ganlikun	0:13413ea9a877	5371	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_AESRST))
ganlikun	0:13413ea9a877	5372	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
ganlikun	0:13413ea9a877	5373	#endif /* STM32F423xx */
ganlikun	0:13413ea9a877	5374
ganlikun	0:13413ea9a877	5375	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	5376	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
ganlikun	0:13413ea9a877	5377
ganlikun	0:13413ea9a877	5378	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	5379	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
ganlikun	0:13413ea9a877	5380	/**
ganlikun	0:13413ea9a877	5381	* @}
ganlikun	0:13413ea9a877	5382	*/
ganlikun	0:13413ea9a877	5383
ganlikun	0:13413ea9a877	5384	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
ganlikun	0:13413ea9a877	5385	* @brief Force or release AHB3 peripheral reset.
ganlikun	0:13413ea9a877	5386	* @{
ganlikun	0:13413ea9a877	5387	*/
ganlikun	0:13413ea9a877	5388	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5389	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	5390	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
ganlikun	0:13413ea9a877	5391
ganlikun	0:13413ea9a877	5392	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
ganlikun	0:13413ea9a877	5393	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
ganlikun	0:13413ea9a877	5394
ganlikun	0:13413ea9a877	5395	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
ganlikun	0:13413ea9a877	5396	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
ganlikun	0:13413ea9a877	5397	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5398	#if defined(STM32F412Cx)
ganlikun	0:13413ea9a877	5399	#define __HAL_RCC_AHB3_FORCE_RESET()
ganlikun	0:13413ea9a877	5400	#define __HAL_RCC_AHB3_RELEASE_RESET()
ganlikun	0:13413ea9a877	5401
ganlikun	0:13413ea9a877	5402	#define __HAL_RCC_FSMC_FORCE_RESET()
ganlikun	0:13413ea9a877	5403	#define __HAL_RCC_QSPI_FORCE_RESET()
ganlikun	0:13413ea9a877	5404
ganlikun	0:13413ea9a877	5405	#define __HAL_RCC_FSMC_RELEASE_RESET()
ganlikun	0:13413ea9a877	5406	#define __HAL_RCC_QSPI_RELEASE_RESET()
ganlikun	0:13413ea9a877	5407	#endif /* STM32F412Cx */
ganlikun	0:13413ea9a877	5408	/**
ganlikun	0:13413ea9a877	5409	* @}
ganlikun	0:13413ea9a877	5410	*/
ganlikun	0:13413ea9a877	5411
ganlikun	0:13413ea9a877	5412	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	5413	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	5414	* @{
ganlikun	0:13413ea9a877	5415	*/
ganlikun	0:13413ea9a877	5416	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	5417	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	5418	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	5419	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	5420	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	5421	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	5422	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	5423	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	5424	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5425	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
ganlikun	0:13413ea9a877	5426	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5427	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	5428	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5429	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	5430	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5431	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5432	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	5433	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	5434	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5435	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	5436	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
ganlikun	0:13413ea9a877	5437	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	5438	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	5439	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5440	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
ganlikun	0:13413ea9a877	5441	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	5442	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
ganlikun	0:13413ea9a877	5443	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
ganlikun	0:13413ea9a877	5444	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5445
ganlikun	0:13413ea9a877	5446	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
ganlikun	0:13413ea9a877	5447	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
ganlikun	0:13413ea9a877	5448	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
ganlikun	0:13413ea9a877	5449	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
ganlikun	0:13413ea9a877	5450	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
ganlikun	0:13413ea9a877	5451	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
ganlikun	0:13413ea9a877	5452	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
ganlikun	0:13413ea9a877	5453	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
ganlikun	0:13413ea9a877	5454	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5455	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
ganlikun	0:13413ea9a877	5456	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5457	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
ganlikun	0:13413ea9a877	5458	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5459	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
ganlikun	0:13413ea9a877	5460	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5461	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5462	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
ganlikun	0:13413ea9a877	5463	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
ganlikun	0:13413ea9a877	5464	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5465	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
ganlikun	0:13413ea9a877	5466	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
ganlikun	0:13413ea9a877	5467	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
ganlikun	0:13413ea9a877	5468	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
ganlikun	0:13413ea9a877	5469	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5470	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
ganlikun	0:13413ea9a877	5471	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
ganlikun	0:13413ea9a877	5472	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
ganlikun	0:13413ea9a877	5473	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
ganlikun	0:13413ea9a877	5474	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5475	/**
ganlikun	0:13413ea9a877	5476	* @}
ganlikun	0:13413ea9a877	5477	*/
ganlikun	0:13413ea9a877	5478
ganlikun	0:13413ea9a877	5479	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	5480	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	5481	* @{
ganlikun	0:13413ea9a877	5482	*/
ganlikun	0:13413ea9a877	5483	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	5484	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5485	#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART9RST))
ganlikun	0:13413ea9a877	5486	#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART10RST))
ganlikun	0:13413ea9a877	5487	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5488	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	5489	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	5490	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	5491	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	5492	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5493	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
ganlikun	0:13413ea9a877	5494	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5495	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
ganlikun	0:13413ea9a877	5496	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5497	#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM2RST))
ganlikun	0:13413ea9a877	5498	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5499
ganlikun	0:13413ea9a877	5500	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
ganlikun	0:13413ea9a877	5501	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5502	#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
ganlikun	0:13413ea9a877	5503	#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
ganlikun	0:13413ea9a877	5504	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5505	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
ganlikun	0:13413ea9a877	5506	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
ganlikun	0:13413ea9a877	5507	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
ganlikun	0:13413ea9a877	5508	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
ganlikun	0:13413ea9a877	5509	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5510	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
ganlikun	0:13413ea9a877	5511	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5512	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
ganlikun	0:13413ea9a877	5513	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5514	#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
ganlikun	0:13413ea9a877	5515	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5516	/**
ganlikun	0:13413ea9a877	5517	* @}
ganlikun	0:13413ea9a877	5518	*/
ganlikun	0:13413ea9a877	5519
ganlikun	0:13413ea9a877	5520	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	5521	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	5522	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	5523	* power consumption.
ganlikun	0:13413ea9a877	5524	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	5525	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	5526	* @{
ganlikun	0:13413ea9a877	5527	*/
ganlikun	0:13413ea9a877	5528	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	5529	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	5530	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	5531	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	5532	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	5533	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	5534	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	5535	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5536	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	5537	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5538
ganlikun	0:13413ea9a877	5539	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
ganlikun	0:13413ea9a877	5540	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
ganlikun	0:13413ea9a877	5541	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
ganlikun	0:13413ea9a877	5542	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
ganlikun	0:13413ea9a877	5543	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
ganlikun	0:13413ea9a877	5544	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
ganlikun	0:13413ea9a877	5545	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
ganlikun	0:13413ea9a877	5546	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5547	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
ganlikun	0:13413ea9a877	5548	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5549	/**
ganlikun	0:13413ea9a877	5550	* @}
ganlikun	0:13413ea9a877	5551	*/
ganlikun	0:13413ea9a877	5552
ganlikun	0:13413ea9a877	5553	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	5554	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	5555	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	5556	* power consumption.
ganlikun	0:13413ea9a877	5557	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	5558	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	5559	* @{
ganlikun	0:13413ea9a877	5560	*/
ganlikun	0:13413ea9a877	5561	#if defined(STM32F423xx)
ganlikun	0:13413ea9a877	5562	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AESLPEN))
ganlikun	0:13413ea9a877	5563	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
ganlikun	0:13413ea9a877	5564	#endif /* STM32F423xx */
ganlikun	0:13413ea9a877	5565
ganlikun	0:13413ea9a877	5566	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	5567	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
ganlikun	0:13413ea9a877	5568
ganlikun	0:13413ea9a877	5569	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	5570	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
ganlikun	0:13413ea9a877	5571	/**
ganlikun	0:13413ea9a877	5572	* @}
ganlikun	0:13413ea9a877	5573	*/
ganlikun	0:13413ea9a877	5574
ganlikun	0:13413ea9a877	5575	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	5576	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	5577	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	5578	* power consumption.
ganlikun	0:13413ea9a877	5579	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	5580	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	5581	* @{
ganlikun	0:13413ea9a877	5582	*/
ganlikun	0:13413ea9a877	5583	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5584	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
ganlikun	0:13413ea9a877	5585	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
ganlikun	0:13413ea9a877	5586
ganlikun	0:13413ea9a877	5587	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
ganlikun	0:13413ea9a877	5588	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
ganlikun	0:13413ea9a877	5589	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5590
ganlikun	0:13413ea9a877	5591	/**
ganlikun	0:13413ea9a877	5592	* @}
ganlikun	0:13413ea9a877	5593	*/
ganlikun	0:13413ea9a877	5594
ganlikun	0:13413ea9a877	5595	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	5596	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	5597	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	5598	* power consumption.
ganlikun	0:13413ea9a877	5599	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	5600	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	5601	* @{
ganlikun	0:13413ea9a877	5602	*/
ganlikun	0:13413ea9a877	5603	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	5604	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	5605	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	5606	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	5607	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	5608	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	5609	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	5610	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	5611	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5612	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
ganlikun	0:13413ea9a877	5613	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5614	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
ganlikun	0:13413ea9a877	5615	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	5616	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5617	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	5618	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5619	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5620	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	5621	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	5622	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5623	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	5624	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
ganlikun	0:13413ea9a877	5625	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	5626	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	5627	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5628	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
ganlikun	0:13413ea9a877	5629	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	5630	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
ganlikun	0:13413ea9a877	5631	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
ganlikun	0:13413ea9a877	5632	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5633
ganlikun	0:13413ea9a877	5634	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
ganlikun	0:13413ea9a877	5635	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
ganlikun	0:13413ea9a877	5636	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
ganlikun	0:13413ea9a877	5637	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
ganlikun	0:13413ea9a877	5638	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
ganlikun	0:13413ea9a877	5639	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
ganlikun	0:13413ea9a877	5640	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
ganlikun	0:13413ea9a877	5641	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
ganlikun	0:13413ea9a877	5642	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5643	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
ganlikun	0:13413ea9a877	5644	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5645	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
ganlikun	0:13413ea9a877	5646	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
ganlikun	0:13413ea9a877	5647	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5648	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
ganlikun	0:13413ea9a877	5649	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5650	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5651	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
ganlikun	0:13413ea9a877	5652	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
ganlikun	0:13413ea9a877	5653	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5654	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
ganlikun	0:13413ea9a877	5655	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
ganlikun	0:13413ea9a877	5656	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
ganlikun	0:13413ea9a877	5657	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
ganlikun	0:13413ea9a877	5658	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5659	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
ganlikun	0:13413ea9a877	5660	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
ganlikun	0:13413ea9a877	5661	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
ganlikun	0:13413ea9a877	5662	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
ganlikun	0:13413ea9a877	5663	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5664	/**
ganlikun	0:13413ea9a877	5665	* @}
ganlikun	0:13413ea9a877	5666	*/
ganlikun	0:13413ea9a877	5667
ganlikun	0:13413ea9a877	5668	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	5669	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	5670	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	5671	* power consumption.
ganlikun	0:13413ea9a877	5672	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	5673	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	5674	* @{
ganlikun	0:13413ea9a877	5675	*/
ganlikun	0:13413ea9a877	5676	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	5677	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5678	#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART9LPEN))
ganlikun	0:13413ea9a877	5679	#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART10LPEN))
ganlikun	0:13413ea9a877	5680	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5681	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	5682	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	5683	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
ganlikun	0:13413ea9a877	5684	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	5685	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	5686	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5687	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
ganlikun	0:13413ea9a877	5688	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5689	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
ganlikun	0:13413ea9a877	5690	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5691	#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM2LPEN))
ganlikun	0:13413ea9a877	5692	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5693
ganlikun	0:13413ea9a877	5694	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
ganlikun	0:13413ea9a877	5695	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5696	#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
ganlikun	0:13413ea9a877	5697	#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
ganlikun	0:13413ea9a877	5698	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5699	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
ganlikun	0:13413ea9a877	5700	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
ganlikun	0:13413ea9a877	5701	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
ganlikun	0:13413ea9a877	5702	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
ganlikun	0:13413ea9a877	5703	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
ganlikun	0:13413ea9a877	5704	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5705	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
ganlikun	0:13413ea9a877	5706	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5707	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
ganlikun	0:13413ea9a877	5708	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5709	#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
ganlikun	0:13413ea9a877	5710	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5711	/**
ganlikun	0:13413ea9a877	5712	* @}
ganlikun	0:13413ea9a877	5713	*/
ganlikun	0:13413ea9a877	5714	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	5715	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	5716
ganlikun	0:13413ea9a877	5717	/------------------------------- PLL Configuration --------------------------/
ganlikun	0:13413ea9a877	5718	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
ganlikun	0:13413ea9a877	5719	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	5720	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5721	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
ganlikun	0:13413ea9a877	5722	* @note This function must be used only when the main PLL is disabled.
ganlikun	0:13413ea9a877	5723	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
ganlikun	0:13413ea9a877	5724	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5725	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
ganlikun	0:13413ea9a877	5726	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
ganlikun	0:13413ea9a877	5727	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
ganlikun	0:13413ea9a877	5728	* @param __PLLM__: specifies the division factor for PLL VCO input clock
ganlikun	0:13413ea9a877	5729	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
ganlikun	0:13413ea9a877	5730	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
ganlikun	0:13413ea9a877	5731	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
ganlikun	0:13413ea9a877	5732	* of 2 MHz to limit PLL jitter.
ganlikun	0:13413ea9a877	5733	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
ganlikun	0:13413ea9a877	5734	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	5735	* @note You have to set the PLLN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5736	* output frequency is between 100 and 432 MHz.
ganlikun	0:13413ea9a877	5737	*
ganlikun	0:13413ea9a877	5738	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
ganlikun	0:13413ea9a877	5739	* This parameter must be a number in the range {2, 4, 6, or 8}.
ganlikun	0:13413ea9a877	5740	*
ganlikun	0:13413ea9a877	5741	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
ganlikun	0:13413ea9a877	5742	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	5743	* @note If the USB OTG FS is used in your application, you have to set the
ganlikun	0:13413ea9a877	5744	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
ganlikun	0:13413ea9a877	5745	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
ganlikun	0:13413ea9a877	5746	* correctly.
ganlikun	0:13413ea9a877	5747	*
ganlikun	0:13413ea9a877	5748	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
ganlikun	0:13413ea9a877	5749	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	5750	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
ganlikun	0:13413ea9a877	5751	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
ganlikun	0:13413ea9a877	5752	*
ganlikun	0:13413ea9a877	5753	*/
ganlikun	0:13413ea9a877	5754	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
ganlikun	0:13413ea9a877	5755	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
ganlikun	0:13413ea9a877	5756	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
ganlikun	0:13413ea9a877	5757	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
ganlikun	0:13413ea9a877	5758	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
ganlikun	0:13413ea9a877	5759	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
ganlikun	0:13413ea9a877	5760	#else
ganlikun	0:13413ea9a877	5761	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
ganlikun	0:13413ea9a877	5762	* @note This function must be used only when the main PLL is disabled.
ganlikun	0:13413ea9a877	5763	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
ganlikun	0:13413ea9a877	5764	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5765	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
ganlikun	0:13413ea9a877	5766	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
ganlikun	0:13413ea9a877	5767	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
ganlikun	0:13413ea9a877	5768	* @param __PLLM__: specifies the division factor for PLL VCO input clock
ganlikun	0:13413ea9a877	5769	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
ganlikun	0:13413ea9a877	5770	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
ganlikun	0:13413ea9a877	5771	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
ganlikun	0:13413ea9a877	5772	* of 2 MHz to limit PLL jitter.
ganlikun	0:13413ea9a877	5773	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
ganlikun	0:13413ea9a877	5774	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
ganlikun	0:13413ea9a877	5775	* Except for STM32F411xE devices where Min_Data = 192.
ganlikun	0:13413ea9a877	5776	* @note You have to set the PLLN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5777	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
ganlikun	0:13413ea9a877	5778	* where frequency is between 192 and 432 MHz.
ganlikun	0:13413ea9a877	5779	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
ganlikun	0:13413ea9a877	5780	* This parameter must be a number in the range {2, 4, 6, or 8}.
ganlikun	0:13413ea9a877	5781	*
ganlikun	0:13413ea9a877	5782	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
ganlikun	0:13413ea9a877	5783	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	5784	* @note If the USB OTG FS is used in your application, you have to set the
ganlikun	0:13413ea9a877	5785	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
ganlikun	0:13413ea9a877	5786	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
ganlikun	0:13413ea9a877	5787	* correctly.
ganlikun	0:13413ea9a877	5788	*
ganlikun	0:13413ea9a877	5789	*/
ganlikun	0:13413ea9a877	5790	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
ganlikun	0:13413ea9a877	5791	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
ganlikun	0:13413ea9a877	5792	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
ganlikun	0:13413ea9a877	5793	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
ganlikun	0:13413ea9a877	5794	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
ganlikun	0:13413ea9a877	5795	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
ganlikun	0:13413ea9a877	5796	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	5797
ganlikun	0:13413ea9a877	5798	/----------------------------PLLI2S Configuration ---------------------------/
ganlikun	0:13413ea9a877	5799	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
ganlikun	0:13413ea9a877	5800	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
ganlikun	0:13413ea9a877	5801	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
ganlikun	0:13413ea9a877	5802	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	5803	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5804
ganlikun	0:13413ea9a877	5805	/** @brief Macros to enable or disable the PLLI2S.
ganlikun	0:13413ea9a877	5806	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
ganlikun	0:13413ea9a877	5807	*/
ganlikun	0:13413ea9a877	5808	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
ganlikun	0:13413ea9a877	5809	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
ganlikun	0:13413ea9a877	5810
ganlikun	0:13413ea9a877	5811	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
ganlikun	0:13413ea9a877	5812	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
ganlikun	0:13413ea9a877	5813	STM32F412Rx \|\| STM32F412Cx */
ganlikun	0:13413ea9a877	5814	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	5815	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
ganlikun	0:13413ea9a877	5816	* @note This macro must be used only when the PLLI2S is disabled.
ganlikun	0:13413ea9a877	5817	* @note PLLI2S clock source is common with the main PLL (configured in
ganlikun	0:13413ea9a877	5818	* HAL_RCC_ClockConfig() API).
ganlikun	0:13413ea9a877	5819	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
ganlikun	0:13413ea9a877	5820	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
ganlikun	0:13413ea9a877	5821	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
ganlikun	0:13413ea9a877	5822	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
ganlikun	0:13413ea9a877	5823	* of 1 MHz to limit PLLI2S jitter.
ganlikun	0:13413ea9a877	5824	*
ganlikun	0:13413ea9a877	5825	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
ganlikun	0:13413ea9a877	5826	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	5827	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5828	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	5829	*
ganlikun	0:13413ea9a877	5830	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
ganlikun	0:13413ea9a877	5831	* This parameter must be a number in the range {2, 4, 6, or 8}.
ganlikun	0:13413ea9a877	5832	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
ganlikun	0:13413ea9a877	5833	*
ganlikun	0:13413ea9a877	5834	* @param __PLLI2SR__: specifies the division factor for I2S clock
ganlikun	0:13413ea9a877	5835	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	5836	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
ganlikun	0:13413ea9a877	5837	* on the I2S clock frequency.
ganlikun	0:13413ea9a877	5838	*
ganlikun	0:13413ea9a877	5839	* @param __PLLI2SQ__: specifies the division factor for SAI clock
ganlikun	0:13413ea9a877	5840	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	5841	*/
ganlikun	0:13413ea9a877	5842	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
ganlikun	0:13413ea9a877	5843	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
ganlikun	0:13413ea9a877	5844	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
ganlikun	0:13413ea9a877	5845	((((__PLLI2SP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
ganlikun	0:13413ea9a877	5846	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
ganlikun	0:13413ea9a877	5847	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
ganlikun	0:13413ea9a877	5848	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
ganlikun	0:13413ea9a877	5849	defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	5850	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
ganlikun	0:13413ea9a877	5851	* @note This macro must be used only when the PLLI2S is disabled.
ganlikun	0:13413ea9a877	5852	* @note PLLI2S clock source is common with the main PLL (configured in
ganlikun	0:13413ea9a877	5853	* HAL_RCC_ClockConfig() API).
ganlikun	0:13413ea9a877	5854	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
ganlikun	0:13413ea9a877	5855	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
ganlikun	0:13413ea9a877	5856	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
ganlikun	0:13413ea9a877	5857	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
ganlikun	0:13413ea9a877	5858	* of 1 MHz to limit PLLI2S jitter.
ganlikun	0:13413ea9a877	5859	*
ganlikun	0:13413ea9a877	5860	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
ganlikun	0:13413ea9a877	5861	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	5862	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5863	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	5864	*
ganlikun	0:13413ea9a877	5865	* @param __PLLI2SR__: specifies the division factor for I2S clock
ganlikun	0:13413ea9a877	5866	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	5867	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
ganlikun	0:13413ea9a877	5868	* on the I2S clock frequency.
ganlikun	0:13413ea9a877	5869	*
ganlikun	0:13413ea9a877	5870	* @param __PLLI2SQ__: specifies the division factor for SAI clock
ganlikun	0:13413ea9a877	5871	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	5872	*/
ganlikun	0:13413ea9a877	5873	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
ganlikun	0:13413ea9a877	5874	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
ganlikun	0:13413ea9a877	5875	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
ganlikun	0:13413ea9a877	5876	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
ganlikun	0:13413ea9a877	5877	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
ganlikun	0:13413ea9a877	5878	#else
ganlikun	0:13413ea9a877	5879	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
ganlikun	0:13413ea9a877	5880	* @note This macro must be used only when the PLLI2S is disabled.
ganlikun	0:13413ea9a877	5881	* @note PLLI2S clock source is common with the main PLL (configured in
ganlikun	0:13413ea9a877	5882	* HAL_RCC_ClockConfig() API).
ganlikun	0:13413ea9a877	5883	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
ganlikun	0:13413ea9a877	5884	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	5885	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5886	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	5887	*
ganlikun	0:13413ea9a877	5888	* @param __PLLI2SR__: specifies the division factor for I2S clock
ganlikun	0:13413ea9a877	5889	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	5890	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
ganlikun	0:13413ea9a877	5891	* on the I2S clock frequency.
ganlikun	0:13413ea9a877	5892	*
ganlikun	0:13413ea9a877	5893	*/
ganlikun	0:13413ea9a877	5894	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
ganlikun	0:13413ea9a877	5895	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
ganlikun	0:13413ea9a877	5896	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
ganlikun	0:13413ea9a877	5897	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	5898
ganlikun	0:13413ea9a877	5899	#if defined(STM32F411xE)
ganlikun	0:13413ea9a877	5900	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
ganlikun	0:13413ea9a877	5901	* @note This macro must be used only when the PLLI2S is disabled.
ganlikun	0:13413ea9a877	5902	* @note This macro must be used only when the PLLI2S is disabled.
ganlikun	0:13413ea9a877	5903	* @note PLLI2S clock source is common with the main PLL (configured in
ganlikun	0:13413ea9a877	5904	* HAL_RCC_ClockConfig() API).
ganlikun	0:13413ea9a877	5905	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
ganlikun	0:13413ea9a877	5906	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
ganlikun	0:13413ea9a877	5907	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
ganlikun	0:13413ea9a877	5908	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
ganlikun	0:13413ea9a877	5909	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
ganlikun	0:13413ea9a877	5910	* of 2 MHz to limit PLLI2S jitter.
ganlikun	0:13413ea9a877	5911	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
ganlikun	0:13413ea9a877	5912	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
ganlikun	0:13413ea9a877	5913	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5914	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	5915	* @param __PLLI2SR__: specifies the division factor for I2S clock
ganlikun	0:13413ea9a877	5916	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	5917	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
ganlikun	0:13413ea9a877	5918	* on the I2S clock frequency.
ganlikun	0:13413ea9a877	5919	*/
ganlikun	0:13413ea9a877	5920	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
ganlikun	0:13413ea9a877	5921	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
ganlikun	0:13413ea9a877	5922	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
ganlikun	0:13413ea9a877	5923	#endif /* STM32F411xE */
ganlikun	0:13413ea9a877	5924
ganlikun	0:13413ea9a877	5925	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	5926	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
ganlikun	0:13413ea9a877	5927	* @note This macro must be used only when the PLLI2S is disabled.
ganlikun	0:13413ea9a877	5928	* @note PLLI2S clock source is common with the main PLL (configured in
ganlikun	0:13413ea9a877	5929	* HAL_RCC_ClockConfig() API)
ganlikun	0:13413ea9a877	5930	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
ganlikun	0:13413ea9a877	5931	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	5932	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5933	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	5934	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
ganlikun	0:13413ea9a877	5935	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	5936	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
ganlikun	0:13413ea9a877	5937	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
ganlikun	0:13413ea9a877	5938	* @param __PLLI2SR__: specifies the division factor for I2S clock
ganlikun	0:13413ea9a877	5939	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	5940	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
ganlikun	0:13413ea9a877	5941	* on the I2S clock frequency.
ganlikun	0:13413ea9a877	5942	*/
ganlikun	0:13413ea9a877	5943	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) \|\
ganlikun	0:13413ea9a877	5944	((__PLLI2SQ__) << 24U) \|\
ganlikun	0:13413ea9a877	5945	((__PLLI2SR__) << 28U))
ganlikun	0:13413ea9a877	5946	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	5947	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	5948
ganlikun	0:13413ea9a877	5949	/------------------------------ PLLSAI Configuration ------------------------/
ganlikun	0:13413ea9a877	5950	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	5951	/** @brief Macros to Enable or Disable the PLLISAI.
ganlikun	0:13413ea9a877	5952	* @note The PLLSAI is only available with STM32F429x/439x Devices.
ganlikun	0:13413ea9a877	5953	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
ganlikun	0:13413ea9a877	5954	*/
ganlikun	0:13413ea9a877	5955	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
ganlikun	0:13413ea9a877	5956	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
ganlikun	0:13413ea9a877	5957
ganlikun	0:13413ea9a877	5958	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	5959	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
ganlikun	0:13413ea9a877	5960	*
ganlikun	0:13413ea9a877	5961	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
ganlikun	0:13413ea9a877	5962	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
ganlikun	0:13413ea9a877	5963	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
ganlikun	0:13413ea9a877	5964	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
ganlikun	0:13413ea9a877	5965	* of 1 MHz to limit PLLI2S jitter.
ganlikun	0:13413ea9a877	5966	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
ganlikun	0:13413ea9a877	5967	*
ganlikun	0:13413ea9a877	5968	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
ganlikun	0:13413ea9a877	5969	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	5970	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5971	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	5972	*
ganlikun	0:13413ea9a877	5973	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
ganlikun	0:13413ea9a877	5974	* This parameter must be a number in the range {2, 4, 6, or 8}.
ganlikun	0:13413ea9a877	5975	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
ganlikun	0:13413ea9a877	5976	*
ganlikun	0:13413ea9a877	5977	* @param __PLLSAIQ__: specifies the division factor for SAI clock
ganlikun	0:13413ea9a877	5978	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	5979	*
ganlikun	0:13413ea9a877	5980	* @param __PLLSAIR__: specifies the division factor for LTDC clock
ganlikun	0:13413ea9a877	5981	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	5982	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
ganlikun	0:13413ea9a877	5983	*/
ganlikun	0:13413ea9a877	5984	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
ganlikun	0:13413ea9a877	5985	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
ganlikun	0:13413ea9a877	5986	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
ganlikun	0:13413ea9a877	5987	((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
ganlikun	0:13413ea9a877	5988	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
ganlikun	0:13413ea9a877	5989	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	5990
ganlikun	0:13413ea9a877	5991	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	5992	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
ganlikun	0:13413ea9a877	5993	*
ganlikun	0:13413ea9a877	5994	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
ganlikun	0:13413ea9a877	5995	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	5996	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	5997	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	5998	*
ganlikun	0:13413ea9a877	5999	* @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
ganlikun	0:13413ea9a877	6000	* This parameter must be a number in the range {2, 4, 6, or 8}.
ganlikun	0:13413ea9a877	6001	*
ganlikun	0:13413ea9a877	6002	* @param __PLLSAIQ__: specifies the division factor for SAI clock
ganlikun	0:13413ea9a877	6003	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	6004	*
ganlikun	0:13413ea9a877	6005	* @param __PLLSAIR__: specifies the division factor for LTDC clock
ganlikun	0:13413ea9a877	6006	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	6007	*/
ganlikun	0:13413ea9a877	6008	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
ganlikun	0:13413ea9a877	6009	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
ganlikun	0:13413ea9a877	6010	((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
ganlikun	0:13413ea9a877	6011	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
ganlikun	0:13413ea9a877	6012	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
ganlikun	0:13413ea9a877	6013	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6014
ganlikun	0:13413ea9a877	6015	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	6016	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
ganlikun	0:13413ea9a877	6017	*
ganlikun	0:13413ea9a877	6018	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
ganlikun	0:13413ea9a877	6019	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
ganlikun	0:13413ea9a877	6020	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
ganlikun	0:13413ea9a877	6021	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
ganlikun	0:13413ea9a877	6022	*
ganlikun	0:13413ea9a877	6023	* @param __PLLSAIQ__: specifies the division factor for SAI clock
ganlikun	0:13413ea9a877	6024	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
ganlikun	0:13413ea9a877	6025	*
ganlikun	0:13413ea9a877	6026	* @param __PLLSAIR__: specifies the division factor for LTDC clock
ganlikun	0:13413ea9a877	6027	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
ganlikun	0:13413ea9a877	6028	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
ganlikun	0:13413ea9a877	6029	*/
ganlikun	0:13413ea9a877	6030	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
ganlikun	0:13413ea9a877	6031	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
ganlikun	0:13413ea9a877	6032	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
ganlikun	0:13413ea9a877	6033	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
ganlikun	0:13413ea9a877	6034	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	6035
ganlikun	0:13413ea9a877	6036	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6037	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	6038
ganlikun	0:13413ea9a877	6039	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
ganlikun	0:13413ea9a877	6040	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6041	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
ganlikun	0:13413ea9a877	6042	* @note This function must be called before enabling the PLLI2S.
ganlikun	0:13413ea9a877	6043	* @param __PLLI2SDivR__: specifies the PLLI2S division factor for SAI1 clock.
ganlikun	0:13413ea9a877	6044	* This parameter must be a number between 1 and 32.
ganlikun	0:13413ea9a877	6045	* SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
ganlikun	0:13413ea9a877	6046	*/
ganlikun	0:13413ea9a877	6047	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
ganlikun	0:13413ea9a877	6048
ganlikun	0:13413ea9a877	6049	/** @brief Macro to configure the SAI clock Divider coming from PLL.
ganlikun	0:13413ea9a877	6050	* @param __PLLDivR__: specifies the PLL division factor for SAI1 clock.
ganlikun	0:13413ea9a877	6051	* This parameter must be a number between 1 and 32.
ganlikun	0:13413ea9a877	6052	* SAI1 clock frequency = f(PLLR) / __PLLDivR__
ganlikun	0:13413ea9a877	6053	*/
ganlikun	0:13413ea9a877	6054	#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
ganlikun	0:13413ea9a877	6055	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6056
ganlikun	0:13413ea9a877	6057	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
ganlikun	0:13413ea9a877	6058	defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6059	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
ganlikun	0:13413ea9a877	6060	* @note This function must be called before enabling the PLLI2S.
ganlikun	0:13413ea9a877	6061	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
ganlikun	0:13413ea9a877	6062	* This parameter must be a number between 1 and 32.
ganlikun	0:13413ea9a877	6063	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
ganlikun	0:13413ea9a877	6064	*/
ganlikun	0:13413ea9a877	6065	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
ganlikun	0:13413ea9a877	6066
ganlikun	0:13413ea9a877	6067	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
ganlikun	0:13413ea9a877	6068	* @note This function must be called before enabling the PLLSAI.
ganlikun	0:13413ea9a877	6069	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
ganlikun	0:13413ea9a877	6070	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
ganlikun	0:13413ea9a877	6071	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
ganlikun	0:13413ea9a877	6072	*/
ganlikun	0:13413ea9a877	6073	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
ganlikun	0:13413ea9a877	6074	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6075
ganlikun	0:13413ea9a877	6076	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6077	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
ganlikun	0:13413ea9a877	6078	*
ganlikun	0:13413ea9a877	6079	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
ganlikun	0:13413ea9a877	6080	* @note This function must be called before enabling the PLLSAI.
ganlikun	0:13413ea9a877	6081	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
ganlikun	0:13413ea9a877	6082	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
ganlikun	0:13413ea9a877	6083	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
ganlikun	0:13413ea9a877	6084	*/
ganlikun	0:13413ea9a877	6085	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
ganlikun	0:13413ea9a877	6086	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6087	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	6088
ganlikun	0:13413ea9a877	6089	/------------------------- Peripheral Clock selection -----------------------/
ganlikun	0:13413ea9a877	6090	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
ganlikun	0:13413ea9a877	6091	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	6092	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
ganlikun	0:13413ea9a877	6093	defined(STM32F479xx)
ganlikun	0:13413ea9a877	6094	/** @brief Macro to configure the I2S clock source (I2SCLK).
ganlikun	0:13413ea9a877	6095	* @note This function must be called before enabling the I2S APB clock.
ganlikun	0:13413ea9a877	6096	* @param __SOURCE__: specifies the I2S clock source.
ganlikun	0:13413ea9a877	6097	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6098	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
ganlikun	0:13413ea9a877	6099	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
ganlikun	0:13413ea9a877	6100	* used as I2S clock source.
ganlikun	0:13413ea9a877	6101	*/
ganlikun	0:13413ea9a877	6102	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
ganlikun	0:13413ea9a877	6103
ganlikun	0:13413ea9a877	6104
ganlikun	0:13413ea9a877	6105	/** @brief Macro to get the I2S clock source (I2SCLK).
ganlikun	0:13413ea9a877	6106	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6107	* @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
ganlikun	0:13413ea9a877	6108	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
ganlikun	0:13413ea9a877	6109	* used as I2S clock source
ganlikun	0:13413ea9a877	6110	*/
ganlikun	0:13413ea9a877	6111	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
ganlikun	0:13413ea9a877	6112	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6113
ganlikun	0:13413ea9a877	6114	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6115
ganlikun	0:13413ea9a877	6116	/** @brief Macro to configure SAI1BlockA clock source selection.
ganlikun	0:13413ea9a877	6117	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
ganlikun	0:13413ea9a877	6118	* @note This function must be called before enabling PLLSAI, PLLI2S and
ganlikun	0:13413ea9a877	6119	* the SAI clock.
ganlikun	0:13413ea9a877	6120	* @param __SOURCE__: specifies the SAI Block A clock source.
ganlikun	0:13413ea9a877	6121	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6122	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
ganlikun	0:13413ea9a877	6123	* as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6124	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
ganlikun	0:13413ea9a877	6125	* as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6126	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
ganlikun	0:13413ea9a877	6127	* used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6128	*/
ganlikun	0:13413ea9a877	6129	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6130
ganlikun	0:13413ea9a877	6131	/** @brief Macro to configure SAI1BlockB clock source selection.
ganlikun	0:13413ea9a877	6132	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
ganlikun	0:13413ea9a877	6133	* @note This function must be called before enabling PLLSAI, PLLI2S and
ganlikun	0:13413ea9a877	6134	* the SAI clock.
ganlikun	0:13413ea9a877	6135	* @param __SOURCE__: specifies the SAI Block B clock source.
ganlikun	0:13413ea9a877	6136	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6137	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
ganlikun	0:13413ea9a877	6138	* as SAI1 Block B clock.
ganlikun	0:13413ea9a877	6139	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
ganlikun	0:13413ea9a877	6140	* as SAI1 Block B clock.
ganlikun	0:13413ea9a877	6141	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
ganlikun	0:13413ea9a877	6142	* used as SAI1 Block B clock.
ganlikun	0:13413ea9a877	6143	*/
ganlikun	0:13413ea9a877	6144	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6145	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6146
ganlikun	0:13413ea9a877	6147	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	6148	/** @brief Macro to configure SAI1 clock source selection.
ganlikun	0:13413ea9a877	6149	* @note This configuration is only available with STM32F446xx Devices.
ganlikun	0:13413ea9a877	6150	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
ganlikun	0:13413ea9a877	6151	* the SAI clock.
ganlikun	0:13413ea9a877	6152	* @param __SOURCE__: specifies the SAI1 clock source.
ganlikun	0:13413ea9a877	6153	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6154	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
ganlikun	0:13413ea9a877	6155	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
ganlikun	0:13413ea9a877	6156	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
ganlikun	0:13413ea9a877	6157	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
ganlikun	0:13413ea9a877	6158	*/
ganlikun	0:13413ea9a877	6159	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6160
ganlikun	0:13413ea9a877	6161	/** @brief Macro to Get SAI1 clock source selection.
ganlikun	0:13413ea9a877	6162	* @note This configuration is only available with STM32F446xx Devices.
ganlikun	0:13413ea9a877	6163	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6164	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
ganlikun	0:13413ea9a877	6165	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
ganlikun	0:13413ea9a877	6166	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
ganlikun	0:13413ea9a877	6167	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
ganlikun	0:13413ea9a877	6168	*/
ganlikun	0:13413ea9a877	6169	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
ganlikun	0:13413ea9a877	6170
ganlikun	0:13413ea9a877	6171	/** @brief Macro to configure SAI2 clock source selection.
ganlikun	0:13413ea9a877	6172	* @note This configuration is only available with STM32F446xx Devices.
ganlikun	0:13413ea9a877	6173	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
ganlikun	0:13413ea9a877	6174	* the SAI clock.
ganlikun	0:13413ea9a877	6175	* @param __SOURCE__: specifies the SAI2 clock source.
ganlikun	0:13413ea9a877	6176	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6177	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
ganlikun	0:13413ea9a877	6178	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
ganlikun	0:13413ea9a877	6179	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
ganlikun	0:13413ea9a877	6180	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
ganlikun	0:13413ea9a877	6181	*/
ganlikun	0:13413ea9a877	6182	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6183
ganlikun	0:13413ea9a877	6184	/** @brief Macro to Get SAI2 clock source selection.
ganlikun	0:13413ea9a877	6185	* @note This configuration is only available with STM32F446xx Devices.
ganlikun	0:13413ea9a877	6186	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6187	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
ganlikun	0:13413ea9a877	6188	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
ganlikun	0:13413ea9a877	6189	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
ganlikun	0:13413ea9a877	6190	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
ganlikun	0:13413ea9a877	6191	*/
ganlikun	0:13413ea9a877	6192	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
ganlikun	0:13413ea9a877	6193
ganlikun	0:13413ea9a877	6194	/** @brief Macro to configure I2S APB1 clock source selection.
ganlikun	0:13413ea9a877	6195	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
ganlikun	0:13413ea9a877	6196	* @param __SOURCE__: specifies the I2S APB1 clock source.
ganlikun	0:13413ea9a877	6197	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6198	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
ganlikun	0:13413ea9a877	6199	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
ganlikun	0:13413ea9a877	6200	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
ganlikun	0:13413ea9a877	6201	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6202	*/
ganlikun	0:13413ea9a877	6203	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6204
ganlikun	0:13413ea9a877	6205	/** @brief Macro to Get I2S APB1 clock source selection.
ganlikun	0:13413ea9a877	6206	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6207	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
ganlikun	0:13413ea9a877	6208	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
ganlikun	0:13413ea9a877	6209	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
ganlikun	0:13413ea9a877	6210	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6211	*/
ganlikun	0:13413ea9a877	6212	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
ganlikun	0:13413ea9a877	6213
ganlikun	0:13413ea9a877	6214	/** @brief Macro to configure I2S APB2 clock source selection.
ganlikun	0:13413ea9a877	6215	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
ganlikun	0:13413ea9a877	6216	* @param __SOURCE__: specifies the SAI Block A clock source.
ganlikun	0:13413ea9a877	6217	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6218	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
ganlikun	0:13413ea9a877	6219	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
ganlikun	0:13413ea9a877	6220	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
ganlikun	0:13413ea9a877	6221	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6222	*/
ganlikun	0:13413ea9a877	6223	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6224
ganlikun	0:13413ea9a877	6225	/** @brief Macro to Get I2S APB2 clock source selection.
ganlikun	0:13413ea9a877	6226	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6227	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
ganlikun	0:13413ea9a877	6228	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
ganlikun	0:13413ea9a877	6229	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
ganlikun	0:13413ea9a877	6230	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6231	*/
ganlikun	0:13413ea9a877	6232	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
ganlikun	0:13413ea9a877	6233
ganlikun	0:13413ea9a877	6234	/** @brief Macro to configure the CEC clock.
ganlikun	0:13413ea9a877	6235	* @param __SOURCE__: specifies the CEC clock source.
ganlikun	0:13413ea9a877	6236	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6237	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
ganlikun	0:13413ea9a877	6238	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
ganlikun	0:13413ea9a877	6239	*/
ganlikun	0:13413ea9a877	6240	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6241
ganlikun	0:13413ea9a877	6242	/** @brief Macro to Get the CEC clock.
ganlikun	0:13413ea9a877	6243	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6244	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
ganlikun	0:13413ea9a877	6245	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
ganlikun	0:13413ea9a877	6246	*/
ganlikun	0:13413ea9a877	6247	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
ganlikun	0:13413ea9a877	6248
ganlikun	0:13413ea9a877	6249	/** @brief Macro to configure the FMPI2C1 clock.
ganlikun	0:13413ea9a877	6250	* @param __SOURCE__: specifies the FMPI2C1 clock source.
ganlikun	0:13413ea9a877	6251	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6252	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6253	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6254	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6255	*/
ganlikun	0:13413ea9a877	6256	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6257
ganlikun	0:13413ea9a877	6258	/** @brief Macro to Get the FMPI2C1 clock.
ganlikun	0:13413ea9a877	6259	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6260	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6261	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6262	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6263	*/
ganlikun	0:13413ea9a877	6264	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
ganlikun	0:13413ea9a877	6265
ganlikun	0:13413ea9a877	6266	/** @brief Macro to configure the CLK48 clock.
ganlikun	0:13413ea9a877	6267	* @param __SOURCE__: specifies the CLK48 clock source.
ganlikun	0:13413ea9a877	6268	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6269	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
ganlikun	0:13413ea9a877	6270	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
ganlikun	0:13413ea9a877	6271	*/
ganlikun	0:13413ea9a877	6272	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6273
ganlikun	0:13413ea9a877	6274	/** @brief Macro to Get the CLK48 clock.
ganlikun	0:13413ea9a877	6275	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6276	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
ganlikun	0:13413ea9a877	6277	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
ganlikun	0:13413ea9a877	6278	*/
ganlikun	0:13413ea9a877	6279	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
ganlikun	0:13413ea9a877	6280
ganlikun	0:13413ea9a877	6281	/** @brief Macro to configure the SDIO clock.
ganlikun	0:13413ea9a877	6282	* @param __SOURCE__: specifies the SDIO clock source.
ganlikun	0:13413ea9a877	6283	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6284	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
ganlikun	0:13413ea9a877	6285	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
ganlikun	0:13413ea9a877	6286	*/
ganlikun	0:13413ea9a877	6287	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6288
ganlikun	0:13413ea9a877	6289	/** @brief Macro to Get the SDIO clock.
ganlikun	0:13413ea9a877	6290	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6291	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
ganlikun	0:13413ea9a877	6292	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
ganlikun	0:13413ea9a877	6293	*/
ganlikun	0:13413ea9a877	6294	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
ganlikun	0:13413ea9a877	6295
ganlikun	0:13413ea9a877	6296	/** @brief Macro to configure the SPDIFRX clock.
ganlikun	0:13413ea9a877	6297	* @param __SOURCE__: specifies the SPDIFRX clock source.
ganlikun	0:13413ea9a877	6298	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6299	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
ganlikun	0:13413ea9a877	6300	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
ganlikun	0:13413ea9a877	6301	*/
ganlikun	0:13413ea9a877	6302	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6303
ganlikun	0:13413ea9a877	6304	/** @brief Macro to Get the SPDIFRX clock.
ganlikun	0:13413ea9a877	6305	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6306	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
ganlikun	0:13413ea9a877	6307	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
ganlikun	0:13413ea9a877	6308	*/
ganlikun	0:13413ea9a877	6309	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
ganlikun	0:13413ea9a877	6310	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	6311
ganlikun	0:13413ea9a877	6312	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6313
ganlikun	0:13413ea9a877	6314	/** @brief Macro to configure the CLK48 clock.
ganlikun	0:13413ea9a877	6315	* @param __SOURCE__: specifies the CLK48 clock source.
ganlikun	0:13413ea9a877	6316	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6317	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
ganlikun	0:13413ea9a877	6318	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
ganlikun	0:13413ea9a877	6319	*/
ganlikun	0:13413ea9a877	6320	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6321
ganlikun	0:13413ea9a877	6322	/** @brief Macro to Get the CLK48 clock.
ganlikun	0:13413ea9a877	6323	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6324	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
ganlikun	0:13413ea9a877	6325	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
ganlikun	0:13413ea9a877	6326	*/
ganlikun	0:13413ea9a877	6327	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
ganlikun	0:13413ea9a877	6328
ganlikun	0:13413ea9a877	6329	/** @brief Macro to configure the SDIO clock.
ganlikun	0:13413ea9a877	6330	* @param __SOURCE__: specifies the SDIO clock source.
ganlikun	0:13413ea9a877	6331	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6332	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
ganlikun	0:13413ea9a877	6333	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
ganlikun	0:13413ea9a877	6334	*/
ganlikun	0:13413ea9a877	6335	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6336
ganlikun	0:13413ea9a877	6337	/** @brief Macro to Get the SDIO clock.
ganlikun	0:13413ea9a877	6338	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6339	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
ganlikun	0:13413ea9a877	6340	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
ganlikun	0:13413ea9a877	6341	*/
ganlikun	0:13413ea9a877	6342	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
ganlikun	0:13413ea9a877	6343
ganlikun	0:13413ea9a877	6344	/** @brief Macro to configure the DSI clock.
ganlikun	0:13413ea9a877	6345	* @param __SOURCE__: specifies the DSI clock source.
ganlikun	0:13413ea9a877	6346	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6347	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
ganlikun	0:13413ea9a877	6348	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
ganlikun	0:13413ea9a877	6349	*/
ganlikun	0:13413ea9a877	6350	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6351
ganlikun	0:13413ea9a877	6352	/** @brief Macro to Get the DSI clock.
ganlikun	0:13413ea9a877	6353	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6354	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
ganlikun	0:13413ea9a877	6355	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
ganlikun	0:13413ea9a877	6356	*/
ganlikun	0:13413ea9a877	6357	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
ganlikun	0:13413ea9a877	6358
ganlikun	0:13413ea9a877	6359	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6360
ganlikun	0:13413ea9a877	6361	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
ganlikun	0:13413ea9a877	6362	defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6363	/** @brief Macro to configure the DFSDM1 clock.
ganlikun	0:13413ea9a877	6364	* @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
ganlikun	0:13413ea9a877	6365	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6366	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
ganlikun	0:13413ea9a877	6367	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
ganlikun	0:13413ea9a877	6368	* @retval None
ganlikun	0:13413ea9a877	6369	*/
ganlikun	0:13413ea9a877	6370	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
ganlikun	0:13413ea9a877	6371
ganlikun	0:13413ea9a877	6372	/** @brief Macro to get the DFSDM1 clock source.
ganlikun	0:13413ea9a877	6373	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6374	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
ganlikun	0:13413ea9a877	6375	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
ganlikun	0:13413ea9a877	6376	*/
ganlikun	0:13413ea9a877	6377	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
ganlikun	0:13413ea9a877	6378
ganlikun	0:13413ea9a877	6379	/** @brief Macro to configure DFSDM1 Audio clock source selection.
ganlikun	0:13413ea9a877	6380	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
ganlikun	0:13413ea9a877	6381	STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6382	* @param __SOURCE__: specifies the DFSDM1 Audio clock source.
ganlikun	0:13413ea9a877	6383	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6384	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
ganlikun	0:13413ea9a877	6385	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
ganlikun	0:13413ea9a877	6386	*/
ganlikun	0:13413ea9a877	6387	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
ganlikun	0:13413ea9a877	6388
ganlikun	0:13413ea9a877	6389	/** @brief Macro to Get DFSDM1 Audio clock source selection.
ganlikun	0:13413ea9a877	6390	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
ganlikun	0:13413ea9a877	6391	STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6392	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6393	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
ganlikun	0:13413ea9a877	6394	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
ganlikun	0:13413ea9a877	6395	*/
ganlikun	0:13413ea9a877	6396	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
ganlikun	0:13413ea9a877	6397
ganlikun	0:13413ea9a877	6398	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6399	/** @brief Macro to configure the DFSDM2 clock.
ganlikun	0:13413ea9a877	6400	* @param __DFSDM2_CLKSOURCE__: specifies the DFSDM1 clock source.
ganlikun	0:13413ea9a877	6401	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6402	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
ganlikun	0:13413ea9a877	6403	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
ganlikun	0:13413ea9a877	6404	* @retval None
ganlikun	0:13413ea9a877	6405	*/
ganlikun	0:13413ea9a877	6406	#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
ganlikun	0:13413ea9a877	6407
ganlikun	0:13413ea9a877	6408	/** @brief Macro to get the DFSDM2 clock source.
ganlikun	0:13413ea9a877	6409	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6410	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
ganlikun	0:13413ea9a877	6411	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
ganlikun	0:13413ea9a877	6412	*/
ganlikun	0:13413ea9a877	6413	#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
ganlikun	0:13413ea9a877	6414
ganlikun	0:13413ea9a877	6415	/** @brief Macro to configure DFSDM1 Audio clock source selection.
ganlikun	0:13413ea9a877	6416	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6417	* @param __SOURCE__: specifies the DFSDM2 Audio clock source.
ganlikun	0:13413ea9a877	6418	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6419	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
ganlikun	0:13413ea9a877	6420	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
ganlikun	0:13413ea9a877	6421	*/
ganlikun	0:13413ea9a877	6422	#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
ganlikun	0:13413ea9a877	6423
ganlikun	0:13413ea9a877	6424	/** @brief Macro to Get DFSDM2 Audio clock source selection.
ganlikun	0:13413ea9a877	6425	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6426	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6427	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
ganlikun	0:13413ea9a877	6428	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
ganlikun	0:13413ea9a877	6429	*/
ganlikun	0:13413ea9a877	6430	#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
ganlikun	0:13413ea9a877	6431
ganlikun	0:13413ea9a877	6432	/** @brief Macro to configure SAI1BlockA clock source selection.
ganlikun	0:13413ea9a877	6433	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6434	* @note This function must be called before enabling PLLSAI, PLLI2S and
ganlikun	0:13413ea9a877	6435	* the SAI clock.
ganlikun	0:13413ea9a877	6436	* @param __SOURCE__: specifies the SAI Block A clock source.
ganlikun	0:13413ea9a877	6437	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6438	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6439	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6440	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6441	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6442	*/
ganlikun	0:13413ea9a877	6443	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6444
ganlikun	0:13413ea9a877	6445	/** @brief Macro to Get SAI1 BlockA clock source selection.
ganlikun	0:13413ea9a877	6446	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6447	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6448	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6449	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6450	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6451	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6452	*/
ganlikun	0:13413ea9a877	6453	#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
ganlikun	0:13413ea9a877	6454
ganlikun	0:13413ea9a877	6455	/** @brief Macro to configure SAI1 BlockB clock source selection.
ganlikun	0:13413ea9a877	6456	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6457	* @note This function must be called before enabling PLLSAI, PLLI2S and
ganlikun	0:13413ea9a877	6458	* the SAI clock.
ganlikun	0:13413ea9a877	6459	* @param __SOURCE__: specifies the SAI Block B clock source.
ganlikun	0:13413ea9a877	6460	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6461	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6462	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6463	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6464	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6465	*/
ganlikun	0:13413ea9a877	6466	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6467
ganlikun	0:13413ea9a877	6468	/** @brief Macro to Get SAI1 BlockB clock source selection.
ganlikun	0:13413ea9a877	6469	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
ganlikun	0:13413ea9a877	6470	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6471	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6472	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6473	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
ganlikun	0:13413ea9a877	6474	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6475	*/
ganlikun	0:13413ea9a877	6476	#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
ganlikun	0:13413ea9a877	6477
ganlikun	0:13413ea9a877	6478	/** @brief Macro to configure the LPTIM1 clock.
ganlikun	0:13413ea9a877	6479	* @param __SOURCE__: specifies the LPTIM1 clock source.
ganlikun	0:13413ea9a877	6480	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6481	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6482	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6483	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6484	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6485	*/
ganlikun	0:13413ea9a877	6486	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6487
ganlikun	0:13413ea9a877	6488	/** @brief Macro to Get the LPTIM1 clock.
ganlikun	0:13413ea9a877	6489	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6490	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6491	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6492	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6493	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6494	*/
ganlikun	0:13413ea9a877	6495	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
ganlikun	0:13413ea9a877	6496	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6497
ganlikun	0:13413ea9a877	6498	/** @brief Macro to configure I2S APB1 clock source selection.
ganlikun	0:13413ea9a877	6499	* @param __SOURCE__: specifies the I2S APB1 clock source.
ganlikun	0:13413ea9a877	6500	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6501	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
ganlikun	0:13413ea9a877	6502	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
ganlikun	0:13413ea9a877	6503	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
ganlikun	0:13413ea9a877	6504	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6505	*/
ganlikun	0:13413ea9a877	6506	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6507
ganlikun	0:13413ea9a877	6508	/** @brief Macro to Get I2S APB1 clock source selection.
ganlikun	0:13413ea9a877	6509	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6510	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
ganlikun	0:13413ea9a877	6511	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
ganlikun	0:13413ea9a877	6512	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
ganlikun	0:13413ea9a877	6513	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6514	*/
ganlikun	0:13413ea9a877	6515	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
ganlikun	0:13413ea9a877	6516
ganlikun	0:13413ea9a877	6517	/** @brief Macro to configure I2S APB2 clock source selection.
ganlikun	0:13413ea9a877	6518	* @param __SOURCE__: specifies the I2S APB2 clock source.
ganlikun	0:13413ea9a877	6519	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6520	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
ganlikun	0:13413ea9a877	6521	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
ganlikun	0:13413ea9a877	6522	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
ganlikun	0:13413ea9a877	6523	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6524	*/
ganlikun	0:13413ea9a877	6525	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6526
ganlikun	0:13413ea9a877	6527	/** @brief Macro to Get I2S APB2 clock source selection.
ganlikun	0:13413ea9a877	6528	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6529	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
ganlikun	0:13413ea9a877	6530	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
ganlikun	0:13413ea9a877	6531	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
ganlikun	0:13413ea9a877	6532	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6533	*/
ganlikun	0:13413ea9a877	6534	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
ganlikun	0:13413ea9a877	6535
ganlikun	0:13413ea9a877	6536	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
ganlikun	0:13413ea9a877	6537	* @note This macro must be called before enabling the I2S APB clock.
ganlikun	0:13413ea9a877	6538	* @param __SOURCE__: specifies the I2S clock source.
ganlikun	0:13413ea9a877	6539	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6540	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
ganlikun	0:13413ea9a877	6541	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
ganlikun	0:13413ea9a877	6542	* used as I2S clock source.
ganlikun	0:13413ea9a877	6543	*/
ganlikun	0:13413ea9a877	6544	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
ganlikun	0:13413ea9a877	6545
ganlikun	0:13413ea9a877	6546	/** @brief Macro to configure the FMPI2C1 clock.
ganlikun	0:13413ea9a877	6547	* @param __SOURCE__: specifies the FMPI2C1 clock source.
ganlikun	0:13413ea9a877	6548	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6549	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6550	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6551	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6552	*/
ganlikun	0:13413ea9a877	6553	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6554
ganlikun	0:13413ea9a877	6555	/** @brief Macro to Get the FMPI2C1 clock.
ganlikun	0:13413ea9a877	6556	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6557	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6558	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6559	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6560	*/
ganlikun	0:13413ea9a877	6561	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
ganlikun	0:13413ea9a877	6562
ganlikun	0:13413ea9a877	6563	/** @brief Macro to configure the CLK48 clock.
ganlikun	0:13413ea9a877	6564	* @param __SOURCE__: specifies the CLK48 clock source.
ganlikun	0:13413ea9a877	6565	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6566	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
ganlikun	0:13413ea9a877	6567	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
ganlikun	0:13413ea9a877	6568	*/
ganlikun	0:13413ea9a877	6569	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6570
ganlikun	0:13413ea9a877	6571	/** @brief Macro to Get the CLK48 clock.
ganlikun	0:13413ea9a877	6572	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6573	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
ganlikun	0:13413ea9a877	6574	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
ganlikun	0:13413ea9a877	6575	*/
ganlikun	0:13413ea9a877	6576	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
ganlikun	0:13413ea9a877	6577
ganlikun	0:13413ea9a877	6578	/** @brief Macro to configure the SDIO clock.
ganlikun	0:13413ea9a877	6579	* @param __SOURCE__: specifies the SDIO clock source.
ganlikun	0:13413ea9a877	6580	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6581	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
ganlikun	0:13413ea9a877	6582	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
ganlikun	0:13413ea9a877	6583	*/
ganlikun	0:13413ea9a877	6584	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6585
ganlikun	0:13413ea9a877	6586	/** @brief Macro to Get the SDIO clock.
ganlikun	0:13413ea9a877	6587	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6588	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
ganlikun	0:13413ea9a877	6589	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
ganlikun	0:13413ea9a877	6590	*/
ganlikun	0:13413ea9a877	6591	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
ganlikun	0:13413ea9a877	6592
ganlikun	0:13413ea9a877	6593	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
ganlikun	0:13413ea9a877	6594
ganlikun	0:13413ea9a877	6595	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	6596	/** @brief Macro to configure I2S clock source selection.
ganlikun	0:13413ea9a877	6597	* @param __SOURCE__: specifies the I2S clock source.
ganlikun	0:13413ea9a877	6598	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6599	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
ganlikun	0:13413ea9a877	6600	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
ganlikun	0:13413ea9a877	6601	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
ganlikun	0:13413ea9a877	6602	*/
ganlikun	0:13413ea9a877	6603	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
ganlikun	0:13413ea9a877	6604
ganlikun	0:13413ea9a877	6605	/** @brief Macro to Get I2S clock source selection.
ganlikun	0:13413ea9a877	6606	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6607	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
ganlikun	0:13413ea9a877	6608	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
ganlikun	0:13413ea9a877	6609	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
ganlikun	0:13413ea9a877	6610	*/
ganlikun	0:13413ea9a877	6611	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
ganlikun	0:13413ea9a877	6612
ganlikun	0:13413ea9a877	6613	/** @brief Macro to configure the FMPI2C1 clock.
ganlikun	0:13413ea9a877	6614	* @param __SOURCE__: specifies the FMPI2C1 clock source.
ganlikun	0:13413ea9a877	6615	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6616	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6617	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6618	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6619	*/
ganlikun	0:13413ea9a877	6620	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6621
ganlikun	0:13413ea9a877	6622	/** @brief Macro to Get the FMPI2C1 clock.
ganlikun	0:13413ea9a877	6623	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6624	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6625	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6626	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
ganlikun	0:13413ea9a877	6627	*/
ganlikun	0:13413ea9a877	6628	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
ganlikun	0:13413ea9a877	6629
ganlikun	0:13413ea9a877	6630	/** @brief Macro to configure the LPTIM1 clock.
ganlikun	0:13413ea9a877	6631	* @param __SOURCE__: specifies the LPTIM1 clock source.
ganlikun	0:13413ea9a877	6632	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6633	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6634	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6635	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6636	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6637	*/
ganlikun	0:13413ea9a877	6638	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
ganlikun	0:13413ea9a877	6639
ganlikun	0:13413ea9a877	6640	/** @brief Macro to Get the LPTIM1 clock.
ganlikun	0:13413ea9a877	6641	* @retval The clock source can be one of the following values:
ganlikun	0:13413ea9a877	6642	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6643	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6644	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6645	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
ganlikun	0:13413ea9a877	6646	*/
ganlikun	0:13413ea9a877	6647	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
ganlikun	0:13413ea9a877	6648	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	6649
ganlikun	0:13413ea9a877	6650	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	6651	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
ganlikun	0:13413ea9a877	6652	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
ganlikun	0:13413ea9a877	6653	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
ganlikun	0:13413ea9a877	6654	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6655	/** @brief Macro to configure the Timers clocks prescalers
ganlikun	0:13413ea9a877	6656	* @note This feature is only available with STM32F429x/439x Devices.
ganlikun	0:13413ea9a877	6657	* @param __PRESC__ : specifies the Timers clocks prescalers selection
ganlikun	0:13413ea9a877	6658	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6659	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
ganlikun	0:13413ea9a877	6660	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
ganlikun	0:13413ea9a877	6661	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
ganlikun	0:13413ea9a877	6662	* division by 4 or more.
ganlikun	0:13413ea9a877	6663	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
ganlikun	0:13413ea9a877	6664	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
ganlikun	0:13413ea9a877	6665	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
ganlikun	0:13413ea9a877	6666	* to division by 8 or more.
ganlikun	0:13413ea9a877	6667	*/
ganlikun	0:13413ea9a877	6668	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
ganlikun	0:13413ea9a877	6669
ganlikun	0:13413ea9a877	6670	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
ganlikun	0:13413ea9a877	6671	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\|\
ganlikun	0:13413ea9a877	6672	STM32F423xx */
ganlikun	0:13413ea9a877	6673
ganlikun	0:13413ea9a877	6674	/----------------------------------------------------------------------------/
ganlikun	0:13413ea9a877	6675
ganlikun	0:13413ea9a877	6676	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6677	/** @brief Enable PLLSAI_RDY interrupt.
ganlikun	0:13413ea9a877	6678	*/
ganlikun	0:13413ea9a877	6679	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
ganlikun	0:13413ea9a877	6680
ganlikun	0:13413ea9a877	6681	/** @brief Disable PLLSAI_RDY interrupt.
ganlikun	0:13413ea9a877	6682	*/
ganlikun	0:13413ea9a877	6683	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
ganlikun	0:13413ea9a877	6684
ganlikun	0:13413ea9a877	6685	/** @brief Clear the PLLSAI RDY interrupt pending bits.
ganlikun	0:13413ea9a877	6686	*/
ganlikun	0:13413ea9a877	6687	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
ganlikun	0:13413ea9a877	6688
ganlikun	0:13413ea9a877	6689	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
ganlikun	0:13413ea9a877	6690	* @retval The new state (TRUE or FALSE).
ganlikun	0:13413ea9a877	6691	*/
ganlikun	0:13413ea9a877	6692	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
ganlikun	0:13413ea9a877	6693
ganlikun	0:13413ea9a877	6694	/** @brief Check PLLSAI RDY flag is set or not.
ganlikun	0:13413ea9a877	6695	* @retval The new state (TRUE or FALSE).
ganlikun	0:13413ea9a877	6696	*/
ganlikun	0:13413ea9a877	6697	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
ganlikun	0:13413ea9a877	6698
ganlikun	0:13413ea9a877	6699	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6700
ganlikun	0:13413ea9a877	6701	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	6702	/** @brief Macros to enable or disable the RCC MCO1 feature.
ganlikun	0:13413ea9a877	6703	*/
ganlikun	0:13413ea9a877	6704	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
ganlikun	0:13413ea9a877	6705	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
ganlikun	0:13413ea9a877	6706
ganlikun	0:13413ea9a877	6707	/** @brief Macros to enable or disable the RCC MCO2 feature.
ganlikun	0:13413ea9a877	6708	*/
ganlikun	0:13413ea9a877	6709	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
ganlikun	0:13413ea9a877	6710	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
ganlikun	0:13413ea9a877	6711
ganlikun	0:13413ea9a877	6712	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	6713
ganlikun	0:13413ea9a877	6714	/**
ganlikun	0:13413ea9a877	6715	* @}
ganlikun	0:13413ea9a877	6716	*/
ganlikun	0:13413ea9a877	6717
ganlikun	0:13413ea9a877	6718	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	6719	/** @addtogroup RCCEx_Exported_Functions
ganlikun	0:13413ea9a877	6720	* @{
ganlikun	0:13413ea9a877	6721	*/
ganlikun	0:13413ea9a877	6722
ganlikun	0:13413ea9a877	6723	/** @addtogroup RCCEx_Exported_Functions_Group1
ganlikun	0:13413ea9a877	6724	* @{
ganlikun	0:13413ea9a877	6725	*/
ganlikun	0:13413ea9a877	6726	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
ganlikun	0:13413ea9a877	6727	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
ganlikun	0:13413ea9a877	6728
ganlikun	0:13413ea9a877	6729	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
ganlikun	0:13413ea9a877	6730
ganlikun	0:13413ea9a877	6731	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
ganlikun	0:13413ea9a877	6732	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
ganlikun	0:13413ea9a877	6733	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
ganlikun	0:13413ea9a877	6734	defined(STM32F423xx)
ganlikun	0:13413ea9a877	6735	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
ganlikun	0:13413ea9a877	6736	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6737	/**
ganlikun	0:13413ea9a877	6738	* @}
ganlikun	0:13413ea9a877	6739	*/
ganlikun	0:13413ea9a877	6740
ganlikun	0:13413ea9a877	6741	/**
ganlikun	0:13413ea9a877	6742	* @}
ganlikun	0:13413ea9a877	6743	*/
ganlikun	0:13413ea9a877	6744	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	6745	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	6746	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	6747	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
ganlikun	0:13413ea9a877	6748	* @{
ganlikun	0:13413ea9a877	6749	*/
ganlikun	0:13413ea9a877	6750
ganlikun	0:13413ea9a877	6751	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
ganlikun	0:13413ea9a877	6752	* @brief RCC registers bit address in the alias region
ganlikun	0:13413ea9a877	6753	* @{
ganlikun	0:13413ea9a877	6754	*/
ganlikun	0:13413ea9a877	6755	/* --- CR Register ---*/
ganlikun	0:13413ea9a877	6756	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	6757	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6758	/* Alias word address of PLLSAION bit */
ganlikun	0:13413ea9a877	6759	#define RCC_PLLSAION_BIT_NUMBER 0x1CU
ganlikun	0:13413ea9a877	6760	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	6761
ganlikun	0:13413ea9a877	6762	#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
ganlikun	0:13413ea9a877	6763	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6764
ganlikun	0:13413ea9a877	6765	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
ganlikun	0:13413ea9a877	6766	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
ganlikun	0:13413ea9a877	6767	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
ganlikun	0:13413ea9a877	6768	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	6769	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6770	/* Alias word address of PLLI2SON bit */
ganlikun	0:13413ea9a877	6771	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
ganlikun	0:13413ea9a877	6772	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	6773	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
ganlikun	0:13413ea9a877	6774	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
ganlikun	0:13413ea9a877	6775	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6776
ganlikun	0:13413ea9a877	6777	/* --- DCKCFGR Register ---*/
ganlikun	0:13413ea9a877	6778	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	6779	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
ganlikun	0:13413ea9a877	6780	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
ganlikun	0:13413ea9a877	6781	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
ganlikun	0:13413ea9a877	6782	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6783	/* Alias word address of TIMPRE bit */
ganlikun	0:13413ea9a877	6784	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
ganlikun	0:13413ea9a877	6785	#define RCC_TIMPRE_BIT_NUMBER 0x18U
ganlikun	0:13413ea9a877	6786	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	6787	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
ganlikun	0:13413ea9a877	6788	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
ganlikun	0:13413ea9a877	6789	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6790
ganlikun	0:13413ea9a877	6791	/* --- CFGR Register ---*/
ganlikun	0:13413ea9a877	6792	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
ganlikun	0:13413ea9a877	6793	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
ganlikun	0:13413ea9a877	6794	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
ganlikun	0:13413ea9a877	6795	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
ganlikun	0:13413ea9a877	6796	defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6797	/* Alias word address of I2SSRC bit */
ganlikun	0:13413ea9a877	6798	#define RCC_I2SSRC_BIT_NUMBER 0x17U
ganlikun	0:13413ea9a877	6799	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	6800
ganlikun	0:13413ea9a877	6801	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
ganlikun	0:13413ea9a877	6802	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
ganlikun	0:13413ea9a877	6803	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6804
ganlikun	0:13413ea9a877	6805	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
ganlikun	0:13413ea9a877	6806	defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6807	/* --- PLLI2SCFGR Register ---*/
ganlikun	0:13413ea9a877	6808	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
ganlikun	0:13413ea9a877	6809	/* Alias word address of PLLI2SSRC bit */
ganlikun	0:13413ea9a877	6810	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
ganlikun	0:13413ea9a877	6811	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	6812
ganlikun	0:13413ea9a877	6813	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
ganlikun	0:13413ea9a877	6814	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \| STM32F423xx */
ganlikun	0:13413ea9a877	6815
ganlikun	0:13413ea9a877	6816	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	6817	/* Alias word address of MCO1EN bit */
ganlikun	0:13413ea9a877	6818	#define RCC_MCO1EN_BIT_NUMBER 0x8U
ganlikun	0:13413ea9a877	6819	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	6820
ganlikun	0:13413ea9a877	6821	/* Alias word address of MCO2EN bit */
ganlikun	0:13413ea9a877	6822	#define RCC_MCO2EN_BIT_NUMBER 0x9U
ganlikun	0:13413ea9a877	6823	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	6824	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	6825
ganlikun	0:13413ea9a877	6826	#define PLL_TIMEOUT_VALUE 2U /* 2 ms */
ganlikun	0:13413ea9a877	6827	/**
ganlikun	0:13413ea9a877	6828	* @}
ganlikun	0:13413ea9a877	6829	*/
ganlikun	0:13413ea9a877	6830
ganlikun	0:13413ea9a877	6831	/**
ganlikun	0:13413ea9a877	6832	* @}
ganlikun	0:13413ea9a877	6833	*/
ganlikun	0:13413ea9a877	6834
ganlikun	0:13413ea9a877	6835	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	6836	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
ganlikun	0:13413ea9a877	6837	* @{
ganlikun	0:13413ea9a877	6838	*/
ganlikun	0:13413ea9a877	6839	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
ganlikun	0:13413ea9a877	6840	* @{
ganlikun	0:13413ea9a877	6841	*/
ganlikun	0:13413ea9a877	6842	#if defined(STM32F411xE)
ganlikun	0:13413ea9a877	6843	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
ganlikun	0:13413ea9a877	6844	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
ganlikun	0:13413ea9a877	6845	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
ganlikun	0:13413ea9a877	6846	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
ganlikun	0:13413ea9a877	6847	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
ganlikun	0:13413ea9a877	6848	STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6849	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
ganlikun	0:13413ea9a877	6850	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
ganlikun	0:13413ea9a877	6851	#endif /* STM32F411xE */
ganlikun	0:13413ea9a877	6852
ganlikun	0:13413ea9a877	6853	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
ganlikun	0:13413ea9a877	6854	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
ganlikun	0:13413ea9a877	6855	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	6856
ganlikun	0:13413ea9a877	6857	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
ganlikun	0:13413ea9a877	6858	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
ganlikun	0:13413ea9a877	6859	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
ganlikun	0:13413ea9a877	6860
ganlikun	0:13413ea9a877	6861	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
ganlikun	0:13413ea9a877	6862	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
ganlikun	0:13413ea9a877	6863	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
ganlikun	0:13413ea9a877	6864
ganlikun	0:13413ea9a877	6865	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	6866	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
ganlikun	0:13413ea9a877	6867	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	6868
ganlikun	0:13413ea9a877	6869	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	6870	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
ganlikun	0:13413ea9a877	6871	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	6872
ganlikun	0:13413ea9a877	6873	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6874	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
ganlikun	0:13413ea9a877	6875	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6876
ganlikun	0:13413ea9a877	6877	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
ganlikun	0:13413ea9a877	6878	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
ganlikun	0:13413ea9a877	6879	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
ganlikun	0:13413ea9a877	6880
ganlikun	0:13413ea9a877	6881	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6882	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
ganlikun	0:13413ea9a877	6883	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6884
ganlikun	0:13413ea9a877	6885	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
ganlikun	0:13413ea9a877	6886
ganlikun	0:13413ea9a877	6887	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	6888	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6889	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
ganlikun	0:13413ea9a877	6890
ganlikun	0:13413ea9a877	6891	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
ganlikun	0:13413ea9a877	6892
ganlikun	0:13413ea9a877	6893	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
ganlikun	0:13413ea9a877	6894
ganlikun	0:13413ea9a877	6895	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
ganlikun	0:13413ea9a877	6896
ganlikun	0:13413ea9a877	6897	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
ganlikun	0:13413ea9a877	6898
ganlikun	0:13413ea9a877	6899	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
ganlikun	0:13413ea9a877	6900
ganlikun	0:13413ea9a877	6901	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
ganlikun	0:13413ea9a877	6902	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
ganlikun	0:13413ea9a877	6903	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
ganlikun	0:13413ea9a877	6904	((VALUE) == RCC_PLLSAIDIVR_16))
ganlikun	0:13413ea9a877	6905	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	6906
ganlikun	0:13413ea9a877	6907	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	6908	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	6909	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
ganlikun	0:13413ea9a877	6910
ganlikun	0:13413ea9a877	6911	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
ganlikun	0:13413ea9a877	6912	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
ganlikun	0:13413ea9a877	6913	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	6914
ganlikun	0:13413ea9a877	6915	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	6916	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
ganlikun	0:13413ea9a877	6917
ganlikun	0:13413ea9a877	6918	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
ganlikun	0:13413ea9a877	6919	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
ganlikun	0:13413ea9a877	6920
ganlikun	0:13413ea9a877	6921	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
ganlikun	0:13413ea9a877	6922	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
ganlikun	0:13413ea9a877	6923	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
ganlikun	0:13413ea9a877	6924
ganlikun	0:13413ea9a877	6925	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
ganlikun	0:13413ea9a877	6926	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
ganlikun	0:13413ea9a877	6927	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
ganlikun	0:13413ea9a877	6928	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
ganlikun	0:13413ea9a877	6929
ganlikun	0:13413ea9a877	6930	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	6931	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
ganlikun	0:13413ea9a877	6932	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	6933	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	6934
ganlikun	0:13413ea9a877	6935	#if defined(STM32F446xx)
ganlikun	0:13413ea9a877	6936	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
ganlikun	0:13413ea9a877	6937
ganlikun	0:13413ea9a877	6938	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
ganlikun	0:13413ea9a877	6939	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
ganlikun	0:13413ea9a877	6940	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
ganlikun	0:13413ea9a877	6941	((VALUE) == RCC_PLLI2SP_DIV8))
ganlikun	0:13413ea9a877	6942
ganlikun	0:13413ea9a877	6943	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
ganlikun	0:13413ea9a877	6944
ganlikun	0:13413ea9a877	6945	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
ganlikun	0:13413ea9a877	6946	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
ganlikun	0:13413ea9a877	6947	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
ganlikun	0:13413ea9a877	6948	((VALUE) == RCC_PLLSAIP_DIV8))
ganlikun	0:13413ea9a877	6949
ganlikun	0:13413ea9a877	6950	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
ganlikun	0:13413ea9a877	6951	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
ganlikun	0:13413ea9a877	6952	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	6953	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
ganlikun	0:13413ea9a877	6954
ganlikun	0:13413ea9a877	6955	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
ganlikun	0:13413ea9a877	6956	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
ganlikun	0:13413ea9a877	6957	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	6958	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	6959
ganlikun	0:13413ea9a877	6960	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
ganlikun	0:13413ea9a877	6961	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
ganlikun	0:13413ea9a877	6962	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	6963	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	6964
ganlikun	0:13413ea9a877	6965	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
ganlikun	0:13413ea9a877	6966	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
ganlikun	0:13413ea9a877	6967	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	6968	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	6969
ganlikun	0:13413ea9a877	6970	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
ganlikun	0:13413ea9a877	6971	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
ganlikun	0:13413ea9a877	6972	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
ganlikun	0:13413ea9a877	6973
ganlikun	0:13413ea9a877	6974	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
ganlikun	0:13413ea9a877	6975	((SOURCE) == RCC_CECCLKSOURCE_LSE))
ganlikun	0:13413ea9a877	6976
ganlikun	0:13413ea9a877	6977	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
ganlikun	0:13413ea9a877	6978	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
ganlikun	0:13413ea9a877	6979
ganlikun	0:13413ea9a877	6980	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
ganlikun	0:13413ea9a877	6981	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
ganlikun	0:13413ea9a877	6982
ganlikun	0:13413ea9a877	6983	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	6984	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
ganlikun	0:13413ea9a877	6985	#endif /* STM32F446xx */
ganlikun	0:13413ea9a877	6986
ganlikun	0:13413ea9a877	6987	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	6988	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
ganlikun	0:13413ea9a877	6989
ganlikun	0:13413ea9a877	6990	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
ganlikun	0:13413ea9a877	6991	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
ganlikun	0:13413ea9a877	6992	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
ganlikun	0:13413ea9a877	6993	((VALUE) == RCC_PLLSAIP_DIV8))
ganlikun	0:13413ea9a877	6994
ganlikun	0:13413ea9a877	6995	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
ganlikun	0:13413ea9a877	6996	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
ganlikun	0:13413ea9a877	6997
ganlikun	0:13413ea9a877	6998	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
ganlikun	0:13413ea9a877	6999	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
ganlikun	0:13413ea9a877	7000
ganlikun	0:13413ea9a877	7001	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	7002	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
ganlikun	0:13413ea9a877	7003
ganlikun	0:13413ea9a877	7004	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
ganlikun	0:13413ea9a877	7005	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
ganlikun	0:13413ea9a877	7006	#endif /* STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	7007
ganlikun	0:13413ea9a877	7008	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
ganlikun	0:13413ea9a877	7009	defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	7010	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
ganlikun	0:13413ea9a877	7011
ganlikun	0:13413ea9a877	7012	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
ganlikun	0:13413ea9a877	7013
ganlikun	0:13413ea9a877	7014	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
ganlikun	0:13413ea9a877	7015	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
ganlikun	0:13413ea9a877	7016
ganlikun	0:13413ea9a877	7017	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
ganlikun	0:13413ea9a877	7018	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
ganlikun	0:13413ea9a877	7019	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	7020	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	7021
ganlikun	0:13413ea9a877	7022	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
ganlikun	0:13413ea9a877	7023	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
ganlikun	0:13413ea9a877	7024	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	7025	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	7026
ganlikun	0:13413ea9a877	7027	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
ganlikun	0:13413ea9a877	7028	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
ganlikun	0:13413ea9a877	7029	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
ganlikun	0:13413ea9a877	7030
ganlikun	0:13413ea9a877	7031	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
ganlikun	0:13413ea9a877	7032	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
ganlikun	0:13413ea9a877	7033
ganlikun	0:13413ea9a877	7034	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
ganlikun	0:13413ea9a877	7035	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
ganlikun	0:13413ea9a877	7036
ganlikun	0:13413ea9a877	7037	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) \|\| \
ganlikun	0:13413ea9a877	7038	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
ganlikun	0:13413ea9a877	7039
ganlikun	0:13413ea9a877	7040	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) \|\| \
ganlikun	0:13413ea9a877	7041	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
ganlikun	0:13413ea9a877	7042
ganlikun	0:13413ea9a877	7043	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	7044	#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) \|\| \
ganlikun	0:13413ea9a877	7045	((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
ganlikun	0:13413ea9a877	7046
ganlikun	0:13413ea9a877	7047	#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) \|\| \
ganlikun	0:13413ea9a877	7048	((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
ganlikun	0:13413ea9a877	7049
ganlikun	0:13413ea9a877	7050	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
ganlikun	0:13413ea9a877	7051	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
ganlikun	0:13413ea9a877	7052	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
ganlikun	0:13413ea9a877	7053	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
ganlikun	0:13413ea9a877	7054
ganlikun	0:13413ea9a877	7055	#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) \|\|\
ganlikun	0:13413ea9a877	7056	((SOURCE) == RCC_SAIACLKSOURCE_EXT) \|\|\
ganlikun	0:13413ea9a877	7057	((SOURCE) == RCC_SAIACLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	7058	((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	7059
ganlikun	0:13413ea9a877	7060	#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) \|\|\
ganlikun	0:13413ea9a877	7061	((SOURCE) == RCC_SAIBCLKSOURCE_EXT) \|\|\
ganlikun	0:13413ea9a877	7062	((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) \|\|\
ganlikun	0:13413ea9a877	7063	((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
ganlikun	0:13413ea9a877	7064
ganlikun	0:13413ea9a877	7065	#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
ganlikun	0:13413ea9a877	7066
ganlikun	0:13413ea9a877	7067	#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
ganlikun	0:13413ea9a877	7068
ganlikun	0:13413ea9a877	7069	#endif /* STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	7070	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	7071
ganlikun	0:13413ea9a877	7072	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
ganlikun	0:13413ea9a877	7073	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
ganlikun	0:13413ea9a877	7074	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
ganlikun	0:13413ea9a877	7075	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	7076	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	7077
ganlikun	0:13413ea9a877	7078	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
ganlikun	0:13413ea9a877	7079	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
ganlikun	0:13413ea9a877	7080
ganlikun	0:13413ea9a877	7081	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
ganlikun	0:13413ea9a877	7082	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
ganlikun	0:13413ea9a877	7083	STM32F412Rx */
ganlikun	0:13413ea9a877	7084
ganlikun	0:13413ea9a877	7085	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
ganlikun	0:13413ea9a877	7086	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
ganlikun	0:13413ea9a877	7087	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
ganlikun	0:13413ea9a877	7088	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
ganlikun	0:13413ea9a877	7089	/**
ganlikun	0:13413ea9a877	7090	* @}
ganlikun	0:13413ea9a877	7091	*/
ganlikun	0:13413ea9a877	7092
ganlikun	0:13413ea9a877	7093	/**
ganlikun	0:13413ea9a877	7094	* @}
ganlikun	0:13413ea9a877	7095	*/
ganlikun	0:13413ea9a877	7096
ganlikun	0:13413ea9a877	7097	/**
ganlikun	0:13413ea9a877	7098	* @}
ganlikun	0:13413ea9a877	7099	*/
ganlikun	0:13413ea9a877	7100
ganlikun	0:13413ea9a877	7101	/**
ganlikun	0:13413ea9a877	7102	* @}
ganlikun	0:13413ea9a877	7103	*/
ganlikun	0:13413ea9a877	7104	#ifdef __cplusplus
ganlikun	0:13413ea9a877	7105	}
ganlikun	0:13413ea9a877	7106	#endif
ganlikun	0:13413ea9a877	7107
ganlikun	0:13413ea9a877	7108	#endif /* __STM32F4xx_HAL_RCC_EX_H */
ganlikun	0:13413ea9a877	7109
ganlikun	0:13413ea9a877	7110	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	7111

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@0:13413ea9a877, 2022-06-12 (annotated)

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