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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_hal_rcc.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of RCC HAL module.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37
ganlikun	0:13413ea9a877	38	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	39	#ifndef __STM32F4xx_HAL_RCC_H
ganlikun	0:13413ea9a877	40	#define __STM32F4xx_HAL_RCC_H
ganlikun	0:13413ea9a877	41
ganlikun	0:13413ea9a877	42	#ifdef __cplusplus
ganlikun	0:13413ea9a877	43	extern "C" {
ganlikun	0:13413ea9a877	44	#endif
ganlikun	0:13413ea9a877	45
ganlikun	0:13413ea9a877	46	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	47	#include "stm32f4xx_hal_def.h"
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	/* Include RCC HAL Extended module */
ganlikun	0:13413ea9a877	50	/* (include on top of file since RCC structures are defined in extended file) */
ganlikun	0:13413ea9a877	51	#include "stm32f4xx_hal_rcc_ex.h"
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	/** @addtogroup STM32F4xx_HAL_Driver
ganlikun	0:13413ea9a877	54	* @{
ganlikun	0:13413ea9a877	55	*/
ganlikun	0:13413ea9a877	56
ganlikun	0:13413ea9a877	57	/** @addtogroup RCC
ganlikun	0:13413ea9a877	58	* @{
ganlikun	0:13413ea9a877	59	*/
ganlikun	0:13413ea9a877	60
ganlikun	0:13413ea9a877	61	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	62	/** @defgroup RCC_Exported_Types RCC Exported Types
ganlikun	0:13413ea9a877	63	* @{
ganlikun	0:13413ea9a877	64	*/
ganlikun	0:13413ea9a877	65
ganlikun	0:13413ea9a877	66	/**
ganlikun	0:13413ea9a877	67	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
ganlikun	0:13413ea9a877	68	*/
ganlikun	0:13413ea9a877	69	typedef struct
ganlikun	0:13413ea9a877	70	{
ganlikun	0:13413ea9a877	71	uint32_t OscillatorType; /*!< The oscillators to be configured.
ganlikun	0:13413ea9a877	72	This parameter can be a value of @ref RCC_Oscillator_Type */
ganlikun	0:13413ea9a877	73
ganlikun	0:13413ea9a877	74	uint32_t HSEState; /*!< The new state of the HSE.
ganlikun	0:13413ea9a877	75	This parameter can be a value of @ref RCC_HSE_Config */
ganlikun	0:13413ea9a877	76
ganlikun	0:13413ea9a877	77	uint32_t LSEState; /*!< The new state of the LSE.
ganlikun	0:13413ea9a877	78	This parameter can be a value of @ref RCC_LSE_Config */
ganlikun	0:13413ea9a877	79
ganlikun	0:13413ea9a877	80	uint32_t HSIState; /*!< The new state of the HSI.
ganlikun	0:13413ea9a877	81	This parameter can be a value of @ref RCC_HSI_Config */
ganlikun	0:13413ea9a877	82
ganlikun	0:13413ea9a877	83	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
ganlikun	0:13413ea9a877	84	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
ganlikun	0:13413ea9a877	85
ganlikun	0:13413ea9a877	86	uint32_t LSIState; /*!< The new state of the LSI.
ganlikun	0:13413ea9a877	87	This parameter can be a value of @ref RCC_LSI_Config */
ganlikun	0:13413ea9a877	88
ganlikun	0:13413ea9a877	89	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
ganlikun	0:13413ea9a877	90	}RCC_OscInitTypeDef;
ganlikun	0:13413ea9a877	91
ganlikun	0:13413ea9a877	92	/**
ganlikun	0:13413ea9a877	93	* @brief RCC System, AHB and APB busses clock configuration structure definition
ganlikun	0:13413ea9a877	94	*/
ganlikun	0:13413ea9a877	95	typedef struct
ganlikun	0:13413ea9a877	96	{
ganlikun	0:13413ea9a877	97	uint32_t ClockType; /*!< The clock to be configured.
ganlikun	0:13413ea9a877	98	This parameter can be a value of @ref RCC_System_Clock_Type */
ganlikun	0:13413ea9a877	99
ganlikun	0:13413ea9a877	100	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
ganlikun	0:13413ea9a877	101	This parameter can be a value of @ref RCC_System_Clock_Source */
ganlikun	0:13413ea9a877	102
ganlikun	0:13413ea9a877	103	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
ganlikun	0:13413ea9a877	104	This parameter can be a value of @ref RCC_AHB_Clock_Source */
ganlikun	0:13413ea9a877	105
ganlikun	0:13413ea9a877	106	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
ganlikun	0:13413ea9a877	107	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
ganlikun	0:13413ea9a877	108
ganlikun	0:13413ea9a877	109	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
ganlikun	0:13413ea9a877	110	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
ganlikun	0:13413ea9a877	111
ganlikun	0:13413ea9a877	112	}RCC_ClkInitTypeDef;
ganlikun	0:13413ea9a877	113
ganlikun	0:13413ea9a877	114	/**
ganlikun	0:13413ea9a877	115	* @}
ganlikun	0:13413ea9a877	116	*/
ganlikun	0:13413ea9a877	117
ganlikun	0:13413ea9a877	118	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	119	/** @defgroup RCC_Exported_Constants RCC Exported Constants
ganlikun	0:13413ea9a877	120	* @{
ganlikun	0:13413ea9a877	121	*/
ganlikun	0:13413ea9a877	122
ganlikun	0:13413ea9a877	123	/** @defgroup RCC_Oscillator_Type Oscillator Type
ganlikun	0:13413ea9a877	124	* @{
ganlikun	0:13413ea9a877	125	*/
ganlikun	0:13413ea9a877	126	#define RCC_OSCILLATORTYPE_NONE 0x00000000U
ganlikun	0:13413ea9a877	127	#define RCC_OSCILLATORTYPE_HSE 0x00000001U
ganlikun	0:13413ea9a877	128	#define RCC_OSCILLATORTYPE_HSI 0x00000002U
ganlikun	0:13413ea9a877	129	#define RCC_OSCILLATORTYPE_LSE 0x00000004U
ganlikun	0:13413ea9a877	130	#define RCC_OSCILLATORTYPE_LSI 0x00000008U
ganlikun	0:13413ea9a877	131	/**
ganlikun	0:13413ea9a877	132	* @}
ganlikun	0:13413ea9a877	133	*/
ganlikun	0:13413ea9a877	134
ganlikun	0:13413ea9a877	135	/** @defgroup RCC_HSE_Config HSE Config
ganlikun	0:13413ea9a877	136	* @{
ganlikun	0:13413ea9a877	137	*/
ganlikun	0:13413ea9a877	138	#define RCC_HSE_OFF 0x00000000U
ganlikun	0:13413ea9a877	139	#define RCC_HSE_ON RCC_CR_HSEON
ganlikun	0:13413ea9a877	140	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
ganlikun	0:13413ea9a877	141	/**
ganlikun	0:13413ea9a877	142	* @}
ganlikun	0:13413ea9a877	143	*/
ganlikun	0:13413ea9a877	144
ganlikun	0:13413ea9a877	145	/** @defgroup RCC_LSE_Config LSE Config
ganlikun	0:13413ea9a877	146	* @{
ganlikun	0:13413ea9a877	147	*/
ganlikun	0:13413ea9a877	148	#define RCC_LSE_OFF 0x00000000U
ganlikun	0:13413ea9a877	149	#define RCC_LSE_ON RCC_BDCR_LSEON
ganlikun	0:13413ea9a877	150	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON))
ganlikun	0:13413ea9a877	151	/**
ganlikun	0:13413ea9a877	152	* @}
ganlikun	0:13413ea9a877	153	*/
ganlikun	0:13413ea9a877	154
ganlikun	0:13413ea9a877	155	/** @defgroup RCC_HSI_Config HSI Config
ganlikun	0:13413ea9a877	156	* @{
ganlikun	0:13413ea9a877	157	*/
ganlikun	0:13413ea9a877	158	#define RCC_HSI_OFF ((uint8_t)0x00)
ganlikun	0:13413ea9a877	159	#define RCC_HSI_ON ((uint8_t)0x01)
ganlikun	0:13413ea9a877	160
ganlikun	0:13413ea9a877	161	#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
ganlikun	0:13413ea9a877	162	/**
ganlikun	0:13413ea9a877	163	* @}
ganlikun	0:13413ea9a877	164	*/
ganlikun	0:13413ea9a877	165
ganlikun	0:13413ea9a877	166	/** @defgroup RCC_LSI_Config LSI Config
ganlikun	0:13413ea9a877	167	* @{
ganlikun	0:13413ea9a877	168	*/
ganlikun	0:13413ea9a877	169	#define RCC_LSI_OFF ((uint8_t)0x00)
ganlikun	0:13413ea9a877	170	#define RCC_LSI_ON ((uint8_t)0x01)
ganlikun	0:13413ea9a877	171	/**
ganlikun	0:13413ea9a877	172	* @}
ganlikun	0:13413ea9a877	173	*/
ganlikun	0:13413ea9a877	174
ganlikun	0:13413ea9a877	175	/** @defgroup RCC_PLL_Config PLL Config
ganlikun	0:13413ea9a877	176	* @{
ganlikun	0:13413ea9a877	177	*/
ganlikun	0:13413ea9a877	178	#define RCC_PLL_NONE ((uint8_t)0x00)
ganlikun	0:13413ea9a877	179	#define RCC_PLL_OFF ((uint8_t)0x01)
ganlikun	0:13413ea9a877	180	#define RCC_PLL_ON ((uint8_t)0x02)
ganlikun	0:13413ea9a877	181	/**
ganlikun	0:13413ea9a877	182	* @}
ganlikun	0:13413ea9a877	183	*/
ganlikun	0:13413ea9a877	184
ganlikun	0:13413ea9a877	185	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
ganlikun	0:13413ea9a877	186	* @{
ganlikun	0:13413ea9a877	187	*/
ganlikun	0:13413ea9a877	188	#define RCC_PLLP_DIV2 0x00000002U
ganlikun	0:13413ea9a877	189	#define RCC_PLLP_DIV4 0x00000004U
ganlikun	0:13413ea9a877	190	#define RCC_PLLP_DIV6 0x00000006U
ganlikun	0:13413ea9a877	191	#define RCC_PLLP_DIV8 0x00000008U
ganlikun	0:13413ea9a877	192	/**
ganlikun	0:13413ea9a877	193	* @}
ganlikun	0:13413ea9a877	194	*/
ganlikun	0:13413ea9a877	195
ganlikun	0:13413ea9a877	196	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
ganlikun	0:13413ea9a877	197	* @{
ganlikun	0:13413ea9a877	198	*/
ganlikun	0:13413ea9a877	199	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
ganlikun	0:13413ea9a877	200	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
ganlikun	0:13413ea9a877	201	/**
ganlikun	0:13413ea9a877	202	* @}
ganlikun	0:13413ea9a877	203	*/
ganlikun	0:13413ea9a877	204
ganlikun	0:13413ea9a877	205	/** @defgroup RCC_System_Clock_Type System Clock Type
ganlikun	0:13413ea9a877	206	* @{
ganlikun	0:13413ea9a877	207	*/
ganlikun	0:13413ea9a877	208	#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
ganlikun	0:13413ea9a877	209	#define RCC_CLOCKTYPE_HCLK 0x00000002U
ganlikun	0:13413ea9a877	210	#define RCC_CLOCKTYPE_PCLK1 0x00000004U
ganlikun	0:13413ea9a877	211	#define RCC_CLOCKTYPE_PCLK2 0x00000008U
ganlikun	0:13413ea9a877	212	/**
ganlikun	0:13413ea9a877	213	* @}
ganlikun	0:13413ea9a877	214	*/
ganlikun	0:13413ea9a877	215
ganlikun	0:13413ea9a877	216	/** @defgroup RCC_System_Clock_Source System Clock Source
ganlikun	0:13413ea9a877	217	* @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
ganlikun	0:13413ea9a877	218	* STM32F446xx devices.
ganlikun	0:13413ea9a877	219	* @{
ganlikun	0:13413ea9a877	220	*/
ganlikun	0:13413ea9a877	221	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
ganlikun	0:13413ea9a877	222	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
ganlikun	0:13413ea9a877	223	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
ganlikun	0:13413ea9a877	224	#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1))
ganlikun	0:13413ea9a877	225	/**
ganlikun	0:13413ea9a877	226	* @}
ganlikun	0:13413ea9a877	227	*/
ganlikun	0:13413ea9a877	228
ganlikun	0:13413ea9a877	229	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
ganlikun	0:13413ea9a877	230	* @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
ganlikun	0:13413ea9a877	231	* STM32F446xx devices.
ganlikun	0:13413ea9a877	232	* @{
ganlikun	0:13413ea9a877	233	*/
ganlikun	0:13413ea9a877	234	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
ganlikun	0:13413ea9a877	235	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
ganlikun	0:13413ea9a877	236	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
ganlikun	0:13413ea9a877	237	#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 \| RCC_CFGR_SWS_1)) /!< PLLR used as system clock /
ganlikun	0:13413ea9a877	238	/**
ganlikun	0:13413ea9a877	239	* @}
ganlikun	0:13413ea9a877	240	*/
ganlikun	0:13413ea9a877	241
ganlikun	0:13413ea9a877	242	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
ganlikun	0:13413ea9a877	243	* @{
ganlikun	0:13413ea9a877	244	*/
ganlikun	0:13413ea9a877	245	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
ganlikun	0:13413ea9a877	246	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
ganlikun	0:13413ea9a877	247	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
ganlikun	0:13413ea9a877	248	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
ganlikun	0:13413ea9a877	249	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
ganlikun	0:13413ea9a877	250	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
ganlikun	0:13413ea9a877	251	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
ganlikun	0:13413ea9a877	252	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
ganlikun	0:13413ea9a877	253	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
ganlikun	0:13413ea9a877	254	/**
ganlikun	0:13413ea9a877	255	* @}
ganlikun	0:13413ea9a877	256	*/
ganlikun	0:13413ea9a877	257
ganlikun	0:13413ea9a877	258	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
ganlikun	0:13413ea9a877	259	* @{
ganlikun	0:13413ea9a877	260	*/
ganlikun	0:13413ea9a877	261	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
ganlikun	0:13413ea9a877	262	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
ganlikun	0:13413ea9a877	263	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
ganlikun	0:13413ea9a877	264	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
ganlikun	0:13413ea9a877	265	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
ganlikun	0:13413ea9a877	266	/**
ganlikun	0:13413ea9a877	267	* @}
ganlikun	0:13413ea9a877	268	*/
ganlikun	0:13413ea9a877	269
ganlikun	0:13413ea9a877	270	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
ganlikun	0:13413ea9a877	271	* @{
ganlikun	0:13413ea9a877	272	*/
ganlikun	0:13413ea9a877	273	#define RCC_RTCCLKSOURCE_LSE 0x00000100U
ganlikun	0:13413ea9a877	274	#define RCC_RTCCLKSOURCE_LSI 0x00000200U
ganlikun	0:13413ea9a877	275	#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
ganlikun	0:13413ea9a877	276	#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
ganlikun	0:13413ea9a877	277	#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
ganlikun	0:13413ea9a877	278	#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
ganlikun	0:13413ea9a877	279	#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
ganlikun	0:13413ea9a877	280	#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
ganlikun	0:13413ea9a877	281	#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
ganlikun	0:13413ea9a877	282	#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
ganlikun	0:13413ea9a877	283	#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
ganlikun	0:13413ea9a877	284	#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
ganlikun	0:13413ea9a877	285	#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
ganlikun	0:13413ea9a877	286	#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
ganlikun	0:13413ea9a877	287	#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
ganlikun	0:13413ea9a877	288	#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
ganlikun	0:13413ea9a877	289	#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
ganlikun	0:13413ea9a877	290	#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
ganlikun	0:13413ea9a877	291	#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
ganlikun	0:13413ea9a877	292	#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
ganlikun	0:13413ea9a877	293	#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
ganlikun	0:13413ea9a877	294	#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
ganlikun	0:13413ea9a877	295	#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
ganlikun	0:13413ea9a877	296	#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
ganlikun	0:13413ea9a877	297	#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
ganlikun	0:13413ea9a877	298	#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
ganlikun	0:13413ea9a877	299	#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
ganlikun	0:13413ea9a877	300	#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
ganlikun	0:13413ea9a877	301	#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
ganlikun	0:13413ea9a877	302	#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
ganlikun	0:13413ea9a877	303	#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
ganlikun	0:13413ea9a877	304	#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
ganlikun	0:13413ea9a877	305	/**
ganlikun	0:13413ea9a877	306	* @}
ganlikun	0:13413ea9a877	307	*/
ganlikun	0:13413ea9a877	308
ganlikun	0:13413ea9a877	309	/** @defgroup RCC_MCO_Index MCO Index
ganlikun	0:13413ea9a877	310	* @{
ganlikun	0:13413ea9a877	311	*/
ganlikun	0:13413ea9a877	312	#define RCC_MCO1 0x00000000U
ganlikun	0:13413ea9a877	313	#define RCC_MCO2 0x00000001U
ganlikun	0:13413ea9a877	314	/**
ganlikun	0:13413ea9a877	315	* @}
ganlikun	0:13413ea9a877	316	*/
ganlikun	0:13413ea9a877	317
ganlikun	0:13413ea9a877	318	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
ganlikun	0:13413ea9a877	319	* @{
ganlikun	0:13413ea9a877	320	*/
ganlikun	0:13413ea9a877	321	#define RCC_MCO1SOURCE_HSI 0x00000000U
ganlikun	0:13413ea9a877	322	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
ganlikun	0:13413ea9a877	323	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
ganlikun	0:13413ea9a877	324	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
ganlikun	0:13413ea9a877	325	/**
ganlikun	0:13413ea9a877	326	* @}
ganlikun	0:13413ea9a877	327	*/
ganlikun	0:13413ea9a877	328
ganlikun	0:13413ea9a877	329	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
ganlikun	0:13413ea9a877	330	* @{
ganlikun	0:13413ea9a877	331	*/
ganlikun	0:13413ea9a877	332	#define RCC_MCODIV_1 0x00000000U
ganlikun	0:13413ea9a877	333	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
ganlikun	0:13413ea9a877	334	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
ganlikun	0:13413ea9a877	335	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
ganlikun	0:13413ea9a877	336	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
ganlikun	0:13413ea9a877	337	/**
ganlikun	0:13413ea9a877	338	* @}
ganlikun	0:13413ea9a877	339	*/
ganlikun	0:13413ea9a877	340
ganlikun	0:13413ea9a877	341	/** @defgroup RCC_Interrupt Interrupts
ganlikun	0:13413ea9a877	342	* @{
ganlikun	0:13413ea9a877	343	*/
ganlikun	0:13413ea9a877	344	#define RCC_IT_LSIRDY ((uint8_t)0x01)
ganlikun	0:13413ea9a877	345	#define RCC_IT_LSERDY ((uint8_t)0x02)
ganlikun	0:13413ea9a877	346	#define RCC_IT_HSIRDY ((uint8_t)0x04)
ganlikun	0:13413ea9a877	347	#define RCC_IT_HSERDY ((uint8_t)0x08)
ganlikun	0:13413ea9a877	348	#define RCC_IT_PLLRDY ((uint8_t)0x10)
ganlikun	0:13413ea9a877	349	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
ganlikun	0:13413ea9a877	350	#define RCC_IT_CSS ((uint8_t)0x80)
ganlikun	0:13413ea9a877	351	/**
ganlikun	0:13413ea9a877	352	* @}
ganlikun	0:13413ea9a877	353	*/
ganlikun	0:13413ea9a877	354
ganlikun	0:13413ea9a877	355	/** @defgroup RCC_Flag Flags
ganlikun	0:13413ea9a877	356	* Elements values convention: 0XXYYYYYb
ganlikun	0:13413ea9a877	357	* - YYYYY : Flag position in the register
ganlikun	0:13413ea9a877	358	* - 0XX : Register index
ganlikun	0:13413ea9a877	359	* - 01: CR register
ganlikun	0:13413ea9a877	360	* - 10: BDCR register
ganlikun	0:13413ea9a877	361	* - 11: CSR register
ganlikun	0:13413ea9a877	362	* @{
ganlikun	0:13413ea9a877	363	*/
ganlikun	0:13413ea9a877	364	/* Flags in the CR register */
ganlikun	0:13413ea9a877	365	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
ganlikun	0:13413ea9a877	366	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
ganlikun	0:13413ea9a877	367	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
ganlikun	0:13413ea9a877	368	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
ganlikun	0:13413ea9a877	369
ganlikun	0:13413ea9a877	370	/* Flags in the BDCR register */
ganlikun	0:13413ea9a877	371	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
ganlikun	0:13413ea9a877	372
ganlikun	0:13413ea9a877	373	/* Flags in the CSR register */
ganlikun	0:13413ea9a877	374	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
ganlikun	0:13413ea9a877	375	#define RCC_FLAG_BORRST ((uint8_t)0x79)
ganlikun	0:13413ea9a877	376	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
ganlikun	0:13413ea9a877	377	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
ganlikun	0:13413ea9a877	378	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
ganlikun	0:13413ea9a877	379	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
ganlikun	0:13413ea9a877	380	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
ganlikun	0:13413ea9a877	381	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
ganlikun	0:13413ea9a877	382	/**
ganlikun	0:13413ea9a877	383	* @}
ganlikun	0:13413ea9a877	384	*/
ganlikun	0:13413ea9a877	385
ganlikun	0:13413ea9a877	386	/**
ganlikun	0:13413ea9a877	387	* @}
ganlikun	0:13413ea9a877	388	*/
ganlikun	0:13413ea9a877	389
ganlikun	0:13413ea9a877	390	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	391	/** @defgroup RCC_Exported_Macros RCC Exported Macros
ganlikun	0:13413ea9a877	392	* @{
ganlikun	0:13413ea9a877	393	*/
ganlikun	0:13413ea9a877	394
ganlikun	0:13413ea9a877	395	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	396	* @brief Enable or disable the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	397	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	398	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	399	* using it.
ganlikun	0:13413ea9a877	400	* @{
ganlikun	0:13413ea9a877	401	*/
ganlikun	0:13413ea9a877	402	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	403	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	404	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
ganlikun	0:13413ea9a877	405	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	406	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
ganlikun	0:13413ea9a877	407	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	408	} while(0U)
ganlikun	0:13413ea9a877	409	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	410	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	411	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
ganlikun	0:13413ea9a877	412	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	413	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
ganlikun	0:13413ea9a877	414	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	415	} while(0U)
ganlikun	0:13413ea9a877	416	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	417	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	418	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
ganlikun	0:13413ea9a877	419	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	420	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
ganlikun	0:13413ea9a877	421	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	422	} while(0U)
ganlikun	0:13413ea9a877	423	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	424	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	425	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
ganlikun	0:13413ea9a877	426	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	427	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
ganlikun	0:13413ea9a877	428	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	429	} while(0U)
ganlikun	0:13413ea9a877	430	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	431	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	432	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
ganlikun	0:13413ea9a877	433	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	434	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
ganlikun	0:13413ea9a877	435	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	436	} while(0U)
ganlikun	0:13413ea9a877	437	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	438	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	439	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
ganlikun	0:13413ea9a877	440	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	441	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
ganlikun	0:13413ea9a877	442	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	443	} while(0U)
ganlikun	0:13413ea9a877	444
ganlikun	0:13413ea9a877	445	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
ganlikun	0:13413ea9a877	446	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
ganlikun	0:13413ea9a877	447	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
ganlikun	0:13413ea9a877	448	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
ganlikun	0:13413ea9a877	449	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
ganlikun	0:13413ea9a877	450	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
ganlikun	0:13413ea9a877	451	/**
ganlikun	0:13413ea9a877	452	* @}
ganlikun	0:13413ea9a877	453	*/
ganlikun	0:13413ea9a877	454
ganlikun	0:13413ea9a877	455	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	456	* @brief Get the enable or disable status of the AHB1 peripheral clock.
ganlikun	0:13413ea9a877	457	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	458	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	459	* using it.
ganlikun	0:13413ea9a877	460	* @{
ganlikun	0:13413ea9a877	461	*/
ganlikun	0:13413ea9a877	462	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
ganlikun	0:13413ea9a877	463	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
ganlikun	0:13413ea9a877	464	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
ganlikun	0:13413ea9a877	465	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
ganlikun	0:13413ea9a877	466	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
ganlikun	0:13413ea9a877	467	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
ganlikun	0:13413ea9a877	468
ganlikun	0:13413ea9a877	469	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
ganlikun	0:13413ea9a877	470	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
ganlikun	0:13413ea9a877	471	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
ganlikun	0:13413ea9a877	472	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
ganlikun	0:13413ea9a877	473	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
ganlikun	0:13413ea9a877	474	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
ganlikun	0:13413ea9a877	475	/**
ganlikun	0:13413ea9a877	476	* @}
ganlikun	0:13413ea9a877	477	*/
ganlikun	0:13413ea9a877	478
ganlikun	0:13413ea9a877	479	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	480	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
ganlikun	0:13413ea9a877	481	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	482	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	483	* using it.
ganlikun	0:13413ea9a877	484	* @{
ganlikun	0:13413ea9a877	485	*/
ganlikun	0:13413ea9a877	486	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	487	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	488	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
ganlikun	0:13413ea9a877	489	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	490	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
ganlikun	0:13413ea9a877	491	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	492	} while(0U)
ganlikun	0:13413ea9a877	493	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	494	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	495	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
ganlikun	0:13413ea9a877	496	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	497	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
ganlikun	0:13413ea9a877	498	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	499	} while(0U)
ganlikun	0:13413ea9a877	500	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	501	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	502	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
ganlikun	0:13413ea9a877	503	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	504	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
ganlikun	0:13413ea9a877	505	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	506	} while(0U)
ganlikun	0:13413ea9a877	507	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	508	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	509	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
ganlikun	0:13413ea9a877	510	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	511	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
ganlikun	0:13413ea9a877	512	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	513	} while(0U)
ganlikun	0:13413ea9a877	514	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	515	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	516	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
ganlikun	0:13413ea9a877	517	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	518	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
ganlikun	0:13413ea9a877	519	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	520	} while(0U)
ganlikun	0:13413ea9a877	521	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	522	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	523	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
ganlikun	0:13413ea9a877	524	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	525	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
ganlikun	0:13413ea9a877	526	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	527	} while(0U)
ganlikun	0:13413ea9a877	528	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	529	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	530	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
ganlikun	0:13413ea9a877	531	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	532	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
ganlikun	0:13413ea9a877	533	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	534	} while(0U)
ganlikun	0:13413ea9a877	535
ganlikun	0:13413ea9a877	536	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
ganlikun	0:13413ea9a877	537	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
ganlikun	0:13413ea9a877	538	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
ganlikun	0:13413ea9a877	539	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
ganlikun	0:13413ea9a877	540	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
ganlikun	0:13413ea9a877	541	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
ganlikun	0:13413ea9a877	542	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
ganlikun	0:13413ea9a877	543	/**
ganlikun	0:13413ea9a877	544	* @}
ganlikun	0:13413ea9a877	545	*/
ganlikun	0:13413ea9a877	546
ganlikun	0:13413ea9a877	547	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	548	* @brief Get the enable or disable status of the APB1 peripheral clock.
ganlikun	0:13413ea9a877	549	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	550	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	551	* using it.
ganlikun	0:13413ea9a877	552	* @{
ganlikun	0:13413ea9a877	553	*/
ganlikun	0:13413ea9a877	554	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
ganlikun	0:13413ea9a877	555	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
ganlikun	0:13413ea9a877	556	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
ganlikun	0:13413ea9a877	557	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
ganlikun	0:13413ea9a877	558	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
ganlikun	0:13413ea9a877	559	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
ganlikun	0:13413ea9a877	560	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
ganlikun	0:13413ea9a877	561
ganlikun	0:13413ea9a877	562	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
ganlikun	0:13413ea9a877	563	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
ganlikun	0:13413ea9a877	564	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
ganlikun	0:13413ea9a877	565	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
ganlikun	0:13413ea9a877	566	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
ganlikun	0:13413ea9a877	567	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
ganlikun	0:13413ea9a877	568	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
ganlikun	0:13413ea9a877	569	/**
ganlikun	0:13413ea9a877	570	* @}
ganlikun	0:13413ea9a877	571	*/
ganlikun	0:13413ea9a877	572
ganlikun	0:13413ea9a877	573	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
ganlikun	0:13413ea9a877	574	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
ganlikun	0:13413ea9a877	575	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	576	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	577	* using it.
ganlikun	0:13413ea9a877	578	* @{
ganlikun	0:13413ea9a877	579	*/
ganlikun	0:13413ea9a877	580	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	581	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	582	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
ganlikun	0:13413ea9a877	583	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	584	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
ganlikun	0:13413ea9a877	585	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	586	} while(0U)
ganlikun	0:13413ea9a877	587	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	588	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	589	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
ganlikun	0:13413ea9a877	590	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	591	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
ganlikun	0:13413ea9a877	592	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	593	} while(0U)
ganlikun	0:13413ea9a877	594	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	595	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	596	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
ganlikun	0:13413ea9a877	597	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	598	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
ganlikun	0:13413ea9a877	599	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	600	} while(0U)
ganlikun	0:13413ea9a877	601	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	602	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	603	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
ganlikun	0:13413ea9a877	604	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	605	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
ganlikun	0:13413ea9a877	606	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	607	} while(0U)
ganlikun	0:13413ea9a877	608	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	609	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	610	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
ganlikun	0:13413ea9a877	611	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	612	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
ganlikun	0:13413ea9a877	613	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	614	} while(0U)
ganlikun	0:13413ea9a877	615	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	616	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	617	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
ganlikun	0:13413ea9a877	618	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	619	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
ganlikun	0:13413ea9a877	620	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	621	} while(0U)
ganlikun	0:13413ea9a877	622	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	623	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	624	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
ganlikun	0:13413ea9a877	625	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	626	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
ganlikun	0:13413ea9a877	627	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	628	} while(0U)
ganlikun	0:13413ea9a877	629	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
ganlikun	0:13413ea9a877	630	__IO uint32_t tmpreg = 0x00U; \
ganlikun	0:13413ea9a877	631	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
ganlikun	0:13413ea9a877	632	/* Delay after an RCC peripheral clock enabling */ \
ganlikun	0:13413ea9a877	633	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
ganlikun	0:13413ea9a877	634	UNUSED(tmpreg); \
ganlikun	0:13413ea9a877	635	} while(0U)
ganlikun	0:13413ea9a877	636
ganlikun	0:13413ea9a877	637	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
ganlikun	0:13413ea9a877	638	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
ganlikun	0:13413ea9a877	639	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
ganlikun	0:13413ea9a877	640	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
ganlikun	0:13413ea9a877	641	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
ganlikun	0:13413ea9a877	642	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
ganlikun	0:13413ea9a877	643	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
ganlikun	0:13413ea9a877	644	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
ganlikun	0:13413ea9a877	645	/**
ganlikun	0:13413ea9a877	646	* @}
ganlikun	0:13413ea9a877	647	*/
ganlikun	0:13413ea9a877	648
ganlikun	0:13413ea9a877	649	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
ganlikun	0:13413ea9a877	650	* @brief Get the enable or disable status of the APB2 peripheral clock.
ganlikun	0:13413ea9a877	651	* @note After reset, the peripheral clock (used for registers read/write access)
ganlikun	0:13413ea9a877	652	* is disabled and the application software has to enable this clock before
ganlikun	0:13413ea9a877	653	* using it.
ganlikun	0:13413ea9a877	654	* @{
ganlikun	0:13413ea9a877	655	*/
ganlikun	0:13413ea9a877	656	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
ganlikun	0:13413ea9a877	657	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
ganlikun	0:13413ea9a877	658	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
ganlikun	0:13413ea9a877	659	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
ganlikun	0:13413ea9a877	660	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
ganlikun	0:13413ea9a877	661	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
ganlikun	0:13413ea9a877	662	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
ganlikun	0:13413ea9a877	663	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
ganlikun	0:13413ea9a877	664
ganlikun	0:13413ea9a877	665	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
ganlikun	0:13413ea9a877	666	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
ganlikun	0:13413ea9a877	667	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
ganlikun	0:13413ea9a877	668	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
ganlikun	0:13413ea9a877	669	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
ganlikun	0:13413ea9a877	670	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
ganlikun	0:13413ea9a877	671	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
ganlikun	0:13413ea9a877	672	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
ganlikun	0:13413ea9a877	673	/**
ganlikun	0:13413ea9a877	674	* @}
ganlikun	0:13413ea9a877	675	*/
ganlikun	0:13413ea9a877	676
ganlikun	0:13413ea9a877	677	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
ganlikun	0:13413ea9a877	678	* @brief Force or release AHB1 peripheral reset.
ganlikun	0:13413ea9a877	679	* @{
ganlikun	0:13413ea9a877	680	*/
ganlikun	0:13413ea9a877	681	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	682	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
ganlikun	0:13413ea9a877	683	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
ganlikun	0:13413ea9a877	684	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
ganlikun	0:13413ea9a877	685	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
ganlikun	0:13413ea9a877	686	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
ganlikun	0:13413ea9a877	687	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
ganlikun	0:13413ea9a877	688
ganlikun	0:13413ea9a877	689	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
ganlikun	0:13413ea9a877	690	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
ganlikun	0:13413ea9a877	691	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
ganlikun	0:13413ea9a877	692	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
ganlikun	0:13413ea9a877	693	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
ganlikun	0:13413ea9a877	694	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
ganlikun	0:13413ea9a877	695	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
ganlikun	0:13413ea9a877	696	/**
ganlikun	0:13413ea9a877	697	* @}
ganlikun	0:13413ea9a877	698	*/
ganlikun	0:13413ea9a877	699
ganlikun	0:13413ea9a877	700	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
ganlikun	0:13413ea9a877	701	* @brief Force or release APB1 peripheral reset.
ganlikun	0:13413ea9a877	702	* @{
ganlikun	0:13413ea9a877	703	*/
ganlikun	0:13413ea9a877	704	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	705	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
ganlikun	0:13413ea9a877	706	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
ganlikun	0:13413ea9a877	707	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
ganlikun	0:13413ea9a877	708	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
ganlikun	0:13413ea9a877	709	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
ganlikun	0:13413ea9a877	710	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
ganlikun	0:13413ea9a877	711	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
ganlikun	0:13413ea9a877	712
ganlikun	0:13413ea9a877	713	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
ganlikun	0:13413ea9a877	714	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
ganlikun	0:13413ea9a877	715	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
ganlikun	0:13413ea9a877	716	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
ganlikun	0:13413ea9a877	717	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
ganlikun	0:13413ea9a877	718	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
ganlikun	0:13413ea9a877	719	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
ganlikun	0:13413ea9a877	720	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
ganlikun	0:13413ea9a877	721	/**
ganlikun	0:13413ea9a877	722	* @}
ganlikun	0:13413ea9a877	723	*/
ganlikun	0:13413ea9a877	724
ganlikun	0:13413ea9a877	725	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
ganlikun	0:13413ea9a877	726	* @brief Force or release APB2 peripheral reset.
ganlikun	0:13413ea9a877	727	* @{
ganlikun	0:13413ea9a877	728	*/
ganlikun	0:13413ea9a877	729	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
ganlikun	0:13413ea9a877	730	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
ganlikun	0:13413ea9a877	731	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
ganlikun	0:13413ea9a877	732	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
ganlikun	0:13413ea9a877	733	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
ganlikun	0:13413ea9a877	734	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
ganlikun	0:13413ea9a877	735	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
ganlikun	0:13413ea9a877	736	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
ganlikun	0:13413ea9a877	737	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
ganlikun	0:13413ea9a877	738
ganlikun	0:13413ea9a877	739	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
ganlikun	0:13413ea9a877	740	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
ganlikun	0:13413ea9a877	741	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
ganlikun	0:13413ea9a877	742	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
ganlikun	0:13413ea9a877	743	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
ganlikun	0:13413ea9a877	744	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
ganlikun	0:13413ea9a877	745	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
ganlikun	0:13413ea9a877	746	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
ganlikun	0:13413ea9a877	747	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
ganlikun	0:13413ea9a877	748	/**
ganlikun	0:13413ea9a877	749	* @}
ganlikun	0:13413ea9a877	750	*/
ganlikun	0:13413ea9a877	751
ganlikun	0:13413ea9a877	752	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	753	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	754	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	755	* power consumption.
ganlikun	0:13413ea9a877	756	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	757	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	758	* @{
ganlikun	0:13413ea9a877	759	*/
ganlikun	0:13413ea9a877	760	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
ganlikun	0:13413ea9a877	761	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
ganlikun	0:13413ea9a877	762	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
ganlikun	0:13413ea9a877	763	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
ganlikun	0:13413ea9a877	764	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
ganlikun	0:13413ea9a877	765	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
ganlikun	0:13413ea9a877	766
ganlikun	0:13413ea9a877	767	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
ganlikun	0:13413ea9a877	768	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
ganlikun	0:13413ea9a877	769	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
ganlikun	0:13413ea9a877	770	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
ganlikun	0:13413ea9a877	771	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
ganlikun	0:13413ea9a877	772	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
ganlikun	0:13413ea9a877	773	/**
ganlikun	0:13413ea9a877	774	* @}
ganlikun	0:13413ea9a877	775	*/
ganlikun	0:13413ea9a877	776
ganlikun	0:13413ea9a877	777	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	778	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	779	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	780	* power consumption.
ganlikun	0:13413ea9a877	781	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	782	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	783	* @{
ganlikun	0:13413ea9a877	784	*/
ganlikun	0:13413ea9a877	785	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
ganlikun	0:13413ea9a877	786	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
ganlikun	0:13413ea9a877	787	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
ganlikun	0:13413ea9a877	788	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
ganlikun	0:13413ea9a877	789	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
ganlikun	0:13413ea9a877	790	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
ganlikun	0:13413ea9a877	791	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
ganlikun	0:13413ea9a877	792
ganlikun	0:13413ea9a877	793	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
ganlikun	0:13413ea9a877	794	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
ganlikun	0:13413ea9a877	795	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
ganlikun	0:13413ea9a877	796	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
ganlikun	0:13413ea9a877	797	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
ganlikun	0:13413ea9a877	798	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
ganlikun	0:13413ea9a877	799	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
ganlikun	0:13413ea9a877	800	/**
ganlikun	0:13413ea9a877	801	* @}
ganlikun	0:13413ea9a877	802	*/
ganlikun	0:13413ea9a877	803
ganlikun	0:13413ea9a877	804	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
ganlikun	0:13413ea9a877	805	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
ganlikun	0:13413ea9a877	806	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
ganlikun	0:13413ea9a877	807	* power consumption.
ganlikun	0:13413ea9a877	808	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
ganlikun	0:13413ea9a877	809	* @note By default, all peripheral clocks are enabled during SLEEP mode.
ganlikun	0:13413ea9a877	810	* @{
ganlikun	0:13413ea9a877	811	*/
ganlikun	0:13413ea9a877	812	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
ganlikun	0:13413ea9a877	813	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
ganlikun	0:13413ea9a877	814	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
ganlikun	0:13413ea9a877	815	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
ganlikun	0:13413ea9a877	816	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
ganlikun	0:13413ea9a877	817	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
ganlikun	0:13413ea9a877	818	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
ganlikun	0:13413ea9a877	819	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
ganlikun	0:13413ea9a877	820
ganlikun	0:13413ea9a877	821	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
ganlikun	0:13413ea9a877	822	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
ganlikun	0:13413ea9a877	823	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
ganlikun	0:13413ea9a877	824	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
ganlikun	0:13413ea9a877	825	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
ganlikun	0:13413ea9a877	826	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
ganlikun	0:13413ea9a877	827	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
ganlikun	0:13413ea9a877	828	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
ganlikun	0:13413ea9a877	829	/**
ganlikun	0:13413ea9a877	830	* @}
ganlikun	0:13413ea9a877	831	*/
ganlikun	0:13413ea9a877	832
ganlikun	0:13413ea9a877	833	/** @defgroup RCC_HSI_Configuration HSI Configuration
ganlikun	0:13413ea9a877	834	* @{
ganlikun	0:13413ea9a877	835	*/
ganlikun	0:13413ea9a877	836
ganlikun	0:13413ea9a877	837	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
ganlikun	0:13413ea9a877	838	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
ganlikun	0:13413ea9a877	839	* It is used (enabled by hardware) as system clock source after startup
ganlikun	0:13413ea9a877	840	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
ganlikun	0:13413ea9a877	841	* of the HSE used directly or indirectly as system clock (if the Clock
ganlikun	0:13413ea9a877	842	* Security System CSS is enabled).
ganlikun	0:13413ea9a877	843	* @note HSI can not be stopped if it is used as system clock source. In this case,
ganlikun	0:13413ea9a877	844	* you have to select another source of the system clock then stop the HSI.
ganlikun	0:13413ea9a877	845	* @note After enabling the HSI, the application software should wait on HSIRDY
ganlikun	0:13413ea9a877	846	* flag to be set indicating that HSI clock is stable and can be used as
ganlikun	0:13413ea9a877	847	* system clock source.
ganlikun	0:13413ea9a877	848	* This parameter can be: ENABLE or DISABLE.
ganlikun	0:13413ea9a877	849	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
ganlikun	0:13413ea9a877	850	* clock cycles.
ganlikun	0:13413ea9a877	851	*/
ganlikun	0:13413ea9a877	852	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
ganlikun	0:13413ea9a877	853	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
ganlikun	0:13413ea9a877	854
ganlikun	0:13413ea9a877	855	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
ganlikun	0:13413ea9a877	856	* @note The calibration is used to compensate for the variations in voltage
ganlikun	0:13413ea9a877	857	* and temperature that influence the frequency of the internal HSI RC.
ganlikun	0:13413ea9a877	858	* @param __HSICalibrationValue__: specifies the calibration trimming value.
ganlikun	0:13413ea9a877	859	* (default is RCC_HSICALIBRATION_DEFAULT).
ganlikun	0:13413ea9a877	860	* This parameter must be a number between 0 and 0x1F.
ganlikun	0:13413ea9a877	861	*/
ganlikun	0:13413ea9a877	862	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
ganlikun	0:13413ea9a877	863	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
ganlikun	0:13413ea9a877	864	/**
ganlikun	0:13413ea9a877	865	* @}
ganlikun	0:13413ea9a877	866	*/
ganlikun	0:13413ea9a877	867
ganlikun	0:13413ea9a877	868	/** @defgroup RCC_LSI_Configuration LSI Configuration
ganlikun	0:13413ea9a877	869	* @{
ganlikun	0:13413ea9a877	870	*/
ganlikun	0:13413ea9a877	871
ganlikun	0:13413ea9a877	872	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
ganlikun	0:13413ea9a877	873	* @note After enabling the LSI, the application software should wait on
ganlikun	0:13413ea9a877	874	* LSIRDY flag to be set indicating that LSI clock is stable and can
ganlikun	0:13413ea9a877	875	* be used to clock the IWDG and/or the RTC.
ganlikun	0:13413ea9a877	876	* @note LSI can not be disabled if the IWDG is running.
ganlikun	0:13413ea9a877	877	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
ganlikun	0:13413ea9a877	878	* clock cycles.
ganlikun	0:13413ea9a877	879	*/
ganlikun	0:13413ea9a877	880	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
ganlikun	0:13413ea9a877	881	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
ganlikun	0:13413ea9a877	882	/**
ganlikun	0:13413ea9a877	883	* @}
ganlikun	0:13413ea9a877	884	*/
ganlikun	0:13413ea9a877	885
ganlikun	0:13413ea9a877	886	/** @defgroup RCC_HSE_Configuration HSE Configuration
ganlikun	0:13413ea9a877	887	* @{
ganlikun	0:13413ea9a877	888	*/
ganlikun	0:13413ea9a877	889
ganlikun	0:13413ea9a877	890	/**
ganlikun	0:13413ea9a877	891	* @brief Macro to configure the External High Speed oscillator (HSE).
ganlikun	0:13413ea9a877	892	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
ganlikun	0:13413ea9a877	893	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
ganlikun	0:13413ea9a877	894	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
ganlikun	0:13413ea9a877	895	* software should wait on HSERDY flag to be set indicating that HSE clock
ganlikun	0:13413ea9a877	896	* is stable and can be used to clock the PLL and/or system clock.
ganlikun	0:13413ea9a877	897	* @note HSE state can not be changed if it is used directly or through the
ganlikun	0:13413ea9a877	898	* PLL as system clock. In this case, you have to select another source
ganlikun	0:13413ea9a877	899	* of the system clock then change the HSE state (ex. disable it).
ganlikun	0:13413ea9a877	900	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
ganlikun	0:13413ea9a877	901	* @note This function reset the CSSON bit, so if the clock security system(CSS)
ganlikun	0:13413ea9a877	902	* was previously enabled you have to enable it again after calling this
ganlikun	0:13413ea9a877	903	* function.
ganlikun	0:13413ea9a877	904	* @param __STATE__: specifies the new state of the HSE.
ganlikun	0:13413ea9a877	905	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	906	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
ganlikun	0:13413ea9a877	907	* 6 HSE oscillator clock cycles.
ganlikun	0:13413ea9a877	908	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
ganlikun	0:13413ea9a877	909	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
ganlikun	0:13413ea9a877	910	*/
ganlikun	0:13413ea9a877	911	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
ganlikun	0:13413ea9a877	912	do { \
ganlikun	0:13413ea9a877	913	if ((__STATE__) == RCC_HSE_ON) \
ganlikun	0:13413ea9a877	914	{ \
ganlikun	0:13413ea9a877	915	SET_BIT(RCC->CR, RCC_CR_HSEON); \
ganlikun	0:13413ea9a877	916	} \
ganlikun	0:13413ea9a877	917	else if ((__STATE__) == RCC_HSE_BYPASS) \
ganlikun	0:13413ea9a877	918	{ \
ganlikun	0:13413ea9a877	919	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
ganlikun	0:13413ea9a877	920	SET_BIT(RCC->CR, RCC_CR_HSEON); \
ganlikun	0:13413ea9a877	921	} \
ganlikun	0:13413ea9a877	922	else \
ganlikun	0:13413ea9a877	923	{ \
ganlikun	0:13413ea9a877	924	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
ganlikun	0:13413ea9a877	925	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
ganlikun	0:13413ea9a877	926	} \
ganlikun	0:13413ea9a877	927	} while(0U)
ganlikun	0:13413ea9a877	928	/**
ganlikun	0:13413ea9a877	929	* @}
ganlikun	0:13413ea9a877	930	*/
ganlikun	0:13413ea9a877	931
ganlikun	0:13413ea9a877	932	/** @defgroup RCC_LSE_Configuration LSE Configuration
ganlikun	0:13413ea9a877	933	* @{
ganlikun	0:13413ea9a877	934	*/
ganlikun	0:13413ea9a877	935
ganlikun	0:13413ea9a877	936	/**
ganlikun	0:13413ea9a877	937	* @brief Macro to configure the External Low Speed oscillator (LSE).
ganlikun	0:13413ea9a877	938	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
ganlikun	0:13413ea9a877	939	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
ganlikun	0:13413ea9a877	940	* @note As the LSE is in the Backup domain and write access is denied to
ganlikun	0:13413ea9a877	941	* this domain after reset, you have to enable write access using
ganlikun	0:13413ea9a877	942	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
ganlikun	0:13413ea9a877	943	* (to be done once after reset).
ganlikun	0:13413ea9a877	944	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
ganlikun	0:13413ea9a877	945	* software should wait on LSERDY flag to be set indicating that LSE clock
ganlikun	0:13413ea9a877	946	* is stable and can be used to clock the RTC.
ganlikun	0:13413ea9a877	947	* @param __STATE__: specifies the new state of the LSE.
ganlikun	0:13413ea9a877	948	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	949	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
ganlikun	0:13413ea9a877	950	* 6 LSE oscillator clock cycles.
ganlikun	0:13413ea9a877	951	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
ganlikun	0:13413ea9a877	952	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
ganlikun	0:13413ea9a877	953	*/
ganlikun	0:13413ea9a877	954	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
ganlikun	0:13413ea9a877	955	do { \
ganlikun	0:13413ea9a877	956	if((__STATE__) == RCC_LSE_ON) \
ganlikun	0:13413ea9a877	957	{ \
ganlikun	0:13413ea9a877	958	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
ganlikun	0:13413ea9a877	959	} \
ganlikun	0:13413ea9a877	960	else if((__STATE__) == RCC_LSE_BYPASS) \
ganlikun	0:13413ea9a877	961	{ \
ganlikun	0:13413ea9a877	962	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
ganlikun	0:13413ea9a877	963	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
ganlikun	0:13413ea9a877	964	} \
ganlikun	0:13413ea9a877	965	else \
ganlikun	0:13413ea9a877	966	{ \
ganlikun	0:13413ea9a877	967	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
ganlikun	0:13413ea9a877	968	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
ganlikun	0:13413ea9a877	969	} \
ganlikun	0:13413ea9a877	970	} while(0U)
ganlikun	0:13413ea9a877	971	/**
ganlikun	0:13413ea9a877	972	* @}
ganlikun	0:13413ea9a877	973	*/
ganlikun	0:13413ea9a877	974
ganlikun	0:13413ea9a877	975	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
ganlikun	0:13413ea9a877	976	* @{
ganlikun	0:13413ea9a877	977	*/
ganlikun	0:13413ea9a877	978
ganlikun	0:13413ea9a877	979	/** @brief Macros to enable or disable the RTC clock.
ganlikun	0:13413ea9a877	980	* @note These macros must be used only after the RTC clock source was selected.
ganlikun	0:13413ea9a877	981	*/
ganlikun	0:13413ea9a877	982	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
ganlikun	0:13413ea9a877	983	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
ganlikun	0:13413ea9a877	984
ganlikun	0:13413ea9a877	985	/** @brief Macros to configure the RTC clock (RTCCLK).
ganlikun	0:13413ea9a877	986	* @note As the RTC clock configuration bits are in the Backup domain and write
ganlikun	0:13413ea9a877	987	* access is denied to this domain after reset, you have to enable write
ganlikun	0:13413ea9a877	988	* access using the Power Backup Access macro before to configure
ganlikun	0:13413ea9a877	989	* the RTC clock source (to be done once after reset).
ganlikun	0:13413ea9a877	990	* @note Once the RTC clock is configured it can't be changed unless the
ganlikun	0:13413ea9a877	991	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
ganlikun	0:13413ea9a877	992	* a Power On Reset (POR).
ganlikun	0:13413ea9a877	993	* @param __RTCCLKSource__: specifies the RTC clock source.
ganlikun	0:13413ea9a877	994	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	995	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
ganlikun	0:13413ea9a877	996	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
ganlikun	0:13413ea9a877	997	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
ganlikun	0:13413ea9a877	998	* as RTC clock, where x:[2,31]
ganlikun	0:13413ea9a877	999	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
ganlikun	0:13413ea9a877	1000	* work in STOP and STANDBY modes, and can be used as wake-up source.
ganlikun	0:13413ea9a877	1001	* However, when the HSE clock is used as RTC clock source, the RTC
ganlikun	0:13413ea9a877	1002	* cannot be used in STOP and STANDBY modes.
ganlikun	0:13413ea9a877	1003	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
ganlikun	0:13413ea9a877	1004	* RTC clock source).
ganlikun	0:13413ea9a877	1005	*/
ganlikun	0:13413ea9a877	1006	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
ganlikun	0:13413ea9a877	1007	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
ganlikun	0:13413ea9a877	1008
ganlikun	0:13413ea9a877	1009	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
ganlikun	0:13413ea9a877	1010	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFFU); \
ganlikun	0:13413ea9a877	1011	} while(0U)
ganlikun	0:13413ea9a877	1012
ganlikun	0:13413ea9a877	1013	/** @brief Macros to force or release the Backup domain reset.
ganlikun	0:13413ea9a877	1014	* @note This function resets the RTC peripheral (including the backup registers)
ganlikun	0:13413ea9a877	1015	* and the RTC clock source selection in RCC_CSR register.
ganlikun	0:13413ea9a877	1016	* @note The BKPSRAM is not affected by this reset.
ganlikun	0:13413ea9a877	1017	*/
ganlikun	0:13413ea9a877	1018	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
ganlikun	0:13413ea9a877	1019	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
ganlikun	0:13413ea9a877	1020	/**
ganlikun	0:13413ea9a877	1021	* @}
ganlikun	0:13413ea9a877	1022	*/
ganlikun	0:13413ea9a877	1023
ganlikun	0:13413ea9a877	1024	/** @defgroup RCC_PLL_Configuration PLL Configuration
ganlikun	0:13413ea9a877	1025	* @{
ganlikun	0:13413ea9a877	1026	*/
ganlikun	0:13413ea9a877	1027
ganlikun	0:13413ea9a877	1028	/** @brief Macros to enable or disable the main PLL.
ganlikun	0:13413ea9a877	1029	* @note After enabling the main PLL, the application software should wait on
ganlikun	0:13413ea9a877	1030	* PLLRDY flag to be set indicating that PLL clock is stable and can
ganlikun	0:13413ea9a877	1031	* be used as system clock source.
ganlikun	0:13413ea9a877	1032	* @note The main PLL can not be disabled if it is used as system clock source
ganlikun	0:13413ea9a877	1033	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
ganlikun	0:13413ea9a877	1034	*/
ganlikun	0:13413ea9a877	1035	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
ganlikun	0:13413ea9a877	1036	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
ganlikun	0:13413ea9a877	1037
ganlikun	0:13413ea9a877	1038	/** @brief Macro to configure the PLL clock source.
ganlikun	0:13413ea9a877	1039	* @note This function must be used only when the main PLL is disabled.
ganlikun	0:13413ea9a877	1040	* @param __PLLSOURCE__: specifies the PLL entry clock source.
ganlikun	0:13413ea9a877	1041	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1042	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
ganlikun	0:13413ea9a877	1043	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
ganlikun	0:13413ea9a877	1044	*
ganlikun	0:13413ea9a877	1045	*/
ganlikun	0:13413ea9a877	1046	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
ganlikun	0:13413ea9a877	1047
ganlikun	0:13413ea9a877	1048	/** @brief Macro to configure the PLL multiplication factor.
ganlikun	0:13413ea9a877	1049	* @note This function must be used only when the main PLL is disabled.
ganlikun	0:13413ea9a877	1050	* @param __PLLM__: specifies the division factor for PLL VCO input clock
ganlikun	0:13413ea9a877	1051	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
ganlikun	0:13413ea9a877	1052	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
ganlikun	0:13413ea9a877	1053	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
ganlikun	0:13413ea9a877	1054	* of 2 MHz to limit PLL jitter.
ganlikun	0:13413ea9a877	1055	*
ganlikun	0:13413ea9a877	1056	*/
ganlikun	0:13413ea9a877	1057	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
ganlikun	0:13413ea9a877	1058	/**
ganlikun	0:13413ea9a877	1059	* @}
ganlikun	0:13413ea9a877	1060	*/
ganlikun	0:13413ea9a877	1061
ganlikun	0:13413ea9a877	1062	/** @defgroup RCC_Get_Clock_source Get Clock source
ganlikun	0:13413ea9a877	1063	* @{
ganlikun	0:13413ea9a877	1064	*/
ganlikun	0:13413ea9a877	1065	/**
ganlikun	0:13413ea9a877	1066	* @brief Macro to configure the system clock source.
ganlikun	0:13413ea9a877	1067	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
ganlikun	0:13413ea9a877	1068	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1069	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
ganlikun	0:13413ea9a877	1070	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
ganlikun	0:13413ea9a877	1071	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
ganlikun	0:13413ea9a877	1072	* - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
ganlikun	0:13413ea9a877	1073	* parameter is available only for STM32F446xx devices.
ganlikun	0:13413ea9a877	1074	*/
ganlikun	0:13413ea9a877	1075	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
ganlikun	0:13413ea9a877	1076
ganlikun	0:13413ea9a877	1077	/** @brief Macro to get the clock source used as system clock.
ganlikun	0:13413ea9a877	1078	* @retval The clock source used as system clock. The returned value can be one
ganlikun	0:13413ea9a877	1079	* of the following:
ganlikun	0:13413ea9a877	1080	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
ganlikun	0:13413ea9a877	1081	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
ganlikun	0:13413ea9a877	1082	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
ganlikun	0:13413ea9a877	1083	* - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
ganlikun	0:13413ea9a877	1084	* is available only for STM32F446xx devices.
ganlikun	0:13413ea9a877	1085	*/
ganlikun	0:13413ea9a877	1086	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
ganlikun	0:13413ea9a877	1087
ganlikun	0:13413ea9a877	1088	/** @brief Macro to get the oscillator used as PLL clock source.
ganlikun	0:13413ea9a877	1089	* @retval The oscillator used as PLL clock source. The returned value can be one
ganlikun	0:13413ea9a877	1090	* of the following:
ganlikun	0:13413ea9a877	1091	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
ganlikun	0:13413ea9a877	1092	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
ganlikun	0:13413ea9a877	1093	*/
ganlikun	0:13413ea9a877	1094	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
ganlikun	0:13413ea9a877	1095	/**
ganlikun	0:13413ea9a877	1096	* @}
ganlikun	0:13413ea9a877	1097	*/
ganlikun	0:13413ea9a877	1098
ganlikun	0:13413ea9a877	1099	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
ganlikun	0:13413ea9a877	1100	* @{
ganlikun	0:13413ea9a877	1101	*/
ganlikun	0:13413ea9a877	1102
ganlikun	0:13413ea9a877	1103	/** @brief Macro to configure the MCO1 clock.
ganlikun	0:13413ea9a877	1104	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
ganlikun	0:13413ea9a877	1105	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1106	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
ganlikun	0:13413ea9a877	1107	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
ganlikun	0:13413ea9a877	1108	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
ganlikun	0:13413ea9a877	1109	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
ganlikun	0:13413ea9a877	1110	* @param __MCODIV__ specifies the MCO clock prescaler.
ganlikun	0:13413ea9a877	1111	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1112	* @arg RCC_MCODIV_1: no division applied to MCOx clock
ganlikun	0:13413ea9a877	1113	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
ganlikun	0:13413ea9a877	1114	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
ganlikun	0:13413ea9a877	1115	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
ganlikun	0:13413ea9a877	1116	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
ganlikun	0:13413ea9a877	1117	*/
ganlikun	0:13413ea9a877	1118	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
ganlikun	0:13413ea9a877	1119	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
ganlikun	0:13413ea9a877	1120
ganlikun	0:13413ea9a877	1121	/** @brief Macro to configure the MCO2 clock.
ganlikun	0:13413ea9a877	1122	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
ganlikun	0:13413ea9a877	1123	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1124	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
ganlikun	0:13413ea9a877	1125	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
ganlikun	0:13413ea9a877	1126	* @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
ganlikun	0:13413ea9a877	1127	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
ganlikun	0:13413ea9a877	1128	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
ganlikun	0:13413ea9a877	1129	* @param __MCODIV__ specifies the MCO clock prescaler.
ganlikun	0:13413ea9a877	1130	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1131	* @arg RCC_MCODIV_1: no division applied to MCOx clock
ganlikun	0:13413ea9a877	1132	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
ganlikun	0:13413ea9a877	1133	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
ganlikun	0:13413ea9a877	1134	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
ganlikun	0:13413ea9a877	1135	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
ganlikun	0:13413ea9a877	1136	* @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
ganlikun	0:13413ea9a877	1137	* at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
ganlikun	0:13413ea9a877	1138	*/
ganlikun	0:13413ea9a877	1139	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
ganlikun	0:13413ea9a877	1140	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 3U)));
ganlikun	0:13413ea9a877	1141	/**
ganlikun	0:13413ea9a877	1142	* @}
ganlikun	0:13413ea9a877	1143	*/
ganlikun	0:13413ea9a877	1144
ganlikun	0:13413ea9a877	1145	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
ganlikun	0:13413ea9a877	1146	* @brief macros to manage the specified RCC Flags and interrupts.
ganlikun	0:13413ea9a877	1147	* @{
ganlikun	0:13413ea9a877	1148	*/
ganlikun	0:13413ea9a877	1149
ganlikun	0:13413ea9a877	1150	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
ganlikun	0:13413ea9a877	1151	* the selected interrupts).
ganlikun	0:13413ea9a877	1152	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
ganlikun	0:13413ea9a877	1153	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1154	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
ganlikun	0:13413ea9a877	1155	* @arg RCC_IT_LSERDY: LSE ready interrupt.
ganlikun	0:13413ea9a877	1156	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
ganlikun	0:13413ea9a877	1157	* @arg RCC_IT_HSERDY: HSE ready interrupt.
ganlikun	0:13413ea9a877	1158	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
ganlikun	0:13413ea9a877	1159	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
ganlikun	0:13413ea9a877	1160	*/
ganlikun	0:13413ea9a877	1161	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
ganlikun	0:13413ea9a877	1162
ganlikun	0:13413ea9a877	1163	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
ganlikun	0:13413ea9a877	1164	* the selected interrupts).
ganlikun	0:13413ea9a877	1165	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
ganlikun	0:13413ea9a877	1166	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1167	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
ganlikun	0:13413ea9a877	1168	* @arg RCC_IT_LSERDY: LSE ready interrupt.
ganlikun	0:13413ea9a877	1169	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
ganlikun	0:13413ea9a877	1170	* @arg RCC_IT_HSERDY: HSE ready interrupt.
ganlikun	0:13413ea9a877	1171	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
ganlikun	0:13413ea9a877	1172	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
ganlikun	0:13413ea9a877	1173	*/
ganlikun	0:13413ea9a877	1174	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
ganlikun	0:13413ea9a877	1175
ganlikun	0:13413ea9a877	1176	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
ganlikun	0:13413ea9a877	1177	* bits to clear the selected interrupt pending bits.
ganlikun	0:13413ea9a877	1178	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
ganlikun	0:13413ea9a877	1179	* This parameter can be any combination of the following values:
ganlikun	0:13413ea9a877	1180	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
ganlikun	0:13413ea9a877	1181	* @arg RCC_IT_LSERDY: LSE ready interrupt.
ganlikun	0:13413ea9a877	1182	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
ganlikun	0:13413ea9a877	1183	* @arg RCC_IT_HSERDY: HSE ready interrupt.
ganlikun	0:13413ea9a877	1184	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
ganlikun	0:13413ea9a877	1185	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
ganlikun	0:13413ea9a877	1186	* @arg RCC_IT_CSS: Clock Security System interrupt
ganlikun	0:13413ea9a877	1187	*/
ganlikun	0:13413ea9a877	1188	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
ganlikun	0:13413ea9a877	1189
ganlikun	0:13413ea9a877	1190	/** @brief Check the RCC's interrupt has occurred or not.
ganlikun	0:13413ea9a877	1191	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
ganlikun	0:13413ea9a877	1192	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1193	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
ganlikun	0:13413ea9a877	1194	* @arg RCC_IT_LSERDY: LSE ready interrupt.
ganlikun	0:13413ea9a877	1195	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
ganlikun	0:13413ea9a877	1196	* @arg RCC_IT_HSERDY: HSE ready interrupt.
ganlikun	0:13413ea9a877	1197	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
ganlikun	0:13413ea9a877	1198	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
ganlikun	0:13413ea9a877	1199	* @arg RCC_IT_CSS: Clock Security System interrupt
ganlikun	0:13413ea9a877	1200	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
ganlikun	0:13413ea9a877	1201	*/
ganlikun	0:13413ea9a877	1202	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
ganlikun	0:13413ea9a877	1203
ganlikun	0:13413ea9a877	1204	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
ganlikun	0:13413ea9a877	1205	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
ganlikun	0:13413ea9a877	1206	*/
ganlikun	0:13413ea9a877	1207	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
ganlikun	0:13413ea9a877	1208
ganlikun	0:13413ea9a877	1209	/** @brief Check RCC flag is set or not.
ganlikun	0:13413ea9a877	1210	* @param __FLAG__: specifies the flag to check.
ganlikun	0:13413ea9a877	1211	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1212	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
ganlikun	0:13413ea9a877	1213	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
ganlikun	0:13413ea9a877	1214	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
ganlikun	0:13413ea9a877	1215	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
ganlikun	0:13413ea9a877	1216	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
ganlikun	0:13413ea9a877	1217	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
ganlikun	0:13413ea9a877	1218	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
ganlikun	0:13413ea9a877	1219	* @arg RCC_FLAG_PINRST: Pin reset.
ganlikun	0:13413ea9a877	1220	* @arg RCC_FLAG_PORRST: POR/PDR reset.
ganlikun	0:13413ea9a877	1221	* @arg RCC_FLAG_SFTRST: Software reset.
ganlikun	0:13413ea9a877	1222	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
ganlikun	0:13413ea9a877	1223	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
ganlikun	0:13413ea9a877	1224	* @arg RCC_FLAG_LPWRRST: Low Power reset.
ganlikun	0:13413ea9a877	1225	* @retval The new state of __FLAG__ (TRUE or FALSE).
ganlikun	0:13413ea9a877	1226	*/
ganlikun	0:13413ea9a877	1227	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
ganlikun	0:13413ea9a877	1228	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
ganlikun	0:13413ea9a877	1229
ganlikun	0:13413ea9a877	1230	/**
ganlikun	0:13413ea9a877	1231	* @}
ganlikun	0:13413ea9a877	1232	*/
ganlikun	0:13413ea9a877	1233
ganlikun	0:13413ea9a877	1234	/**
ganlikun	0:13413ea9a877	1235	* @}
ganlikun	0:13413ea9a877	1236	*/
ganlikun	0:13413ea9a877	1237
ganlikun	0:13413ea9a877	1238	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	1239	/** @addtogroup RCC_Exported_Functions
ganlikun	0:13413ea9a877	1240	* @{
ganlikun	0:13413ea9a877	1241	*/
ganlikun	0:13413ea9a877	1242
ganlikun	0:13413ea9a877	1243	/** @addtogroup RCC_Exported_Functions_Group1
ganlikun	0:13413ea9a877	1244	* @{
ganlikun	0:13413ea9a877	1245	*/
ganlikun	0:13413ea9a877	1246	/* Initialization and de-initialization functions ******************************/
ganlikun	0:13413ea9a877	1247	void HAL_RCC_DeInit(void);
ganlikun	0:13413ea9a877	1248	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
ganlikun	0:13413ea9a877	1249	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
ganlikun	0:13413ea9a877	1250	/**
ganlikun	0:13413ea9a877	1251	* @}
ganlikun	0:13413ea9a877	1252	*/
ganlikun	0:13413ea9a877	1253
ganlikun	0:13413ea9a877	1254	/** @addtogroup RCC_Exported_Functions_Group2
ganlikun	0:13413ea9a877	1255	* @{
ganlikun	0:13413ea9a877	1256	*/
ganlikun	0:13413ea9a877	1257	/* Peripheral Control functions ************************************************/
ganlikun	0:13413ea9a877	1258	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
ganlikun	0:13413ea9a877	1259	void HAL_RCC_EnableCSS(void);
ganlikun	0:13413ea9a877	1260	void HAL_RCC_DisableCSS(void);
ganlikun	0:13413ea9a877	1261	uint32_t HAL_RCC_GetSysClockFreq(void);
ganlikun	0:13413ea9a877	1262	uint32_t HAL_RCC_GetHCLKFreq(void);
ganlikun	0:13413ea9a877	1263	uint32_t HAL_RCC_GetPCLK1Freq(void);
ganlikun	0:13413ea9a877	1264	uint32_t HAL_RCC_GetPCLK2Freq(void);
ganlikun	0:13413ea9a877	1265	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
ganlikun	0:13413ea9a877	1266	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
ganlikun	0:13413ea9a877	1267
ganlikun	0:13413ea9a877	1268	/* CSS NMI IRQ handler */
ganlikun	0:13413ea9a877	1269	void HAL_RCC_NMI_IRQHandler(void);
ganlikun	0:13413ea9a877	1270
ganlikun	0:13413ea9a877	1271	/* User Callbacks in non blocking mode (IT mode) */
ganlikun	0:13413ea9a877	1272	void HAL_RCC_CSSCallback(void);
ganlikun	0:13413ea9a877	1273
ganlikun	0:13413ea9a877	1274	/**
ganlikun	0:13413ea9a877	1275	* @}
ganlikun	0:13413ea9a877	1276	*/
ganlikun	0:13413ea9a877	1277
ganlikun	0:13413ea9a877	1278	/**
ganlikun	0:13413ea9a877	1279	* @}
ganlikun	0:13413ea9a877	1280	*/
ganlikun	0:13413ea9a877	1281
ganlikun	0:13413ea9a877	1282	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	1283	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	1284	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	1285	/** @defgroup RCC_Private_Constants RCC Private Constants
ganlikun	0:13413ea9a877	1286	* @{
ganlikun	0:13413ea9a877	1287	*/
ganlikun	0:13413ea9a877	1288
ganlikun	0:13413ea9a877	1289	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
ganlikun	0:13413ea9a877	1290	* @brief RCC registers bit address in the alias region
ganlikun	0:13413ea9a877	1291	* @{
ganlikun	0:13413ea9a877	1292	*/
ganlikun	0:13413ea9a877	1293	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
ganlikun	0:13413ea9a877	1294	/* --- CR Register ---*/
ganlikun	0:13413ea9a877	1295	/* Alias word address of HSION bit */
ganlikun	0:13413ea9a877	1296	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
ganlikun	0:13413ea9a877	1297	#define RCC_HSION_BIT_NUMBER 0x00U
ganlikun	0:13413ea9a877	1298	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	1299	/* Alias word address of CSSON bit */
ganlikun	0:13413ea9a877	1300	#define RCC_CSSON_BIT_NUMBER 0x13U
ganlikun	0:13413ea9a877	1301	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	1302	/* Alias word address of PLLON bit */
ganlikun	0:13413ea9a877	1303	#define RCC_PLLON_BIT_NUMBER 0x18U
ganlikun	0:13413ea9a877	1304	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	1305
ganlikun	0:13413ea9a877	1306	/* --- BDCR Register ---*/
ganlikun	0:13413ea9a877	1307	/* Alias word address of RTCEN bit */
ganlikun	0:13413ea9a877	1308	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
ganlikun	0:13413ea9a877	1309	#define RCC_RTCEN_BIT_NUMBER 0x0FU
ganlikun	0:13413ea9a877	1310	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	1311	/* Alias word address of BDRST bit */
ganlikun	0:13413ea9a877	1312	#define RCC_BDRST_BIT_NUMBER 0x10U
ganlikun	0:13413ea9a877	1313	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	1314
ganlikun	0:13413ea9a877	1315	/* --- CSR Register ---*/
ganlikun	0:13413ea9a877	1316	/* Alias word address of LSION bit */
ganlikun	0:13413ea9a877	1317	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
ganlikun	0:13413ea9a877	1318	#define RCC_LSION_BIT_NUMBER 0x00U
ganlikun	0:13413ea9a877	1319	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
ganlikun	0:13413ea9a877	1320
ganlikun	0:13413ea9a877	1321	/* CR register byte 3 (Bits[23:16]) base address */
ganlikun	0:13413ea9a877	1322	#define RCC_CR_BYTE2_ADDRESS 0x40023802U
ganlikun	0:13413ea9a877	1323
ganlikun	0:13413ea9a877	1324	/* CIR register byte 2 (Bits[15:8]) base address */
ganlikun	0:13413ea9a877	1325	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
ganlikun	0:13413ea9a877	1326
ganlikun	0:13413ea9a877	1327	/* CIR register byte 3 (Bits[23:16]) base address */
ganlikun	0:13413ea9a877	1328	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
ganlikun	0:13413ea9a877	1329
ganlikun	0:13413ea9a877	1330	/* BDCR register base address */
ganlikun	0:13413ea9a877	1331	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
ganlikun	0:13413ea9a877	1332
ganlikun	0:13413ea9a877	1333	#define RCC_DBP_TIMEOUT_VALUE 2U
ganlikun	0:13413ea9a877	1334	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
ganlikun	0:13413ea9a877	1335
ganlikun	0:13413ea9a877	1336	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
ganlikun	0:13413ea9a877	1337	#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
ganlikun	0:13413ea9a877	1338	#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
ganlikun	0:13413ea9a877	1339
ganlikun	0:13413ea9a877	1340	/**
ganlikun	0:13413ea9a877	1341	* @}
ganlikun	0:13413ea9a877	1342	*/
ganlikun	0:13413ea9a877	1343
ganlikun	0:13413ea9a877	1344	/**
ganlikun	0:13413ea9a877	1345	* @}
ganlikun	0:13413ea9a877	1346	*/
ganlikun	0:13413ea9a877	1347
ganlikun	0:13413ea9a877	1348	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	1349	/** @defgroup RCC_Private_Macros RCC Private Macros
ganlikun	0:13413ea9a877	1350	* @{
ganlikun	0:13413ea9a877	1351	*/
ganlikun	0:13413ea9a877	1352
ganlikun	0:13413ea9a877	1353	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
ganlikun	0:13413ea9a877	1354	* @{
ganlikun	0:13413ea9a877	1355	*/
ganlikun	0:13413ea9a877	1356	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
ganlikun	0:13413ea9a877	1357
ganlikun	0:13413ea9a877	1358	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
ganlikun	0:13413ea9a877	1359	((HSE) == RCC_HSE_BYPASS))
ganlikun	0:13413ea9a877	1360
ganlikun	0:13413ea9a877	1361	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
ganlikun	0:13413ea9a877	1362	((LSE) == RCC_LSE_BYPASS))
ganlikun	0:13413ea9a877	1363
ganlikun	0:13413ea9a877	1364	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
ganlikun	0:13413ea9a877	1365
ganlikun	0:13413ea9a877	1366	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
ganlikun	0:13413ea9a877	1367
ganlikun	0:13413ea9a877	1368	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
ganlikun	0:13413ea9a877	1369
ganlikun	0:13413ea9a877	1370	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
ganlikun	0:13413ea9a877	1371	((SOURCE) == RCC_PLLSOURCE_HSE))
ganlikun	0:13413ea9a877	1372
ganlikun	0:13413ea9a877	1373	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
ganlikun	0:13413ea9a877	1374	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
ganlikun	0:13413ea9a877	1375	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
ganlikun	0:13413ea9a877	1376	((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
ganlikun	0:13413ea9a877	1377
ganlikun	0:13413ea9a877	1378	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
ganlikun	0:13413ea9a877	1379	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
ganlikun	0:13413ea9a877	1380	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
ganlikun	0:13413ea9a877	1381	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) \|\| \
ganlikun	0:13413ea9a877	1382	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
ganlikun	0:13413ea9a877	1383	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) \|\| \
ganlikun	0:13413ea9a877	1384	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) \|\| \
ganlikun	0:13413ea9a877	1385	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) \|\| \
ganlikun	0:13413ea9a877	1386	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
ganlikun	0:13413ea9a877	1387	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) \|\| \
ganlikun	0:13413ea9a877	1388	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) \|\| \
ganlikun	0:13413ea9a877	1389	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) \|\| \
ganlikun	0:13413ea9a877	1390	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) \|\| \
ganlikun	0:13413ea9a877	1391	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) \|\| \
ganlikun	0:13413ea9a877	1392	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) \|\| \
ganlikun	0:13413ea9a877	1393	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) \|\| \
ganlikun	0:13413ea9a877	1394	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) \|\| \
ganlikun	0:13413ea9a877	1395	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) \|\| \
ganlikun	0:13413ea9a877	1396	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) \|\| \
ganlikun	0:13413ea9a877	1397	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) \|\| \
ganlikun	0:13413ea9a877	1398	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) \|\| \
ganlikun	0:13413ea9a877	1399	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) \|\| \
ganlikun	0:13413ea9a877	1400	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) \|\| \
ganlikun	0:13413ea9a877	1401	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) \|\| \
ganlikun	0:13413ea9a877	1402	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) \|\| \
ganlikun	0:13413ea9a877	1403	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) \|\| \
ganlikun	0:13413ea9a877	1404	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) \|\| \
ganlikun	0:13413ea9a877	1405	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) \|\| \
ganlikun	0:13413ea9a877	1406	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) \|\| \
ganlikun	0:13413ea9a877	1407	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) \|\| \
ganlikun	0:13413ea9a877	1408	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) \|\| \
ganlikun	0:13413ea9a877	1409	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
ganlikun	0:13413ea9a877	1410
ganlikun	0:13413ea9a877	1411	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
ganlikun	0:13413ea9a877	1412
ganlikun	0:13413ea9a877	1413	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) \|\| ((VALUE) == 4U) \|\| ((VALUE) == 6U) \|\| ((VALUE) == 8U))
ganlikun	0:13413ea9a877	1414
ganlikun	0:13413ea9a877	1415	#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
ganlikun	0:13413ea9a877	1416
ganlikun	0:13413ea9a877	1417	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
ganlikun	0:13413ea9a877	1418	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
ganlikun	0:13413ea9a877	1419	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
ganlikun	0:13413ea9a877	1420	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
ganlikun	0:13413ea9a877	1421	((HCLK) == RCC_SYSCLK_DIV512))
ganlikun	0:13413ea9a877	1422
ganlikun	0:13413ea9a877	1423	#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
ganlikun	0:13413ea9a877	1424
ganlikun	0:13413ea9a877	1425	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
ganlikun	0:13413ea9a877	1426	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
ganlikun	0:13413ea9a877	1427	((PCLK) == RCC_HCLK_DIV16))
ganlikun	0:13413ea9a877	1428
ganlikun	0:13413ea9a877	1429	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
ganlikun	0:13413ea9a877	1430
ganlikun	0:13413ea9a877	1431	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
ganlikun	0:13413ea9a877	1432	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
ganlikun	0:13413ea9a877	1433
ganlikun	0:13413ea9a877	1434	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
ganlikun	0:13413ea9a877	1435	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
ganlikun	0:13413ea9a877	1436	((DIV) == RCC_MCODIV_5))
ganlikun	0:13413ea9a877	1437	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
ganlikun	0:13413ea9a877	1438
ganlikun	0:13413ea9a877	1439	/**
ganlikun	0:13413ea9a877	1440	* @}
ganlikun	0:13413ea9a877	1441	*/
ganlikun	0:13413ea9a877	1442
ganlikun	0:13413ea9a877	1443	/**
ganlikun	0:13413ea9a877	1444	* @}
ganlikun	0:13413ea9a877	1445	*/
ganlikun	0:13413ea9a877	1446
ganlikun	0:13413ea9a877	1447	/**
ganlikun	0:13413ea9a877	1448	* @}
ganlikun	0:13413ea9a877	1449	*/
ganlikun	0:13413ea9a877	1450
ganlikun	0:13413ea9a877	1451	/**
ganlikun	0:13413ea9a877	1452	* @}
ganlikun	0:13413ea9a877	1453	*/
ganlikun	0:13413ea9a877	1454
ganlikun	0:13413ea9a877	1455	#ifdef __cplusplus
ganlikun	0:13413ea9a877	1456	}
ganlikun	0:13413ea9a877	1457	#endif
ganlikun	0:13413ea9a877	1458
ganlikun	0:13413ea9a877	1459	#endif /* __STM32F4xx_HAL_RCC_H */
ganlikun	0:13413ea9a877	1460
ganlikun	0:13413ea9a877	1461	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1462

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h@0:13413ea9a877, 2022-06-12 (annotated)

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