Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_hal_rcc.c
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief RCC HAL module driver.
ganlikun 0:13413ea9a877 8 * This file provides firmware functions to manage the following
ganlikun 0:13413ea9a877 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
ganlikun 0:13413ea9a877 10 * + Initialization and de-initialization functions
ganlikun 0:13413ea9a877 11 * + Peripheral Control functions
ganlikun 0:13413ea9a877 12 *
ganlikun 0:13413ea9a877 13 @verbatim
ganlikun 0:13413ea9a877 14 ==============================================================================
ganlikun 0:13413ea9a877 15 ##### RCC specific features #####
ganlikun 0:13413ea9a877 16 ==============================================================================
ganlikun 0:13413ea9a877 17 [..]
ganlikun 0:13413ea9a877 18 After reset the device is running from Internal High Speed oscillator
ganlikun 0:13413ea9a877 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
ganlikun 0:13413ea9a877 20 and I-Cache are disabled, and all peripherals are off except internal
ganlikun 0:13413ea9a877 21 SRAM, Flash and JTAG.
ganlikun 0:13413ea9a877 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
ganlikun 0:13413ea9a877 23 all peripherals mapped on these busses are running at HSI speed.
ganlikun 0:13413ea9a877 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
ganlikun 0:13413ea9a877 25 (+) All GPIOs are in input floating state, except the JTAG pins which
ganlikun 0:13413ea9a877 26 are assigned to be used for debug purpose.
ganlikun 0:13413ea9a877 27
ganlikun 0:13413ea9a877 28 [..]
ganlikun 0:13413ea9a877 29 Once the device started from reset, the user application has to:
ganlikun 0:13413ea9a877 30 (+) Configure the clock source to be used to drive the System clock
ganlikun 0:13413ea9a877 31 (if the application needs higher frequency/performance)
ganlikun 0:13413ea9a877 32 (+) Configure the System clock frequency and Flash settings
ganlikun 0:13413ea9a877 33 (+) Configure the AHB and APB busses prescalers
ganlikun 0:13413ea9a877 34 (+) Enable the clock for the peripheral(s) to be used
ganlikun 0:13413ea9a877 35 (+) Configure the clock source(s) for peripherals which clocks are not
ganlikun 0:13413ea9a877 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
ganlikun 0:13413ea9a877 37
ganlikun 0:13413ea9a877 38 ##### RCC Limitations #####
ganlikun 0:13413ea9a877 39 ==============================================================================
ganlikun 0:13413ea9a877 40 [..]
ganlikun 0:13413ea9a877 41 A delay between an RCC peripheral clock enable and the effective peripheral
ganlikun 0:13413ea9a877 42 enabling should be taken into account in order to manage the peripheral read/write
ganlikun 0:13413ea9a877 43 from/to registers.
ganlikun 0:13413ea9a877 44 (+) This delay depends on the peripheral mapping.
ganlikun 0:13413ea9a877 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
ganlikun 0:13413ea9a877 46 after the clock enable bit is set on the hardware register
ganlikun 0:13413ea9a877 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
ganlikun 0:13413ea9a877 48 after the clock enable bit is set on the hardware register
ganlikun 0:13413ea9a877 49
ganlikun 0:13413ea9a877 50 [..]
ganlikun 0:13413ea9a877 51 Implemented Workaround:
ganlikun 0:13413ea9a877 52 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
ganlikun 0:13413ea9a877 53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
ganlikun 0:13413ea9a877 54
ganlikun 0:13413ea9a877 55 @endverbatim
ganlikun 0:13413ea9a877 56 ******************************************************************************
ganlikun 0:13413ea9a877 57 * @attention
ganlikun 0:13413ea9a877 58 *
ganlikun 0:13413ea9a877 59 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 60 *
ganlikun 0:13413ea9a877 61 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 62 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 63 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 64 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 65 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 66 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 67 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 69 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 70 * without specific prior written permission.
ganlikun 0:13413ea9a877 71 *
ganlikun 0:13413ea9a877 72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 82 *
ganlikun 0:13413ea9a877 83 ******************************************************************************
ganlikun 0:13413ea9a877 84 */
ganlikun 0:13413ea9a877 85
ganlikun 0:13413ea9a877 86 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 87 #include "stm32f4xx_hal.h"
ganlikun 0:13413ea9a877 88
ganlikun 0:13413ea9a877 89 /** @addtogroup STM32F4xx_HAL_Driver
ganlikun 0:13413ea9a877 90 * @{
ganlikun 0:13413ea9a877 91 */
ganlikun 0:13413ea9a877 92
ganlikun 0:13413ea9a877 93 /** @defgroup RCC RCC
ganlikun 0:13413ea9a877 94 * @brief RCC HAL module driver
ganlikun 0:13413ea9a877 95 * @{
ganlikun 0:13413ea9a877 96 */
ganlikun 0:13413ea9a877 97
ganlikun 0:13413ea9a877 98 #ifdef HAL_RCC_MODULE_ENABLED
ganlikun 0:13413ea9a877 99
ganlikun 0:13413ea9a877 100 /* Private typedef -----------------------------------------------------------*/
ganlikun 0:13413ea9a877 101 /* Private define ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 102 /** @addtogroup RCC_Private_Constants
ganlikun 0:13413ea9a877 103 * @{
ganlikun 0:13413ea9a877 104 */
ganlikun 0:13413ea9a877 105 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
ganlikun 0:13413ea9a877 106
ganlikun 0:13413ea9a877 107 /* Private macro -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 108 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
ganlikun 0:13413ea9a877 109 #define MCO1_GPIO_PORT GPIOA
ganlikun 0:13413ea9a877 110 #define MCO1_PIN GPIO_PIN_8
ganlikun 0:13413ea9a877 111
ganlikun 0:13413ea9a877 112 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
ganlikun 0:13413ea9a877 113 #define MCO2_GPIO_PORT GPIOC
ganlikun 0:13413ea9a877 114 #define MCO2_PIN GPIO_PIN_9
ganlikun 0:13413ea9a877 115 /**
ganlikun 0:13413ea9a877 116 * @}
ganlikun 0:13413ea9a877 117 */
ganlikun 0:13413ea9a877 118
ganlikun 0:13413ea9a877 119 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 120 /** @defgroup RCC_Private_Variables RCC Private Variables
ganlikun 0:13413ea9a877 121 * @{
ganlikun 0:13413ea9a877 122 */
ganlikun 0:13413ea9a877 123 /**
ganlikun 0:13413ea9a877 124 * @}
ganlikun 0:13413ea9a877 125 */
ganlikun 0:13413ea9a877 126 /* Private function prototypes -----------------------------------------------*/
ganlikun 0:13413ea9a877 127 /* Private functions ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 128
ganlikun 0:13413ea9a877 129 /** @defgroup RCC_Exported_Functions RCC Exported Functions
ganlikun 0:13413ea9a877 130 * @{
ganlikun 0:13413ea9a877 131 */
ganlikun 0:13413ea9a877 132
ganlikun 0:13413ea9a877 133 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
ganlikun 0:13413ea9a877 134 * @brief Initialization and Configuration functions
ganlikun 0:13413ea9a877 135 *
ganlikun 0:13413ea9a877 136 @verbatim
ganlikun 0:13413ea9a877 137 ===============================================================================
ganlikun 0:13413ea9a877 138 ##### Initialization and de-initialization functions #####
ganlikun 0:13413ea9a877 139 ===============================================================================
ganlikun 0:13413ea9a877 140 [..]
ganlikun 0:13413ea9a877 141 This section provides functions allowing to configure the internal/external oscillators
ganlikun 0:13413ea9a877 142 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
ganlikun 0:13413ea9a877 143 and APB2).
ganlikun 0:13413ea9a877 144
ganlikun 0:13413ea9a877 145 [..] Internal/external clock and PLL configuration
ganlikun 0:13413ea9a877 146 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
ganlikun 0:13413ea9a877 147 the PLL as System clock source.
ganlikun 0:13413ea9a877 148
ganlikun 0:13413ea9a877 149 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
ganlikun 0:13413ea9a877 150 clock source.
ganlikun 0:13413ea9a877 151
ganlikun 0:13413ea9a877 152 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
ganlikun 0:13413ea9a877 153 through the PLL as System clock source. Can be used also as RTC clock source.
ganlikun 0:13413ea9a877 154
ganlikun 0:13413ea9a877 155 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
ganlikun 0:13413ea9a877 156
ganlikun 0:13413ea9a877 157 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
ganlikun 0:13413ea9a877 158 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
ganlikun 0:13413ea9a877 159 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
ganlikun 0:13413ea9a877 160 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
ganlikun 0:13413ea9a877 161
ganlikun 0:13413ea9a877 162 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
ganlikun 0:13413ea9a877 163 and if a HSE clock failure occurs(HSE used directly or through PLL as System
ganlikun 0:13413ea9a877 164 clock source), the System clocks automatically switched to HSI and an interrupt
ganlikun 0:13413ea9a877 165 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
ganlikun 0:13413ea9a877 166 (Non-Maskable Interrupt) exception vector.
ganlikun 0:13413ea9a877 167
ganlikun 0:13413ea9a877 168 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
ganlikun 0:13413ea9a877 169 clock (through a configurable prescaler) on PA8 pin.
ganlikun 0:13413ea9a877 170
ganlikun 0:13413ea9a877 171 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
ganlikun 0:13413ea9a877 172 clock (through a configurable prescaler) on PC9 pin.
ganlikun 0:13413ea9a877 173
ganlikun 0:13413ea9a877 174 [..] System, AHB and APB busses clocks configuration
ganlikun 0:13413ea9a877 175 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
ganlikun 0:13413ea9a877 176 HSE and PLL.
ganlikun 0:13413ea9a877 177 The AHB clock (HCLK) is derived from System clock through configurable
ganlikun 0:13413ea9a877 178 prescaler and used to clock the CPU, memory and peripherals mapped
ganlikun 0:13413ea9a877 179 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
ganlikun 0:13413ea9a877 180 from AHB clock through configurable prescalers and used to clock
ganlikun 0:13413ea9a877 181 the peripherals mapped on these busses. You can use
ganlikun 0:13413ea9a877 182 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
ganlikun 0:13413ea9a877 183
ganlikun 0:13413ea9a877 184 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
ganlikun 0:13413ea9a877 185 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
ganlikun 0:13413ea9a877 186 Depending on the device voltage range, the maximum frequency should
ganlikun 0:13413ea9a877 187 be adapted accordingly (refer to the product datasheets for more details).
ganlikun 0:13413ea9a877 188
ganlikun 0:13413ea9a877 189 (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
ganlikun 0:13413ea9a877 190 the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
ganlikun 0:13413ea9a877 191 Depending on the device voltage range, the maximum frequency should
ganlikun 0:13413ea9a877 192 be adapted accordingly (refer to the product datasheets for more details).
ganlikun 0:13413ea9a877 193
ganlikun 0:13413ea9a877 194 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
ganlikun 0:13413ea9a877 195 PCLK2 84 MHz and PCLK1 42 MHz.
ganlikun 0:13413ea9a877 196 Depending on the device voltage range, the maximum frequency should
ganlikun 0:13413ea9a877 197 be adapted accordingly (refer to the product datasheets for more details).
ganlikun 0:13413ea9a877 198
ganlikun 0:13413ea9a877 199 (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
ganlikun 0:13413ea9a877 200 PCLK2 100 MHz and PCLK1 50 MHz.
ganlikun 0:13413ea9a877 201 Depending on the device voltage range, the maximum frequency should
ganlikun 0:13413ea9a877 202 be adapted accordingly (refer to the product datasheets for more details).
ganlikun 0:13413ea9a877 203
ganlikun 0:13413ea9a877 204 @endverbatim
ganlikun 0:13413ea9a877 205 * @{
ganlikun 0:13413ea9a877 206 */
ganlikun 0:13413ea9a877 207
ganlikun 0:13413ea9a877 208 /**
ganlikun 0:13413ea9a877 209 * @brief Resets the RCC clock configuration to the default reset state.
ganlikun 0:13413ea9a877 210 * @note The default reset state of the clock configuration is given below:
ganlikun 0:13413ea9a877 211 * - HSI ON and used as system clock source
ganlikun 0:13413ea9a877 212 * - HSE and PLL OFF
ganlikun 0:13413ea9a877 213 * - AHB, APB1 and APB2 prescaler set to 1.
ganlikun 0:13413ea9a877 214 * - CSS, MCO1 and MCO2 OFF
ganlikun 0:13413ea9a877 215 * - All interrupts disabled
ganlikun 0:13413ea9a877 216 * @note This function doesn't modify the configuration of the
ganlikun 0:13413ea9a877 217 * - Peripheral clocks
ganlikun 0:13413ea9a877 218 * - LSI, LSE and RTC clocks
ganlikun 0:13413ea9a877 219 * @retval None
ganlikun 0:13413ea9a877 220 */
ganlikun 0:13413ea9a877 221 __weak void HAL_RCC_DeInit(void)
ganlikun 0:13413ea9a877 222 {}
ganlikun 0:13413ea9a877 223
ganlikun 0:13413ea9a877 224 /**
ganlikun 0:13413ea9a877 225 * @brief Initializes the RCC Oscillators according to the specified parameters in the
ganlikun 0:13413ea9a877 226 * RCC_OscInitTypeDef.
ganlikun 0:13413ea9a877 227 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
ganlikun 0:13413ea9a877 228 * contains the configuration information for the RCC Oscillators.
ganlikun 0:13413ea9a877 229 * @note The PLL is not disabled when used as system clock.
ganlikun 0:13413ea9a877 230 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
ganlikun 0:13413ea9a877 231 * supported by this API. User should request a transition to LSE Off
ganlikun 0:13413ea9a877 232 * first and then LSE On or LSE Bypass.
ganlikun 0:13413ea9a877 233 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
ganlikun 0:13413ea9a877 234 * supported by this API. User should request a transition to HSE Off
ganlikun 0:13413ea9a877 235 * first and then HSE On or HSE Bypass.
ganlikun 0:13413ea9a877 236 * @retval HAL status
ganlikun 0:13413ea9a877 237 */
ganlikun 0:13413ea9a877 238 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
ganlikun 0:13413ea9a877 239 {
ganlikun 0:13413ea9a877 240 uint32_t tickstart = 0U;
ganlikun 0:13413ea9a877 241
ganlikun 0:13413ea9a877 242 /* Check the parameters */
ganlikun 0:13413ea9a877 243 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
ganlikun 0:13413ea9a877 244 /*------------------------------- HSE Configuration ------------------------*/
ganlikun 0:13413ea9a877 245 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
ganlikun 0:13413ea9a877 246 {
ganlikun 0:13413ea9a877 247 /* Check the parameters */
ganlikun 0:13413ea9a877 248 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
ganlikun 0:13413ea9a877 249 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
ganlikun 0:13413ea9a877 250 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
ganlikun 0:13413ea9a877 251 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
ganlikun 0:13413ea9a877 252 {
ganlikun 0:13413ea9a877 253 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
ganlikun 0:13413ea9a877 254 {
ganlikun 0:13413ea9a877 255 return HAL_ERROR;
ganlikun 0:13413ea9a877 256 }
ganlikun 0:13413ea9a877 257 }
ganlikun 0:13413ea9a877 258 else
ganlikun 0:13413ea9a877 259 {
ganlikun 0:13413ea9a877 260 /* Set the new HSE configuration ---------------------------------------*/
ganlikun 0:13413ea9a877 261 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
ganlikun 0:13413ea9a877 262
ganlikun 0:13413ea9a877 263 /* Check the HSE State */
ganlikun 0:13413ea9a877 264 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
ganlikun 0:13413ea9a877 265 {
ganlikun 0:13413ea9a877 266 /* Get Start Tick*/
ganlikun 0:13413ea9a877 267 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 268
ganlikun 0:13413ea9a877 269 /* Wait till HSE is ready */
ganlikun 0:13413ea9a877 270 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
ganlikun 0:13413ea9a877 271 {
ganlikun 0:13413ea9a877 272 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 273 {
ganlikun 0:13413ea9a877 274 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 275 }
ganlikun 0:13413ea9a877 276 }
ganlikun 0:13413ea9a877 277 }
ganlikun 0:13413ea9a877 278 else
ganlikun 0:13413ea9a877 279 {
ganlikun 0:13413ea9a877 280 /* Get Start Tick*/
ganlikun 0:13413ea9a877 281 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 282
ganlikun 0:13413ea9a877 283 /* Wait till HSE is bypassed or disabled */
ganlikun 0:13413ea9a877 284 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
ganlikun 0:13413ea9a877 285 {
ganlikun 0:13413ea9a877 286 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 287 {
ganlikun 0:13413ea9a877 288 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 289 }
ganlikun 0:13413ea9a877 290 }
ganlikun 0:13413ea9a877 291 }
ganlikun 0:13413ea9a877 292 }
ganlikun 0:13413ea9a877 293 }
ganlikun 0:13413ea9a877 294 /*----------------------------- HSI Configuration --------------------------*/
ganlikun 0:13413ea9a877 295 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
ganlikun 0:13413ea9a877 296 {
ganlikun 0:13413ea9a877 297 /* Check the parameters */
ganlikun 0:13413ea9a877 298 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
ganlikun 0:13413ea9a877 299 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
ganlikun 0:13413ea9a877 300
ganlikun 0:13413ea9a877 301 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
ganlikun 0:13413ea9a877 302 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
ganlikun 0:13413ea9a877 303 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
ganlikun 0:13413ea9a877 304 {
ganlikun 0:13413ea9a877 305 /* When HSI is used as system clock it will not disabled */
ganlikun 0:13413ea9a877 306 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
ganlikun 0:13413ea9a877 307 {
ganlikun 0:13413ea9a877 308 return HAL_ERROR;
ganlikun 0:13413ea9a877 309 }
ganlikun 0:13413ea9a877 310 /* Otherwise, just the calibration is allowed */
ganlikun 0:13413ea9a877 311 else
ganlikun 0:13413ea9a877 312 {
ganlikun 0:13413ea9a877 313 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
ganlikun 0:13413ea9a877 314 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
ganlikun 0:13413ea9a877 315 }
ganlikun 0:13413ea9a877 316 }
ganlikun 0:13413ea9a877 317 else
ganlikun 0:13413ea9a877 318 {
ganlikun 0:13413ea9a877 319 /* Check the HSI State */
ganlikun 0:13413ea9a877 320 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
ganlikun 0:13413ea9a877 321 {
ganlikun 0:13413ea9a877 322 /* Enable the Internal High Speed oscillator (HSI). */
ganlikun 0:13413ea9a877 323 __HAL_RCC_HSI_ENABLE();
ganlikun 0:13413ea9a877 324
ganlikun 0:13413ea9a877 325 /* Get Start Tick*/
ganlikun 0:13413ea9a877 326 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 327
ganlikun 0:13413ea9a877 328 /* Wait till HSI is ready */
ganlikun 0:13413ea9a877 329 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
ganlikun 0:13413ea9a877 330 {
ganlikun 0:13413ea9a877 331 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 332 {
ganlikun 0:13413ea9a877 333 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 334 }
ganlikun 0:13413ea9a877 335 }
ganlikun 0:13413ea9a877 336
ganlikun 0:13413ea9a877 337 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
ganlikun 0:13413ea9a877 338 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
ganlikun 0:13413ea9a877 339 }
ganlikun 0:13413ea9a877 340 else
ganlikun 0:13413ea9a877 341 {
ganlikun 0:13413ea9a877 342 /* Disable the Internal High Speed oscillator (HSI). */
ganlikun 0:13413ea9a877 343 __HAL_RCC_HSI_DISABLE();
ganlikun 0:13413ea9a877 344
ganlikun 0:13413ea9a877 345 /* Get Start Tick*/
ganlikun 0:13413ea9a877 346 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 347
ganlikun 0:13413ea9a877 348 /* Wait till HSI is ready */
ganlikun 0:13413ea9a877 349 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
ganlikun 0:13413ea9a877 350 {
ganlikun 0:13413ea9a877 351 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 352 {
ganlikun 0:13413ea9a877 353 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 354 }
ganlikun 0:13413ea9a877 355 }
ganlikun 0:13413ea9a877 356 }
ganlikun 0:13413ea9a877 357 }
ganlikun 0:13413ea9a877 358 }
ganlikun 0:13413ea9a877 359 /*------------------------------ LSI Configuration -------------------------*/
ganlikun 0:13413ea9a877 360 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
ganlikun 0:13413ea9a877 361 {
ganlikun 0:13413ea9a877 362 /* Check the parameters */
ganlikun 0:13413ea9a877 363 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
ganlikun 0:13413ea9a877 364
ganlikun 0:13413ea9a877 365 /* Check the LSI State */
ganlikun 0:13413ea9a877 366 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
ganlikun 0:13413ea9a877 367 {
ganlikun 0:13413ea9a877 368 /* Enable the Internal Low Speed oscillator (LSI). */
ganlikun 0:13413ea9a877 369 __HAL_RCC_LSI_ENABLE();
ganlikun 0:13413ea9a877 370
ganlikun 0:13413ea9a877 371 /* Get Start Tick*/
ganlikun 0:13413ea9a877 372 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 373
ganlikun 0:13413ea9a877 374 /* Wait till LSI is ready */
ganlikun 0:13413ea9a877 375 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
ganlikun 0:13413ea9a877 376 {
ganlikun 0:13413ea9a877 377 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 378 {
ganlikun 0:13413ea9a877 379 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 380 }
ganlikun 0:13413ea9a877 381 }
ganlikun 0:13413ea9a877 382 }
ganlikun 0:13413ea9a877 383 else
ganlikun 0:13413ea9a877 384 {
ganlikun 0:13413ea9a877 385 /* Disable the Internal Low Speed oscillator (LSI). */
ganlikun 0:13413ea9a877 386 __HAL_RCC_LSI_DISABLE();
ganlikun 0:13413ea9a877 387
ganlikun 0:13413ea9a877 388 /* Get Start Tick*/
ganlikun 0:13413ea9a877 389 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 390
ganlikun 0:13413ea9a877 391 /* Wait till LSI is ready */
ganlikun 0:13413ea9a877 392 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
ganlikun 0:13413ea9a877 393 {
ganlikun 0:13413ea9a877 394 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 395 {
ganlikun 0:13413ea9a877 396 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 397 }
ganlikun 0:13413ea9a877 398 }
ganlikun 0:13413ea9a877 399 }
ganlikun 0:13413ea9a877 400 }
ganlikun 0:13413ea9a877 401 /*------------------------------ LSE Configuration -------------------------*/
ganlikun 0:13413ea9a877 402 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
ganlikun 0:13413ea9a877 403 {
ganlikun 0:13413ea9a877 404 /* Check the parameters */
ganlikun 0:13413ea9a877 405 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
ganlikun 0:13413ea9a877 406
ganlikun 0:13413ea9a877 407 /* Enable Power Clock*/
ganlikun 0:13413ea9a877 408 __HAL_RCC_PWR_CLK_ENABLE();
ganlikun 0:13413ea9a877 409
ganlikun 0:13413ea9a877 410 /* Enable write access to Backup domain */
ganlikun 0:13413ea9a877 411 PWR->CR |= PWR_CR_DBP;
ganlikun 0:13413ea9a877 412
ganlikun 0:13413ea9a877 413 /* Wait for Backup domain Write protection enable */
ganlikun 0:13413ea9a877 414 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 415
ganlikun 0:13413ea9a877 416 while((PWR->CR & PWR_CR_DBP) == RESET)
ganlikun 0:13413ea9a877 417 {
ganlikun 0:13413ea9a877 418 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 419 {
ganlikun 0:13413ea9a877 420 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 421 }
ganlikun 0:13413ea9a877 422 }
ganlikun 0:13413ea9a877 423
ganlikun 0:13413ea9a877 424 /* Set the new LSE configuration -----------------------------------------*/
ganlikun 0:13413ea9a877 425 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
ganlikun 0:13413ea9a877 426 /* Check the LSE State */
ganlikun 0:13413ea9a877 427 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
ganlikun 0:13413ea9a877 428 {
ganlikun 0:13413ea9a877 429 /* Get Start Tick*/
ganlikun 0:13413ea9a877 430 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 431
ganlikun 0:13413ea9a877 432 /* Wait till LSE is ready */
ganlikun 0:13413ea9a877 433 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
ganlikun 0:13413ea9a877 434 {
ganlikun 0:13413ea9a877 435 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 436 {
ganlikun 0:13413ea9a877 437 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 438 }
ganlikun 0:13413ea9a877 439 }
ganlikun 0:13413ea9a877 440 }
ganlikun 0:13413ea9a877 441 else
ganlikun 0:13413ea9a877 442 {
ganlikun 0:13413ea9a877 443 /* Get Start Tick*/
ganlikun 0:13413ea9a877 444 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 445
ganlikun 0:13413ea9a877 446 /* Wait till LSE is ready */
ganlikun 0:13413ea9a877 447 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
ganlikun 0:13413ea9a877 448 {
ganlikun 0:13413ea9a877 449 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 450 {
ganlikun 0:13413ea9a877 451 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 452 }
ganlikun 0:13413ea9a877 453 }
ganlikun 0:13413ea9a877 454 }
ganlikun 0:13413ea9a877 455 }
ganlikun 0:13413ea9a877 456 /*-------------------------------- PLL Configuration -----------------------*/
ganlikun 0:13413ea9a877 457 /* Check the parameters */
ganlikun 0:13413ea9a877 458 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
ganlikun 0:13413ea9a877 459 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
ganlikun 0:13413ea9a877 460 {
ganlikun 0:13413ea9a877 461 /* Check if the PLL is used as system clock or not */
ganlikun 0:13413ea9a877 462 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
ganlikun 0:13413ea9a877 463 {
ganlikun 0:13413ea9a877 464 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
ganlikun 0:13413ea9a877 465 {
ganlikun 0:13413ea9a877 466 /* Check the parameters */
ganlikun 0:13413ea9a877 467 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
ganlikun 0:13413ea9a877 468 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
ganlikun 0:13413ea9a877 469 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
ganlikun 0:13413ea9a877 470 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
ganlikun 0:13413ea9a877 471 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
ganlikun 0:13413ea9a877 472
ganlikun 0:13413ea9a877 473 /* Disable the main PLL. */
ganlikun 0:13413ea9a877 474 __HAL_RCC_PLL_DISABLE();
ganlikun 0:13413ea9a877 475
ganlikun 0:13413ea9a877 476 /* Get Start Tick*/
ganlikun 0:13413ea9a877 477 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 478
ganlikun 0:13413ea9a877 479 /* Wait till PLL is ready */
ganlikun 0:13413ea9a877 480 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
ganlikun 0:13413ea9a877 481 {
ganlikun 0:13413ea9a877 482 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 483 {
ganlikun 0:13413ea9a877 484 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 485 }
ganlikun 0:13413ea9a877 486 }
ganlikun 0:13413ea9a877 487
ganlikun 0:13413ea9a877 488 /* Configure the main PLL clock source, multiplication and division factors. */
ganlikun 0:13413ea9a877 489 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
ganlikun 0:13413ea9a877 490 RCC_OscInitStruct->PLL.PLLM | \
ganlikun 0:13413ea9a877 491 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
ganlikun 0:13413ea9a877 492 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
ganlikun 0:13413ea9a877 493 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
ganlikun 0:13413ea9a877 494 /* Enable the main PLL. */
ganlikun 0:13413ea9a877 495 __HAL_RCC_PLL_ENABLE();
ganlikun 0:13413ea9a877 496
ganlikun 0:13413ea9a877 497 /* Get Start Tick*/
ganlikun 0:13413ea9a877 498 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 499
ganlikun 0:13413ea9a877 500 /* Wait till PLL is ready */
ganlikun 0:13413ea9a877 501 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
ganlikun 0:13413ea9a877 502 {
ganlikun 0:13413ea9a877 503 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 504 {
ganlikun 0:13413ea9a877 505 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 506 }
ganlikun 0:13413ea9a877 507 }
ganlikun 0:13413ea9a877 508 }
ganlikun 0:13413ea9a877 509 else
ganlikun 0:13413ea9a877 510 {
ganlikun 0:13413ea9a877 511 /* Disable the main PLL. */
ganlikun 0:13413ea9a877 512 __HAL_RCC_PLL_DISABLE();
ganlikun 0:13413ea9a877 513
ganlikun 0:13413ea9a877 514 /* Get Start Tick*/
ganlikun 0:13413ea9a877 515 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 516
ganlikun 0:13413ea9a877 517 /* Wait till PLL is ready */
ganlikun 0:13413ea9a877 518 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
ganlikun 0:13413ea9a877 519 {
ganlikun 0:13413ea9a877 520 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 521 {
ganlikun 0:13413ea9a877 522 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 523 }
ganlikun 0:13413ea9a877 524 }
ganlikun 0:13413ea9a877 525 }
ganlikun 0:13413ea9a877 526 }
ganlikun 0:13413ea9a877 527 else
ganlikun 0:13413ea9a877 528 {
ganlikun 0:13413ea9a877 529 return HAL_ERROR;
ganlikun 0:13413ea9a877 530 }
ganlikun 0:13413ea9a877 531 }
ganlikun 0:13413ea9a877 532 return HAL_OK;
ganlikun 0:13413ea9a877 533 }
ganlikun 0:13413ea9a877 534
ganlikun 0:13413ea9a877 535 /**
ganlikun 0:13413ea9a877 536 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
ganlikun 0:13413ea9a877 537 * parameters in the RCC_ClkInitStruct.
ganlikun 0:13413ea9a877 538 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
ganlikun 0:13413ea9a877 539 * contains the configuration information for the RCC peripheral.
ganlikun 0:13413ea9a877 540 * @param FLatency: FLASH Latency, this parameter depend on device selected
ganlikun 0:13413ea9a877 541 *
ganlikun 0:13413ea9a877 542 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
ganlikun 0:13413ea9a877 543 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
ganlikun 0:13413ea9a877 544 *
ganlikun 0:13413ea9a877 545 * @note The HSI is used (enabled by hardware) as system clock source after
ganlikun 0:13413ea9a877 546 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
ganlikun 0:13413ea9a877 547 * of failure of the HSE used directly or indirectly as system clock
ganlikun 0:13413ea9a877 548 * (if the Clock Security System CSS is enabled).
ganlikun 0:13413ea9a877 549 *
ganlikun 0:13413ea9a877 550 * @note A switch from one clock source to another occurs only if the target
ganlikun 0:13413ea9a877 551 * clock source is ready (clock stable after startup delay or PLL locked).
ganlikun 0:13413ea9a877 552 * If a clock source which is not yet ready is selected, the switch will
ganlikun 0:13413ea9a877 553 * occur when the clock source will be ready.
ganlikun 0:13413ea9a877 554 *
ganlikun 0:13413ea9a877 555 * @note Depending on the device voltage range, the software has to set correctly
ganlikun 0:13413ea9a877 556 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
ganlikun 0:13413ea9a877 557 * (for more details refer to section above "Initialization/de-initialization functions")
ganlikun 0:13413ea9a877 558 * @retval None
ganlikun 0:13413ea9a877 559 */
ganlikun 0:13413ea9a877 560 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
ganlikun 0:13413ea9a877 561 {
ganlikun 0:13413ea9a877 562 uint32_t tickstart = 0U;
ganlikun 0:13413ea9a877 563
ganlikun 0:13413ea9a877 564 /* Check the parameters */
ganlikun 0:13413ea9a877 565 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
ganlikun 0:13413ea9a877 566 assert_param(IS_FLASH_LATENCY(FLatency));
ganlikun 0:13413ea9a877 567
ganlikun 0:13413ea9a877 568 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
ganlikun 0:13413ea9a877 569 must be correctly programmed according to the frequency of the CPU clock
ganlikun 0:13413ea9a877 570 (HCLK) and the supply voltage of the device. */
ganlikun 0:13413ea9a877 571
ganlikun 0:13413ea9a877 572 /* Increasing the number of wait states because of higher CPU frequency */
ganlikun 0:13413ea9a877 573 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
ganlikun 0:13413ea9a877 574 {
ganlikun 0:13413ea9a877 575 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
ganlikun 0:13413ea9a877 576 __HAL_FLASH_SET_LATENCY(FLatency);
ganlikun 0:13413ea9a877 577
ganlikun 0:13413ea9a877 578 /* Check that the new number of wait states is taken into account to access the Flash
ganlikun 0:13413ea9a877 579 memory by reading the FLASH_ACR register */
ganlikun 0:13413ea9a877 580 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
ganlikun 0:13413ea9a877 581 {
ganlikun 0:13413ea9a877 582 return HAL_ERROR;
ganlikun 0:13413ea9a877 583 }
ganlikun 0:13413ea9a877 584 }
ganlikun 0:13413ea9a877 585
ganlikun 0:13413ea9a877 586 /*-------------------------- HCLK Configuration --------------------------*/
ganlikun 0:13413ea9a877 587 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
ganlikun 0:13413ea9a877 588 {
ganlikun 0:13413ea9a877 589 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
ganlikun 0:13413ea9a877 590 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
ganlikun 0:13413ea9a877 591 }
ganlikun 0:13413ea9a877 592
ganlikun 0:13413ea9a877 593 /*------------------------- SYSCLK Configuration ---------------------------*/
ganlikun 0:13413ea9a877 594 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
ganlikun 0:13413ea9a877 595 {
ganlikun 0:13413ea9a877 596 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
ganlikun 0:13413ea9a877 597
ganlikun 0:13413ea9a877 598 /* HSE is selected as System Clock Source */
ganlikun 0:13413ea9a877 599 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
ganlikun 0:13413ea9a877 600 {
ganlikun 0:13413ea9a877 601 /* Check the HSE ready flag */
ganlikun 0:13413ea9a877 602 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
ganlikun 0:13413ea9a877 603 {
ganlikun 0:13413ea9a877 604 return HAL_ERROR;
ganlikun 0:13413ea9a877 605 }
ganlikun 0:13413ea9a877 606 }
ganlikun 0:13413ea9a877 607 /* PLL is selected as System Clock Source */
ganlikun 0:13413ea9a877 608 else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
ganlikun 0:13413ea9a877 609 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
ganlikun 0:13413ea9a877 610 {
ganlikun 0:13413ea9a877 611 /* Check the PLL ready flag */
ganlikun 0:13413ea9a877 612 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
ganlikun 0:13413ea9a877 613 {
ganlikun 0:13413ea9a877 614 return HAL_ERROR;
ganlikun 0:13413ea9a877 615 }
ganlikun 0:13413ea9a877 616 }
ganlikun 0:13413ea9a877 617 /* HSI is selected as System Clock Source */
ganlikun 0:13413ea9a877 618 else
ganlikun 0:13413ea9a877 619 {
ganlikun 0:13413ea9a877 620 /* Check the HSI ready flag */
ganlikun 0:13413ea9a877 621 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
ganlikun 0:13413ea9a877 622 {
ganlikun 0:13413ea9a877 623 return HAL_ERROR;
ganlikun 0:13413ea9a877 624 }
ganlikun 0:13413ea9a877 625 }
ganlikun 0:13413ea9a877 626
ganlikun 0:13413ea9a877 627 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
ganlikun 0:13413ea9a877 628 /* Get Start Tick*/
ganlikun 0:13413ea9a877 629 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 630
ganlikun 0:13413ea9a877 631 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
ganlikun 0:13413ea9a877 632 {
ganlikun 0:13413ea9a877 633 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
ganlikun 0:13413ea9a877 634 {
ganlikun 0:13413ea9a877 635 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 636 {
ganlikun 0:13413ea9a877 637 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 638 }
ganlikun 0:13413ea9a877 639 }
ganlikun 0:13413ea9a877 640 }
ganlikun 0:13413ea9a877 641 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
ganlikun 0:13413ea9a877 642 {
ganlikun 0:13413ea9a877 643 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
ganlikun 0:13413ea9a877 644 {
ganlikun 0:13413ea9a877 645 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 646 {
ganlikun 0:13413ea9a877 647 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 648 }
ganlikun 0:13413ea9a877 649 }
ganlikun 0:13413ea9a877 650 }
ganlikun 0:13413ea9a877 651 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
ganlikun 0:13413ea9a877 652 {
ganlikun 0:13413ea9a877 653 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
ganlikun 0:13413ea9a877 654 {
ganlikun 0:13413ea9a877 655 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 656 {
ganlikun 0:13413ea9a877 657 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 658 }
ganlikun 0:13413ea9a877 659 }
ganlikun 0:13413ea9a877 660 }
ganlikun 0:13413ea9a877 661 else
ganlikun 0:13413ea9a877 662 {
ganlikun 0:13413ea9a877 663 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
ganlikun 0:13413ea9a877 664 {
ganlikun 0:13413ea9a877 665 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
ganlikun 0:13413ea9a877 666 {
ganlikun 0:13413ea9a877 667 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 668 }
ganlikun 0:13413ea9a877 669 }
ganlikun 0:13413ea9a877 670 }
ganlikun 0:13413ea9a877 671 }
ganlikun 0:13413ea9a877 672
ganlikun 0:13413ea9a877 673 /* Decreasing the number of wait states because of lower CPU frequency */
ganlikun 0:13413ea9a877 674 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
ganlikun 0:13413ea9a877 675 {
ganlikun 0:13413ea9a877 676 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
ganlikun 0:13413ea9a877 677 __HAL_FLASH_SET_LATENCY(FLatency);
ganlikun 0:13413ea9a877 678
ganlikun 0:13413ea9a877 679 /* Check that the new number of wait states is taken into account to access the Flash
ganlikun 0:13413ea9a877 680 memory by reading the FLASH_ACR register */
ganlikun 0:13413ea9a877 681 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
ganlikun 0:13413ea9a877 682 {
ganlikun 0:13413ea9a877 683 return HAL_ERROR;
ganlikun 0:13413ea9a877 684 }
ganlikun 0:13413ea9a877 685 }
ganlikun 0:13413ea9a877 686
ganlikun 0:13413ea9a877 687 /*-------------------------- PCLK1 Configuration ---------------------------*/
ganlikun 0:13413ea9a877 688 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
ganlikun 0:13413ea9a877 689 {
ganlikun 0:13413ea9a877 690 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
ganlikun 0:13413ea9a877 691 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
ganlikun 0:13413ea9a877 692 }
ganlikun 0:13413ea9a877 693
ganlikun 0:13413ea9a877 694 /*-------------------------- PCLK2 Configuration ---------------------------*/
ganlikun 0:13413ea9a877 695 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
ganlikun 0:13413ea9a877 696 {
ganlikun 0:13413ea9a877 697 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
ganlikun 0:13413ea9a877 698 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
ganlikun 0:13413ea9a877 699 }
ganlikun 0:13413ea9a877 700
ganlikun 0:13413ea9a877 701 /* Update the SystemCoreClock global variable */
ganlikun 0:13413ea9a877 702 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
ganlikun 0:13413ea9a877 703
ganlikun 0:13413ea9a877 704 /* Configure the source of time base considering new system clocks settings*/
ganlikun 0:13413ea9a877 705 HAL_InitTick (TICK_INT_PRIORITY);
ganlikun 0:13413ea9a877 706
ganlikun 0:13413ea9a877 707 return HAL_OK;
ganlikun 0:13413ea9a877 708 }
ganlikun 0:13413ea9a877 709
ganlikun 0:13413ea9a877 710 /**
ganlikun 0:13413ea9a877 711 * @}
ganlikun 0:13413ea9a877 712 */
ganlikun 0:13413ea9a877 713
ganlikun 0:13413ea9a877 714 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
ganlikun 0:13413ea9a877 715 * @brief RCC clocks control functions
ganlikun 0:13413ea9a877 716 *
ganlikun 0:13413ea9a877 717 @verbatim
ganlikun 0:13413ea9a877 718 ===============================================================================
ganlikun 0:13413ea9a877 719 ##### Peripheral Control functions #####
ganlikun 0:13413ea9a877 720 ===============================================================================
ganlikun 0:13413ea9a877 721 [..]
ganlikun 0:13413ea9a877 722 This subsection provides a set of functions allowing to control the RCC Clocks
ganlikun 0:13413ea9a877 723 frequencies.
ganlikun 0:13413ea9a877 724
ganlikun 0:13413ea9a877 725 @endverbatim
ganlikun 0:13413ea9a877 726 * @{
ganlikun 0:13413ea9a877 727 */
ganlikun 0:13413ea9a877 728
ganlikun 0:13413ea9a877 729 /**
ganlikun 0:13413ea9a877 730 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
ganlikun 0:13413ea9a877 731 * @note PA8/PC9 should be configured in alternate function mode.
ganlikun 0:13413ea9a877 732 * @param RCC_MCOx: specifies the output direction for the clock source.
ganlikun 0:13413ea9a877 733 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 734 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
ganlikun 0:13413ea9a877 735 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
ganlikun 0:13413ea9a877 736 * @param RCC_MCOSource: specifies the clock source to output.
ganlikun 0:13413ea9a877 737 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 738 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
ganlikun 0:13413ea9a877 739 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
ganlikun 0:13413ea9a877 740 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
ganlikun 0:13413ea9a877 741 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
ganlikun 0:13413ea9a877 742 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
ganlikun 0:13413ea9a877 743 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
ganlikun 0:13413ea9a877 744 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
ganlikun 0:13413ea9a877 745 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
ganlikun 0:13413ea9a877 746 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
ganlikun 0:13413ea9a877 747 * @param RCC_MCODiv: specifies the MCOx prescaler.
ganlikun 0:13413ea9a877 748 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 749 * @arg RCC_MCODIV_1: no division applied to MCOx clock
ganlikun 0:13413ea9a877 750 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
ganlikun 0:13413ea9a877 751 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
ganlikun 0:13413ea9a877 752 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
ganlikun 0:13413ea9a877 753 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
ganlikun 0:13413ea9a877 754 * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
ganlikun 0:13413ea9a877 755 * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
ganlikun 0:13413ea9a877 756 * @retval None
ganlikun 0:13413ea9a877 757 */
ganlikun 0:13413ea9a877 758 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
ganlikun 0:13413ea9a877 759 {
ganlikun 0:13413ea9a877 760 GPIO_InitTypeDef GPIO_InitStruct;
ganlikun 0:13413ea9a877 761 /* Check the parameters */
ganlikun 0:13413ea9a877 762 assert_param(IS_RCC_MCO(RCC_MCOx));
ganlikun 0:13413ea9a877 763 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
ganlikun 0:13413ea9a877 764 /* RCC_MCO1 */
ganlikun 0:13413ea9a877 765 if(RCC_MCOx == RCC_MCO1)
ganlikun 0:13413ea9a877 766 {
ganlikun 0:13413ea9a877 767 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
ganlikun 0:13413ea9a877 768
ganlikun 0:13413ea9a877 769 /* MCO1 Clock Enable */
ganlikun 0:13413ea9a877 770 __MCO1_CLK_ENABLE();
ganlikun 0:13413ea9a877 771
ganlikun 0:13413ea9a877 772 /* Configure the MCO1 pin in alternate function mode */
ganlikun 0:13413ea9a877 773 GPIO_InitStruct.Pin = MCO1_PIN;
ganlikun 0:13413ea9a877 774 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
ganlikun 0:13413ea9a877 775 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
ganlikun 0:13413ea9a877 776 GPIO_InitStruct.Pull = GPIO_NOPULL;
ganlikun 0:13413ea9a877 777 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
ganlikun 0:13413ea9a877 778 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
ganlikun 0:13413ea9a877 779
ganlikun 0:13413ea9a877 780 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
ganlikun 0:13413ea9a877 781 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
ganlikun 0:13413ea9a877 782
ganlikun 0:13413ea9a877 783 /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
ganlikun 0:13413ea9a877 784 #if defined(RCC_CFGR_MCO1EN)
ganlikun 0:13413ea9a877 785 __HAL_RCC_MCO1_ENABLE();
ganlikun 0:13413ea9a877 786 #endif /* RCC_CFGR_MCO1EN */
ganlikun 0:13413ea9a877 787 }
ganlikun 0:13413ea9a877 788 #if defined(RCC_CFGR_MCO2)
ganlikun 0:13413ea9a877 789 else
ganlikun 0:13413ea9a877 790 {
ganlikun 0:13413ea9a877 791 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
ganlikun 0:13413ea9a877 792
ganlikun 0:13413ea9a877 793 /* MCO2 Clock Enable */
ganlikun 0:13413ea9a877 794 __MCO2_CLK_ENABLE();
ganlikun 0:13413ea9a877 795
ganlikun 0:13413ea9a877 796 /* Configure the MCO2 pin in alternate function mode */
ganlikun 0:13413ea9a877 797 GPIO_InitStruct.Pin = MCO2_PIN;
ganlikun 0:13413ea9a877 798 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
ganlikun 0:13413ea9a877 799 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
ganlikun 0:13413ea9a877 800 GPIO_InitStruct.Pull = GPIO_NOPULL;
ganlikun 0:13413ea9a877 801 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
ganlikun 0:13413ea9a877 802 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
ganlikun 0:13413ea9a877 803
ganlikun 0:13413ea9a877 804 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
ganlikun 0:13413ea9a877 805 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
ganlikun 0:13413ea9a877 806
ganlikun 0:13413ea9a877 807 /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
ganlikun 0:13413ea9a877 808 #if defined(RCC_CFGR_MCO2EN)
ganlikun 0:13413ea9a877 809 __HAL_RCC_MCO2_ENABLE();
ganlikun 0:13413ea9a877 810 #endif /* RCC_CFGR_MCO2EN */
ganlikun 0:13413ea9a877 811 }
ganlikun 0:13413ea9a877 812 #endif /* RCC_CFGR_MCO2 */
ganlikun 0:13413ea9a877 813 }
ganlikun 0:13413ea9a877 814
ganlikun 0:13413ea9a877 815 /**
ganlikun 0:13413ea9a877 816 * @brief Enables the Clock Security System.
ganlikun 0:13413ea9a877 817 * @note If a failure is detected on the HSE oscillator clock, this oscillator
ganlikun 0:13413ea9a877 818 * is automatically disabled and an interrupt is generated to inform the
ganlikun 0:13413ea9a877 819 * software about the failure (Clock Security System Interrupt, CSSI),
ganlikun 0:13413ea9a877 820 * allowing the MCU to perform rescue operations. The CSSI is linked to
ganlikun 0:13413ea9a877 821 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
ganlikun 0:13413ea9a877 822 * @retval None
ganlikun 0:13413ea9a877 823 */
ganlikun 0:13413ea9a877 824 void HAL_RCC_EnableCSS(void)
ganlikun 0:13413ea9a877 825 {
ganlikun 0:13413ea9a877 826 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
ganlikun 0:13413ea9a877 827 }
ganlikun 0:13413ea9a877 828
ganlikun 0:13413ea9a877 829 /**
ganlikun 0:13413ea9a877 830 * @brief Disables the Clock Security System.
ganlikun 0:13413ea9a877 831 * @retval None
ganlikun 0:13413ea9a877 832 */
ganlikun 0:13413ea9a877 833 void HAL_RCC_DisableCSS(void)
ganlikun 0:13413ea9a877 834 {
ganlikun 0:13413ea9a877 835 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
ganlikun 0:13413ea9a877 836 }
ganlikun 0:13413ea9a877 837
ganlikun 0:13413ea9a877 838 /**
ganlikun 0:13413ea9a877 839 * @brief Returns the SYSCLK frequency
ganlikun 0:13413ea9a877 840 *
ganlikun 0:13413ea9a877 841 * @note The system frequency computed by this function is not the real
ganlikun 0:13413ea9a877 842 * frequency in the chip. It is calculated based on the predefined
ganlikun 0:13413ea9a877 843 * constant and the selected clock source:
ganlikun 0:13413ea9a877 844 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
ganlikun 0:13413ea9a877 845 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
ganlikun 0:13413ea9a877 846 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
ganlikun 0:13413ea9a877 847 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
ganlikun 0:13413ea9a877 848 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
ganlikun 0:13413ea9a877 849 * 16 MHz) but the real value may vary depending on the variations
ganlikun 0:13413ea9a877 850 * in voltage and temperature.
ganlikun 0:13413ea9a877 851 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
ganlikun 0:13413ea9a877 852 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
ganlikun 0:13413ea9a877 853 * frequency of the crystal used. Otherwise, this function may
ganlikun 0:13413ea9a877 854 * have wrong result.
ganlikun 0:13413ea9a877 855 *
ganlikun 0:13413ea9a877 856 * @note The result of this function could be not correct when using fractional
ganlikun 0:13413ea9a877 857 * value for HSE crystal.
ganlikun 0:13413ea9a877 858 *
ganlikun 0:13413ea9a877 859 * @note This function can be used by the user application to compute the
ganlikun 0:13413ea9a877 860 * baudrate for the communication peripherals or configure other parameters.
ganlikun 0:13413ea9a877 861 *
ganlikun 0:13413ea9a877 862 * @note Each time SYSCLK changes, this function must be called to update the
ganlikun 0:13413ea9a877 863 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
ganlikun 0:13413ea9a877 864 *
ganlikun 0:13413ea9a877 865 *
ganlikun 0:13413ea9a877 866 * @retval SYSCLK frequency
ganlikun 0:13413ea9a877 867 */
ganlikun 0:13413ea9a877 868 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
ganlikun 0:13413ea9a877 869 {
ganlikun 0:13413ea9a877 870 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
ganlikun 0:13413ea9a877 871 uint32_t sysclockfreq = 0U;
ganlikun 0:13413ea9a877 872
ganlikun 0:13413ea9a877 873 /* Get SYSCLK source -------------------------------------------------------*/
ganlikun 0:13413ea9a877 874 switch (RCC->CFGR & RCC_CFGR_SWS)
ganlikun 0:13413ea9a877 875 {
ganlikun 0:13413ea9a877 876 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
ganlikun 0:13413ea9a877 877 {
ganlikun 0:13413ea9a877 878 sysclockfreq = HSI_VALUE;
ganlikun 0:13413ea9a877 879 break;
ganlikun 0:13413ea9a877 880 }
ganlikun 0:13413ea9a877 881 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
ganlikun 0:13413ea9a877 882 {
ganlikun 0:13413ea9a877 883 sysclockfreq = HSE_VALUE;
ganlikun 0:13413ea9a877 884 break;
ganlikun 0:13413ea9a877 885 }
ganlikun 0:13413ea9a877 886 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
ganlikun 0:13413ea9a877 887 {
ganlikun 0:13413ea9a877 888 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
ganlikun 0:13413ea9a877 889 SYSCLK = PLL_VCO / PLLP */
ganlikun 0:13413ea9a877 890 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
ganlikun 0:13413ea9a877 891 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
ganlikun 0:13413ea9a877 892 {
ganlikun 0:13413ea9a877 893 /* HSE used as PLL clock source */
ganlikun 0:13413ea9a877 894 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
ganlikun 0:13413ea9a877 895 }
ganlikun 0:13413ea9a877 896 else
ganlikun 0:13413ea9a877 897 {
ganlikun 0:13413ea9a877 898 /* HSI used as PLL clock source */
ganlikun 0:13413ea9a877 899 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
ganlikun 0:13413ea9a877 900 }
ganlikun 0:13413ea9a877 901 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
ganlikun 0:13413ea9a877 902
ganlikun 0:13413ea9a877 903 sysclockfreq = pllvco/pllp;
ganlikun 0:13413ea9a877 904 break;
ganlikun 0:13413ea9a877 905 }
ganlikun 0:13413ea9a877 906 default:
ganlikun 0:13413ea9a877 907 {
ganlikun 0:13413ea9a877 908 sysclockfreq = HSI_VALUE;
ganlikun 0:13413ea9a877 909 break;
ganlikun 0:13413ea9a877 910 }
ganlikun 0:13413ea9a877 911 }
ganlikun 0:13413ea9a877 912 return sysclockfreq;
ganlikun 0:13413ea9a877 913 }
ganlikun 0:13413ea9a877 914
ganlikun 0:13413ea9a877 915 /**
ganlikun 0:13413ea9a877 916 * @brief Returns the HCLK frequency
ganlikun 0:13413ea9a877 917 * @note Each time HCLK changes, this function must be called to update the
ganlikun 0:13413ea9a877 918 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
ganlikun 0:13413ea9a877 919 *
ganlikun 0:13413ea9a877 920 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
ganlikun 0:13413ea9a877 921 * and updated within this function
ganlikun 0:13413ea9a877 922 * @retval HCLK frequency
ganlikun 0:13413ea9a877 923 */
ganlikun 0:13413ea9a877 924 uint32_t HAL_RCC_GetHCLKFreq(void)
ganlikun 0:13413ea9a877 925 {
ganlikun 0:13413ea9a877 926 return SystemCoreClock;
ganlikun 0:13413ea9a877 927 }
ganlikun 0:13413ea9a877 928
ganlikun 0:13413ea9a877 929 /**
ganlikun 0:13413ea9a877 930 * @brief Returns the PCLK1 frequency
ganlikun 0:13413ea9a877 931 * @note Each time PCLK1 changes, this function must be called to update the
ganlikun 0:13413ea9a877 932 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
ganlikun 0:13413ea9a877 933 * @retval PCLK1 frequency
ganlikun 0:13413ea9a877 934 */
ganlikun 0:13413ea9a877 935 uint32_t HAL_RCC_GetPCLK1Freq(void)
ganlikun 0:13413ea9a877 936 {
ganlikun 0:13413ea9a877 937 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
ganlikun 0:13413ea9a877 938 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
ganlikun 0:13413ea9a877 939 }
ganlikun 0:13413ea9a877 940
ganlikun 0:13413ea9a877 941 /**
ganlikun 0:13413ea9a877 942 * @brief Returns the PCLK2 frequency
ganlikun 0:13413ea9a877 943 * @note Each time PCLK2 changes, this function must be called to update the
ganlikun 0:13413ea9a877 944 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
ganlikun 0:13413ea9a877 945 * @retval PCLK2 frequency
ganlikun 0:13413ea9a877 946 */
ganlikun 0:13413ea9a877 947 uint32_t HAL_RCC_GetPCLK2Freq(void)
ganlikun 0:13413ea9a877 948 {
ganlikun 0:13413ea9a877 949 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
ganlikun 0:13413ea9a877 950 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
ganlikun 0:13413ea9a877 951 }
ganlikun 0:13413ea9a877 952
ganlikun 0:13413ea9a877 953 /**
ganlikun 0:13413ea9a877 954 * @brief Configures the RCC_OscInitStruct according to the internal
ganlikun 0:13413ea9a877 955 * RCC configuration registers.
ganlikun 0:13413ea9a877 956 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
ganlikun 0:13413ea9a877 957 * will be configured.
ganlikun 0:13413ea9a877 958 * @retval None
ganlikun 0:13413ea9a877 959 */
ganlikun 0:13413ea9a877 960 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
ganlikun 0:13413ea9a877 961 {
ganlikun 0:13413ea9a877 962 /* Set all possible values for the Oscillator type parameter ---------------*/
ganlikun 0:13413ea9a877 963 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
ganlikun 0:13413ea9a877 964
ganlikun 0:13413ea9a877 965 /* Get the HSE configuration -----------------------------------------------*/
ganlikun 0:13413ea9a877 966 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
ganlikun 0:13413ea9a877 967 {
ganlikun 0:13413ea9a877 968 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
ganlikun 0:13413ea9a877 969 }
ganlikun 0:13413ea9a877 970 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
ganlikun 0:13413ea9a877 971 {
ganlikun 0:13413ea9a877 972 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
ganlikun 0:13413ea9a877 973 }
ganlikun 0:13413ea9a877 974 else
ganlikun 0:13413ea9a877 975 {
ganlikun 0:13413ea9a877 976 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
ganlikun 0:13413ea9a877 977 }
ganlikun 0:13413ea9a877 978
ganlikun 0:13413ea9a877 979 /* Get the HSI configuration -----------------------------------------------*/
ganlikun 0:13413ea9a877 980 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
ganlikun 0:13413ea9a877 981 {
ganlikun 0:13413ea9a877 982 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
ganlikun 0:13413ea9a877 983 }
ganlikun 0:13413ea9a877 984 else
ganlikun 0:13413ea9a877 985 {
ganlikun 0:13413ea9a877 986 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
ganlikun 0:13413ea9a877 987 }
ganlikun 0:13413ea9a877 988
ganlikun 0:13413ea9a877 989 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
ganlikun 0:13413ea9a877 990
ganlikun 0:13413ea9a877 991 /* Get the LSE configuration -----------------------------------------------*/
ganlikun 0:13413ea9a877 992 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
ganlikun 0:13413ea9a877 993 {
ganlikun 0:13413ea9a877 994 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
ganlikun 0:13413ea9a877 995 }
ganlikun 0:13413ea9a877 996 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
ganlikun 0:13413ea9a877 997 {
ganlikun 0:13413ea9a877 998 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
ganlikun 0:13413ea9a877 999 }
ganlikun 0:13413ea9a877 1000 else
ganlikun 0:13413ea9a877 1001 {
ganlikun 0:13413ea9a877 1002 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
ganlikun 0:13413ea9a877 1003 }
ganlikun 0:13413ea9a877 1004
ganlikun 0:13413ea9a877 1005 /* Get the LSI configuration -----------------------------------------------*/
ganlikun 0:13413ea9a877 1006 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
ganlikun 0:13413ea9a877 1007 {
ganlikun 0:13413ea9a877 1008 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
ganlikun 0:13413ea9a877 1009 }
ganlikun 0:13413ea9a877 1010 else
ganlikun 0:13413ea9a877 1011 {
ganlikun 0:13413ea9a877 1012 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
ganlikun 0:13413ea9a877 1013 }
ganlikun 0:13413ea9a877 1014
ganlikun 0:13413ea9a877 1015 /* Get the PLL configuration -----------------------------------------------*/
ganlikun 0:13413ea9a877 1016 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
ganlikun 0:13413ea9a877 1017 {
ganlikun 0:13413ea9a877 1018 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
ganlikun 0:13413ea9a877 1019 }
ganlikun 0:13413ea9a877 1020 else
ganlikun 0:13413ea9a877 1021 {
ganlikun 0:13413ea9a877 1022 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
ganlikun 0:13413ea9a877 1023 }
ganlikun 0:13413ea9a877 1024 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
ganlikun 0:13413ea9a877 1025 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
ganlikun 0:13413ea9a877 1026 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
ganlikun 0:13413ea9a877 1027 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
ganlikun 0:13413ea9a877 1028 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
ganlikun 0:13413ea9a877 1029 }
ganlikun 0:13413ea9a877 1030
ganlikun 0:13413ea9a877 1031 /**
ganlikun 0:13413ea9a877 1032 * @brief Configures the RCC_ClkInitStruct according to the internal
ganlikun 0:13413ea9a877 1033 * RCC configuration registers.
ganlikun 0:13413ea9a877 1034 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
ganlikun 0:13413ea9a877 1035 * will be configured.
ganlikun 0:13413ea9a877 1036 * @param pFLatency: Pointer on the Flash Latency.
ganlikun 0:13413ea9a877 1037 * @retval None
ganlikun 0:13413ea9a877 1038 */
ganlikun 0:13413ea9a877 1039 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
ganlikun 0:13413ea9a877 1040 {
ganlikun 0:13413ea9a877 1041 /* Set all possible values for the Clock type parameter --------------------*/
ganlikun 0:13413ea9a877 1042 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
ganlikun 0:13413ea9a877 1043
ganlikun 0:13413ea9a877 1044 /* Get the SYSCLK configuration --------------------------------------------*/
ganlikun 0:13413ea9a877 1045 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
ganlikun 0:13413ea9a877 1046
ganlikun 0:13413ea9a877 1047 /* Get the HCLK configuration ----------------------------------------------*/
ganlikun 0:13413ea9a877 1048 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
ganlikun 0:13413ea9a877 1049
ganlikun 0:13413ea9a877 1050 /* Get the APB1 configuration ----------------------------------------------*/
ganlikun 0:13413ea9a877 1051 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
ganlikun 0:13413ea9a877 1052
ganlikun 0:13413ea9a877 1053 /* Get the APB2 configuration ----------------------------------------------*/
ganlikun 0:13413ea9a877 1054 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
ganlikun 0:13413ea9a877 1055
ganlikun 0:13413ea9a877 1056 /* Get the Flash Wait State (Latency) configuration ------------------------*/
ganlikun 0:13413ea9a877 1057 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
ganlikun 0:13413ea9a877 1058 }
ganlikun 0:13413ea9a877 1059
ganlikun 0:13413ea9a877 1060 /**
ganlikun 0:13413ea9a877 1061 * @brief This function handles the RCC CSS interrupt request.
ganlikun 0:13413ea9a877 1062 * @note This API should be called under the NMI_Handler().
ganlikun 0:13413ea9a877 1063 * @retval None
ganlikun 0:13413ea9a877 1064 */
ganlikun 0:13413ea9a877 1065 void HAL_RCC_NMI_IRQHandler(void)
ganlikun 0:13413ea9a877 1066 {
ganlikun 0:13413ea9a877 1067 /* Check RCC CSSF flag */
ganlikun 0:13413ea9a877 1068 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
ganlikun 0:13413ea9a877 1069 {
ganlikun 0:13413ea9a877 1070 /* RCC Clock Security System interrupt user callback */
ganlikun 0:13413ea9a877 1071 HAL_RCC_CSSCallback();
ganlikun 0:13413ea9a877 1072
ganlikun 0:13413ea9a877 1073 /* Clear RCC CSS pending bit */
ganlikun 0:13413ea9a877 1074 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
ganlikun 0:13413ea9a877 1075 }
ganlikun 0:13413ea9a877 1076 }
ganlikun 0:13413ea9a877 1077
ganlikun 0:13413ea9a877 1078 /**
ganlikun 0:13413ea9a877 1079 * @brief RCC Clock Security System interrupt callback
ganlikun 0:13413ea9a877 1080 * @retval None
ganlikun 0:13413ea9a877 1081 */
ganlikun 0:13413ea9a877 1082 __weak void HAL_RCC_CSSCallback(void)
ganlikun 0:13413ea9a877 1083 {
ganlikun 0:13413ea9a877 1084 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1085 the HAL_RCC_CSSCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1086 */
ganlikun 0:13413ea9a877 1087 }
ganlikun 0:13413ea9a877 1088
ganlikun 0:13413ea9a877 1089 /**
ganlikun 0:13413ea9a877 1090 * @}
ganlikun 0:13413ea9a877 1091 */
ganlikun 0:13413ea9a877 1092
ganlikun 0:13413ea9a877 1093 /**
ganlikun 0:13413ea9a877 1094 * @}
ganlikun 0:13413ea9a877 1095 */
ganlikun 0:13413ea9a877 1096
ganlikun 0:13413ea9a877 1097 #endif /* HAL_RCC_MODULE_ENABLED */
ganlikun 0:13413ea9a877 1098 /**
ganlikun 0:13413ea9a877 1099 * @}
ganlikun 0:13413ea9a877 1100 */
ganlikun 0:13413ea9a877 1101
ganlikun 0:13413ea9a877 1102 /**
ganlikun 0:13413ea9a877 1103 * @}
ganlikun 0:13413ea9a877 1104 */
ganlikun 0:13413ea9a877 1105
ganlikun 0:13413ea9a877 1106 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 1107