Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_hal_qspi.c
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief QSPI HAL module driver.
ganlikun 0:13413ea9a877 8 * This file provides firmware functions to manage the following
ganlikun 0:13413ea9a877 9 * functionalities of the QuadSPI interface (QSPI).
ganlikun 0:13413ea9a877 10 * + Initialization and de-initialization functions
ganlikun 0:13413ea9a877 11 * + Indirect functional mode management
ganlikun 0:13413ea9a877 12 * + Memory-mapped functional mode management
ganlikun 0:13413ea9a877 13 * + Auto-polling functional mode management
ganlikun 0:13413ea9a877 14 * + Interrupts and flags management
ganlikun 0:13413ea9a877 15 * + DMA channel configuration for indirect functional mode
ganlikun 0:13413ea9a877 16 * + Errors management and abort functionality
ganlikun 0:13413ea9a877 17 *
ganlikun 0:13413ea9a877 18 *
ganlikun 0:13413ea9a877 19 @verbatim
ganlikun 0:13413ea9a877 20 ===============================================================================
ganlikun 0:13413ea9a877 21 ##### How to use this driver #####
ganlikun 0:13413ea9a877 22 ===============================================================================
ganlikun 0:13413ea9a877 23 [..]
ganlikun 0:13413ea9a877 24 *** Initialization ***
ganlikun 0:13413ea9a877 25 ======================
ganlikun 0:13413ea9a877 26 [..]
ganlikun 0:13413ea9a877 27 (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
ganlikun 0:13413ea9a877 28 (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
ganlikun 0:13413ea9a877 29 (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
ganlikun 0:13413ea9a877 30 (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
ganlikun 0:13413ea9a877 31 (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
ganlikun 0:13413ea9a877 32 (++) If interrupt mode is used, enable and configure QuadSPI global
ganlikun 0:13413ea9a877 33 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
ganlikun 0:13413ea9a877 34 (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
ganlikun 0:13413ea9a877 35 with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
ganlikun 0:13413ea9a877 36 link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
ganlikun 0:13413ea9a877 37 DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
ganlikun 0:13413ea9a877 38 (#) Configure the flash size, the clock prescaler, the fifo threshold, the
ganlikun 0:13413ea9a877 39 clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
ganlikun 0:13413ea9a877 40
ganlikun 0:13413ea9a877 41 *** Indirect functional mode ***
ganlikun 0:13413ea9a877 42 ================================
ganlikun 0:13413ea9a877 43 [..]
ganlikun 0:13413ea9a877 44 (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
ganlikun 0:13413ea9a877 45 functions :
ganlikun 0:13413ea9a877 46 (++) Instruction phase : the mode used and if present the instruction opcode.
ganlikun 0:13413ea9a877 47 (++) Address phase : the mode used and if present the size and the address value.
ganlikun 0:13413ea9a877 48 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
ganlikun 0:13413ea9a877 49 bytes values.
ganlikun 0:13413ea9a877 50 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
ganlikun 0:13413ea9a877 51 (++) Data phase : the mode used and if present the number of bytes.
ganlikun 0:13413ea9a877 52 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
ganlikun 0:13413ea9a877 53 if activated.
ganlikun 0:13413ea9a877 54 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
ganlikun 0:13413ea9a877 55 (#) If no data is required for the command, it is sent directly to the memory :
ganlikun 0:13413ea9a877 56 (++) In polling mode, the output of the function is done when the transfer is complete.
ganlikun 0:13413ea9a877 57 (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
ganlikun 0:13413ea9a877 58 (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
ganlikun 0:13413ea9a877 59 HAL_QSPI_Transmit_IT() after the command configuration :
ganlikun 0:13413ea9a877 60 (++) In polling mode, the output of the function is done when the transfer is complete.
ganlikun 0:13413ea9a877 61 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
ganlikun 0:13413ea9a877 62 is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
ganlikun 0:13413ea9a877 63 (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
ganlikun 0:13413ea9a877 64 HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
ganlikun 0:13413ea9a877 65 (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
ganlikun 0:13413ea9a877 66 HAL_QSPI_Receive_IT() after the command configuration :
ganlikun 0:13413ea9a877 67 (++) In polling mode, the output of the function is done when the transfer is complete.
ganlikun 0:13413ea9a877 68 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
ganlikun 0:13413ea9a877 69 is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
ganlikun 0:13413ea9a877 70 (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
ganlikun 0:13413ea9a877 71 HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
ganlikun 0:13413ea9a877 72
ganlikun 0:13413ea9a877 73 *** Auto-polling functional mode ***
ganlikun 0:13413ea9a877 74 ====================================
ganlikun 0:13413ea9a877 75 [..]
ganlikun 0:13413ea9a877 76 (#) Configure the command sequence and the auto-polling functional mode using the
ganlikun 0:13413ea9a877 77 HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
ganlikun 0:13413ea9a877 78 (++) Instruction phase : the mode used and if present the instruction opcode.
ganlikun 0:13413ea9a877 79 (++) Address phase : the mode used and if present the size and the address value.
ganlikun 0:13413ea9a877 80 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
ganlikun 0:13413ea9a877 81 bytes values.
ganlikun 0:13413ea9a877 82 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
ganlikun 0:13413ea9a877 83 (++) Data phase : the mode used.
ganlikun 0:13413ea9a877 84 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
ganlikun 0:13413ea9a877 85 if activated.
ganlikun 0:13413ea9a877 86 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
ganlikun 0:13413ea9a877 87 (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
ganlikun 0:13413ea9a877 88 the polling interval and the automatic stop activation.
ganlikun 0:13413ea9a877 89 (#) After the configuration :
ganlikun 0:13413ea9a877 90 (++) In polling mode, the output of the function is done when the status match is reached. The
ganlikun 0:13413ea9a877 91 automatic stop is activated to avoid an infinite loop.
ganlikun 0:13413ea9a877 92 (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
ganlikun 0:13413ea9a877 93
ganlikun 0:13413ea9a877 94 *** Memory-mapped functional mode ***
ganlikun 0:13413ea9a877 95 =====================================
ganlikun 0:13413ea9a877 96 [..]
ganlikun 0:13413ea9a877 97 (#) Configure the command sequence and the memory-mapped functional mode using the
ganlikun 0:13413ea9a877 98 HAL_QSPI_MemoryMapped() functions :
ganlikun 0:13413ea9a877 99 (++) Instruction phase : the mode used and if present the instruction opcode.
ganlikun 0:13413ea9a877 100 (++) Address phase : the mode used and the size.
ganlikun 0:13413ea9a877 101 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
ganlikun 0:13413ea9a877 102 bytes values.
ganlikun 0:13413ea9a877 103 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
ganlikun 0:13413ea9a877 104 (++) Data phase : the mode used.
ganlikun 0:13413ea9a877 105 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
ganlikun 0:13413ea9a877 106 if activated.
ganlikun 0:13413ea9a877 107 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
ganlikun 0:13413ea9a877 108 (++) The timeout activation and the timeout period.
ganlikun 0:13413ea9a877 109 (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
ganlikun 0:13413ea9a877 110 the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
ganlikun 0:13413ea9a877 111
ganlikun 0:13413ea9a877 112 *** Errors management and abort functionality ***
ganlikun 0:13413ea9a877 113 ==================================================
ganlikun 0:13413ea9a877 114 [..]
ganlikun 0:13413ea9a877 115 (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
ganlikun 0:13413ea9a877 116 (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
ganlikun 0:13413ea9a877 117 flushes the fifo :
ganlikun 0:13413ea9a877 118 (++) In polling mode, the output of the function is done when the transfer
ganlikun 0:13413ea9a877 119 complete bit is set and the busy bit cleared.
ganlikun 0:13413ea9a877 120 (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
ganlikun 0:13413ea9a877 121 the transfer complete bi is set.
ganlikun 0:13413ea9a877 122
ganlikun 0:13413ea9a877 123 *** Control functions ***
ganlikun 0:13413ea9a877 124 =========================
ganlikun 0:13413ea9a877 125 [..]
ganlikun 0:13413ea9a877 126 (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
ganlikun 0:13413ea9a877 127 (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
ganlikun 0:13413ea9a877 128 (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
ganlikun 0:13413ea9a877 129 (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
ganlikun 0:13413ea9a877 130
ganlikun 0:13413ea9a877 131 *** Workarounds linked to Silicon Limitation ***
ganlikun 0:13413ea9a877 132 ====================================================
ganlikun 0:13413ea9a877 133 [..]
ganlikun 0:13413ea9a877 134 (#) Workarounds Implemented inside HAL Driver
ganlikun 0:13413ea9a877 135 (++) Extra data written in the FIFO at the end of a read transfer
ganlikun 0:13413ea9a877 136
ganlikun 0:13413ea9a877 137 @endverbatim
ganlikun 0:13413ea9a877 138 ******************************************************************************
ganlikun 0:13413ea9a877 139 * @attention
ganlikun 0:13413ea9a877 140 *
ganlikun 0:13413ea9a877 141 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 142 *
ganlikun 0:13413ea9a877 143 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 144 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 145 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 146 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 147 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 148 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 149 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 150 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 151 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 152 * without specific prior written permission.
ganlikun 0:13413ea9a877 153 *
ganlikun 0:13413ea9a877 154 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 155 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 156 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 157 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 158 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 159 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 160 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 161 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 162 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 163 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 164 *
ganlikun 0:13413ea9a877 165 ******************************************************************************
ganlikun 0:13413ea9a877 166 */
ganlikun 0:13413ea9a877 167
ganlikun 0:13413ea9a877 168 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 169 #include "stm32f4xx_hal.h"
ganlikun 0:13413ea9a877 170
ganlikun 0:13413ea9a877 171 /** @addtogroup STM32F4xx_HAL_Driver
ganlikun 0:13413ea9a877 172 * @{
ganlikun 0:13413ea9a877 173 */
ganlikun 0:13413ea9a877 174
ganlikun 0:13413ea9a877 175 /** @defgroup QSPI QSPI
ganlikun 0:13413ea9a877 176 * @brief QSPI HAL module driver
ganlikun 0:13413ea9a877 177 * @{
ganlikun 0:13413ea9a877 178 */
ganlikun 0:13413ea9a877 179 #ifdef HAL_QSPI_MODULE_ENABLED
ganlikun 0:13413ea9a877 180
ganlikun 0:13413ea9a877 181 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
ganlikun 0:13413ea9a877 182 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
ganlikun 0:13413ea9a877 183
ganlikun 0:13413ea9a877 184 /* Private typedef -----------------------------------------------------------*/
ganlikun 0:13413ea9a877 185 /* Private define ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 186 /** @addtogroup QSPI_Private_Constants
ganlikun 0:13413ea9a877 187 * @{
ganlikun 0:13413ea9a877 188 */
ganlikun 0:13413ea9a877 189 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
ganlikun 0:13413ea9a877 190 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
ganlikun 0:13413ea9a877 191 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
ganlikun 0:13413ea9a877 192 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
ganlikun 0:13413ea9a877 193 /**
ganlikun 0:13413ea9a877 194 * @}
ganlikun 0:13413ea9a877 195 */
ganlikun 0:13413ea9a877 196
ganlikun 0:13413ea9a877 197 /* Private macro -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 198 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
ganlikun 0:13413ea9a877 199 * @{
ganlikun 0:13413ea9a877 200 */
ganlikun 0:13413ea9a877 201 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
ganlikun 0:13413ea9a877 202 ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
ganlikun 0:13413ea9a877 203 ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
ganlikun 0:13413ea9a877 204 ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
ganlikun 0:13413ea9a877 205 /**
ganlikun 0:13413ea9a877 206 * @}
ganlikun 0:13413ea9a877 207 */
ganlikun 0:13413ea9a877 208
ganlikun 0:13413ea9a877 209 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 210 /* Private function prototypes -----------------------------------------------*/
ganlikun 0:13413ea9a877 211 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
ganlikun 0:13413ea9a877 212 * @{
ganlikun 0:13413ea9a877 213 */
ganlikun 0:13413ea9a877 214 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
ganlikun 0:13413ea9a877 215 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
ganlikun 0:13413ea9a877 216 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
ganlikun 0:13413ea9a877 217 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
ganlikun 0:13413ea9a877 218 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
ganlikun 0:13413ea9a877 219 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
ganlikun 0:13413ea9a877 220 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
ganlikun 0:13413ea9a877 221 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
ganlikun 0:13413ea9a877 222 /**
ganlikun 0:13413ea9a877 223 * @}
ganlikun 0:13413ea9a877 224 */
ganlikun 0:13413ea9a877 225
ganlikun 0:13413ea9a877 226 /* Exported functions ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 227
ganlikun 0:13413ea9a877 228 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
ganlikun 0:13413ea9a877 229 * @{
ganlikun 0:13413ea9a877 230 */
ganlikun 0:13413ea9a877 231
ganlikun 0:13413ea9a877 232 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
ganlikun 0:13413ea9a877 233 * @brief Initialization and Configuration functions
ganlikun 0:13413ea9a877 234 *
ganlikun 0:13413ea9a877 235 @verbatim
ganlikun 0:13413ea9a877 236 ===============================================================================
ganlikun 0:13413ea9a877 237 ##### Initialization and Configuration functions #####
ganlikun 0:13413ea9a877 238 ===============================================================================
ganlikun 0:13413ea9a877 239 [..]
ganlikun 0:13413ea9a877 240 This subsection provides a set of functions allowing to :
ganlikun 0:13413ea9a877 241 (+) Initialize the QuadSPI.
ganlikun 0:13413ea9a877 242 (+) De-initialize the QuadSPI.
ganlikun 0:13413ea9a877 243
ganlikun 0:13413ea9a877 244 @endverbatim
ganlikun 0:13413ea9a877 245 * @{
ganlikun 0:13413ea9a877 246 */
ganlikun 0:13413ea9a877 247
ganlikun 0:13413ea9a877 248 /**
ganlikun 0:13413ea9a877 249 * @brief Initializes the QSPI mode according to the specified parameters
ganlikun 0:13413ea9a877 250 * in the QSPI_InitTypeDef and creates the associated handle.
ganlikun 0:13413ea9a877 251 * @param hqspi: qspi handle
ganlikun 0:13413ea9a877 252 * @retval HAL status
ganlikun 0:13413ea9a877 253 */
ganlikun 0:13413ea9a877 254 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 255 {
ganlikun 0:13413ea9a877 256 HAL_StatusTypeDef status = HAL_ERROR;
ganlikun 0:13413ea9a877 257 uint32_t tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 258
ganlikun 0:13413ea9a877 259 /* Check the QSPI handle allocation */
ganlikun 0:13413ea9a877 260 if(hqspi == NULL)
ganlikun 0:13413ea9a877 261 {
ganlikun 0:13413ea9a877 262 return HAL_ERROR;
ganlikun 0:13413ea9a877 263 }
ganlikun 0:13413ea9a877 264
ganlikun 0:13413ea9a877 265 /* Check the parameters */
ganlikun 0:13413ea9a877 266 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
ganlikun 0:13413ea9a877 267 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
ganlikun 0:13413ea9a877 268 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
ganlikun 0:13413ea9a877 269 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
ganlikun 0:13413ea9a877 270 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
ganlikun 0:13413ea9a877 271 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
ganlikun 0:13413ea9a877 272 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
ganlikun 0:13413ea9a877 273 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
ganlikun 0:13413ea9a877 274
ganlikun 0:13413ea9a877 275 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
ganlikun 0:13413ea9a877 276 {
ganlikun 0:13413ea9a877 277 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
ganlikun 0:13413ea9a877 278 }
ganlikun 0:13413ea9a877 279
ganlikun 0:13413ea9a877 280 /* Process locked */
ganlikun 0:13413ea9a877 281 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 282
ganlikun 0:13413ea9a877 283 if(hqspi->State == HAL_QSPI_STATE_RESET)
ganlikun 0:13413ea9a877 284 {
ganlikun 0:13413ea9a877 285 /* Allocate lock resource and initialize it */
ganlikun 0:13413ea9a877 286 hqspi->Lock = HAL_UNLOCKED;
ganlikun 0:13413ea9a877 287
ganlikun 0:13413ea9a877 288 /* Init the low level hardware : GPIO, CLOCK */
ganlikun 0:13413ea9a877 289 HAL_QSPI_MspInit(hqspi);
ganlikun 0:13413ea9a877 290
ganlikun 0:13413ea9a877 291 /* Configure the default timeout for the QSPI memory access */
ganlikun 0:13413ea9a877 292 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
ganlikun 0:13413ea9a877 293 }
ganlikun 0:13413ea9a877 294
ganlikun 0:13413ea9a877 295 /* Configure QSPI FIFO Threshold */
ganlikun 0:13413ea9a877 296 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U));
ganlikun 0:13413ea9a877 297
ganlikun 0:13413ea9a877 298 /* Wait till BUSY flag reset */
ganlikun 0:13413ea9a877 299 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
ganlikun 0:13413ea9a877 300
ganlikun 0:13413ea9a877 301 if(status == HAL_OK)
ganlikun 0:13413ea9a877 302 {
ganlikun 0:13413ea9a877 303
ganlikun 0:13413ea9a877 304 /* Configure QSPI Clock Prescaler and Sample Shift */
ganlikun 0:13413ea9a877 305 MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
ganlikun 0:13413ea9a877 306
ganlikun 0:13413ea9a877 307 /* Configure QSPI Flash Size, CS High Time and Clock Mode */
ganlikun 0:13413ea9a877 308 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
ganlikun 0:13413ea9a877 309 ((hqspi->Init.FlashSize << 16U) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
ganlikun 0:13413ea9a877 310
ganlikun 0:13413ea9a877 311 /* Enable the QSPI peripheral */
ganlikun 0:13413ea9a877 312 __HAL_QSPI_ENABLE(hqspi);
ganlikun 0:13413ea9a877 313
ganlikun 0:13413ea9a877 314 /* Set QSPI error code to none */
ganlikun 0:13413ea9a877 315 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 316
ganlikun 0:13413ea9a877 317 /* Initialize the QSPI state */
ganlikun 0:13413ea9a877 318 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 319 }
ganlikun 0:13413ea9a877 320
ganlikun 0:13413ea9a877 321 /* Release Lock */
ganlikun 0:13413ea9a877 322 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 323
ganlikun 0:13413ea9a877 324 /* Return function status */
ganlikun 0:13413ea9a877 325 return status;
ganlikun 0:13413ea9a877 326 }
ganlikun 0:13413ea9a877 327
ganlikun 0:13413ea9a877 328 /**
ganlikun 0:13413ea9a877 329 * @brief DeInitializes the QSPI peripheral
ganlikun 0:13413ea9a877 330 * @param hqspi: qspi handle
ganlikun 0:13413ea9a877 331 * @retval HAL status
ganlikun 0:13413ea9a877 332 */
ganlikun 0:13413ea9a877 333 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 334 {
ganlikun 0:13413ea9a877 335 /* Check the QSPI handle allocation */
ganlikun 0:13413ea9a877 336 if(hqspi == NULL)
ganlikun 0:13413ea9a877 337 {
ganlikun 0:13413ea9a877 338 return HAL_ERROR;
ganlikun 0:13413ea9a877 339 }
ganlikun 0:13413ea9a877 340
ganlikun 0:13413ea9a877 341 /* Process locked */
ganlikun 0:13413ea9a877 342 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 343
ganlikun 0:13413ea9a877 344 /* Disable the QSPI Peripheral Clock */
ganlikun 0:13413ea9a877 345 __HAL_QSPI_DISABLE(hqspi);
ganlikun 0:13413ea9a877 346
ganlikun 0:13413ea9a877 347 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
ganlikun 0:13413ea9a877 348 HAL_QSPI_MspDeInit(hqspi);
ganlikun 0:13413ea9a877 349
ganlikun 0:13413ea9a877 350 /* Set QSPI error code to none */
ganlikun 0:13413ea9a877 351 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 352
ganlikun 0:13413ea9a877 353 /* Initialize the QSPI state */
ganlikun 0:13413ea9a877 354 hqspi->State = HAL_QSPI_STATE_RESET;
ganlikun 0:13413ea9a877 355
ganlikun 0:13413ea9a877 356 /* Release Lock */
ganlikun 0:13413ea9a877 357 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 358
ganlikun 0:13413ea9a877 359 return HAL_OK;
ganlikun 0:13413ea9a877 360 }
ganlikun 0:13413ea9a877 361
ganlikun 0:13413ea9a877 362 /**
ganlikun 0:13413ea9a877 363 * @brief QSPI MSP Init
ganlikun 0:13413ea9a877 364 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 365 * @retval None
ganlikun 0:13413ea9a877 366 */
ganlikun 0:13413ea9a877 367 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 368 {
ganlikun 0:13413ea9a877 369 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 370 UNUSED(hqspi);
ganlikun 0:13413ea9a877 371
ganlikun 0:13413ea9a877 372 /* NOTE : This function should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 373 the HAL_QSPI_MspInit can be implemented in the user file
ganlikun 0:13413ea9a877 374 */
ganlikun 0:13413ea9a877 375 }
ganlikun 0:13413ea9a877 376
ganlikun 0:13413ea9a877 377 /**
ganlikun 0:13413ea9a877 378 * @brief QSPI MSP DeInit
ganlikun 0:13413ea9a877 379 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 380 * @retval None
ganlikun 0:13413ea9a877 381 */
ganlikun 0:13413ea9a877 382 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 383 {
ganlikun 0:13413ea9a877 384 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 385 UNUSED(hqspi);
ganlikun 0:13413ea9a877 386
ganlikun 0:13413ea9a877 387 /* NOTE : This function should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 388 the HAL_QSPI_MspDeInit can be implemented in the user file
ganlikun 0:13413ea9a877 389 */
ganlikun 0:13413ea9a877 390 }
ganlikun 0:13413ea9a877 391
ganlikun 0:13413ea9a877 392 /**
ganlikun 0:13413ea9a877 393 * @}
ganlikun 0:13413ea9a877 394 */
ganlikun 0:13413ea9a877 395
ganlikun 0:13413ea9a877 396 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
ganlikun 0:13413ea9a877 397 * @brief QSPI Transmit/Receive functions
ganlikun 0:13413ea9a877 398 *
ganlikun 0:13413ea9a877 399 @verbatim
ganlikun 0:13413ea9a877 400 ===============================================================================
ganlikun 0:13413ea9a877 401 ##### IO operation functions #####
ganlikun 0:13413ea9a877 402 ===============================================================================
ganlikun 0:13413ea9a877 403 [..]
ganlikun 0:13413ea9a877 404 This subsection provides a set of functions allowing to :
ganlikun 0:13413ea9a877 405 (+) Handle the interrupts.
ganlikun 0:13413ea9a877 406 (+) Handle the command sequence.
ganlikun 0:13413ea9a877 407 (+) Transmit data in blocking, interrupt or DMA mode.
ganlikun 0:13413ea9a877 408 (+) Receive data in blocking, interrupt or DMA mode.
ganlikun 0:13413ea9a877 409 (+) Manage the auto-polling functional mode.
ganlikun 0:13413ea9a877 410 (+) Manage the memory-mapped functional mode.
ganlikun 0:13413ea9a877 411
ganlikun 0:13413ea9a877 412 @endverbatim
ganlikun 0:13413ea9a877 413 * @{
ganlikun 0:13413ea9a877 414 */
ganlikun 0:13413ea9a877 415
ganlikun 0:13413ea9a877 416 /**
ganlikun 0:13413ea9a877 417 * @brief This function handles QSPI interrupt request.
ganlikun 0:13413ea9a877 418 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 419 * @retval None.
ganlikun 0:13413ea9a877 420 */
ganlikun 0:13413ea9a877 421 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 422 {
ganlikun 0:13413ea9a877 423 __IO uint32_t *data_reg;
ganlikun 0:13413ea9a877 424 uint32_t flag = READ_REG(hqspi->Instance->SR);
ganlikun 0:13413ea9a877 425 uint32_t itsource = READ_REG(hqspi->Instance->CR);
ganlikun 0:13413ea9a877 426
ganlikun 0:13413ea9a877 427 /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
ganlikun 0:13413ea9a877 428 if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
ganlikun 0:13413ea9a877 429 {
ganlikun 0:13413ea9a877 430 data_reg = &hqspi->Instance->DR;
ganlikun 0:13413ea9a877 431
ganlikun 0:13413ea9a877 432 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
ganlikun 0:13413ea9a877 433 {
ganlikun 0:13413ea9a877 434 /* Transmission process */
ganlikun 0:13413ea9a877 435 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
ganlikun 0:13413ea9a877 436 {
ganlikun 0:13413ea9a877 437 if (hqspi->TxXferCount > 0U)
ganlikun 0:13413ea9a877 438 {
ganlikun 0:13413ea9a877 439 /* Fill the FIFO until it is full */
ganlikun 0:13413ea9a877 440 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
ganlikun 0:13413ea9a877 441 hqspi->TxXferCount--;
ganlikun 0:13413ea9a877 442 }
ganlikun 0:13413ea9a877 443 else
ganlikun 0:13413ea9a877 444 {
ganlikun 0:13413ea9a877 445 /* No more data available for the transfer */
ganlikun 0:13413ea9a877 446 /* Disable the QSPI FIFO Threshold Interrupt */
ganlikun 0:13413ea9a877 447 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
ganlikun 0:13413ea9a877 448 break;
ganlikun 0:13413ea9a877 449 }
ganlikun 0:13413ea9a877 450 }
ganlikun 0:13413ea9a877 451 }
ganlikun 0:13413ea9a877 452 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
ganlikun 0:13413ea9a877 453 {
ganlikun 0:13413ea9a877 454 /* Receiving Process */
ganlikun 0:13413ea9a877 455 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
ganlikun 0:13413ea9a877 456 {
ganlikun 0:13413ea9a877 457 if (hqspi->RxXferCount > 0U)
ganlikun 0:13413ea9a877 458 {
ganlikun 0:13413ea9a877 459 /* Read the FIFO until it is empty */
ganlikun 0:13413ea9a877 460 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
ganlikun 0:13413ea9a877 461 hqspi->RxXferCount--;
ganlikun 0:13413ea9a877 462 }
ganlikun 0:13413ea9a877 463 else
ganlikun 0:13413ea9a877 464 {
ganlikun 0:13413ea9a877 465 /* All data have been received for the transfer */
ganlikun 0:13413ea9a877 466 /* Disable the QSPI FIFO Threshold Interrupt */
ganlikun 0:13413ea9a877 467 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
ganlikun 0:13413ea9a877 468 break;
ganlikun 0:13413ea9a877 469 }
ganlikun 0:13413ea9a877 470 }
ganlikun 0:13413ea9a877 471 }
ganlikun 0:13413ea9a877 472
ganlikun 0:13413ea9a877 473 /* FIFO Threshold callback */
ganlikun 0:13413ea9a877 474 HAL_QSPI_FifoThresholdCallback(hqspi);
ganlikun 0:13413ea9a877 475 }
ganlikun 0:13413ea9a877 476
ganlikun 0:13413ea9a877 477 /* QSPI Transfer Complete interrupt occurred -------------------------------*/
ganlikun 0:13413ea9a877 478 else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
ganlikun 0:13413ea9a877 479 {
ganlikun 0:13413ea9a877 480 /* Clear interrupt */
ganlikun 0:13413ea9a877 481 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 482
ganlikun 0:13413ea9a877 483 /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
ganlikun 0:13413ea9a877 484 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
ganlikun 0:13413ea9a877 485
ganlikun 0:13413ea9a877 486 /* Transfer complete callback */
ganlikun 0:13413ea9a877 487 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
ganlikun 0:13413ea9a877 488 {
ganlikun 0:13413ea9a877 489 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
ganlikun 0:13413ea9a877 490 {
ganlikun 0:13413ea9a877 491 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 492 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 493
ganlikun 0:13413ea9a877 494 /* Disable the DMA channel */
ganlikun 0:13413ea9a877 495 __HAL_DMA_DISABLE(hqspi->hdma);
ganlikun 0:13413ea9a877 496 }
ganlikun 0:13413ea9a877 497
ganlikun 0:13413ea9a877 498 /* Clear Busy bit */
ganlikun 0:13413ea9a877 499 HAL_QSPI_Abort_IT(hqspi);
ganlikun 0:13413ea9a877 500
ganlikun 0:13413ea9a877 501 /* Change state of QSPI */
ganlikun 0:13413ea9a877 502 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 503
ganlikun 0:13413ea9a877 504 /* TX Complete callback */
ganlikun 0:13413ea9a877 505 HAL_QSPI_TxCpltCallback(hqspi);
ganlikun 0:13413ea9a877 506 }
ganlikun 0:13413ea9a877 507 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
ganlikun 0:13413ea9a877 508 {
ganlikun 0:13413ea9a877 509 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
ganlikun 0:13413ea9a877 510 {
ganlikun 0:13413ea9a877 511 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 512 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 513
ganlikun 0:13413ea9a877 514 /* Disable the DMA channel */
ganlikun 0:13413ea9a877 515 __HAL_DMA_DISABLE(hqspi->hdma);
ganlikun 0:13413ea9a877 516 }
ganlikun 0:13413ea9a877 517 else
ganlikun 0:13413ea9a877 518 {
ganlikun 0:13413ea9a877 519 data_reg = &hqspi->Instance->DR;
ganlikun 0:13413ea9a877 520 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
ganlikun 0:13413ea9a877 521 {
ganlikun 0:13413ea9a877 522 if (hqspi->RxXferCount > 0U)
ganlikun 0:13413ea9a877 523 {
ganlikun 0:13413ea9a877 524 /* Read the last data received in the FIFO until it is empty */
ganlikun 0:13413ea9a877 525 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
ganlikun 0:13413ea9a877 526 hqspi->RxXferCount--;
ganlikun 0:13413ea9a877 527 }
ganlikun 0:13413ea9a877 528 else
ganlikun 0:13413ea9a877 529 {
ganlikun 0:13413ea9a877 530 /* All data have been received for the transfer */
ganlikun 0:13413ea9a877 531 break;
ganlikun 0:13413ea9a877 532 }
ganlikun 0:13413ea9a877 533 }
ganlikun 0:13413ea9a877 534 }
ganlikun 0:13413ea9a877 535 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
ganlikun 0:13413ea9a877 536 HAL_QSPI_Abort_IT(hqspi);
ganlikun 0:13413ea9a877 537
ganlikun 0:13413ea9a877 538 /* Change state of QSPI */
ganlikun 0:13413ea9a877 539 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 540
ganlikun 0:13413ea9a877 541 /* RX Complete callback */
ganlikun 0:13413ea9a877 542 HAL_QSPI_RxCpltCallback(hqspi);
ganlikun 0:13413ea9a877 543 }
ganlikun 0:13413ea9a877 544 else if(hqspi->State == HAL_QSPI_STATE_BUSY)
ganlikun 0:13413ea9a877 545 {
ganlikun 0:13413ea9a877 546 /* Change state of QSPI */
ganlikun 0:13413ea9a877 547 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 548
ganlikun 0:13413ea9a877 549 /* Command Complete callback */
ganlikun 0:13413ea9a877 550 HAL_QSPI_CmdCpltCallback(hqspi);
ganlikun 0:13413ea9a877 551 }
ganlikun 0:13413ea9a877 552 else if(hqspi->State == HAL_QSPI_STATE_ABORT)
ganlikun 0:13413ea9a877 553 {
ganlikun 0:13413ea9a877 554 /* Change state of QSPI */
ganlikun 0:13413ea9a877 555 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 556
ganlikun 0:13413ea9a877 557 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
ganlikun 0:13413ea9a877 558 {
ganlikun 0:13413ea9a877 559 /* Abort called by the user */
ganlikun 0:13413ea9a877 560
ganlikun 0:13413ea9a877 561 /* Abort Complete callback */
ganlikun 0:13413ea9a877 562 HAL_QSPI_AbortCpltCallback(hqspi);
ganlikun 0:13413ea9a877 563 }
ganlikun 0:13413ea9a877 564 else
ganlikun 0:13413ea9a877 565 {
ganlikun 0:13413ea9a877 566 /* Abort due to an error (eg : DMA error) */
ganlikun 0:13413ea9a877 567
ganlikun 0:13413ea9a877 568 /* Error callback */
ganlikun 0:13413ea9a877 569 HAL_QSPI_ErrorCallback(hqspi);
ganlikun 0:13413ea9a877 570 }
ganlikun 0:13413ea9a877 571 }
ganlikun 0:13413ea9a877 572 }
ganlikun 0:13413ea9a877 573
ganlikun 0:13413ea9a877 574 /* QSPI Status Match interrupt occurred ------------------------------------*/
ganlikun 0:13413ea9a877 575 else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
ganlikun 0:13413ea9a877 576 {
ganlikun 0:13413ea9a877 577 /* Clear interrupt */
ganlikun 0:13413ea9a877 578 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
ganlikun 0:13413ea9a877 579
ganlikun 0:13413ea9a877 580 /* Check if the automatic poll mode stop is activated */
ganlikun 0:13413ea9a877 581 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
ganlikun 0:13413ea9a877 582 {
ganlikun 0:13413ea9a877 583 /* Disable the QSPI Transfer Error and Status Match Interrupts */
ganlikun 0:13413ea9a877 584 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
ganlikun 0:13413ea9a877 585
ganlikun 0:13413ea9a877 586 /* Change state of QSPI */
ganlikun 0:13413ea9a877 587 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 588 }
ganlikun 0:13413ea9a877 589
ganlikun 0:13413ea9a877 590 /* Status match callback */
ganlikun 0:13413ea9a877 591 HAL_QSPI_StatusMatchCallback(hqspi);
ganlikun 0:13413ea9a877 592 }
ganlikun 0:13413ea9a877 593
ganlikun 0:13413ea9a877 594 /* QSPI Transfer Error interrupt occurred ----------------------------------*/
ganlikun 0:13413ea9a877 595 else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
ganlikun 0:13413ea9a877 596 {
ganlikun 0:13413ea9a877 597 /* Clear interrupt */
ganlikun 0:13413ea9a877 598 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
ganlikun 0:13413ea9a877 599
ganlikun 0:13413ea9a877 600 /* Disable all the QSPI Interrupts */
ganlikun 0:13413ea9a877 601 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
ganlikun 0:13413ea9a877 602
ganlikun 0:13413ea9a877 603 /* Set error code */
ganlikun 0:13413ea9a877 604 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
ganlikun 0:13413ea9a877 605
ganlikun 0:13413ea9a877 606 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
ganlikun 0:13413ea9a877 607 {
ganlikun 0:13413ea9a877 608 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 609 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 610
ganlikun 0:13413ea9a877 611 /* Disable the DMA channel */
ganlikun 0:13413ea9a877 612 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
ganlikun 0:13413ea9a877 613 HAL_DMA_Abort_IT(hqspi->hdma);
ganlikun 0:13413ea9a877 614 }
ganlikun 0:13413ea9a877 615 else
ganlikun 0:13413ea9a877 616 {
ganlikun 0:13413ea9a877 617 /* Change state of QSPI */
ganlikun 0:13413ea9a877 618 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 619
ganlikun 0:13413ea9a877 620 /* Error callback */
ganlikun 0:13413ea9a877 621 HAL_QSPI_ErrorCallback(hqspi);
ganlikun 0:13413ea9a877 622 }
ganlikun 0:13413ea9a877 623 }
ganlikun 0:13413ea9a877 624
ganlikun 0:13413ea9a877 625 /* QSPI Timeout interrupt occurred -----------------------------------------*/
ganlikun 0:13413ea9a877 626 else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
ganlikun 0:13413ea9a877 627 {
ganlikun 0:13413ea9a877 628 /* Clear interrupt */
ganlikun 0:13413ea9a877 629 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
ganlikun 0:13413ea9a877 630
ganlikun 0:13413ea9a877 631 /* Time out callback */
ganlikun 0:13413ea9a877 632 HAL_QSPI_TimeOutCallback(hqspi);
ganlikun 0:13413ea9a877 633 }
ganlikun 0:13413ea9a877 634 }
ganlikun 0:13413ea9a877 635
ganlikun 0:13413ea9a877 636 /**
ganlikun 0:13413ea9a877 637 * @brief Sets the command configuration.
ganlikun 0:13413ea9a877 638 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 639 * @param cmd : structure that contains the command configuration information
ganlikun 0:13413ea9a877 640 * @param Timeout : Time out duration
ganlikun 0:13413ea9a877 641 * @note This function is used only in Indirect Read or Write Modes
ganlikun 0:13413ea9a877 642 * @retval HAL status
ganlikun 0:13413ea9a877 643 */
ganlikun 0:13413ea9a877 644 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
ganlikun 0:13413ea9a877 645 {
ganlikun 0:13413ea9a877 646 HAL_StatusTypeDef status = HAL_ERROR;
ganlikun 0:13413ea9a877 647 uint32_t tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 648
ganlikun 0:13413ea9a877 649 /* Check the parameters */
ganlikun 0:13413ea9a877 650 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
ganlikun 0:13413ea9a877 651 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
ganlikun 0:13413ea9a877 652 {
ganlikun 0:13413ea9a877 653 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
ganlikun 0:13413ea9a877 654 }
ganlikun 0:13413ea9a877 655
ganlikun 0:13413ea9a877 656 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
ganlikun 0:13413ea9a877 657 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 658 {
ganlikun 0:13413ea9a877 659 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
ganlikun 0:13413ea9a877 660 }
ganlikun 0:13413ea9a877 661
ganlikun 0:13413ea9a877 662 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
ganlikun 0:13413ea9a877 663 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
ganlikun 0:13413ea9a877 664 {
ganlikun 0:13413ea9a877 665 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
ganlikun 0:13413ea9a877 666 }
ganlikun 0:13413ea9a877 667
ganlikun 0:13413ea9a877 668 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
ganlikun 0:13413ea9a877 669 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
ganlikun 0:13413ea9a877 670
ganlikun 0:13413ea9a877 671 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
ganlikun 0:13413ea9a877 672 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
ganlikun 0:13413ea9a877 673 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
ganlikun 0:13413ea9a877 674
ganlikun 0:13413ea9a877 675 /* Process locked */
ganlikun 0:13413ea9a877 676 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 677
ganlikun 0:13413ea9a877 678 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 679 {
ganlikun 0:13413ea9a877 680 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 681
ganlikun 0:13413ea9a877 682 /* Update QSPI state */
ganlikun 0:13413ea9a877 683 hqspi->State = HAL_QSPI_STATE_BUSY;
ganlikun 0:13413ea9a877 684
ganlikun 0:13413ea9a877 685 /* Wait till BUSY flag reset */
ganlikun 0:13413ea9a877 686 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
ganlikun 0:13413ea9a877 687
ganlikun 0:13413ea9a877 688 if (status == HAL_OK)
ganlikun 0:13413ea9a877 689 {
ganlikun 0:13413ea9a877 690 /* Call the configuration function */
ganlikun 0:13413ea9a877 691 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
ganlikun 0:13413ea9a877 692
ganlikun 0:13413ea9a877 693 if (cmd->DataMode == QSPI_DATA_NONE)
ganlikun 0:13413ea9a877 694 {
ganlikun 0:13413ea9a877 695 /* When there is no data phase, the transfer start as soon as the configuration is done
ganlikun 0:13413ea9a877 696 so wait until TC flag is set to go back in idle state */
ganlikun 0:13413ea9a877 697 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
ganlikun 0:13413ea9a877 698
ganlikun 0:13413ea9a877 699 if (status == HAL_OK)
ganlikun 0:13413ea9a877 700 {
ganlikun 0:13413ea9a877 701 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 702
ganlikun 0:13413ea9a877 703 /* Update QSPI state */
ganlikun 0:13413ea9a877 704 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 705 }
ganlikun 0:13413ea9a877 706
ganlikun 0:13413ea9a877 707 }
ganlikun 0:13413ea9a877 708 else
ganlikun 0:13413ea9a877 709 {
ganlikun 0:13413ea9a877 710 /* Update QSPI state */
ganlikun 0:13413ea9a877 711 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 712 }
ganlikun 0:13413ea9a877 713 }
ganlikun 0:13413ea9a877 714 }
ganlikun 0:13413ea9a877 715 else
ganlikun 0:13413ea9a877 716 {
ganlikun 0:13413ea9a877 717 status = HAL_BUSY;
ganlikun 0:13413ea9a877 718 }
ganlikun 0:13413ea9a877 719
ganlikun 0:13413ea9a877 720 /* Process unlocked */
ganlikun 0:13413ea9a877 721 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 722
ganlikun 0:13413ea9a877 723 /* Return function status */
ganlikun 0:13413ea9a877 724 return status;
ganlikun 0:13413ea9a877 725 }
ganlikun 0:13413ea9a877 726
ganlikun 0:13413ea9a877 727 /**
ganlikun 0:13413ea9a877 728 * @brief Sets the command configuration in interrupt mode.
ganlikun 0:13413ea9a877 729 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 730 * @param cmd : structure that contains the command configuration information
ganlikun 0:13413ea9a877 731 * @note This function is used only in Indirect Read or Write Modes
ganlikun 0:13413ea9a877 732 * @retval HAL status
ganlikun 0:13413ea9a877 733 */
ganlikun 0:13413ea9a877 734 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
ganlikun 0:13413ea9a877 735 {
ganlikun 0:13413ea9a877 736 __IO uint32_t count = 0U;
ganlikun 0:13413ea9a877 737 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 738
ganlikun 0:13413ea9a877 739 /* Check the parameters */
ganlikun 0:13413ea9a877 740 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
ganlikun 0:13413ea9a877 741 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
ganlikun 0:13413ea9a877 742 {
ganlikun 0:13413ea9a877 743 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
ganlikun 0:13413ea9a877 744 }
ganlikun 0:13413ea9a877 745
ganlikun 0:13413ea9a877 746 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
ganlikun 0:13413ea9a877 747 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 748 {
ganlikun 0:13413ea9a877 749 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
ganlikun 0:13413ea9a877 750 }
ganlikun 0:13413ea9a877 751
ganlikun 0:13413ea9a877 752 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
ganlikun 0:13413ea9a877 753 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
ganlikun 0:13413ea9a877 754 {
ganlikun 0:13413ea9a877 755 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
ganlikun 0:13413ea9a877 756 }
ganlikun 0:13413ea9a877 757
ganlikun 0:13413ea9a877 758 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
ganlikun 0:13413ea9a877 759 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
ganlikun 0:13413ea9a877 760
ganlikun 0:13413ea9a877 761 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
ganlikun 0:13413ea9a877 762 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
ganlikun 0:13413ea9a877 763 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
ganlikun 0:13413ea9a877 764
ganlikun 0:13413ea9a877 765 /* Process locked */
ganlikun 0:13413ea9a877 766 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 767
ganlikun 0:13413ea9a877 768 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 769 {
ganlikun 0:13413ea9a877 770 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 771
ganlikun 0:13413ea9a877 772 /* Update QSPI state */
ganlikun 0:13413ea9a877 773 hqspi->State = HAL_QSPI_STATE_BUSY;
ganlikun 0:13413ea9a877 774
ganlikun 0:13413ea9a877 775 /* Wait till BUSY flag reset */
ganlikun 0:13413ea9a877 776 count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
ganlikun 0:13413ea9a877 777 do
ganlikun 0:13413ea9a877 778 {
ganlikun 0:13413ea9a877 779 if (count-- == 0U)
ganlikun 0:13413ea9a877 780 {
ganlikun 0:13413ea9a877 781 hqspi->State = HAL_QSPI_STATE_ERROR;
ganlikun 0:13413ea9a877 782 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
ganlikun 0:13413ea9a877 783 status = HAL_TIMEOUT;
ganlikun 0:13413ea9a877 784 }
ganlikun 0:13413ea9a877 785 }
ganlikun 0:13413ea9a877 786 while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
ganlikun 0:13413ea9a877 787
ganlikun 0:13413ea9a877 788 if (status == HAL_OK)
ganlikun 0:13413ea9a877 789 {
ganlikun 0:13413ea9a877 790 if (cmd->DataMode == QSPI_DATA_NONE)
ganlikun 0:13413ea9a877 791 {
ganlikun 0:13413ea9a877 792 /* Clear interrupt */
ganlikun 0:13413ea9a877 793 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 794 }
ganlikun 0:13413ea9a877 795
ganlikun 0:13413ea9a877 796 /* Call the configuration function */
ganlikun 0:13413ea9a877 797 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
ganlikun 0:13413ea9a877 798
ganlikun 0:13413ea9a877 799 if (cmd->DataMode == QSPI_DATA_NONE)
ganlikun 0:13413ea9a877 800 {
ganlikun 0:13413ea9a877 801 /* When there is no data phase, the transfer start as soon as the configuration is done
ganlikun 0:13413ea9a877 802 so activate TC and TE interrupts */
ganlikun 0:13413ea9a877 803 /* Process unlocked */
ganlikun 0:13413ea9a877 804 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 805
ganlikun 0:13413ea9a877 806 /* Enable the QSPI Transfer Error Interrupt */
ganlikun 0:13413ea9a877 807 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
ganlikun 0:13413ea9a877 808 }
ganlikun 0:13413ea9a877 809 else
ganlikun 0:13413ea9a877 810 {
ganlikun 0:13413ea9a877 811 /* Update QSPI state */
ganlikun 0:13413ea9a877 812 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 813
ganlikun 0:13413ea9a877 814 /* Process unlocked */
ganlikun 0:13413ea9a877 815 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 816 }
ganlikun 0:13413ea9a877 817 }
ganlikun 0:13413ea9a877 818 else
ganlikun 0:13413ea9a877 819 {
ganlikun 0:13413ea9a877 820 /* Process unlocked */
ganlikun 0:13413ea9a877 821 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 822 }
ganlikun 0:13413ea9a877 823 }
ganlikun 0:13413ea9a877 824 else
ganlikun 0:13413ea9a877 825 {
ganlikun 0:13413ea9a877 826 status = HAL_BUSY;
ganlikun 0:13413ea9a877 827
ganlikun 0:13413ea9a877 828 /* Process unlocked */
ganlikun 0:13413ea9a877 829 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 830 }
ganlikun 0:13413ea9a877 831
ganlikun 0:13413ea9a877 832 /* Return function status */
ganlikun 0:13413ea9a877 833 return status;
ganlikun 0:13413ea9a877 834 }
ganlikun 0:13413ea9a877 835
ganlikun 0:13413ea9a877 836 /**
ganlikun 0:13413ea9a877 837 * @brief Transmit an amount of data in blocking mode.
ganlikun 0:13413ea9a877 838 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 839 * @param pData: pointer to data buffer
ganlikun 0:13413ea9a877 840 * @param Timeout : Time out duration
ganlikun 0:13413ea9a877 841 * @note This function is used only in Indirect Write Mode
ganlikun 0:13413ea9a877 842 * @retval HAL status
ganlikun 0:13413ea9a877 843 */
ganlikun 0:13413ea9a877 844 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
ganlikun 0:13413ea9a877 845 {
ganlikun 0:13413ea9a877 846 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 847 uint32_t tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 848 __IO uint32_t *data_reg = &hqspi->Instance->DR;
ganlikun 0:13413ea9a877 849
ganlikun 0:13413ea9a877 850 /* Process locked */
ganlikun 0:13413ea9a877 851 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 852
ganlikun 0:13413ea9a877 853 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 854 {
ganlikun 0:13413ea9a877 855 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 856
ganlikun 0:13413ea9a877 857 if(pData != NULL )
ganlikun 0:13413ea9a877 858 {
ganlikun 0:13413ea9a877 859 /* Update state */
ganlikun 0:13413ea9a877 860 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
ganlikun 0:13413ea9a877 861
ganlikun 0:13413ea9a877 862 /* Configure counters and size of the handle */
ganlikun 0:13413ea9a877 863 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 864 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 865 hqspi->pTxBuffPtr = pData;
ganlikun 0:13413ea9a877 866
ganlikun 0:13413ea9a877 867 /* Configure QSPI: CCR register with functional as indirect write */
ganlikun 0:13413ea9a877 868 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
ganlikun 0:13413ea9a877 869
ganlikun 0:13413ea9a877 870 while(hqspi->TxXferCount > 0U)
ganlikun 0:13413ea9a877 871 {
ganlikun 0:13413ea9a877 872 /* Wait until FT flag is set to send data */
ganlikun 0:13413ea9a877 873 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
ganlikun 0:13413ea9a877 874
ganlikun 0:13413ea9a877 875 if (status != HAL_OK)
ganlikun 0:13413ea9a877 876 {
ganlikun 0:13413ea9a877 877 break;
ganlikun 0:13413ea9a877 878 }
ganlikun 0:13413ea9a877 879
ganlikun 0:13413ea9a877 880 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
ganlikun 0:13413ea9a877 881 hqspi->TxXferCount--;
ganlikun 0:13413ea9a877 882 }
ganlikun 0:13413ea9a877 883
ganlikun 0:13413ea9a877 884 if (status == HAL_OK)
ganlikun 0:13413ea9a877 885 {
ganlikun 0:13413ea9a877 886 /* Wait until TC flag is set to go back in idle state */
ganlikun 0:13413ea9a877 887 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
ganlikun 0:13413ea9a877 888
ganlikun 0:13413ea9a877 889 if (status == HAL_OK)
ganlikun 0:13413ea9a877 890 {
ganlikun 0:13413ea9a877 891 /* Clear Transfer Complete bit */
ganlikun 0:13413ea9a877 892 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 893
ganlikun 0:13413ea9a877 894 /* Clear Busy bit */
ganlikun 0:13413ea9a877 895 status = HAL_QSPI_Abort(hqspi);
ganlikun 0:13413ea9a877 896 }
ganlikun 0:13413ea9a877 897 }
ganlikun 0:13413ea9a877 898
ganlikun 0:13413ea9a877 899 /* Update QSPI state */
ganlikun 0:13413ea9a877 900 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 901 }
ganlikun 0:13413ea9a877 902 else
ganlikun 0:13413ea9a877 903 {
ganlikun 0:13413ea9a877 904 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 905 status = HAL_ERROR;
ganlikun 0:13413ea9a877 906 }
ganlikun 0:13413ea9a877 907 }
ganlikun 0:13413ea9a877 908 else
ganlikun 0:13413ea9a877 909 {
ganlikun 0:13413ea9a877 910 status = HAL_BUSY;
ganlikun 0:13413ea9a877 911 }
ganlikun 0:13413ea9a877 912
ganlikun 0:13413ea9a877 913 /* Process unlocked */
ganlikun 0:13413ea9a877 914 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 915
ganlikun 0:13413ea9a877 916 return status;
ganlikun 0:13413ea9a877 917 }
ganlikun 0:13413ea9a877 918
ganlikun 0:13413ea9a877 919
ganlikun 0:13413ea9a877 920 /**
ganlikun 0:13413ea9a877 921 * @brief Receive an amount of data in blocking mode
ganlikun 0:13413ea9a877 922 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 923 * @param pData: pointer to data buffer
ganlikun 0:13413ea9a877 924 * @param Timeout : Time out duration
ganlikun 0:13413ea9a877 925 * @note This function is used only in Indirect Read Mode
ganlikun 0:13413ea9a877 926 * @retval HAL status
ganlikun 0:13413ea9a877 927 */
ganlikun 0:13413ea9a877 928 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
ganlikun 0:13413ea9a877 929 {
ganlikun 0:13413ea9a877 930 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 931 uint32_t tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 932 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
ganlikun 0:13413ea9a877 933 __IO uint32_t *data_reg = &hqspi->Instance->DR;
ganlikun 0:13413ea9a877 934
ganlikun 0:13413ea9a877 935 /* Process locked */
ganlikun 0:13413ea9a877 936 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 937
ganlikun 0:13413ea9a877 938 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 939 {
ganlikun 0:13413ea9a877 940 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 941 if(pData != NULL )
ganlikun 0:13413ea9a877 942 {
ganlikun 0:13413ea9a877 943 /* Update state */
ganlikun 0:13413ea9a877 944 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
ganlikun 0:13413ea9a877 945
ganlikun 0:13413ea9a877 946 /* Configure counters and size of the handle */
ganlikun 0:13413ea9a877 947 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 948 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 949 hqspi->pRxBuffPtr = pData;
ganlikun 0:13413ea9a877 950
ganlikun 0:13413ea9a877 951 /* Configure QSPI: CCR register with functional as indirect read */
ganlikun 0:13413ea9a877 952 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
ganlikun 0:13413ea9a877 953
ganlikun 0:13413ea9a877 954 /* Start the transfer by re-writing the address in AR register */
ganlikun 0:13413ea9a877 955 WRITE_REG(hqspi->Instance->AR, addr_reg);
ganlikun 0:13413ea9a877 956
ganlikun 0:13413ea9a877 957 while(hqspi->RxXferCount > 0U)
ganlikun 0:13413ea9a877 958 {
ganlikun 0:13413ea9a877 959 /* Wait until FT or TC flag is set to read received data */
ganlikun 0:13413ea9a877 960 status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
ganlikun 0:13413ea9a877 961
ganlikun 0:13413ea9a877 962 if (status != HAL_OK)
ganlikun 0:13413ea9a877 963 {
ganlikun 0:13413ea9a877 964 break;
ganlikun 0:13413ea9a877 965 }
ganlikun 0:13413ea9a877 966
ganlikun 0:13413ea9a877 967 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
ganlikun 0:13413ea9a877 968 hqspi->RxXferCount--;
ganlikun 0:13413ea9a877 969 }
ganlikun 0:13413ea9a877 970
ganlikun 0:13413ea9a877 971 if (status == HAL_OK)
ganlikun 0:13413ea9a877 972 {
ganlikun 0:13413ea9a877 973 /* Wait until TC flag is set to go back in idle state */
ganlikun 0:13413ea9a877 974 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
ganlikun 0:13413ea9a877 975
ganlikun 0:13413ea9a877 976 if (status == HAL_OK)
ganlikun 0:13413ea9a877 977 {
ganlikun 0:13413ea9a877 978 /* Clear Transfer Complete bit */
ganlikun 0:13413ea9a877 979 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 980
ganlikun 0:13413ea9a877 981 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
ganlikun 0:13413ea9a877 982 status = HAL_QSPI_Abort(hqspi);
ganlikun 0:13413ea9a877 983 }
ganlikun 0:13413ea9a877 984 }
ganlikun 0:13413ea9a877 985
ganlikun 0:13413ea9a877 986 /* Update QSPI state */
ganlikun 0:13413ea9a877 987 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 988 }
ganlikun 0:13413ea9a877 989 else
ganlikun 0:13413ea9a877 990 {
ganlikun 0:13413ea9a877 991 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 992 status = HAL_ERROR;
ganlikun 0:13413ea9a877 993 }
ganlikun 0:13413ea9a877 994 }
ganlikun 0:13413ea9a877 995 else
ganlikun 0:13413ea9a877 996 {
ganlikun 0:13413ea9a877 997 status = HAL_BUSY;
ganlikun 0:13413ea9a877 998 }
ganlikun 0:13413ea9a877 999
ganlikun 0:13413ea9a877 1000 /* Process unlocked */
ganlikun 0:13413ea9a877 1001 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1002
ganlikun 0:13413ea9a877 1003 return status;
ganlikun 0:13413ea9a877 1004 }
ganlikun 0:13413ea9a877 1005
ganlikun 0:13413ea9a877 1006 /**
ganlikun 0:13413ea9a877 1007 * @brief Send an amount of data in interrupt mode
ganlikun 0:13413ea9a877 1008 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1009 * @param pData: pointer to data buffer
ganlikun 0:13413ea9a877 1010 * @note This function is used only in Indirect Write Mode
ganlikun 0:13413ea9a877 1011 * @retval HAL status
ganlikun 0:13413ea9a877 1012 */
ganlikun 0:13413ea9a877 1013 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
ganlikun 0:13413ea9a877 1014 {
ganlikun 0:13413ea9a877 1015 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 1016
ganlikun 0:13413ea9a877 1017 /* Process locked */
ganlikun 0:13413ea9a877 1018 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 1019
ganlikun 0:13413ea9a877 1020 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 1021 {
ganlikun 0:13413ea9a877 1022 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 1023 if(pData != NULL )
ganlikun 0:13413ea9a877 1024 {
ganlikun 0:13413ea9a877 1025 /* Update state */
ganlikun 0:13413ea9a877 1026 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
ganlikun 0:13413ea9a877 1027
ganlikun 0:13413ea9a877 1028 /* Configure counters and size of the handle */
ganlikun 0:13413ea9a877 1029 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 1030 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 1031 hqspi->pTxBuffPtr = pData;
ganlikun 0:13413ea9a877 1032
ganlikun 0:13413ea9a877 1033 /* Configure QSPI: CCR register with functional as indirect write */
ganlikun 0:13413ea9a877 1034 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
ganlikun 0:13413ea9a877 1035
ganlikun 0:13413ea9a877 1036 /* Clear interrupt */
ganlikun 0:13413ea9a877 1037 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 1038
ganlikun 0:13413ea9a877 1039 /* Process unlocked */
ganlikun 0:13413ea9a877 1040 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1041
ganlikun 0:13413ea9a877 1042 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
ganlikun 0:13413ea9a877 1043 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
ganlikun 0:13413ea9a877 1044
ganlikun 0:13413ea9a877 1045 }
ganlikun 0:13413ea9a877 1046 else
ganlikun 0:13413ea9a877 1047 {
ganlikun 0:13413ea9a877 1048 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1049 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1050
ganlikun 0:13413ea9a877 1051 /* Process unlocked */
ganlikun 0:13413ea9a877 1052 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1053 }
ganlikun 0:13413ea9a877 1054 }
ganlikun 0:13413ea9a877 1055 else
ganlikun 0:13413ea9a877 1056 {
ganlikun 0:13413ea9a877 1057 status = HAL_BUSY;
ganlikun 0:13413ea9a877 1058
ganlikun 0:13413ea9a877 1059 /* Process unlocked */
ganlikun 0:13413ea9a877 1060 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1061 }
ganlikun 0:13413ea9a877 1062
ganlikun 0:13413ea9a877 1063 return status;
ganlikun 0:13413ea9a877 1064 }
ganlikun 0:13413ea9a877 1065
ganlikun 0:13413ea9a877 1066 /**
ganlikun 0:13413ea9a877 1067 * @brief Receive an amount of data in no-blocking mode with Interrupt
ganlikun 0:13413ea9a877 1068 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1069 * @param pData: pointer to data buffer
ganlikun 0:13413ea9a877 1070 * @note This function is used only in Indirect Read Mode
ganlikun 0:13413ea9a877 1071 * @retval HAL status
ganlikun 0:13413ea9a877 1072 */
ganlikun 0:13413ea9a877 1073 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
ganlikun 0:13413ea9a877 1074 {
ganlikun 0:13413ea9a877 1075 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 1076 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
ganlikun 0:13413ea9a877 1077
ganlikun 0:13413ea9a877 1078 /* Process locked */
ganlikun 0:13413ea9a877 1079 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 1080
ganlikun 0:13413ea9a877 1081 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 1082 {
ganlikun 0:13413ea9a877 1083 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 1084
ganlikun 0:13413ea9a877 1085 if(pData != NULL )
ganlikun 0:13413ea9a877 1086 {
ganlikun 0:13413ea9a877 1087 /* Update state */
ganlikun 0:13413ea9a877 1088 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
ganlikun 0:13413ea9a877 1089
ganlikun 0:13413ea9a877 1090 /* Configure counters and size of the handle */
ganlikun 0:13413ea9a877 1091 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 1092 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
ganlikun 0:13413ea9a877 1093 hqspi->pRxBuffPtr = pData;
ganlikun 0:13413ea9a877 1094
ganlikun 0:13413ea9a877 1095 /* Configure QSPI: CCR register with functional as indirect read */
ganlikun 0:13413ea9a877 1096 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
ganlikun 0:13413ea9a877 1097
ganlikun 0:13413ea9a877 1098 /* Start the transfer by re-writing the address in AR register */
ganlikun 0:13413ea9a877 1099 WRITE_REG(hqspi->Instance->AR, addr_reg);
ganlikun 0:13413ea9a877 1100
ganlikun 0:13413ea9a877 1101 /* Clear interrupt */
ganlikun 0:13413ea9a877 1102 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 1103
ganlikun 0:13413ea9a877 1104 /* Process unlocked */
ganlikun 0:13413ea9a877 1105 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1106
ganlikun 0:13413ea9a877 1107 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
ganlikun 0:13413ea9a877 1108 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
ganlikun 0:13413ea9a877 1109 }
ganlikun 0:13413ea9a877 1110 else
ganlikun 0:13413ea9a877 1111 {
ganlikun 0:13413ea9a877 1112 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1113 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1114
ganlikun 0:13413ea9a877 1115 /* Process unlocked */
ganlikun 0:13413ea9a877 1116 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1117 }
ganlikun 0:13413ea9a877 1118 }
ganlikun 0:13413ea9a877 1119 else
ganlikun 0:13413ea9a877 1120 {
ganlikun 0:13413ea9a877 1121 status = HAL_BUSY;
ganlikun 0:13413ea9a877 1122
ganlikun 0:13413ea9a877 1123 /* Process unlocked */
ganlikun 0:13413ea9a877 1124 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1125 }
ganlikun 0:13413ea9a877 1126
ganlikun 0:13413ea9a877 1127 return status;
ganlikun 0:13413ea9a877 1128 }
ganlikun 0:13413ea9a877 1129
ganlikun 0:13413ea9a877 1130 /**
ganlikun 0:13413ea9a877 1131 * @brief Sends an amount of data in non blocking mode with DMA.
ganlikun 0:13413ea9a877 1132 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1133 * @param pData: pointer to data buffer
ganlikun 0:13413ea9a877 1134 * @note This function is used only in Indirect Write Mode
ganlikun 0:13413ea9a877 1135 * @note If DMA peripheral access is configured as halfword, the number
ganlikun 0:13413ea9a877 1136 * of data and the fifo threshold should be aligned on halfword
ganlikun 0:13413ea9a877 1137 * @note If DMA peripheral access is configured as word, the number
ganlikun 0:13413ea9a877 1138 * of data and the fifo threshold should be aligned on word
ganlikun 0:13413ea9a877 1139 * @retval HAL status
ganlikun 0:13413ea9a877 1140 */
ganlikun 0:13413ea9a877 1141 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
ganlikun 0:13413ea9a877 1142 {
ganlikun 0:13413ea9a877 1143 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 1144 uint32_t *tmp;
ganlikun 0:13413ea9a877 1145 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
ganlikun 0:13413ea9a877 1146
ganlikun 0:13413ea9a877 1147 /* Process locked */
ganlikun 0:13413ea9a877 1148 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 1149
ganlikun 0:13413ea9a877 1150 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 1151 {
ganlikun 0:13413ea9a877 1152 /* Clear the error code */
ganlikun 0:13413ea9a877 1153 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 1154
ganlikun 0:13413ea9a877 1155 if(pData != NULL )
ganlikun 0:13413ea9a877 1156 {
ganlikun 0:13413ea9a877 1157 /* Configure counters of the handle */
ganlikun 0:13413ea9a877 1158 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
ganlikun 0:13413ea9a877 1159 {
ganlikun 0:13413ea9a877 1160 hqspi->TxXferCount = data_size;
ganlikun 0:13413ea9a877 1161 }
ganlikun 0:13413ea9a877 1162 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
ganlikun 0:13413ea9a877 1163 {
ganlikun 0:13413ea9a877 1164 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
ganlikun 0:13413ea9a877 1165 {
ganlikun 0:13413ea9a877 1166 /* The number of data or the fifo threshold is not aligned on halfword
ganlikun 0:13413ea9a877 1167 => no transfer possible with DMA peripheral access configured as halfword */
ganlikun 0:13413ea9a877 1168 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1169 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1170
ganlikun 0:13413ea9a877 1171 /* Process unlocked */
ganlikun 0:13413ea9a877 1172 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1173 }
ganlikun 0:13413ea9a877 1174 else
ganlikun 0:13413ea9a877 1175 {
ganlikun 0:13413ea9a877 1176 hqspi->TxXferCount = (data_size >> 1);
ganlikun 0:13413ea9a877 1177 }
ganlikun 0:13413ea9a877 1178 }
ganlikun 0:13413ea9a877 1179 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
ganlikun 0:13413ea9a877 1180 {
ganlikun 0:13413ea9a877 1181 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
ganlikun 0:13413ea9a877 1182 {
ganlikun 0:13413ea9a877 1183 /* The number of data or the fifo threshold is not aligned on word
ganlikun 0:13413ea9a877 1184 => no transfer possible with DMA peripheral access configured as word */
ganlikun 0:13413ea9a877 1185 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1186 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1187
ganlikun 0:13413ea9a877 1188 /* Process unlocked */
ganlikun 0:13413ea9a877 1189 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1190 }
ganlikun 0:13413ea9a877 1191 else
ganlikun 0:13413ea9a877 1192 {
ganlikun 0:13413ea9a877 1193 hqspi->TxXferCount = (data_size >> 2U);
ganlikun 0:13413ea9a877 1194 }
ganlikun 0:13413ea9a877 1195 }
ganlikun 0:13413ea9a877 1196
ganlikun 0:13413ea9a877 1197 if (status == HAL_OK)
ganlikun 0:13413ea9a877 1198 {
ganlikun 0:13413ea9a877 1199 /* Update state */
ganlikun 0:13413ea9a877 1200 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
ganlikun 0:13413ea9a877 1201
ganlikun 0:13413ea9a877 1202 /* Clear interrupt */
ganlikun 0:13413ea9a877 1203 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
ganlikun 0:13413ea9a877 1204
ganlikun 0:13413ea9a877 1205 /* Configure size and pointer of the handle */
ganlikun 0:13413ea9a877 1206 hqspi->TxXferSize = hqspi->TxXferCount;
ganlikun 0:13413ea9a877 1207 hqspi->pTxBuffPtr = pData;
ganlikun 0:13413ea9a877 1208
ganlikun 0:13413ea9a877 1209 /* Configure QSPI: CCR register with functional mode as indirect write */
ganlikun 0:13413ea9a877 1210 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
ganlikun 0:13413ea9a877 1211
ganlikun 0:13413ea9a877 1212 /* Set the QSPI DMA transfer complete callback */
ganlikun 0:13413ea9a877 1213 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
ganlikun 0:13413ea9a877 1214
ganlikun 0:13413ea9a877 1215 /* Set the QSPI DMA Half transfer complete callback */
ganlikun 0:13413ea9a877 1216 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
ganlikun 0:13413ea9a877 1217
ganlikun 0:13413ea9a877 1218 /* Set the DMA error callback */
ganlikun 0:13413ea9a877 1219 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
ganlikun 0:13413ea9a877 1220
ganlikun 0:13413ea9a877 1221 /* Clear the DMA abort callback */
ganlikun 0:13413ea9a877 1222 hqspi->hdma->XferAbortCallback = NULL;
ganlikun 0:13413ea9a877 1223
ganlikun 0:13413ea9a877 1224 #if defined (QSPI1_V2_1L)
ganlikun 0:13413ea9a877 1225 /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
ganlikun 0:13413ea9a877 1226 AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
ganlikun 0:13413ea9a877 1227 Change the following configuration of DMA peripheral
ganlikun 0:13413ea9a877 1228 - Enable peripheral increment
ganlikun 0:13413ea9a877 1229 - Disable memory increment
ganlikun 0:13413ea9a877 1230 - Set DMA direction as peripheral to memory mode */
ganlikun 0:13413ea9a877 1231
ganlikun 0:13413ea9a877 1232 /* Enable peripheral increment mode of the DMA */
ganlikun 0:13413ea9a877 1233 hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
ganlikun 0:13413ea9a877 1234
ganlikun 0:13413ea9a877 1235 /* Disable memory increment mode of the DMA */
ganlikun 0:13413ea9a877 1236 hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
ganlikun 0:13413ea9a877 1237
ganlikun 0:13413ea9a877 1238 /* Update peripheral/memory increment mode bits */
ganlikun 0:13413ea9a877 1239 MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
ganlikun 0:13413ea9a877 1240
ganlikun 0:13413ea9a877 1241 /* Configure the direction of the DMA */
ganlikun 0:13413ea9a877 1242 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
ganlikun 0:13413ea9a877 1243 #else
ganlikun 0:13413ea9a877 1244 /* Configure the direction of the DMA */
ganlikun 0:13413ea9a877 1245 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
ganlikun 0:13413ea9a877 1246 #endif /* QSPI1_V2_1L */
ganlikun 0:13413ea9a877 1247
ganlikun 0:13413ea9a877 1248 /* Update direction mode bit */
ganlikun 0:13413ea9a877 1249 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
ganlikun 0:13413ea9a877 1250
ganlikun 0:13413ea9a877 1251 /* Enable the QSPI transmit DMA Channel */
ganlikun 0:13413ea9a877 1252 tmp = (uint32_t*)&pData;
ganlikun 0:13413ea9a877 1253 HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
ganlikun 0:13413ea9a877 1254
ganlikun 0:13413ea9a877 1255 /* Process unlocked */
ganlikun 0:13413ea9a877 1256 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1257
ganlikun 0:13413ea9a877 1258 /* Enable the QSPI transfer error Interrupt */
ganlikun 0:13413ea9a877 1259 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
ganlikun 0:13413ea9a877 1260
ganlikun 0:13413ea9a877 1261 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 1262 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 1263 }
ganlikun 0:13413ea9a877 1264 }
ganlikun 0:13413ea9a877 1265 else
ganlikun 0:13413ea9a877 1266 {
ganlikun 0:13413ea9a877 1267 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1268
ganlikun 0:13413ea9a877 1269 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1270
ganlikun 0:13413ea9a877 1271 /* Process unlocked */
ganlikun 0:13413ea9a877 1272 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1273 }
ganlikun 0:13413ea9a877 1274 }
ganlikun 0:13413ea9a877 1275 else
ganlikun 0:13413ea9a877 1276 {
ganlikun 0:13413ea9a877 1277 status = HAL_BUSY;
ganlikun 0:13413ea9a877 1278
ganlikun 0:13413ea9a877 1279 /* Process unlocked */
ganlikun 0:13413ea9a877 1280 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1281 }
ganlikun 0:13413ea9a877 1282
ganlikun 0:13413ea9a877 1283 return status;
ganlikun 0:13413ea9a877 1284 }
ganlikun 0:13413ea9a877 1285
ganlikun 0:13413ea9a877 1286 /**
ganlikun 0:13413ea9a877 1287 * @brief Receives an amount of data in non blocking mode with DMA.
ganlikun 0:13413ea9a877 1288 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1289 * @param pData: pointer to data buffer.
ganlikun 0:13413ea9a877 1290 * @note This function is used only in Indirect Read Mode
ganlikun 0:13413ea9a877 1291 * @note If DMA peripheral access is configured as halfword, the number
ganlikun 0:13413ea9a877 1292 * of data and the fifo threshold should be aligned on halfword
ganlikun 0:13413ea9a877 1293 * @note If DMA peripheral access is configured as word, the number
ganlikun 0:13413ea9a877 1294 * of data and the fifo threshold should be aligned on word
ganlikun 0:13413ea9a877 1295 * @retval HAL status
ganlikun 0:13413ea9a877 1296 */
ganlikun 0:13413ea9a877 1297 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
ganlikun 0:13413ea9a877 1298 {
ganlikun 0:13413ea9a877 1299 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 1300 uint32_t *tmp;
ganlikun 0:13413ea9a877 1301 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
ganlikun 0:13413ea9a877 1302 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
ganlikun 0:13413ea9a877 1303
ganlikun 0:13413ea9a877 1304 /* Process locked */
ganlikun 0:13413ea9a877 1305 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 1306
ganlikun 0:13413ea9a877 1307 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 1308 {
ganlikun 0:13413ea9a877 1309 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 1310
ganlikun 0:13413ea9a877 1311 if(pData != NULL )
ganlikun 0:13413ea9a877 1312 {
ganlikun 0:13413ea9a877 1313 /* Configure counters of the handle */
ganlikun 0:13413ea9a877 1314 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
ganlikun 0:13413ea9a877 1315 {
ganlikun 0:13413ea9a877 1316 hqspi->RxXferCount = data_size;
ganlikun 0:13413ea9a877 1317 }
ganlikun 0:13413ea9a877 1318 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
ganlikun 0:13413ea9a877 1319 {
ganlikun 0:13413ea9a877 1320 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
ganlikun 0:13413ea9a877 1321 {
ganlikun 0:13413ea9a877 1322 /* The number of data or the fifo threshold is not aligned on halfword
ganlikun 0:13413ea9a877 1323 => no transfer possible with DMA peripheral access configured as halfword */
ganlikun 0:13413ea9a877 1324 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1325 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1326
ganlikun 0:13413ea9a877 1327 /* Process unlocked */
ganlikun 0:13413ea9a877 1328 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1329 }
ganlikun 0:13413ea9a877 1330 else
ganlikun 0:13413ea9a877 1331 {
ganlikun 0:13413ea9a877 1332 hqspi->RxXferCount = (data_size >> 1U);
ganlikun 0:13413ea9a877 1333 }
ganlikun 0:13413ea9a877 1334 }
ganlikun 0:13413ea9a877 1335 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
ganlikun 0:13413ea9a877 1336 {
ganlikun 0:13413ea9a877 1337 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
ganlikun 0:13413ea9a877 1338 {
ganlikun 0:13413ea9a877 1339 /* The number of data or the fifo threshold is not aligned on word
ganlikun 0:13413ea9a877 1340 => no transfer possible with DMA peripheral access configured as word */
ganlikun 0:13413ea9a877 1341 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1342 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1343
ganlikun 0:13413ea9a877 1344 /* Process unlocked */
ganlikun 0:13413ea9a877 1345 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1346 }
ganlikun 0:13413ea9a877 1347 else
ganlikun 0:13413ea9a877 1348 {
ganlikun 0:13413ea9a877 1349 hqspi->RxXferCount = (data_size >> 2U);
ganlikun 0:13413ea9a877 1350 }
ganlikun 0:13413ea9a877 1351 }
ganlikun 0:13413ea9a877 1352
ganlikun 0:13413ea9a877 1353 if (status == HAL_OK)
ganlikun 0:13413ea9a877 1354 {
ganlikun 0:13413ea9a877 1355 /* Update state */
ganlikun 0:13413ea9a877 1356 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
ganlikun 0:13413ea9a877 1357
ganlikun 0:13413ea9a877 1358 /* Clear interrupt */
ganlikun 0:13413ea9a877 1359 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
ganlikun 0:13413ea9a877 1360
ganlikun 0:13413ea9a877 1361 /* Configure size and pointer of the handle */
ganlikun 0:13413ea9a877 1362 hqspi->RxXferSize = hqspi->RxXferCount;
ganlikun 0:13413ea9a877 1363 hqspi->pRxBuffPtr = pData;
ganlikun 0:13413ea9a877 1364
ganlikun 0:13413ea9a877 1365 /* Set the QSPI DMA transfer complete callback */
ganlikun 0:13413ea9a877 1366 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
ganlikun 0:13413ea9a877 1367
ganlikun 0:13413ea9a877 1368 /* Set the QSPI DMA Half transfer complete callback */
ganlikun 0:13413ea9a877 1369 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
ganlikun 0:13413ea9a877 1370
ganlikun 0:13413ea9a877 1371 /* Set the DMA error callback */
ganlikun 0:13413ea9a877 1372 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
ganlikun 0:13413ea9a877 1373
ganlikun 0:13413ea9a877 1374 /* Clear the DMA abort callback */
ganlikun 0:13413ea9a877 1375 hqspi->hdma->XferAbortCallback = NULL;
ganlikun 0:13413ea9a877 1376
ganlikun 0:13413ea9a877 1377 #if defined (QSPI1_V2_1L)
ganlikun 0:13413ea9a877 1378 /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
ganlikun 0:13413ea9a877 1379 AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
ganlikun 0:13413ea9a877 1380 Change the following configuration of DMA peripheral
ganlikun 0:13413ea9a877 1381 - Enable peripheral increment
ganlikun 0:13413ea9a877 1382 - Disable memory increment
ganlikun 0:13413ea9a877 1383 - Set DMA direction as memory to peripheral mode
ganlikun 0:13413ea9a877 1384 - 4 Extra words (32-bits) are added for read operation to guarantee
ganlikun 0:13413ea9a877 1385 the last data is transferred from DMA FIFO to RAM memory */
ganlikun 0:13413ea9a877 1386
ganlikun 0:13413ea9a877 1387 /* Enable peripheral increment of the DMA */
ganlikun 0:13413ea9a877 1388 hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
ganlikun 0:13413ea9a877 1389
ganlikun 0:13413ea9a877 1390 /* Disable memory increment of the DMA */
ganlikun 0:13413ea9a877 1391 hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
ganlikun 0:13413ea9a877 1392
ganlikun 0:13413ea9a877 1393 /* Update peripheral/memory increment mode bits */
ganlikun 0:13413ea9a877 1394 MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
ganlikun 0:13413ea9a877 1395
ganlikun 0:13413ea9a877 1396 /* Configure the direction of the DMA */
ganlikun 0:13413ea9a877 1397 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
ganlikun 0:13413ea9a877 1398
ganlikun 0:13413ea9a877 1399 /* 4 Extra words (32-bits) are needed for read operation to guarantee
ganlikun 0:13413ea9a877 1400 the last data is transferred from DMA FIFO to RAM memory */
ganlikun 0:13413ea9a877 1401 WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
ganlikun 0:13413ea9a877 1402
ganlikun 0:13413ea9a877 1403 /* Update direction mode bit */
ganlikun 0:13413ea9a877 1404 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
ganlikun 0:13413ea9a877 1405
ganlikun 0:13413ea9a877 1406 /* Configure QSPI: CCR register with functional as indirect read */
ganlikun 0:13413ea9a877 1407 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
ganlikun 0:13413ea9a877 1408
ganlikun 0:13413ea9a877 1409 /* Start the transfer by re-writing the address in AR register */
ganlikun 0:13413ea9a877 1410 WRITE_REG(hqspi->Instance->AR, addr_reg);
ganlikun 0:13413ea9a877 1411
ganlikun 0:13413ea9a877 1412 /* Enable the DMA Channel */
ganlikun 0:13413ea9a877 1413 tmp = (uint32_t*)&pData;
ganlikun 0:13413ea9a877 1414 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
ganlikun 0:13413ea9a877 1415
ganlikun 0:13413ea9a877 1416 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 1417 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 1418
ganlikun 0:13413ea9a877 1419 /* Process unlocked */
ganlikun 0:13413ea9a877 1420 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1421
ganlikun 0:13413ea9a877 1422 /* Enable the QSPI transfer error Interrupt */
ganlikun 0:13413ea9a877 1423 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
ganlikun 0:13413ea9a877 1424 #else
ganlikun 0:13413ea9a877 1425 /* Configure the direction of the DMA */
ganlikun 0:13413ea9a877 1426 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
ganlikun 0:13413ea9a877 1427
ganlikun 0:13413ea9a877 1428 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
ganlikun 0:13413ea9a877 1429
ganlikun 0:13413ea9a877 1430 /* Enable the DMA Channel */
ganlikun 0:13413ea9a877 1431 tmp = (uint32_t*)&pData;
ganlikun 0:13413ea9a877 1432 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
ganlikun 0:13413ea9a877 1433
ganlikun 0:13413ea9a877 1434 /* Configure QSPI: CCR register with functional as indirect read */
ganlikun 0:13413ea9a877 1435 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
ganlikun 0:13413ea9a877 1436
ganlikun 0:13413ea9a877 1437 /* Start the transfer by re-writing the address in AR register */
ganlikun 0:13413ea9a877 1438 WRITE_REG(hqspi->Instance->AR, addr_reg);
ganlikun 0:13413ea9a877 1439
ganlikun 0:13413ea9a877 1440 /* Process unlocked */
ganlikun 0:13413ea9a877 1441 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1442
ganlikun 0:13413ea9a877 1443 /* Enable the QSPI transfer error Interrupt */
ganlikun 0:13413ea9a877 1444 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
ganlikun 0:13413ea9a877 1445
ganlikun 0:13413ea9a877 1446 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 1447 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 1448 #endif /* QSPI1_V2_1L */
ganlikun 0:13413ea9a877 1449 }
ganlikun 0:13413ea9a877 1450 }
ganlikun 0:13413ea9a877 1451 else
ganlikun 0:13413ea9a877 1452 {
ganlikun 0:13413ea9a877 1453 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
ganlikun 0:13413ea9a877 1454 status = HAL_ERROR;
ganlikun 0:13413ea9a877 1455
ganlikun 0:13413ea9a877 1456 /* Process unlocked */
ganlikun 0:13413ea9a877 1457 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1458 }
ganlikun 0:13413ea9a877 1459 }
ganlikun 0:13413ea9a877 1460 else
ganlikun 0:13413ea9a877 1461 {
ganlikun 0:13413ea9a877 1462 status = HAL_BUSY;
ganlikun 0:13413ea9a877 1463
ganlikun 0:13413ea9a877 1464 /* Process unlocked */
ganlikun 0:13413ea9a877 1465 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1466 }
ganlikun 0:13413ea9a877 1467
ganlikun 0:13413ea9a877 1468 return status;
ganlikun 0:13413ea9a877 1469 }
ganlikun 0:13413ea9a877 1470
ganlikun 0:13413ea9a877 1471 /**
ganlikun 0:13413ea9a877 1472 * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
ganlikun 0:13413ea9a877 1473 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1474 * @param cmd: structure that contains the command configuration information.
ganlikun 0:13413ea9a877 1475 * @param cfg: structure that contains the polling configuration information.
ganlikun 0:13413ea9a877 1476 * @param Timeout : Time out duration
ganlikun 0:13413ea9a877 1477 * @note This function is used only in Automatic Polling Mode
ganlikun 0:13413ea9a877 1478 * @retval HAL status
ganlikun 0:13413ea9a877 1479 */
ganlikun 0:13413ea9a877 1480 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
ganlikun 0:13413ea9a877 1481 {
ganlikun 0:13413ea9a877 1482 HAL_StatusTypeDef status = HAL_ERROR;
ganlikun 0:13413ea9a877 1483 uint32_t tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 1484
ganlikun 0:13413ea9a877 1485 /* Check the parameters */
ganlikun 0:13413ea9a877 1486 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
ganlikun 0:13413ea9a877 1487 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
ganlikun 0:13413ea9a877 1488 {
ganlikun 0:13413ea9a877 1489 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
ganlikun 0:13413ea9a877 1490 }
ganlikun 0:13413ea9a877 1491
ganlikun 0:13413ea9a877 1492 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
ganlikun 0:13413ea9a877 1493 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 1494 {
ganlikun 0:13413ea9a877 1495 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
ganlikun 0:13413ea9a877 1496 }
ganlikun 0:13413ea9a877 1497
ganlikun 0:13413ea9a877 1498 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
ganlikun 0:13413ea9a877 1499 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
ganlikun 0:13413ea9a877 1500 {
ganlikun 0:13413ea9a877 1501 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
ganlikun 0:13413ea9a877 1502 }
ganlikun 0:13413ea9a877 1503
ganlikun 0:13413ea9a877 1504 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
ganlikun 0:13413ea9a877 1505 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
ganlikun 0:13413ea9a877 1506
ganlikun 0:13413ea9a877 1507 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
ganlikun 0:13413ea9a877 1508 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
ganlikun 0:13413ea9a877 1509 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
ganlikun 0:13413ea9a877 1510
ganlikun 0:13413ea9a877 1511 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
ganlikun 0:13413ea9a877 1512 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
ganlikun 0:13413ea9a877 1513 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
ganlikun 0:13413ea9a877 1514
ganlikun 0:13413ea9a877 1515 /* Process locked */
ganlikun 0:13413ea9a877 1516 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 1517
ganlikun 0:13413ea9a877 1518 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 1519 {
ganlikun 0:13413ea9a877 1520
ganlikun 0:13413ea9a877 1521 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 1522
ganlikun 0:13413ea9a877 1523 /* Update state */
ganlikun 0:13413ea9a877 1524 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
ganlikun 0:13413ea9a877 1525
ganlikun 0:13413ea9a877 1526 /* Wait till BUSY flag reset */
ganlikun 0:13413ea9a877 1527 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
ganlikun 0:13413ea9a877 1528
ganlikun 0:13413ea9a877 1529 if (status == HAL_OK)
ganlikun 0:13413ea9a877 1530 {
ganlikun 0:13413ea9a877 1531 /* Configure QSPI: PSMAR register with the status match value */
ganlikun 0:13413ea9a877 1532 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
ganlikun 0:13413ea9a877 1533
ganlikun 0:13413ea9a877 1534 /* Configure QSPI: PSMKR register with the status mask value */
ganlikun 0:13413ea9a877 1535 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
ganlikun 0:13413ea9a877 1536
ganlikun 0:13413ea9a877 1537 /* Configure QSPI: PIR register with the interval value */
ganlikun 0:13413ea9a877 1538 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
ganlikun 0:13413ea9a877 1539
ganlikun 0:13413ea9a877 1540 /* Configure QSPI: CR register with Match mode and Automatic stop enabled
ganlikun 0:13413ea9a877 1541 (otherwise there will be an infinite loop in blocking mode) */
ganlikun 0:13413ea9a877 1542 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
ganlikun 0:13413ea9a877 1543 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
ganlikun 0:13413ea9a877 1544
ganlikun 0:13413ea9a877 1545 /* Call the configuration function */
ganlikun 0:13413ea9a877 1546 cmd->NbData = cfg->StatusBytesSize;
ganlikun 0:13413ea9a877 1547 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
ganlikun 0:13413ea9a877 1548
ganlikun 0:13413ea9a877 1549 /* Wait until SM flag is set to go back in idle state */
ganlikun 0:13413ea9a877 1550 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
ganlikun 0:13413ea9a877 1551
ganlikun 0:13413ea9a877 1552 if (status == HAL_OK)
ganlikun 0:13413ea9a877 1553 {
ganlikun 0:13413ea9a877 1554 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
ganlikun 0:13413ea9a877 1555
ganlikun 0:13413ea9a877 1556 /* Update state */
ganlikun 0:13413ea9a877 1557 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 1558 }
ganlikun 0:13413ea9a877 1559 }
ganlikun 0:13413ea9a877 1560 }
ganlikun 0:13413ea9a877 1561 else
ganlikun 0:13413ea9a877 1562 {
ganlikun 0:13413ea9a877 1563 status = HAL_BUSY;
ganlikun 0:13413ea9a877 1564 }
ganlikun 0:13413ea9a877 1565 /* Process unlocked */
ganlikun 0:13413ea9a877 1566 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1567
ganlikun 0:13413ea9a877 1568 /* Return function status */
ganlikun 0:13413ea9a877 1569 return status;
ganlikun 0:13413ea9a877 1570 }
ganlikun 0:13413ea9a877 1571
ganlikun 0:13413ea9a877 1572 /**
ganlikun 0:13413ea9a877 1573 * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
ganlikun 0:13413ea9a877 1574 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1575 * @param cmd: structure that contains the command configuration information.
ganlikun 0:13413ea9a877 1576 * @param cfg: structure that contains the polling configuration information.
ganlikun 0:13413ea9a877 1577 * @note This function is used only in Automatic Polling Mode
ganlikun 0:13413ea9a877 1578 * @retval HAL status
ganlikun 0:13413ea9a877 1579 */
ganlikun 0:13413ea9a877 1580 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
ganlikun 0:13413ea9a877 1581 {
ganlikun 0:13413ea9a877 1582 __IO uint32_t count = 0U;
ganlikun 0:13413ea9a877 1583 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 1584
ganlikun 0:13413ea9a877 1585 /* Check the parameters */
ganlikun 0:13413ea9a877 1586 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
ganlikun 0:13413ea9a877 1587 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
ganlikun 0:13413ea9a877 1588 {
ganlikun 0:13413ea9a877 1589 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
ganlikun 0:13413ea9a877 1590 }
ganlikun 0:13413ea9a877 1591
ganlikun 0:13413ea9a877 1592 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
ganlikun 0:13413ea9a877 1593 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 1594 {
ganlikun 0:13413ea9a877 1595 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
ganlikun 0:13413ea9a877 1596 }
ganlikun 0:13413ea9a877 1597
ganlikun 0:13413ea9a877 1598 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
ganlikun 0:13413ea9a877 1599 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
ganlikun 0:13413ea9a877 1600 {
ganlikun 0:13413ea9a877 1601 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
ganlikun 0:13413ea9a877 1602 }
ganlikun 0:13413ea9a877 1603
ganlikun 0:13413ea9a877 1604 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
ganlikun 0:13413ea9a877 1605 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
ganlikun 0:13413ea9a877 1606
ganlikun 0:13413ea9a877 1607 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
ganlikun 0:13413ea9a877 1608 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
ganlikun 0:13413ea9a877 1609 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
ganlikun 0:13413ea9a877 1610
ganlikun 0:13413ea9a877 1611 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
ganlikun 0:13413ea9a877 1612 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
ganlikun 0:13413ea9a877 1613 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
ganlikun 0:13413ea9a877 1614 assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
ganlikun 0:13413ea9a877 1615
ganlikun 0:13413ea9a877 1616 /* Process locked */
ganlikun 0:13413ea9a877 1617 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 1618
ganlikun 0:13413ea9a877 1619 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 1620 {
ganlikun 0:13413ea9a877 1621 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 1622
ganlikun 0:13413ea9a877 1623 /* Update state */
ganlikun 0:13413ea9a877 1624 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
ganlikun 0:13413ea9a877 1625
ganlikun 0:13413ea9a877 1626 /* Wait till BUSY flag reset */
ganlikun 0:13413ea9a877 1627 count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
ganlikun 0:13413ea9a877 1628 do
ganlikun 0:13413ea9a877 1629 {
ganlikun 0:13413ea9a877 1630 if (count-- == 0U)
ganlikun 0:13413ea9a877 1631 {
ganlikun 0:13413ea9a877 1632 hqspi->State = HAL_QSPI_STATE_ERROR;
ganlikun 0:13413ea9a877 1633 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
ganlikun 0:13413ea9a877 1634 status = HAL_TIMEOUT;
ganlikun 0:13413ea9a877 1635 }
ganlikun 0:13413ea9a877 1636 }
ganlikun 0:13413ea9a877 1637 while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
ganlikun 0:13413ea9a877 1638
ganlikun 0:13413ea9a877 1639 if (status == HAL_OK)
ganlikun 0:13413ea9a877 1640 {
ganlikun 0:13413ea9a877 1641 /* Configure QSPI: PSMAR register with the status match value */
ganlikun 0:13413ea9a877 1642 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
ganlikun 0:13413ea9a877 1643
ganlikun 0:13413ea9a877 1644 /* Configure QSPI: PSMKR register with the status mask value */
ganlikun 0:13413ea9a877 1645 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
ganlikun 0:13413ea9a877 1646
ganlikun 0:13413ea9a877 1647 /* Configure QSPI: PIR register with the interval value */
ganlikun 0:13413ea9a877 1648 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
ganlikun 0:13413ea9a877 1649
ganlikun 0:13413ea9a877 1650 /* Configure QSPI: CR register with Match mode and Automatic stop mode */
ganlikun 0:13413ea9a877 1651 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
ganlikun 0:13413ea9a877 1652 (cfg->MatchMode | cfg->AutomaticStop));
ganlikun 0:13413ea9a877 1653
ganlikun 0:13413ea9a877 1654 /* Clear interrupt */
ganlikun 0:13413ea9a877 1655 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
ganlikun 0:13413ea9a877 1656
ganlikun 0:13413ea9a877 1657 /* Call the configuration function */
ganlikun 0:13413ea9a877 1658 cmd->NbData = cfg->StatusBytesSize;
ganlikun 0:13413ea9a877 1659 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
ganlikun 0:13413ea9a877 1660
ganlikun 0:13413ea9a877 1661 /* Process unlocked */
ganlikun 0:13413ea9a877 1662 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1663
ganlikun 0:13413ea9a877 1664 /* Enable the QSPI Transfer Error and status match Interrupt */
ganlikun 0:13413ea9a877 1665 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
ganlikun 0:13413ea9a877 1666
ganlikun 0:13413ea9a877 1667 }
ganlikun 0:13413ea9a877 1668 else
ganlikun 0:13413ea9a877 1669 {
ganlikun 0:13413ea9a877 1670 /* Process unlocked */
ganlikun 0:13413ea9a877 1671 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1672 }
ganlikun 0:13413ea9a877 1673 }
ganlikun 0:13413ea9a877 1674 else
ganlikun 0:13413ea9a877 1675 {
ganlikun 0:13413ea9a877 1676 status = HAL_BUSY;
ganlikun 0:13413ea9a877 1677
ganlikun 0:13413ea9a877 1678 /* Process unlocked */
ganlikun 0:13413ea9a877 1679 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1680 }
ganlikun 0:13413ea9a877 1681
ganlikun 0:13413ea9a877 1682 /* Return function status */
ganlikun 0:13413ea9a877 1683 return status;
ganlikun 0:13413ea9a877 1684 }
ganlikun 0:13413ea9a877 1685
ganlikun 0:13413ea9a877 1686 /**
ganlikun 0:13413ea9a877 1687 * @brief Configure the Memory Mapped mode.
ganlikun 0:13413ea9a877 1688 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1689 * @param cmd: structure that contains the command configuration information.
ganlikun 0:13413ea9a877 1690 * @param cfg: structure that contains the memory mapped configuration information.
ganlikun 0:13413ea9a877 1691 * @note This function is used only in Memory mapped Mode
ganlikun 0:13413ea9a877 1692 * @retval HAL status
ganlikun 0:13413ea9a877 1693 */
ganlikun 0:13413ea9a877 1694 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
ganlikun 0:13413ea9a877 1695 {
ganlikun 0:13413ea9a877 1696 HAL_StatusTypeDef status = HAL_ERROR;
ganlikun 0:13413ea9a877 1697 uint32_t tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 1698
ganlikun 0:13413ea9a877 1699 /* Check the parameters */
ganlikun 0:13413ea9a877 1700 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
ganlikun 0:13413ea9a877 1701 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
ganlikun 0:13413ea9a877 1702 {
ganlikun 0:13413ea9a877 1703 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
ganlikun 0:13413ea9a877 1704 }
ganlikun 0:13413ea9a877 1705
ganlikun 0:13413ea9a877 1706 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
ganlikun 0:13413ea9a877 1707 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 1708 {
ganlikun 0:13413ea9a877 1709 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
ganlikun 0:13413ea9a877 1710 }
ganlikun 0:13413ea9a877 1711
ganlikun 0:13413ea9a877 1712 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
ganlikun 0:13413ea9a877 1713 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
ganlikun 0:13413ea9a877 1714 {
ganlikun 0:13413ea9a877 1715 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
ganlikun 0:13413ea9a877 1716 }
ganlikun 0:13413ea9a877 1717
ganlikun 0:13413ea9a877 1718 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
ganlikun 0:13413ea9a877 1719 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
ganlikun 0:13413ea9a877 1720
ganlikun 0:13413ea9a877 1721 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
ganlikun 0:13413ea9a877 1722 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
ganlikun 0:13413ea9a877 1723 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
ganlikun 0:13413ea9a877 1724
ganlikun 0:13413ea9a877 1725 assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
ganlikun 0:13413ea9a877 1726
ganlikun 0:13413ea9a877 1727 /* Process locked */
ganlikun 0:13413ea9a877 1728 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 1729
ganlikun 0:13413ea9a877 1730 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 1731 {
ganlikun 0:13413ea9a877 1732 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
ganlikun 0:13413ea9a877 1733
ganlikun 0:13413ea9a877 1734 /* Update state */
ganlikun 0:13413ea9a877 1735 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
ganlikun 0:13413ea9a877 1736
ganlikun 0:13413ea9a877 1737 /* Wait till BUSY flag reset */
ganlikun 0:13413ea9a877 1738 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
ganlikun 0:13413ea9a877 1739
ganlikun 0:13413ea9a877 1740 if (status == HAL_OK)
ganlikun 0:13413ea9a877 1741 {
ganlikun 0:13413ea9a877 1742 /* Configure QSPI: CR register with timeout counter enable */
ganlikun 0:13413ea9a877 1743 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
ganlikun 0:13413ea9a877 1744
ganlikun 0:13413ea9a877 1745 if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
ganlikun 0:13413ea9a877 1746 {
ganlikun 0:13413ea9a877 1747 assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
ganlikun 0:13413ea9a877 1748
ganlikun 0:13413ea9a877 1749 /* Configure QSPI: LPTR register with the low-power timeout value */
ganlikun 0:13413ea9a877 1750 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
ganlikun 0:13413ea9a877 1751
ganlikun 0:13413ea9a877 1752 /* Clear interrupt */
ganlikun 0:13413ea9a877 1753 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
ganlikun 0:13413ea9a877 1754
ganlikun 0:13413ea9a877 1755 /* Enable the QSPI TimeOut Interrupt */
ganlikun 0:13413ea9a877 1756 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
ganlikun 0:13413ea9a877 1757 }
ganlikun 0:13413ea9a877 1758
ganlikun 0:13413ea9a877 1759 /* Call the configuration function */
ganlikun 0:13413ea9a877 1760 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
ganlikun 0:13413ea9a877 1761 }
ganlikun 0:13413ea9a877 1762 }
ganlikun 0:13413ea9a877 1763 else
ganlikun 0:13413ea9a877 1764 {
ganlikun 0:13413ea9a877 1765 status = HAL_BUSY;
ganlikun 0:13413ea9a877 1766 }
ganlikun 0:13413ea9a877 1767
ganlikun 0:13413ea9a877 1768 /* Process unlocked */
ganlikun 0:13413ea9a877 1769 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1770
ganlikun 0:13413ea9a877 1771 /* Return function status */
ganlikun 0:13413ea9a877 1772 return status;
ganlikun 0:13413ea9a877 1773 }
ganlikun 0:13413ea9a877 1774
ganlikun 0:13413ea9a877 1775 /**
ganlikun 0:13413ea9a877 1776 * @brief Transfer Error callbacks
ganlikun 0:13413ea9a877 1777 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1778 * @retval None
ganlikun 0:13413ea9a877 1779 */
ganlikun 0:13413ea9a877 1780 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1781 {
ganlikun 0:13413ea9a877 1782 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1783 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1784
ganlikun 0:13413ea9a877 1785 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1786 the HAL_QSPI_ErrorCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1787 */
ganlikun 0:13413ea9a877 1788 }
ganlikun 0:13413ea9a877 1789
ganlikun 0:13413ea9a877 1790 /**
ganlikun 0:13413ea9a877 1791 * @brief Abort completed callback.
ganlikun 0:13413ea9a877 1792 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1793 * @retval None
ganlikun 0:13413ea9a877 1794 */
ganlikun 0:13413ea9a877 1795 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1796 {
ganlikun 0:13413ea9a877 1797 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1798 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1799
ganlikun 0:13413ea9a877 1800 /* NOTE: This function should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1801 the HAL_QSPI_AbortCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1802 */
ganlikun 0:13413ea9a877 1803 }
ganlikun 0:13413ea9a877 1804
ganlikun 0:13413ea9a877 1805 /**
ganlikun 0:13413ea9a877 1806 * @brief Command completed callback.
ganlikun 0:13413ea9a877 1807 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1808 * @retval None
ganlikun 0:13413ea9a877 1809 */
ganlikun 0:13413ea9a877 1810 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1811 {
ganlikun 0:13413ea9a877 1812 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1813 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1814
ganlikun 0:13413ea9a877 1815 /* NOTE: This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1816 the HAL_QSPI_CmdCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1817 */
ganlikun 0:13413ea9a877 1818 }
ganlikun 0:13413ea9a877 1819
ganlikun 0:13413ea9a877 1820 /**
ganlikun 0:13413ea9a877 1821 * @brief Rx Transfer completed callbacks.
ganlikun 0:13413ea9a877 1822 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1823 * @retval None
ganlikun 0:13413ea9a877 1824 */
ganlikun 0:13413ea9a877 1825 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1826 {
ganlikun 0:13413ea9a877 1827 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1828 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1829
ganlikun 0:13413ea9a877 1830 /* NOTE: This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1831 the HAL_QSPI_RxCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1832 */
ganlikun 0:13413ea9a877 1833 }
ganlikun 0:13413ea9a877 1834
ganlikun 0:13413ea9a877 1835 /**
ganlikun 0:13413ea9a877 1836 * @brief Tx Transfer completed callbacks.
ganlikun 0:13413ea9a877 1837 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1838 * @retval None
ganlikun 0:13413ea9a877 1839 */
ganlikun 0:13413ea9a877 1840 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1841 {
ganlikun 0:13413ea9a877 1842 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1843 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1844
ganlikun 0:13413ea9a877 1845 /* NOTE: This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1846 the HAL_QSPI_TxCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1847 */
ganlikun 0:13413ea9a877 1848 }
ganlikun 0:13413ea9a877 1849
ganlikun 0:13413ea9a877 1850 /**
ganlikun 0:13413ea9a877 1851 * @brief Rx Half Transfer completed callbacks.
ganlikun 0:13413ea9a877 1852 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1853 * @retval None
ganlikun 0:13413ea9a877 1854 */
ganlikun 0:13413ea9a877 1855 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1856 {
ganlikun 0:13413ea9a877 1857 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1858 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1859
ganlikun 0:13413ea9a877 1860 /* NOTE: This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1861 the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1862 */
ganlikun 0:13413ea9a877 1863 }
ganlikun 0:13413ea9a877 1864
ganlikun 0:13413ea9a877 1865 /**
ganlikun 0:13413ea9a877 1866 * @brief Tx Half Transfer completed callbacks.
ganlikun 0:13413ea9a877 1867 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1868 * @retval None
ganlikun 0:13413ea9a877 1869 */
ganlikun 0:13413ea9a877 1870 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1871 {
ganlikun 0:13413ea9a877 1872 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1873 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1874
ganlikun 0:13413ea9a877 1875 /* NOTE: This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1876 the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1877 */
ganlikun 0:13413ea9a877 1878 }
ganlikun 0:13413ea9a877 1879
ganlikun 0:13413ea9a877 1880 /**
ganlikun 0:13413ea9a877 1881 * @brief FIFO Threshold callbacks
ganlikun 0:13413ea9a877 1882 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1883 * @retval None
ganlikun 0:13413ea9a877 1884 */
ganlikun 0:13413ea9a877 1885 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1886 {
ganlikun 0:13413ea9a877 1887 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1888 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1889
ganlikun 0:13413ea9a877 1890 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1891 the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1892 */
ganlikun 0:13413ea9a877 1893 }
ganlikun 0:13413ea9a877 1894
ganlikun 0:13413ea9a877 1895 /**
ganlikun 0:13413ea9a877 1896 * @brief Status Match callbacks
ganlikun 0:13413ea9a877 1897 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1898 * @retval None
ganlikun 0:13413ea9a877 1899 */
ganlikun 0:13413ea9a877 1900 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1901 {
ganlikun 0:13413ea9a877 1902 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1903 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1904
ganlikun 0:13413ea9a877 1905 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1906 the HAL_QSPI_StatusMatchCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1907 */
ganlikun 0:13413ea9a877 1908 }
ganlikun 0:13413ea9a877 1909
ganlikun 0:13413ea9a877 1910 /**
ganlikun 0:13413ea9a877 1911 * @brief Timeout callbacks
ganlikun 0:13413ea9a877 1912 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1913 * @retval None
ganlikun 0:13413ea9a877 1914 */
ganlikun 0:13413ea9a877 1915 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1916 {
ganlikun 0:13413ea9a877 1917 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1918 UNUSED(hqspi);
ganlikun 0:13413ea9a877 1919
ganlikun 0:13413ea9a877 1920 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1921 the HAL_QSPI_TimeOutCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1922 */
ganlikun 0:13413ea9a877 1923 }
ganlikun 0:13413ea9a877 1924
ganlikun 0:13413ea9a877 1925 /**
ganlikun 0:13413ea9a877 1926 * @}
ganlikun 0:13413ea9a877 1927 */
ganlikun 0:13413ea9a877 1928
ganlikun 0:13413ea9a877 1929 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
ganlikun 0:13413ea9a877 1930 * @brief QSPI control and State functions
ganlikun 0:13413ea9a877 1931 *
ganlikun 0:13413ea9a877 1932 @verbatim
ganlikun 0:13413ea9a877 1933 ===============================================================================
ganlikun 0:13413ea9a877 1934 ##### Peripheral Control and State functions #####
ganlikun 0:13413ea9a877 1935 ===============================================================================
ganlikun 0:13413ea9a877 1936 [..]
ganlikun 0:13413ea9a877 1937 This subsection provides a set of functions allowing to :
ganlikun 0:13413ea9a877 1938 (+) Check in run-time the state of the driver.
ganlikun 0:13413ea9a877 1939 (+) Check the error code set during last operation.
ganlikun 0:13413ea9a877 1940 (+) Abort any operation.
ganlikun 0:13413ea9a877 1941
ganlikun 0:13413ea9a877 1942 @endverbatim
ganlikun 0:13413ea9a877 1943 * @{
ganlikun 0:13413ea9a877 1944 */
ganlikun 0:13413ea9a877 1945
ganlikun 0:13413ea9a877 1946 /**
ganlikun 0:13413ea9a877 1947 * @brief Return the QSPI handle state.
ganlikun 0:13413ea9a877 1948 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1949 * @retval HAL state
ganlikun 0:13413ea9a877 1950 */
ganlikun 0:13413ea9a877 1951 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1952 {
ganlikun 0:13413ea9a877 1953 /* Return QSPI handle state */
ganlikun 0:13413ea9a877 1954 return hqspi->State;
ganlikun 0:13413ea9a877 1955 }
ganlikun 0:13413ea9a877 1956
ganlikun 0:13413ea9a877 1957 /**
ganlikun 0:13413ea9a877 1958 * @brief Return the QSPI error code
ganlikun 0:13413ea9a877 1959 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1960 * @retval QSPI Error Code
ganlikun 0:13413ea9a877 1961 */
ganlikun 0:13413ea9a877 1962 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1963 {
ganlikun 0:13413ea9a877 1964 return hqspi->ErrorCode;
ganlikun 0:13413ea9a877 1965 }
ganlikun 0:13413ea9a877 1966
ganlikun 0:13413ea9a877 1967 /**
ganlikun 0:13413ea9a877 1968 * @brief Abort the current transmission
ganlikun 0:13413ea9a877 1969 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 1970 * @retval HAL status
ganlikun 0:13413ea9a877 1971 */
ganlikun 0:13413ea9a877 1972 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 1973 {
ganlikun 0:13413ea9a877 1974 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 1975 uint32_t tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 1976
ganlikun 0:13413ea9a877 1977 /* Check if the state is in one of the busy states */
ganlikun 0:13413ea9a877 1978 if ((hqspi->State & 0x2U) != 0U)
ganlikun 0:13413ea9a877 1979 {
ganlikun 0:13413ea9a877 1980 /* Process unlocked */
ganlikun 0:13413ea9a877 1981 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 1982
ganlikun 0:13413ea9a877 1983 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
ganlikun 0:13413ea9a877 1984 {
ganlikun 0:13413ea9a877 1985 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 1986 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 1987
ganlikun 0:13413ea9a877 1988 /* Abort DMA channel */
ganlikun 0:13413ea9a877 1989 status = HAL_DMA_Abort(hqspi->hdma);
ganlikun 0:13413ea9a877 1990 if(status != HAL_OK)
ganlikun 0:13413ea9a877 1991 {
ganlikun 0:13413ea9a877 1992 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
ganlikun 0:13413ea9a877 1993 }
ganlikun 0:13413ea9a877 1994 }
ganlikun 0:13413ea9a877 1995
ganlikun 0:13413ea9a877 1996 /* Configure QSPI: CR register with Abort request */
ganlikun 0:13413ea9a877 1997 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
ganlikun 0:13413ea9a877 1998
ganlikun 0:13413ea9a877 1999 /* Wait until TC flag is set to go back in idle state */
ganlikun 0:13413ea9a877 2000 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
ganlikun 0:13413ea9a877 2001
ganlikun 0:13413ea9a877 2002 if(status == HAL_OK)
ganlikun 0:13413ea9a877 2003 {
ganlikun 0:13413ea9a877 2004 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 2005
ganlikun 0:13413ea9a877 2006 /* Wait until BUSY flag is reset */
ganlikun 0:13413ea9a877 2007 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
ganlikun 0:13413ea9a877 2008 }
ganlikun 0:13413ea9a877 2009
ganlikun 0:13413ea9a877 2010 if (status == HAL_OK)
ganlikun 0:13413ea9a877 2011 {
ganlikun 0:13413ea9a877 2012 /* Update state */
ganlikun 0:13413ea9a877 2013 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 2014 }
ganlikun 0:13413ea9a877 2015 }
ganlikun 0:13413ea9a877 2016
ganlikun 0:13413ea9a877 2017 return status;
ganlikun 0:13413ea9a877 2018 }
ganlikun 0:13413ea9a877 2019
ganlikun 0:13413ea9a877 2020 /**
ganlikun 0:13413ea9a877 2021 * @brief Abort the current transmission (non-blocking function)
ganlikun 0:13413ea9a877 2022 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 2023 * @retval HAL status
ganlikun 0:13413ea9a877 2024 */
ganlikun 0:13413ea9a877 2025 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 2026 {
ganlikun 0:13413ea9a877 2027 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 2028
ganlikun 0:13413ea9a877 2029 /* Check if the state is in one of the busy states */
ganlikun 0:13413ea9a877 2030 if ((hqspi->State & 0x2U) != 0U)
ganlikun 0:13413ea9a877 2031 {
ganlikun 0:13413ea9a877 2032 /* Process unlocked */
ganlikun 0:13413ea9a877 2033 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 2034
ganlikun 0:13413ea9a877 2035 /* Update QSPI state */
ganlikun 0:13413ea9a877 2036 hqspi->State = HAL_QSPI_STATE_ABORT;
ganlikun 0:13413ea9a877 2037
ganlikun 0:13413ea9a877 2038 /* Disable all interrupts */
ganlikun 0:13413ea9a877 2039 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
ganlikun 0:13413ea9a877 2040
ganlikun 0:13413ea9a877 2041 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
ganlikun 0:13413ea9a877 2042 {
ganlikun 0:13413ea9a877 2043 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 2044 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 2045
ganlikun 0:13413ea9a877 2046 /* Abort DMA channel */
ganlikun 0:13413ea9a877 2047 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
ganlikun 0:13413ea9a877 2048 HAL_DMA_Abort_IT(hqspi->hdma);
ganlikun 0:13413ea9a877 2049 }
ganlikun 0:13413ea9a877 2050 else
ganlikun 0:13413ea9a877 2051 {
ganlikun 0:13413ea9a877 2052 /* Clear interrupt */
ganlikun 0:13413ea9a877 2053 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 2054
ganlikun 0:13413ea9a877 2055 /* Enable the QSPI Transfer Complete Interrupt */
ganlikun 0:13413ea9a877 2056 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
ganlikun 0:13413ea9a877 2057
ganlikun 0:13413ea9a877 2058 /* Configure QSPI: CR register with Abort request */
ganlikun 0:13413ea9a877 2059 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
ganlikun 0:13413ea9a877 2060 }
ganlikun 0:13413ea9a877 2061 }
ganlikun 0:13413ea9a877 2062
ganlikun 0:13413ea9a877 2063 return status;
ganlikun 0:13413ea9a877 2064 }
ganlikun 0:13413ea9a877 2065
ganlikun 0:13413ea9a877 2066 /** @brief Set QSPI timeout
ganlikun 0:13413ea9a877 2067 * @param hqspi: QSPI handle.
ganlikun 0:13413ea9a877 2068 * @param Timeout: Timeout for the QSPI memory access.
ganlikun 0:13413ea9a877 2069 * @retval None
ganlikun 0:13413ea9a877 2070 */
ganlikun 0:13413ea9a877 2071 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
ganlikun 0:13413ea9a877 2072 {
ganlikun 0:13413ea9a877 2073 hqspi->Timeout = Timeout;
ganlikun 0:13413ea9a877 2074 }
ganlikun 0:13413ea9a877 2075
ganlikun 0:13413ea9a877 2076 /** @brief Set QSPI Fifo threshold.
ganlikun 0:13413ea9a877 2077 * @param hqspi: QSPI handle.
ganlikun 0:13413ea9a877 2078 * @param Threshold: Threshold of the Fifo (value between 1 and 16).
ganlikun 0:13413ea9a877 2079 * @retval HAL status
ganlikun 0:13413ea9a877 2080 */
ganlikun 0:13413ea9a877 2081 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
ganlikun 0:13413ea9a877 2082 {
ganlikun 0:13413ea9a877 2083 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:13413ea9a877 2084
ganlikun 0:13413ea9a877 2085 /* Process locked */
ganlikun 0:13413ea9a877 2086 __HAL_LOCK(hqspi);
ganlikun 0:13413ea9a877 2087
ganlikun 0:13413ea9a877 2088 if(hqspi->State == HAL_QSPI_STATE_READY)
ganlikun 0:13413ea9a877 2089 {
ganlikun 0:13413ea9a877 2090 /* Synchronize init structure with new FIFO threshold value */
ganlikun 0:13413ea9a877 2091 hqspi->Init.FifoThreshold = Threshold;
ganlikun 0:13413ea9a877 2092
ganlikun 0:13413ea9a877 2093 /* Configure QSPI FIFO Threshold */
ganlikun 0:13413ea9a877 2094 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
ganlikun 0:13413ea9a877 2095 ((hqspi->Init.FifoThreshold - 1U) << POSITION_VAL(QUADSPI_CR_FTHRES)));
ganlikun 0:13413ea9a877 2096 }
ganlikun 0:13413ea9a877 2097 else
ganlikun 0:13413ea9a877 2098 {
ganlikun 0:13413ea9a877 2099 status = HAL_BUSY;
ganlikun 0:13413ea9a877 2100 }
ganlikun 0:13413ea9a877 2101
ganlikun 0:13413ea9a877 2102 /* Process unlocked */
ganlikun 0:13413ea9a877 2103 __HAL_UNLOCK(hqspi);
ganlikun 0:13413ea9a877 2104
ganlikun 0:13413ea9a877 2105 /* Return function status */
ganlikun 0:13413ea9a877 2106 return status;
ganlikun 0:13413ea9a877 2107 }
ganlikun 0:13413ea9a877 2108
ganlikun 0:13413ea9a877 2109 /** @brief Get QSPI Fifo threshold.
ganlikun 0:13413ea9a877 2110 * @param hqspi: QSPI handle.
ganlikun 0:13413ea9a877 2111 * @retval Fifo threshold (value between 1 and 16)
ganlikun 0:13413ea9a877 2112 */
ganlikun 0:13413ea9a877 2113 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
ganlikun 0:13413ea9a877 2114 {
ganlikun 0:13413ea9a877 2115 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1U);
ganlikun 0:13413ea9a877 2116 }
ganlikun 0:13413ea9a877 2117
ganlikun 0:13413ea9a877 2118 /**
ganlikun 0:13413ea9a877 2119 * @}
ganlikun 0:13413ea9a877 2120 */
ganlikun 0:13413ea9a877 2121
ganlikun 0:13413ea9a877 2122 /* Private functions ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 2123
ganlikun 0:13413ea9a877 2124 /**
ganlikun 0:13413ea9a877 2125 * @brief DMA QSPI receive process complete callback.
ganlikun 0:13413ea9a877 2126 * @param hdma: DMA handle
ganlikun 0:13413ea9a877 2127 * @retval None
ganlikun 0:13413ea9a877 2128 */
ganlikun 0:13413ea9a877 2129 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
ganlikun 0:13413ea9a877 2130 {
ganlikun 0:13413ea9a877 2131 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
ganlikun 0:13413ea9a877 2132 hqspi->RxXferCount = 0U;
ganlikun 0:13413ea9a877 2133
ganlikun 0:13413ea9a877 2134 /* Enable the QSPI transfer complete Interrupt */
ganlikun 0:13413ea9a877 2135 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
ganlikun 0:13413ea9a877 2136 }
ganlikun 0:13413ea9a877 2137
ganlikun 0:13413ea9a877 2138 /**
ganlikun 0:13413ea9a877 2139 * @brief DMA QSPI transmit process complete callback.
ganlikun 0:13413ea9a877 2140 * @param hdma: DMA handle
ganlikun 0:13413ea9a877 2141 * @retval None
ganlikun 0:13413ea9a877 2142 */
ganlikun 0:13413ea9a877 2143 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
ganlikun 0:13413ea9a877 2144 {
ganlikun 0:13413ea9a877 2145 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
ganlikun 0:13413ea9a877 2146 hqspi->TxXferCount = 0U;
ganlikun 0:13413ea9a877 2147
ganlikun 0:13413ea9a877 2148 /* Enable the QSPI transfer complete Interrupt */
ganlikun 0:13413ea9a877 2149 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
ganlikun 0:13413ea9a877 2150 }
ganlikun 0:13413ea9a877 2151
ganlikun 0:13413ea9a877 2152 /**
ganlikun 0:13413ea9a877 2153 * @brief DMA QSPI receive process half complete callback
ganlikun 0:13413ea9a877 2154 * @param hdma : DMA handle
ganlikun 0:13413ea9a877 2155 * @retval None
ganlikun 0:13413ea9a877 2156 */
ganlikun 0:13413ea9a877 2157 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
ganlikun 0:13413ea9a877 2158 {
ganlikun 0:13413ea9a877 2159 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
ganlikun 0:13413ea9a877 2160
ganlikun 0:13413ea9a877 2161 HAL_QSPI_RxHalfCpltCallback(hqspi);
ganlikun 0:13413ea9a877 2162 }
ganlikun 0:13413ea9a877 2163
ganlikun 0:13413ea9a877 2164 /**
ganlikun 0:13413ea9a877 2165 * @brief DMA QSPI transmit process half complete callback
ganlikun 0:13413ea9a877 2166 * @param hdma : DMA handle
ganlikun 0:13413ea9a877 2167 * @retval None
ganlikun 0:13413ea9a877 2168 */
ganlikun 0:13413ea9a877 2169 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
ganlikun 0:13413ea9a877 2170 {
ganlikun 0:13413ea9a877 2171 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
ganlikun 0:13413ea9a877 2172
ganlikun 0:13413ea9a877 2173 HAL_QSPI_TxHalfCpltCallback(hqspi);
ganlikun 0:13413ea9a877 2174 }
ganlikun 0:13413ea9a877 2175
ganlikun 0:13413ea9a877 2176 /**
ganlikun 0:13413ea9a877 2177 * @brief DMA QSPI communication error callback.
ganlikun 0:13413ea9a877 2178 * @param hdma: DMA handle
ganlikun 0:13413ea9a877 2179 * @retval None
ganlikun 0:13413ea9a877 2180 */
ganlikun 0:13413ea9a877 2181 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
ganlikun 0:13413ea9a877 2182 {
ganlikun 0:13413ea9a877 2183 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
ganlikun 0:13413ea9a877 2184
ganlikun 0:13413ea9a877 2185 /* if DMA error is FIFO error ignore it */
ganlikun 0:13413ea9a877 2186 if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
ganlikun 0:13413ea9a877 2187 {
ganlikun 0:13413ea9a877 2188 hqspi->RxXferCount = 0U;
ganlikun 0:13413ea9a877 2189 hqspi->TxXferCount = 0U;
ganlikun 0:13413ea9a877 2190 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
ganlikun 0:13413ea9a877 2191
ganlikun 0:13413ea9a877 2192 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
ganlikun 0:13413ea9a877 2193 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
ganlikun 0:13413ea9a877 2194
ganlikun 0:13413ea9a877 2195 /* Abort the QSPI */
ganlikun 0:13413ea9a877 2196 HAL_QSPI_Abort_IT(hqspi);
ganlikun 0:13413ea9a877 2197 }
ganlikun 0:13413ea9a877 2198 }
ganlikun 0:13413ea9a877 2199
ganlikun 0:13413ea9a877 2200 /**
ganlikun 0:13413ea9a877 2201 * @brief DMA QSPI abort complete callback.
ganlikun 0:13413ea9a877 2202 * @param hdma: DMA handle
ganlikun 0:13413ea9a877 2203 * @retval None
ganlikun 0:13413ea9a877 2204 */
ganlikun 0:13413ea9a877 2205 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
ganlikun 0:13413ea9a877 2206 {
ganlikun 0:13413ea9a877 2207 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
ganlikun 0:13413ea9a877 2208
ganlikun 0:13413ea9a877 2209 hqspi->RxXferCount = 0U;
ganlikun 0:13413ea9a877 2210 hqspi->TxXferCount = 0U;
ganlikun 0:13413ea9a877 2211
ganlikun 0:13413ea9a877 2212 if(hqspi->State == HAL_QSPI_STATE_ABORT)
ganlikun 0:13413ea9a877 2213 {
ganlikun 0:13413ea9a877 2214 /* DMA Abort called by QSPI abort */
ganlikun 0:13413ea9a877 2215 /* Clear interrupt */
ganlikun 0:13413ea9a877 2216 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
ganlikun 0:13413ea9a877 2217
ganlikun 0:13413ea9a877 2218 /* Enable the QSPI Transfer Complete Interrupt */
ganlikun 0:13413ea9a877 2219 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
ganlikun 0:13413ea9a877 2220
ganlikun 0:13413ea9a877 2221 /* Configure QSPI: CR register with Abort request */
ganlikun 0:13413ea9a877 2222 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
ganlikun 0:13413ea9a877 2223 }
ganlikun 0:13413ea9a877 2224 else
ganlikun 0:13413ea9a877 2225 {
ganlikun 0:13413ea9a877 2226 /* DMA Abort called due to a transfer error interrupt */
ganlikun 0:13413ea9a877 2227 /* Change state of QSPI */
ganlikun 0:13413ea9a877 2228 hqspi->State = HAL_QSPI_STATE_READY;
ganlikun 0:13413ea9a877 2229
ganlikun 0:13413ea9a877 2230 /* Error callback */
ganlikun 0:13413ea9a877 2231 HAL_QSPI_ErrorCallback(hqspi);
ganlikun 0:13413ea9a877 2232 }
ganlikun 0:13413ea9a877 2233 }
ganlikun 0:13413ea9a877 2234 /**
ganlikun 0:13413ea9a877 2235 * @brief Wait for a flag state until timeout.
ganlikun 0:13413ea9a877 2236 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 2237 * @param Flag: Flag checked
ganlikun 0:13413ea9a877 2238 * @param State: Value of the flag expected
ganlikun 0:13413ea9a877 2239 * @param Timeout: Duration of the time out
ganlikun 0:13413ea9a877 2240 * @param tickstart: tick start value
ganlikun 0:13413ea9a877 2241 * @retval HAL status
ganlikun 0:13413ea9a877 2242 */
ganlikun 0:13413ea9a877 2243 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
ganlikun 0:13413ea9a877 2244 FlagStatus State, uint32_t tickstart, uint32_t Timeout)
ganlikun 0:13413ea9a877 2245 {
ganlikun 0:13413ea9a877 2246 /* Wait until flag is in expected state */
ganlikun 0:13413ea9a877 2247 while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
ganlikun 0:13413ea9a877 2248 {
ganlikun 0:13413ea9a877 2249 /* Check for the Timeout */
ganlikun 0:13413ea9a877 2250 if (Timeout != HAL_MAX_DELAY)
ganlikun 0:13413ea9a877 2251 {
ganlikun 0:13413ea9a877 2252 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
ganlikun 0:13413ea9a877 2253 {
ganlikun 0:13413ea9a877 2254 hqspi->State = HAL_QSPI_STATE_ERROR;
ganlikun 0:13413ea9a877 2255 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
ganlikun 0:13413ea9a877 2256
ganlikun 0:13413ea9a877 2257 return HAL_ERROR;
ganlikun 0:13413ea9a877 2258 }
ganlikun 0:13413ea9a877 2259 }
ganlikun 0:13413ea9a877 2260 }
ganlikun 0:13413ea9a877 2261 return HAL_OK;
ganlikun 0:13413ea9a877 2262 }
ganlikun 0:13413ea9a877 2263
ganlikun 0:13413ea9a877 2264 /**
ganlikun 0:13413ea9a877 2265 * @brief Configure the communication registers.
ganlikun 0:13413ea9a877 2266 * @param hqspi: QSPI handle
ganlikun 0:13413ea9a877 2267 * @param cmd: structure that contains the command configuration information
ganlikun 0:13413ea9a877 2268 * @param FunctionalMode: functional mode to configured
ganlikun 0:13413ea9a877 2269 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 2270 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
ganlikun 0:13413ea9a877 2271 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
ganlikun 0:13413ea9a877 2272 * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
ganlikun 0:13413ea9a877 2273 * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
ganlikun 0:13413ea9a877 2274 * @retval None
ganlikun 0:13413ea9a877 2275 */
ganlikun 0:13413ea9a877 2276 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
ganlikun 0:13413ea9a877 2277 {
ganlikun 0:13413ea9a877 2278 assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
ganlikun 0:13413ea9a877 2279
ganlikun 0:13413ea9a877 2280 if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
ganlikun 0:13413ea9a877 2281 {
ganlikun 0:13413ea9a877 2282 /* Configure QSPI: DLR register with the number of data to read or write */
ganlikun 0:13413ea9a877 2283 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
ganlikun 0:13413ea9a877 2284 }
ganlikun 0:13413ea9a877 2285
ganlikun 0:13413ea9a877 2286 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
ganlikun 0:13413ea9a877 2287 {
ganlikun 0:13413ea9a877 2288 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
ganlikun 0:13413ea9a877 2289 {
ganlikun 0:13413ea9a877 2290 /* Configure QSPI: ABR register with alternate bytes value */
ganlikun 0:13413ea9a877 2291 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
ganlikun 0:13413ea9a877 2292
ganlikun 0:13413ea9a877 2293 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 2294 {
ganlikun 0:13413ea9a877 2295 /*---- Command with instruction, address and alternate bytes ----*/
ganlikun 0:13413ea9a877 2296 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2297 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2298 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
ganlikun 0:13413ea9a877 2299 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
ganlikun 0:13413ea9a877 2300 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
ganlikun 0:13413ea9a877 2301
ganlikun 0:13413ea9a877 2302 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
ganlikun 0:13413ea9a877 2303 {
ganlikun 0:13413ea9a877 2304 /* Configure QSPI: AR register with address value */
ganlikun 0:13413ea9a877 2305 WRITE_REG(hqspi->Instance->AR, cmd->Address);
ganlikun 0:13413ea9a877 2306 }
ganlikun 0:13413ea9a877 2307 }
ganlikun 0:13413ea9a877 2308 else
ganlikun 0:13413ea9a877 2309 {
ganlikun 0:13413ea9a877 2310 /*---- Command with instruction and alternate bytes ----*/
ganlikun 0:13413ea9a877 2311 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2312 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2313 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
ganlikun 0:13413ea9a877 2314 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
ganlikun 0:13413ea9a877 2315 cmd->Instruction | FunctionalMode));
ganlikun 0:13413ea9a877 2316 }
ganlikun 0:13413ea9a877 2317 }
ganlikun 0:13413ea9a877 2318 else
ganlikun 0:13413ea9a877 2319 {
ganlikun 0:13413ea9a877 2320 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 2321 {
ganlikun 0:13413ea9a877 2322 /*---- Command with instruction and address ----*/
ganlikun 0:13413ea9a877 2323 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2324 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2325 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
ganlikun 0:13413ea9a877 2326 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
ganlikun 0:13413ea9a877 2327 cmd->Instruction | FunctionalMode));
ganlikun 0:13413ea9a877 2328
ganlikun 0:13413ea9a877 2329 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
ganlikun 0:13413ea9a877 2330 {
ganlikun 0:13413ea9a877 2331 /* Configure QSPI: AR register with address value */
ganlikun 0:13413ea9a877 2332 WRITE_REG(hqspi->Instance->AR, cmd->Address);
ganlikun 0:13413ea9a877 2333 }
ganlikun 0:13413ea9a877 2334 }
ganlikun 0:13413ea9a877 2335 else
ganlikun 0:13413ea9a877 2336 {
ganlikun 0:13413ea9a877 2337 /*---- Command with only instruction ----*/
ganlikun 0:13413ea9a877 2338 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2339 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2340 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
ganlikun 0:13413ea9a877 2341 cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
ganlikun 0:13413ea9a877 2342 FunctionalMode));
ganlikun 0:13413ea9a877 2343 }
ganlikun 0:13413ea9a877 2344 }
ganlikun 0:13413ea9a877 2345 }
ganlikun 0:13413ea9a877 2346 else
ganlikun 0:13413ea9a877 2347 {
ganlikun 0:13413ea9a877 2348 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
ganlikun 0:13413ea9a877 2349 {
ganlikun 0:13413ea9a877 2350 /* Configure QSPI: ABR register with alternate bytes value */
ganlikun 0:13413ea9a877 2351 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
ganlikun 0:13413ea9a877 2352
ganlikun 0:13413ea9a877 2353 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 2354 {
ganlikun 0:13413ea9a877 2355 /*---- Command with address and alternate bytes ----*/
ganlikun 0:13413ea9a877 2356 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2357 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2358 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
ganlikun 0:13413ea9a877 2359 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
ganlikun 0:13413ea9a877 2360 cmd->InstructionMode | FunctionalMode));
ganlikun 0:13413ea9a877 2361
ganlikun 0:13413ea9a877 2362 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
ganlikun 0:13413ea9a877 2363 {
ganlikun 0:13413ea9a877 2364 /* Configure QSPI: AR register with address value */
ganlikun 0:13413ea9a877 2365 WRITE_REG(hqspi->Instance->AR, cmd->Address);
ganlikun 0:13413ea9a877 2366 }
ganlikun 0:13413ea9a877 2367 }
ganlikun 0:13413ea9a877 2368 else
ganlikun 0:13413ea9a877 2369 {
ganlikun 0:13413ea9a877 2370 /*---- Command with only alternate bytes ----*/
ganlikun 0:13413ea9a877 2371 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2372 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2373 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
ganlikun 0:13413ea9a877 2374 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
ganlikun 0:13413ea9a877 2375 FunctionalMode));
ganlikun 0:13413ea9a877 2376 }
ganlikun 0:13413ea9a877 2377 }
ganlikun 0:13413ea9a877 2378 else
ganlikun 0:13413ea9a877 2379 {
ganlikun 0:13413ea9a877 2380 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
ganlikun 0:13413ea9a877 2381 {
ganlikun 0:13413ea9a877 2382 /*---- Command with only address ----*/
ganlikun 0:13413ea9a877 2383 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2384 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2385 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
ganlikun 0:13413ea9a877 2386 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
ganlikun 0:13413ea9a877 2387 FunctionalMode));
ganlikun 0:13413ea9a877 2388
ganlikun 0:13413ea9a877 2389 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
ganlikun 0:13413ea9a877 2390 {
ganlikun 0:13413ea9a877 2391 /* Configure QSPI: AR register with address value */
ganlikun 0:13413ea9a877 2392 WRITE_REG(hqspi->Instance->AR, cmd->Address);
ganlikun 0:13413ea9a877 2393 }
ganlikun 0:13413ea9a877 2394 }
ganlikun 0:13413ea9a877 2395 else
ganlikun 0:13413ea9a877 2396 {
ganlikun 0:13413ea9a877 2397 /*---- Command with only data phase ----*/
ganlikun 0:13413ea9a877 2398 if (cmd->DataMode != QSPI_DATA_NONE)
ganlikun 0:13413ea9a877 2399 {
ganlikun 0:13413ea9a877 2400 /* Configure QSPI: CCR register with all communications parameters */
ganlikun 0:13413ea9a877 2401 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
ganlikun 0:13413ea9a877 2402 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
ganlikun 0:13413ea9a877 2403 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
ganlikun 0:13413ea9a877 2404 }
ganlikun 0:13413ea9a877 2405 }
ganlikun 0:13413ea9a877 2406 }
ganlikun 0:13413ea9a877 2407 }
ganlikun 0:13413ea9a877 2408 }
ganlikun 0:13413ea9a877 2409 /**
ganlikun 0:13413ea9a877 2410 * @}
ganlikun 0:13413ea9a877 2411 */
ganlikun 0:13413ea9a877 2412 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx
ganlikun 0:13413ea9a877 2413 STM32F413xx || STM32F423xx */
ganlikun 0:13413ea9a877 2414
ganlikun 0:13413ea9a877 2415 #endif /* HAL_QSPI_MODULE_ENABLED */
ganlikun 0:13413ea9a877 2416 /**
ganlikun 0:13413ea9a877 2417 * @}
ganlikun 0:13413ea9a877 2418 */
ganlikun 0:13413ea9a877 2419
ganlikun 0:13413ea9a877 2420 /**
ganlikun 0:13413ea9a877 2421 * @}
ganlikun 0:13413ea9a877 2422 */
ganlikun 0:13413ea9a877 2423
ganlikun 0:13413ea9a877 2424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 2425