Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

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ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_hal_pwr_ex.h
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief Header file of PWR HAL Extension module.
ganlikun 0:13413ea9a877 8 ******************************************************************************
ganlikun 0:13413ea9a877 9 * @attention
ganlikun 0:13413ea9a877 10 *
ganlikun 0:13413ea9a877 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 12 *
ganlikun 0:13413ea9a877 13 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 14 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 15 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 16 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 18 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 19 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 21 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 22 * without specific prior written permission.
ganlikun 0:13413ea9a877 23 *
ganlikun 0:13413ea9a877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 34 *
ganlikun 0:13413ea9a877 35 ******************************************************************************
ganlikun 0:13413ea9a877 36 */
ganlikun 0:13413ea9a877 37
ganlikun 0:13413ea9a877 38 /* Define to prevent recursive inclusion -------------------------------------*/
ganlikun 0:13413ea9a877 39 #ifndef __STM32F4xx_HAL_PWR_EX_H
ganlikun 0:13413ea9a877 40 #define __STM32F4xx_HAL_PWR_EX_H
ganlikun 0:13413ea9a877 41
ganlikun 0:13413ea9a877 42 #ifdef __cplusplus
ganlikun 0:13413ea9a877 43 extern "C" {
ganlikun 0:13413ea9a877 44 #endif
ganlikun 0:13413ea9a877 45
ganlikun 0:13413ea9a877 46 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 47 #include "stm32f4xx_hal_def.h"
ganlikun 0:13413ea9a877 48
ganlikun 0:13413ea9a877 49 /** @addtogroup STM32F4xx_HAL_Driver
ganlikun 0:13413ea9a877 50 * @{
ganlikun 0:13413ea9a877 51 */
ganlikun 0:13413ea9a877 52
ganlikun 0:13413ea9a877 53 /** @addtogroup PWREx
ganlikun 0:13413ea9a877 54 * @{
ganlikun 0:13413ea9a877 55 */
ganlikun 0:13413ea9a877 56
ganlikun 0:13413ea9a877 57 /* Exported types ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 58 /* Exported constants --------------------------------------------------------*/
ganlikun 0:13413ea9a877 59 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
ganlikun 0:13413ea9a877 60 * @{
ganlikun 0:13413ea9a877 61 */
ganlikun 0:13413ea9a877 62 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
ganlikun 0:13413ea9a877 63 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
ganlikun 0:13413ea9a877 64
ganlikun 0:13413ea9a877 65 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
ganlikun 0:13413ea9a877 66 * @{
ganlikun 0:13413ea9a877 67 */
ganlikun 0:13413ea9a877 68 #define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
ganlikun 0:13413ea9a877 69 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
ganlikun 0:13413ea9a877 70 /**
ganlikun 0:13413ea9a877 71 * @}
ganlikun 0:13413ea9a877 72 */
ganlikun 0:13413ea9a877 73
ganlikun 0:13413ea9a877 74 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
ganlikun 0:13413ea9a877 75 * @{
ganlikun 0:13413ea9a877 76 */
ganlikun 0:13413ea9a877 77 #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
ganlikun 0:13413ea9a877 78 #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
ganlikun 0:13413ea9a877 79 #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
ganlikun 0:13413ea9a877 80 /**
ganlikun 0:13413ea9a877 81 * @}
ganlikun 0:13413ea9a877 82 */
ganlikun 0:13413ea9a877 83 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
ganlikun 0:13413ea9a877 84
ganlikun 0:13413ea9a877 85 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
ganlikun 0:13413ea9a877 86 * @{
ganlikun 0:13413ea9a877 87 */
ganlikun 0:13413ea9a877 88 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 89 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
ganlikun 0:13413ea9a877 90 #define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
ganlikun 0:13413ea9a877 91 #else
ganlikun 0:13413ea9a877 92 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
ganlikun 0:13413ea9a877 93 180 MHz by activating the over-drive mode. */
ganlikun 0:13413ea9a877 94 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
ganlikun 0:13413ea9a877 95 168 MHz by activating the over-drive mode. */
ganlikun 0:13413ea9a877 96 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
ganlikun 0:13413ea9a877 97 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
ganlikun 0:13413ea9a877 98 /**
ganlikun 0:13413ea9a877 99 * @}
ganlikun 0:13413ea9a877 100 */
ganlikun 0:13413ea9a877 101 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
ganlikun 0:13413ea9a877 102 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
ganlikun 0:13413ea9a877 103 /** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
ganlikun 0:13413ea9a877 104 * @{
ganlikun 0:13413ea9a877 105 */
ganlikun 0:13413ea9a877 106 #define PWR_WAKEUP_PIN2 0x00000080U
ganlikun 0:13413ea9a877 107 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
ganlikun 0:13413ea9a877 108 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
ganlikun 0:13413ea9a877 109 #define PWR_WAKEUP_PIN3 0x00000040U
ganlikun 0:13413ea9a877 110 #endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
ganlikun 0:13413ea9a877 111 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
ganlikun 0:13413ea9a877 112 /**
ganlikun 0:13413ea9a877 113 * @}
ganlikun 0:13413ea9a877 114 */
ganlikun 0:13413ea9a877 115 #endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
ganlikun 0:13413ea9a877 116 STM32F413xx || STM32F423xx */
ganlikun 0:13413ea9a877 117
ganlikun 0:13413ea9a877 118 /**
ganlikun 0:13413ea9a877 119 * @}
ganlikun 0:13413ea9a877 120 */
ganlikun 0:13413ea9a877 121
ganlikun 0:13413ea9a877 122 /* Exported macro ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 123 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
ganlikun 0:13413ea9a877 124 * @{
ganlikun 0:13413ea9a877 125 */
ganlikun 0:13413ea9a877 126
ganlikun 0:13413ea9a877 127 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 128 /** @brief macros configure the main internal regulator output voltage.
ganlikun 0:13413ea9a877 129 * @param __REGULATOR__: specifies the regulator output voltage to achieve
ganlikun 0:13413ea9a877 130 * a tradeoff between performance and power consumption when the device does
ganlikun 0:13413ea9a877 131 * not operate at the maximum frequency (refer to the datasheets for more details).
ganlikun 0:13413ea9a877 132 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 133 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
ganlikun 0:13413ea9a877 134 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
ganlikun 0:13413ea9a877 135 * @retval None
ganlikun 0:13413ea9a877 136 */
ganlikun 0:13413ea9a877 137 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
ganlikun 0:13413ea9a877 138 __IO uint32_t tmpreg = 0x00U; \
ganlikun 0:13413ea9a877 139 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
ganlikun 0:13413ea9a877 140 /* Delay after an RCC peripheral clock enabling */ \
ganlikun 0:13413ea9a877 141 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
ganlikun 0:13413ea9a877 142 UNUSED(tmpreg); \
ganlikun 0:13413ea9a877 143 } while(0U)
ganlikun 0:13413ea9a877 144 #else
ganlikun 0:13413ea9a877 145 /** @brief macros configure the main internal regulator output voltage.
ganlikun 0:13413ea9a877 146 * @param __REGULATOR__: specifies the regulator output voltage to achieve
ganlikun 0:13413ea9a877 147 * a tradeoff between performance and power consumption when the device does
ganlikun 0:13413ea9a877 148 * not operate at the maximum frequency (refer to the datasheets for more details).
ganlikun 0:13413ea9a877 149 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 150 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
ganlikun 0:13413ea9a877 151 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
ganlikun 0:13413ea9a877 152 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
ganlikun 0:13413ea9a877 153 * @retval None
ganlikun 0:13413ea9a877 154 */
ganlikun 0:13413ea9a877 155 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
ganlikun 0:13413ea9a877 156 __IO uint32_t tmpreg = 0x00U; \
ganlikun 0:13413ea9a877 157 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
ganlikun 0:13413ea9a877 158 /* Delay after an RCC peripheral clock enabling */ \
ganlikun 0:13413ea9a877 159 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
ganlikun 0:13413ea9a877 160 UNUSED(tmpreg); \
ganlikun 0:13413ea9a877 161 } while(0U)
ganlikun 0:13413ea9a877 162 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
ganlikun 0:13413ea9a877 163
ganlikun 0:13413ea9a877 164 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
ganlikun 0:13413ea9a877 165 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
ganlikun 0:13413ea9a877 166 /** @brief Macros to enable or disable the Over drive mode.
ganlikun 0:13413ea9a877 167 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
ganlikun 0:13413ea9a877 168 */
ganlikun 0:13413ea9a877 169 #define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
ganlikun 0:13413ea9a877 170 #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
ganlikun 0:13413ea9a877 171
ganlikun 0:13413ea9a877 172 /** @brief Macros to enable or disable the Over drive switching.
ganlikun 0:13413ea9a877 173 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
ganlikun 0:13413ea9a877 174 */
ganlikun 0:13413ea9a877 175 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
ganlikun 0:13413ea9a877 176 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
ganlikun 0:13413ea9a877 177
ganlikun 0:13413ea9a877 178 /** @brief Macros to enable or disable the Under drive mode.
ganlikun 0:13413ea9a877 179 * @note This mode is enabled only with STOP low power mode.
ganlikun 0:13413ea9a877 180 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
ganlikun 0:13413ea9a877 181 * mode is only available when the main regulator or the low power regulator
ganlikun 0:13413ea9a877 182 * is in low voltage mode.
ganlikun 0:13413ea9a877 183 * @note If the Under-drive mode was enabled, it is automatically disabled after
ganlikun 0:13413ea9a877 184 * exiting Stop mode.
ganlikun 0:13413ea9a877 185 * When the voltage regulator operates in Under-drive mode, an additional
ganlikun 0:13413ea9a877 186 * startup delay is induced when waking up from Stop mode.
ganlikun 0:13413ea9a877 187 */
ganlikun 0:13413ea9a877 188 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
ganlikun 0:13413ea9a877 189 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
ganlikun 0:13413ea9a877 190
ganlikun 0:13413ea9a877 191 /** @brief Check PWR flag is set or not.
ganlikun 0:13413ea9a877 192 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
ganlikun 0:13413ea9a877 193 * @param __FLAG__: specifies the flag to check.
ganlikun 0:13413ea9a877 194 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 195 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
ganlikun 0:13413ea9a877 196 * is ready
ganlikun 0:13413ea9a877 197 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
ganlikun 0:13413ea9a877 198 * switching is ready
ganlikun 0:13413ea9a877 199 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
ganlikun 0:13413ea9a877 200 * is enabled in Stop mode
ganlikun 0:13413ea9a877 201 * @retval The new state of __FLAG__ (TRUE or FALSE).
ganlikun 0:13413ea9a877 202 */
ganlikun 0:13413ea9a877 203 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
ganlikun 0:13413ea9a877 204
ganlikun 0:13413ea9a877 205 /** @brief Clear the Under-Drive Ready flag.
ganlikun 0:13413ea9a877 206 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
ganlikun 0:13413ea9a877 207 */
ganlikun 0:13413ea9a877 208 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
ganlikun 0:13413ea9a877 209
ganlikun 0:13413ea9a877 210 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
ganlikun 0:13413ea9a877 211 /**
ganlikun 0:13413ea9a877 212 * @}
ganlikun 0:13413ea9a877 213 */
ganlikun 0:13413ea9a877 214
ganlikun 0:13413ea9a877 215 /* Exported functions --------------------------------------------------------*/
ganlikun 0:13413ea9a877 216 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
ganlikun 0:13413ea9a877 217 * @{
ganlikun 0:13413ea9a877 218 */
ganlikun 0:13413ea9a877 219
ganlikun 0:13413ea9a877 220 /** @addtogroup PWREx_Exported_Functions_Group1
ganlikun 0:13413ea9a877 221 * @{
ganlikun 0:13413ea9a877 222 */
ganlikun 0:13413ea9a877 223 void HAL_PWREx_EnableFlashPowerDown(void);
ganlikun 0:13413ea9a877 224 void HAL_PWREx_DisableFlashPowerDown(void);
ganlikun 0:13413ea9a877 225 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
ganlikun 0:13413ea9a877 226 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
ganlikun 0:13413ea9a877 227 uint32_t HAL_PWREx_GetVoltageRange(void);
ganlikun 0:13413ea9a877 228 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
ganlikun 0:13413ea9a877 229
ganlikun 0:13413ea9a877 230 #if defined(STM32F469xx) || defined(STM32F479xx)
ganlikun 0:13413ea9a877 231 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
ganlikun 0:13413ea9a877 232 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
ganlikun 0:13413ea9a877 233 #endif /* STM32F469xx || STM32F479xx */
ganlikun 0:13413ea9a877 234
ganlikun 0:13413ea9a877 235 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
ganlikun 0:13413ea9a877 236 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
ganlikun 0:13413ea9a877 237 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
ganlikun 0:13413ea9a877 238 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
ganlikun 0:13413ea9a877 239 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
ganlikun 0:13413ea9a877 240 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
ganlikun 0:13413ea9a877 241 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
ganlikun 0:13413ea9a877 242 #endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
ganlikun 0:13413ea9a877 243 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
ganlikun 0:13413ea9a877 244
ganlikun 0:13413ea9a877 245 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
ganlikun 0:13413ea9a877 246 defined(STM32F469xx) || defined(STM32F479xx)
ganlikun 0:13413ea9a877 247 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
ganlikun 0:13413ea9a877 248 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
ganlikun 0:13413ea9a877 249 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
ganlikun 0:13413ea9a877 250 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
ganlikun 0:13413ea9a877 251
ganlikun 0:13413ea9a877 252 /**
ganlikun 0:13413ea9a877 253 * @}
ganlikun 0:13413ea9a877 254 */
ganlikun 0:13413ea9a877 255
ganlikun 0:13413ea9a877 256 /**
ganlikun 0:13413ea9a877 257 * @}
ganlikun 0:13413ea9a877 258 */
ganlikun 0:13413ea9a877 259 /* Private types -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 260 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 261 /* Private constants ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 262 /** @defgroup PWREx_Private_Constants PWREx Private Constants
ganlikun 0:13413ea9a877 263 * @{
ganlikun 0:13413ea9a877 264 */
ganlikun 0:13413ea9a877 265
ganlikun 0:13413ea9a877 266 /** @defgroup PWREx_register_alias_address PWREx Register alias address
ganlikun 0:13413ea9a877 267 * @{
ganlikun 0:13413ea9a877 268 */
ganlikun 0:13413ea9a877 269 /* ------------- PWR registers bit address in the alias region ---------------*/
ganlikun 0:13413ea9a877 270 /* --- CR Register ---*/
ganlikun 0:13413ea9a877 271 /* Alias word address of FPDS bit */
ganlikun 0:13413ea9a877 272 #define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
ganlikun 0:13413ea9a877 273 #define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 274
ganlikun 0:13413ea9a877 275 /* Alias word address of ODEN bit */
ganlikun 0:13413ea9a877 276 #define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
ganlikun 0:13413ea9a877 277 #define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 278
ganlikun 0:13413ea9a877 279 /* Alias word address of ODSWEN bit */
ganlikun 0:13413ea9a877 280 #define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
ganlikun 0:13413ea9a877 281 #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 282
ganlikun 0:13413ea9a877 283 /* Alias word address of MRLVDS bit */
ganlikun 0:13413ea9a877 284 #define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
ganlikun 0:13413ea9a877 285 #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 286
ganlikun 0:13413ea9a877 287 /* Alias word address of LPLVDS bit */
ganlikun 0:13413ea9a877 288 #define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
ganlikun 0:13413ea9a877 289 #define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 290
ganlikun 0:13413ea9a877 291 /**
ganlikun 0:13413ea9a877 292 * @}
ganlikun 0:13413ea9a877 293 */
ganlikun 0:13413ea9a877 294
ganlikun 0:13413ea9a877 295 /** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
ganlikun 0:13413ea9a877 296 * @{
ganlikun 0:13413ea9a877 297 */
ganlikun 0:13413ea9a877 298 /* --- CSR Register ---*/
ganlikun 0:13413ea9a877 299 /* Alias word address of BRE bit */
ganlikun 0:13413ea9a877 300 #define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
ganlikun 0:13413ea9a877 301 #define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 302
ganlikun 0:13413ea9a877 303 #if defined(STM32F469xx) || defined(STM32F479xx)
ganlikun 0:13413ea9a877 304 /* Alias word address of WUPP bit */
ganlikun 0:13413ea9a877 305 #define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP)
ganlikun 0:13413ea9a877 306 #define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 307 #endif /* STM32F469xx || STM32F479xx */
ganlikun 0:13413ea9a877 308 /**
ganlikun 0:13413ea9a877 309 * @}
ganlikun 0:13413ea9a877 310 */
ganlikun 0:13413ea9a877 311
ganlikun 0:13413ea9a877 312 /**
ganlikun 0:13413ea9a877 313 * @}
ganlikun 0:13413ea9a877 314 */
ganlikun 0:13413ea9a877 315
ganlikun 0:13413ea9a877 316 /* Private macros ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 317 /** @defgroup PWREx_Private_Macros PWREx Private Macros
ganlikun 0:13413ea9a877 318 * @{
ganlikun 0:13413ea9a877 319 */
ganlikun 0:13413ea9a877 320
ganlikun 0:13413ea9a877 321 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
ganlikun 0:13413ea9a877 322 * @{
ganlikun 0:13413ea9a877 323 */
ganlikun 0:13413ea9a877 324 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
ganlikun 0:13413ea9a877 325 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
ganlikun 0:13413ea9a877 326 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
ganlikun 0:13413ea9a877 327 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
ganlikun 0:13413ea9a877 328 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
ganlikun 0:13413ea9a877 329
ganlikun 0:13413ea9a877 330 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
ganlikun 0:13413ea9a877 331 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
ganlikun 0:13413ea9a877 332 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
ganlikun 0:13413ea9a877 333 #else
ganlikun 0:13413ea9a877 334 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
ganlikun 0:13413ea9a877 335 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
ganlikun 0:13413ea9a877 336 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
ganlikun 0:13413ea9a877 337 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
ganlikun 0:13413ea9a877 338
ganlikun 0:13413ea9a877 339 #if defined(STM32F446xx)
ganlikun 0:13413ea9a877 340 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
ganlikun 0:13413ea9a877 341 #elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\
ganlikun 0:13413ea9a877 342 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
ganlikun 0:13413ea9a877 343 defined(STM32F423xx)
ganlikun 0:13413ea9a877 344 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
ganlikun 0:13413ea9a877 345 ((PIN) == PWR_WAKEUP_PIN3))
ganlikun 0:13413ea9a877 346 #else
ganlikun 0:13413ea9a877 347 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
ganlikun 0:13413ea9a877 348 #endif /* STM32F446xx */
ganlikun 0:13413ea9a877 349 /**
ganlikun 0:13413ea9a877 350 * @}
ganlikun 0:13413ea9a877 351 */
ganlikun 0:13413ea9a877 352
ganlikun 0:13413ea9a877 353 /**
ganlikun 0:13413ea9a877 354 * @}
ganlikun 0:13413ea9a877 355 */
ganlikun 0:13413ea9a877 356
ganlikun 0:13413ea9a877 357 /**
ganlikun 0:13413ea9a877 358 * @}
ganlikun 0:13413ea9a877 359 */
ganlikun 0:13413ea9a877 360
ganlikun 0:13413ea9a877 361 /**
ganlikun 0:13413ea9a877 362 * @}
ganlikun 0:13413ea9a877 363 */
ganlikun 0:13413ea9a877 364
ganlikun 0:13413ea9a877 365 #ifdef __cplusplus
ganlikun 0:13413ea9a877 366 }
ganlikun 0:13413ea9a877 367 #endif
ganlikun 0:13413ea9a877 368
ganlikun 0:13413ea9a877 369
ganlikun 0:13413ea9a877 370 #endif /* __STM32F4xx_HAL_PWR_EX_H */
ganlikun 0:13413ea9a877 371
ganlikun 0:13413ea9a877 372 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 373