Gan likun
001
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c@0:13413ea9a877, 2022-06-12 (annotated)
- Committer:
- ganlikun
- Date:
- Sun Jun 12 14:02:44 2022 +0000
- Revision:
- 0:13413ea9a877
00
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| ganlikun | 0:13413ea9a877 | 1 | /** |
| ganlikun | 0:13413ea9a877 | 2 | ****************************************************************************** |
| ganlikun | 0:13413ea9a877 | 3 | * @file stm32f4xx_hal_pwr_ex.c |
| ganlikun | 0:13413ea9a877 | 4 | * @author MCD Application Team |
| ganlikun | 0:13413ea9a877 | 5 | * @version V1.7.1 |
| ganlikun | 0:13413ea9a877 | 6 | * @date 14-April-2017 |
| ganlikun | 0:13413ea9a877 | 7 | * @brief Extended PWR HAL module driver. |
| ganlikun | 0:13413ea9a877 | 8 | * This file provides firmware functions to manage the following |
| ganlikun | 0:13413ea9a877 | 9 | * functionalities of PWR extension peripheral: |
| ganlikun | 0:13413ea9a877 | 10 | * + Peripheral Extended features functions |
| ganlikun | 0:13413ea9a877 | 11 | * |
| ganlikun | 0:13413ea9a877 | 12 | ****************************************************************************** |
| ganlikun | 0:13413ea9a877 | 13 | * @attention |
| ganlikun | 0:13413ea9a877 | 14 | * |
| ganlikun | 0:13413ea9a877 | 15 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| ganlikun | 0:13413ea9a877 | 16 | * |
| ganlikun | 0:13413ea9a877 | 17 | * Redistribution and use in source and binary forms, with or without modification, |
| ganlikun | 0:13413ea9a877 | 18 | * are permitted provided that the following conditions are met: |
| ganlikun | 0:13413ea9a877 | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
| ganlikun | 0:13413ea9a877 | 20 | * this list of conditions and the following disclaimer. |
| ganlikun | 0:13413ea9a877 | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| ganlikun | 0:13413ea9a877 | 22 | * this list of conditions and the following disclaimer in the documentation |
| ganlikun | 0:13413ea9a877 | 23 | * and/or other materials provided with the distribution. |
| ganlikun | 0:13413ea9a877 | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| ganlikun | 0:13413ea9a877 | 25 | * may be used to endorse or promote products derived from this software |
| ganlikun | 0:13413ea9a877 | 26 | * without specific prior written permission. |
| ganlikun | 0:13413ea9a877 | 27 | * |
| ganlikun | 0:13413ea9a877 | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| ganlikun | 0:13413ea9a877 | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| ganlikun | 0:13413ea9a877 | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| ganlikun | 0:13413ea9a877 | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| ganlikun | 0:13413ea9a877 | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| ganlikun | 0:13413ea9a877 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| ganlikun | 0:13413ea9a877 | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| ganlikun | 0:13413ea9a877 | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| ganlikun | 0:13413ea9a877 | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| ganlikun | 0:13413ea9a877 | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| ganlikun | 0:13413ea9a877 | 38 | * |
| ganlikun | 0:13413ea9a877 | 39 | ****************************************************************************** |
| ganlikun | 0:13413ea9a877 | 40 | */ |
| ganlikun | 0:13413ea9a877 | 41 | |
| ganlikun | 0:13413ea9a877 | 42 | /* Includes ------------------------------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 43 | #include "stm32f4xx_hal.h" |
| ganlikun | 0:13413ea9a877 | 44 | |
| ganlikun | 0:13413ea9a877 | 45 | /** @addtogroup STM32F4xx_HAL_Driver |
| ganlikun | 0:13413ea9a877 | 46 | * @{ |
| ganlikun | 0:13413ea9a877 | 47 | */ |
| ganlikun | 0:13413ea9a877 | 48 | |
| ganlikun | 0:13413ea9a877 | 49 | /** @defgroup PWREx PWREx |
| ganlikun | 0:13413ea9a877 | 50 | * @brief PWR HAL module driver |
| ganlikun | 0:13413ea9a877 | 51 | * @{ |
| ganlikun | 0:13413ea9a877 | 52 | */ |
| ganlikun | 0:13413ea9a877 | 53 | |
| ganlikun | 0:13413ea9a877 | 54 | #ifdef HAL_PWR_MODULE_ENABLED |
| ganlikun | 0:13413ea9a877 | 55 | |
| ganlikun | 0:13413ea9a877 | 56 | /* Private typedef -----------------------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 57 | /* Private define ------------------------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 58 | /** @addtogroup PWREx_Private_Constants |
| ganlikun | 0:13413ea9a877 | 59 | * @{ |
| ganlikun | 0:13413ea9a877 | 60 | */ |
| ganlikun | 0:13413ea9a877 | 61 | #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U |
| ganlikun | 0:13413ea9a877 | 62 | #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U |
| ganlikun | 0:13413ea9a877 | 63 | #define PWR_BKPREG_TIMEOUT_VALUE 1000U |
| ganlikun | 0:13413ea9a877 | 64 | #define PWR_VOSRDY_TIMEOUT_VALUE 1000U |
| ganlikun | 0:13413ea9a877 | 65 | /** |
| ganlikun | 0:13413ea9a877 | 66 | * @} |
| ganlikun | 0:13413ea9a877 | 67 | */ |
| ganlikun | 0:13413ea9a877 | 68 | |
| ganlikun | 0:13413ea9a877 | 69 | |
| ganlikun | 0:13413ea9a877 | 70 | /* Private macro -------------------------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 71 | /* Private variables ---------------------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 72 | /* Private function prototypes -----------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 73 | /* Private functions ---------------------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 74 | /** @defgroup PWREx_Exported_Functions PWREx Exported Functions |
| ganlikun | 0:13413ea9a877 | 75 | * @{ |
| ganlikun | 0:13413ea9a877 | 76 | */ |
| ganlikun | 0:13413ea9a877 | 77 | |
| ganlikun | 0:13413ea9a877 | 78 | /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions |
| ganlikun | 0:13413ea9a877 | 79 | * @brief Peripheral Extended features functions |
| ganlikun | 0:13413ea9a877 | 80 | * |
| ganlikun | 0:13413ea9a877 | 81 | @verbatim |
| ganlikun | 0:13413ea9a877 | 82 | |
| ganlikun | 0:13413ea9a877 | 83 | =============================================================================== |
| ganlikun | 0:13413ea9a877 | 84 | ##### Peripheral extended features functions ##### |
| ganlikun | 0:13413ea9a877 | 85 | =============================================================================== |
| ganlikun | 0:13413ea9a877 | 86 | |
| ganlikun | 0:13413ea9a877 | 87 | *** Main and Backup Regulators configuration *** |
| ganlikun | 0:13413ea9a877 | 88 | ================================================ |
| ganlikun | 0:13413ea9a877 | 89 | [..] |
| ganlikun | 0:13413ea9a877 | 90 | (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from |
| ganlikun | 0:13413ea9a877 | 91 | the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is |
| ganlikun | 0:13413ea9a877 | 92 | retained even in Standby or VBAT mode when the low power backup regulator |
| ganlikun | 0:13413ea9a877 | 93 | is enabled. It can be considered as an internal EEPROM when VBAT is |
| ganlikun | 0:13413ea9a877 | 94 | always present. You can use the HAL_PWREx_EnableBkUpReg() function to |
| ganlikun | 0:13413ea9a877 | 95 | enable the low power backup regulator. |
| ganlikun | 0:13413ea9a877 | 96 | |
| ganlikun | 0:13413ea9a877 | 97 | (+) When the backup domain is supplied by VDD (analog switch connected to VDD) |
| ganlikun | 0:13413ea9a877 | 98 | the backup SRAM is powered from VDD which replaces the VBAT power supply to |
| ganlikun | 0:13413ea9a877 | 99 | save battery life. |
| ganlikun | 0:13413ea9a877 | 100 | |
| ganlikun | 0:13413ea9a877 | 101 | (+) The backup SRAM is not mass erased by a tamper event. It is read |
| ganlikun | 0:13413ea9a877 | 102 | protected to prevent confidential data, such as cryptographic private |
| ganlikun | 0:13413ea9a877 | 103 | key, from being accessed. The backup SRAM can be erased only through |
| ganlikun | 0:13413ea9a877 | 104 | the Flash interface when a protection level change from level 1 to |
| ganlikun | 0:13413ea9a877 | 105 | level 0 is requested. |
| ganlikun | 0:13413ea9a877 | 106 | -@- Refer to the description of Read protection (RDP) in the Flash |
| ganlikun | 0:13413ea9a877 | 107 | programming manual. |
| ganlikun | 0:13413ea9a877 | 108 | |
| ganlikun | 0:13413ea9a877 | 109 | (+) The main internal regulator can be configured to have a tradeoff between |
| ganlikun | 0:13413ea9a877 | 110 | performance and power consumption when the device does not operate at |
| ganlikun | 0:13413ea9a877 | 111 | the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() |
| ganlikun | 0:13413ea9a877 | 112 | macro which configure VOS bit in PWR_CR register |
| ganlikun | 0:13413ea9a877 | 113 | |
| ganlikun | 0:13413ea9a877 | 114 | Refer to the product datasheets for more details. |
| ganlikun | 0:13413ea9a877 | 115 | |
| ganlikun | 0:13413ea9a877 | 116 | *** FLASH Power Down configuration **** |
| ganlikun | 0:13413ea9a877 | 117 | ======================================= |
| ganlikun | 0:13413ea9a877 | 118 | [..] |
| ganlikun | 0:13413ea9a877 | 119 | (+) By setting the FPDS bit in the PWR_CR register by using the |
| ganlikun | 0:13413ea9a877 | 120 | HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power |
| ganlikun | 0:13413ea9a877 | 121 | down mode when the device enters Stop mode. When the Flash memory |
| ganlikun | 0:13413ea9a877 | 122 | is in power down mode, an additional startup delay is incurred when |
| ganlikun | 0:13413ea9a877 | 123 | waking up from Stop mode. |
| ganlikun | 0:13413ea9a877 | 124 | |
| ganlikun | 0:13413ea9a877 | 125 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL |
| ganlikun | 0:13413ea9a877 | 126 | is OFF and the HSI or HSE clock source is selected as system clock. |
| ganlikun | 0:13413ea9a877 | 127 | The new value programmed is active only when the PLL is ON. |
| ganlikun | 0:13413ea9a877 | 128 | When the PLL is OFF, the voltage scale 3 is automatically selected. |
| ganlikun | 0:13413ea9a877 | 129 | Refer to the datasheets for more details. |
| ganlikun | 0:13413ea9a877 | 130 | |
| ganlikun | 0:13413ea9a877 | 131 | *** Over-Drive and Under-Drive configuration **** |
| ganlikun | 0:13413ea9a877 | 132 | ================================================= |
| ganlikun | 0:13413ea9a877 | 133 | [..] |
| ganlikun | 0:13413ea9a877 | 134 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has |
| ganlikun | 0:13413ea9a877 | 135 | 2 operating modes available: |
| ganlikun | 0:13413ea9a877 | 136 | (++) Normal mode: The CPU and core logic operate at maximum frequency at a given |
| ganlikun | 0:13413ea9a877 | 137 | voltage scaling (scale 1, scale 2 or scale 3) |
| ganlikun | 0:13413ea9a877 | 138 | (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a |
| ganlikun | 0:13413ea9a877 | 139 | higher frequency than the normal mode for a given voltage scaling (scale 1, |
| ganlikun | 0:13413ea9a877 | 140 | scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and |
| ganlikun | 0:13413ea9a877 | 141 | disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow |
| ganlikun | 0:13413ea9a877 | 142 | the sequence described in Reference manual. |
| ganlikun | 0:13413ea9a877 | 143 | |
| ganlikun | 0:13413ea9a877 | 144 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator |
| ganlikun | 0:13413ea9a877 | 145 | supplies a low power voltage to the 1.2V domain, thus preserving the content of registers |
| ganlikun | 0:13413ea9a877 | 146 | and internal SRAM. 2 operating modes are available: |
| ganlikun | 0:13413ea9a877 | 147 | (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only |
| ganlikun | 0:13413ea9a877 | 148 | available when the main regulator or the low power regulator is used in Scale 3 or |
| ganlikun | 0:13413ea9a877 | 149 | low voltage mode. |
| ganlikun | 0:13413ea9a877 | 150 | (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only |
| ganlikun | 0:13413ea9a877 | 151 | available when the main regulator or the low power regulator is in low voltage mode. |
| ganlikun | 0:13413ea9a877 | 152 | |
| ganlikun | 0:13413ea9a877 | 153 | @endverbatim |
| ganlikun | 0:13413ea9a877 | 154 | * @{ |
| ganlikun | 0:13413ea9a877 | 155 | */ |
| ganlikun | 0:13413ea9a877 | 156 | |
| ganlikun | 0:13413ea9a877 | 157 | /** |
| ganlikun | 0:13413ea9a877 | 158 | * @brief Enables the Backup Regulator. |
| ganlikun | 0:13413ea9a877 | 159 | * @retval HAL status |
| ganlikun | 0:13413ea9a877 | 160 | */ |
| ganlikun | 0:13413ea9a877 | 161 | HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) |
| ganlikun | 0:13413ea9a877 | 162 | { |
| ganlikun | 0:13413ea9a877 | 163 | uint32_t tickstart = 0U; |
| ganlikun | 0:13413ea9a877 | 164 | |
| ganlikun | 0:13413ea9a877 | 165 | *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; |
| ganlikun | 0:13413ea9a877 | 166 | |
| ganlikun | 0:13413ea9a877 | 167 | /* Get tick */ |
| ganlikun | 0:13413ea9a877 | 168 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 169 | |
| ganlikun | 0:13413ea9a877 | 170 | /* Wait till Backup regulator ready flag is set */ |
| ganlikun | 0:13413ea9a877 | 171 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) |
| ganlikun | 0:13413ea9a877 | 172 | { |
| ganlikun | 0:13413ea9a877 | 173 | if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 174 | { |
| ganlikun | 0:13413ea9a877 | 175 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 176 | } |
| ganlikun | 0:13413ea9a877 | 177 | } |
| ganlikun | 0:13413ea9a877 | 178 | return HAL_OK; |
| ganlikun | 0:13413ea9a877 | 179 | } |
| ganlikun | 0:13413ea9a877 | 180 | |
| ganlikun | 0:13413ea9a877 | 181 | /** |
| ganlikun | 0:13413ea9a877 | 182 | * @brief Disables the Backup Regulator. |
| ganlikun | 0:13413ea9a877 | 183 | * @retval HAL status |
| ganlikun | 0:13413ea9a877 | 184 | */ |
| ganlikun | 0:13413ea9a877 | 185 | HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) |
| ganlikun | 0:13413ea9a877 | 186 | { |
| ganlikun | 0:13413ea9a877 | 187 | uint32_t tickstart = 0U; |
| ganlikun | 0:13413ea9a877 | 188 | |
| ganlikun | 0:13413ea9a877 | 189 | *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; |
| ganlikun | 0:13413ea9a877 | 190 | |
| ganlikun | 0:13413ea9a877 | 191 | /* Get tick */ |
| ganlikun | 0:13413ea9a877 | 192 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 193 | |
| ganlikun | 0:13413ea9a877 | 194 | /* Wait till Backup regulator ready flag is set */ |
| ganlikun | 0:13413ea9a877 | 195 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) |
| ganlikun | 0:13413ea9a877 | 196 | { |
| ganlikun | 0:13413ea9a877 | 197 | if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 198 | { |
| ganlikun | 0:13413ea9a877 | 199 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 200 | } |
| ganlikun | 0:13413ea9a877 | 201 | } |
| ganlikun | 0:13413ea9a877 | 202 | return HAL_OK; |
| ganlikun | 0:13413ea9a877 | 203 | } |
| ganlikun | 0:13413ea9a877 | 204 | |
| ganlikun | 0:13413ea9a877 | 205 | /** |
| ganlikun | 0:13413ea9a877 | 206 | * @brief Enables the Flash Power Down in Stop mode. |
| ganlikun | 0:13413ea9a877 | 207 | * @retval None |
| ganlikun | 0:13413ea9a877 | 208 | */ |
| ganlikun | 0:13413ea9a877 | 209 | void HAL_PWREx_EnableFlashPowerDown(void) |
| ganlikun | 0:13413ea9a877 | 210 | { |
| ganlikun | 0:13413ea9a877 | 211 | *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; |
| ganlikun | 0:13413ea9a877 | 212 | } |
| ganlikun | 0:13413ea9a877 | 213 | |
| ganlikun | 0:13413ea9a877 | 214 | /** |
| ganlikun | 0:13413ea9a877 | 215 | * @brief Disables the Flash Power Down in Stop mode. |
| ganlikun | 0:13413ea9a877 | 216 | * @retval None |
| ganlikun | 0:13413ea9a877 | 217 | */ |
| ganlikun | 0:13413ea9a877 | 218 | void HAL_PWREx_DisableFlashPowerDown(void) |
| ganlikun | 0:13413ea9a877 | 219 | { |
| ganlikun | 0:13413ea9a877 | 220 | *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; |
| ganlikun | 0:13413ea9a877 | 221 | } |
| ganlikun | 0:13413ea9a877 | 222 | |
| ganlikun | 0:13413ea9a877 | 223 | /** |
| ganlikun | 0:13413ea9a877 | 224 | * @brief Return Voltage Scaling Range. |
| ganlikun | 0:13413ea9a877 | 225 | * @retval The configured scale for the regulator voltage(VOS bit field). |
| ganlikun | 0:13413ea9a877 | 226 | * The returned value can be one of the following: |
| ganlikun | 0:13413ea9a877 | 227 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode |
| ganlikun | 0:13413ea9a877 | 228 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode |
| ganlikun | 0:13413ea9a877 | 229 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode |
| ganlikun | 0:13413ea9a877 | 230 | */ |
| ganlikun | 0:13413ea9a877 | 231 | uint32_t HAL_PWREx_GetVoltageRange(void) |
| ganlikun | 0:13413ea9a877 | 232 | { |
| ganlikun | 0:13413ea9a877 | 233 | return (PWR->CR & PWR_CR_VOS); |
| ganlikun | 0:13413ea9a877 | 234 | } |
| ganlikun | 0:13413ea9a877 | 235 | |
| ganlikun | 0:13413ea9a877 | 236 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| ganlikun | 0:13413ea9a877 | 237 | /** |
| ganlikun | 0:13413ea9a877 | 238 | * @brief Configures the main internal regulator output voltage. |
| ganlikun | 0:13413ea9a877 | 239 | * @param VoltageScaling: specifies the regulator output voltage to achieve |
| ganlikun | 0:13413ea9a877 | 240 | * a tradeoff between performance and power consumption. |
| ganlikun | 0:13413ea9a877 | 241 | * This parameter can be one of the following values: |
| ganlikun | 0:13413ea9a877 | 242 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, |
| ganlikun | 0:13413ea9a877 | 243 | * the maximum value of fHCLK = 168 MHz. |
| ganlikun | 0:13413ea9a877 | 244 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, |
| ganlikun | 0:13413ea9a877 | 245 | * the maximum value of fHCLK = 144 MHz. |
| ganlikun | 0:13413ea9a877 | 246 | * @note When moving from Range 1 to Range 2, the system frequency must be decreased to |
| ganlikun | 0:13413ea9a877 | 247 | * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. |
| ganlikun | 0:13413ea9a877 | 248 | * When moving from Range 2 to Range 1, the system frequency can be increased to |
| ganlikun | 0:13413ea9a877 | 249 | * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. |
| ganlikun | 0:13413ea9a877 | 250 | * @retval HAL Status |
| ganlikun | 0:13413ea9a877 | 251 | */ |
| ganlikun | 0:13413ea9a877 | 252 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) |
| ganlikun | 0:13413ea9a877 | 253 | { |
| ganlikun | 0:13413ea9a877 | 254 | uint32_t tickstart = 0U; |
| ganlikun | 0:13413ea9a877 | 255 | |
| ganlikun | 0:13413ea9a877 | 256 | assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); |
| ganlikun | 0:13413ea9a877 | 257 | |
| ganlikun | 0:13413ea9a877 | 258 | /* Enable PWR RCC Clock Peripheral */ |
| ganlikun | 0:13413ea9a877 | 259 | __HAL_RCC_PWR_CLK_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 260 | |
| ganlikun | 0:13413ea9a877 | 261 | /* Set Range */ |
| ganlikun | 0:13413ea9a877 | 262 | __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); |
| ganlikun | 0:13413ea9a877 | 263 | |
| ganlikun | 0:13413ea9a877 | 264 | /* Get Start Tick*/ |
| ganlikun | 0:13413ea9a877 | 265 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 266 | while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) |
| ganlikun | 0:13413ea9a877 | 267 | { |
| ganlikun | 0:13413ea9a877 | 268 | if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 269 | { |
| ganlikun | 0:13413ea9a877 | 270 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 271 | } |
| ganlikun | 0:13413ea9a877 | 272 | } |
| ganlikun | 0:13413ea9a877 | 273 | |
| ganlikun | 0:13413ea9a877 | 274 | return HAL_OK; |
| ganlikun | 0:13413ea9a877 | 275 | } |
| ganlikun | 0:13413ea9a877 | 276 | |
| ganlikun | 0:13413ea9a877 | 277 | #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
| ganlikun | 0:13413ea9a877 | 278 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ |
| ganlikun | 0:13413ea9a877 | 279 | defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ |
| ganlikun | 0:13413ea9a877 | 280 | defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ |
| ganlikun | 0:13413ea9a877 | 281 | defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) |
| ganlikun | 0:13413ea9a877 | 282 | /** |
| ganlikun | 0:13413ea9a877 | 283 | * @brief Configures the main internal regulator output voltage. |
| ganlikun | 0:13413ea9a877 | 284 | * @param VoltageScaling: specifies the regulator output voltage to achieve |
| ganlikun | 0:13413ea9a877 | 285 | * a tradeoff between performance and power consumption. |
| ganlikun | 0:13413ea9a877 | 286 | * This parameter can be one of the following values: |
| ganlikun | 0:13413ea9a877 | 287 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, |
| ganlikun | 0:13413ea9a877 | 288 | * the maximum value of fHCLK is 168 MHz. It can be extended to |
| ganlikun | 0:13413ea9a877 | 289 | * 180 MHz by activating the over-drive mode. |
| ganlikun | 0:13413ea9a877 | 290 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, |
| ganlikun | 0:13413ea9a877 | 291 | * the maximum value of fHCLK is 144 MHz. It can be extended to, |
| ganlikun | 0:13413ea9a877 | 292 | * 168 MHz by activating the over-drive mode. |
| ganlikun | 0:13413ea9a877 | 293 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, |
| ganlikun | 0:13413ea9a877 | 294 | * the maximum value of fHCLK is 120 MHz. |
| ganlikun | 0:13413ea9a877 | 295 | * @note To update the system clock frequency(SYSCLK): |
| ganlikun | 0:13413ea9a877 | 296 | * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). |
| ganlikun | 0:13413ea9a877 | 297 | * - Call the HAL_RCC_OscConfig() to configure the PLL. |
| ganlikun | 0:13413ea9a877 | 298 | * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. |
| ganlikun | 0:13413ea9a877 | 299 | * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). |
| ganlikun | 0:13413ea9a877 | 300 | * @note The scale can be modified only when the HSI or HSE clock source is selected |
| ganlikun | 0:13413ea9a877 | 301 | * as system clock source, otherwise the API returns HAL_ERROR. |
| ganlikun | 0:13413ea9a877 | 302 | * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits |
| ganlikun | 0:13413ea9a877 | 303 | * value in the PWR_CR1 register are not taken in account. |
| ganlikun | 0:13413ea9a877 | 304 | * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. |
| ganlikun | 0:13413ea9a877 | 305 | * @note The new voltage scale is active only when the PLL is ON. |
| ganlikun | 0:13413ea9a877 | 306 | * @retval HAL Status |
| ganlikun | 0:13413ea9a877 | 307 | */ |
| ganlikun | 0:13413ea9a877 | 308 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) |
| ganlikun | 0:13413ea9a877 | 309 | { |
| ganlikun | 0:13413ea9a877 | 310 | uint32_t tickstart = 0U; |
| ganlikun | 0:13413ea9a877 | 311 | |
| ganlikun | 0:13413ea9a877 | 312 | assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); |
| ganlikun | 0:13413ea9a877 | 313 | |
| ganlikun | 0:13413ea9a877 | 314 | /* Enable PWR RCC Clock Peripheral */ |
| ganlikun | 0:13413ea9a877 | 315 | __HAL_RCC_PWR_CLK_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 316 | |
| ganlikun | 0:13413ea9a877 | 317 | /* Check if the PLL is used as system clock or not */ |
| ganlikun | 0:13413ea9a877 | 318 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) |
| ganlikun | 0:13413ea9a877 | 319 | { |
| ganlikun | 0:13413ea9a877 | 320 | /* Disable the main PLL */ |
| ganlikun | 0:13413ea9a877 | 321 | __HAL_RCC_PLL_DISABLE(); |
| ganlikun | 0:13413ea9a877 | 322 | |
| ganlikun | 0:13413ea9a877 | 323 | /* Get Start Tick */ |
| ganlikun | 0:13413ea9a877 | 324 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 325 | /* Wait till PLL is disabled */ |
| ganlikun | 0:13413ea9a877 | 326 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
| ganlikun | 0:13413ea9a877 | 327 | { |
| ganlikun | 0:13413ea9a877 | 328 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 329 | { |
| ganlikun | 0:13413ea9a877 | 330 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 331 | } |
| ganlikun | 0:13413ea9a877 | 332 | } |
| ganlikun | 0:13413ea9a877 | 333 | |
| ganlikun | 0:13413ea9a877 | 334 | /* Set Range */ |
| ganlikun | 0:13413ea9a877 | 335 | __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); |
| ganlikun | 0:13413ea9a877 | 336 | |
| ganlikun | 0:13413ea9a877 | 337 | /* Enable the main PLL */ |
| ganlikun | 0:13413ea9a877 | 338 | __HAL_RCC_PLL_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 339 | |
| ganlikun | 0:13413ea9a877 | 340 | /* Get Start Tick */ |
| ganlikun | 0:13413ea9a877 | 341 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 342 | /* Wait till PLL is ready */ |
| ganlikun | 0:13413ea9a877 | 343 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
| ganlikun | 0:13413ea9a877 | 344 | { |
| ganlikun | 0:13413ea9a877 | 345 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 346 | { |
| ganlikun | 0:13413ea9a877 | 347 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 348 | } |
| ganlikun | 0:13413ea9a877 | 349 | } |
| ganlikun | 0:13413ea9a877 | 350 | |
| ganlikun | 0:13413ea9a877 | 351 | /* Get Start Tick */ |
| ganlikun | 0:13413ea9a877 | 352 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 353 | while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) |
| ganlikun | 0:13413ea9a877 | 354 | { |
| ganlikun | 0:13413ea9a877 | 355 | if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 356 | { |
| ganlikun | 0:13413ea9a877 | 357 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 358 | } |
| ganlikun | 0:13413ea9a877 | 359 | } |
| ganlikun | 0:13413ea9a877 | 360 | } |
| ganlikun | 0:13413ea9a877 | 361 | else |
| ganlikun | 0:13413ea9a877 | 362 | { |
| ganlikun | 0:13413ea9a877 | 363 | return HAL_ERROR; |
| ganlikun | 0:13413ea9a877 | 364 | } |
| ganlikun | 0:13413ea9a877 | 365 | |
| ganlikun | 0:13413ea9a877 | 366 | return HAL_OK; |
| ganlikun | 0:13413ea9a877 | 367 | } |
| ganlikun | 0:13413ea9a877 | 368 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| ganlikun | 0:13413ea9a877 | 369 | |
| ganlikun | 0:13413ea9a877 | 370 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| ganlikun | 0:13413ea9a877 | 371 | /** |
| ganlikun | 0:13413ea9a877 | 372 | * @brief Enables Wakeup Pin Detection on high level (rising edge). |
| ganlikun | 0:13413ea9a877 | 373 | * @retval None |
| ganlikun | 0:13413ea9a877 | 374 | */ |
| ganlikun | 0:13413ea9a877 | 375 | void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void) |
| ganlikun | 0:13413ea9a877 | 376 | { |
| ganlikun | 0:13413ea9a877 | 377 | *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE; |
| ganlikun | 0:13413ea9a877 | 378 | } |
| ganlikun | 0:13413ea9a877 | 379 | |
| ganlikun | 0:13413ea9a877 | 380 | /** |
| ganlikun | 0:13413ea9a877 | 381 | * @brief Enables Wakeup Pin Detection on low level (falling edge). |
| ganlikun | 0:13413ea9a877 | 382 | * @retval None |
| ganlikun | 0:13413ea9a877 | 383 | */ |
| ganlikun | 0:13413ea9a877 | 384 | void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void) |
| ganlikun | 0:13413ea9a877 | 385 | { |
| ganlikun | 0:13413ea9a877 | 386 | *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE; |
| ganlikun | 0:13413ea9a877 | 387 | } |
| ganlikun | 0:13413ea9a877 | 388 | #endif /* STM32F469xx || STM32F479xx */ |
| ganlikun | 0:13413ea9a877 | 389 | |
| ganlikun | 0:13413ea9a877 | 390 | #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ |
| ganlikun | 0:13413ea9a877 | 391 | defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ |
| ganlikun | 0:13413ea9a877 | 392 | defined(STM32F413xx) || defined(STM32F423xx) |
| ganlikun | 0:13413ea9a877 | 393 | /** |
| ganlikun | 0:13413ea9a877 | 394 | * @brief Enables Main Regulator low voltage mode. |
| ganlikun | 0:13413ea9a877 | 395 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ |
| ganlikun | 0:13413ea9a877 | 396 | * STM32F413xx/STM32F423xx devices. |
| ganlikun | 0:13413ea9a877 | 397 | * @retval None |
| ganlikun | 0:13413ea9a877 | 398 | */ |
| ganlikun | 0:13413ea9a877 | 399 | void HAL_PWREx_EnableMainRegulatorLowVoltage(void) |
| ganlikun | 0:13413ea9a877 | 400 | { |
| ganlikun | 0:13413ea9a877 | 401 | *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; |
| ganlikun | 0:13413ea9a877 | 402 | } |
| ganlikun | 0:13413ea9a877 | 403 | |
| ganlikun | 0:13413ea9a877 | 404 | /** |
| ganlikun | 0:13413ea9a877 | 405 | * @brief Disables Main Regulator low voltage mode. |
| ganlikun | 0:13413ea9a877 | 406 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ |
| ganlikun | 0:13413ea9a877 | 407 | * STM32F413xx/STM32F423xxdevices. |
| ganlikun | 0:13413ea9a877 | 408 | * @retval None |
| ganlikun | 0:13413ea9a877 | 409 | */ |
| ganlikun | 0:13413ea9a877 | 410 | void HAL_PWREx_DisableMainRegulatorLowVoltage(void) |
| ganlikun | 0:13413ea9a877 | 411 | { |
| ganlikun | 0:13413ea9a877 | 412 | *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; |
| ganlikun | 0:13413ea9a877 | 413 | } |
| ganlikun | 0:13413ea9a877 | 414 | |
| ganlikun | 0:13413ea9a877 | 415 | /** |
| ganlikun | 0:13413ea9a877 | 416 | * @brief Enables Low Power Regulator low voltage mode. |
| ganlikun | 0:13413ea9a877 | 417 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ |
| ganlikun | 0:13413ea9a877 | 418 | * STM32F413xx/STM32F423xx devices. |
| ganlikun | 0:13413ea9a877 | 419 | * @retval None |
| ganlikun | 0:13413ea9a877 | 420 | */ |
| ganlikun | 0:13413ea9a877 | 421 | void HAL_PWREx_EnableLowRegulatorLowVoltage(void) |
| ganlikun | 0:13413ea9a877 | 422 | { |
| ganlikun | 0:13413ea9a877 | 423 | *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; |
| ganlikun | 0:13413ea9a877 | 424 | } |
| ganlikun | 0:13413ea9a877 | 425 | |
| ganlikun | 0:13413ea9a877 | 426 | /** |
| ganlikun | 0:13413ea9a877 | 427 | * @brief Disables Low Power Regulator low voltage mode. |
| ganlikun | 0:13413ea9a877 | 428 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ |
| ganlikun | 0:13413ea9a877 | 429 | * STM32F413xx/STM32F423xx devices. |
| ganlikun | 0:13413ea9a877 | 430 | * @retval None |
| ganlikun | 0:13413ea9a877 | 431 | */ |
| ganlikun | 0:13413ea9a877 | 432 | void HAL_PWREx_DisableLowRegulatorLowVoltage(void) |
| ganlikun | 0:13413ea9a877 | 433 | { |
| ganlikun | 0:13413ea9a877 | 434 | *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; |
| ganlikun | 0:13413ea9a877 | 435 | } |
| ganlikun | 0:13413ea9a877 | 436 | |
| ganlikun | 0:13413ea9a877 | 437 | #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || |
| ganlikun | 0:13413ea9a877 | 438 | STM32F413xx || STM32F423xx */ |
| ganlikun | 0:13413ea9a877 | 439 | |
| ganlikun | 0:13413ea9a877 | 440 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| ganlikun | 0:13413ea9a877 | 441 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| ganlikun | 0:13413ea9a877 | 442 | /** |
| ganlikun | 0:13413ea9a877 | 443 | * @brief Activates the Over-Drive mode. |
| ganlikun | 0:13413ea9a877 | 444 | * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. |
| ganlikun | 0:13413ea9a877 | 445 | * This mode allows the CPU and the core logic to operate at a higher frequency |
| ganlikun | 0:13413ea9a877 | 446 | * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). |
| ganlikun | 0:13413ea9a877 | 447 | * @note It is recommended to enter or exit Over-drive mode when the application is not running |
| ganlikun | 0:13413ea9a877 | 448 | * critical tasks and when the system clock source is either HSI or HSE. |
| ganlikun | 0:13413ea9a877 | 449 | * During the Over-drive switch activation, no peripheral clocks should be enabled. |
| ganlikun | 0:13413ea9a877 | 450 | * The peripheral clocks must be enabled once the Over-drive mode is activated. |
| ganlikun | 0:13413ea9a877 | 451 | * @retval HAL status |
| ganlikun | 0:13413ea9a877 | 452 | */ |
| ganlikun | 0:13413ea9a877 | 453 | HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) |
| ganlikun | 0:13413ea9a877 | 454 | { |
| ganlikun | 0:13413ea9a877 | 455 | uint32_t tickstart = 0U; |
| ganlikun | 0:13413ea9a877 | 456 | |
| ganlikun | 0:13413ea9a877 | 457 | __HAL_RCC_PWR_CLK_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 458 | |
| ganlikun | 0:13413ea9a877 | 459 | /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ |
| ganlikun | 0:13413ea9a877 | 460 | __HAL_PWR_OVERDRIVE_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 461 | |
| ganlikun | 0:13413ea9a877 | 462 | /* Get tick */ |
| ganlikun | 0:13413ea9a877 | 463 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 464 | |
| ganlikun | 0:13413ea9a877 | 465 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) |
| ganlikun | 0:13413ea9a877 | 466 | { |
| ganlikun | 0:13413ea9a877 | 467 | if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 468 | { |
| ganlikun | 0:13413ea9a877 | 469 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 470 | } |
| ganlikun | 0:13413ea9a877 | 471 | } |
| ganlikun | 0:13413ea9a877 | 472 | |
| ganlikun | 0:13413ea9a877 | 473 | /* Enable the Over-drive switch */ |
| ganlikun | 0:13413ea9a877 | 474 | __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 475 | |
| ganlikun | 0:13413ea9a877 | 476 | /* Get tick */ |
| ganlikun | 0:13413ea9a877 | 477 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 478 | |
| ganlikun | 0:13413ea9a877 | 479 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) |
| ganlikun | 0:13413ea9a877 | 480 | { |
| ganlikun | 0:13413ea9a877 | 481 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 482 | { |
| ganlikun | 0:13413ea9a877 | 483 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 484 | } |
| ganlikun | 0:13413ea9a877 | 485 | } |
| ganlikun | 0:13413ea9a877 | 486 | return HAL_OK; |
| ganlikun | 0:13413ea9a877 | 487 | } |
| ganlikun | 0:13413ea9a877 | 488 | |
| ganlikun | 0:13413ea9a877 | 489 | /** |
| ganlikun | 0:13413ea9a877 | 490 | * @brief Deactivates the Over-Drive mode. |
| ganlikun | 0:13413ea9a877 | 491 | * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. |
| ganlikun | 0:13413ea9a877 | 492 | * This mode allows the CPU and the core logic to operate at a higher frequency |
| ganlikun | 0:13413ea9a877 | 493 | * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). |
| ganlikun | 0:13413ea9a877 | 494 | * @note It is recommended to enter or exit Over-drive mode when the application is not running |
| ganlikun | 0:13413ea9a877 | 495 | * critical tasks and when the system clock source is either HSI or HSE. |
| ganlikun | 0:13413ea9a877 | 496 | * During the Over-drive switch activation, no peripheral clocks should be enabled. |
| ganlikun | 0:13413ea9a877 | 497 | * The peripheral clocks must be enabled once the Over-drive mode is activated. |
| ganlikun | 0:13413ea9a877 | 498 | * @retval HAL status |
| ganlikun | 0:13413ea9a877 | 499 | */ |
| ganlikun | 0:13413ea9a877 | 500 | HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) |
| ganlikun | 0:13413ea9a877 | 501 | { |
| ganlikun | 0:13413ea9a877 | 502 | uint32_t tickstart = 0U; |
| ganlikun | 0:13413ea9a877 | 503 | |
| ganlikun | 0:13413ea9a877 | 504 | __HAL_RCC_PWR_CLK_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 505 | |
| ganlikun | 0:13413ea9a877 | 506 | /* Disable the Over-drive switch */ |
| ganlikun | 0:13413ea9a877 | 507 | __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); |
| ganlikun | 0:13413ea9a877 | 508 | |
| ganlikun | 0:13413ea9a877 | 509 | /* Get tick */ |
| ganlikun | 0:13413ea9a877 | 510 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 511 | |
| ganlikun | 0:13413ea9a877 | 512 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) |
| ganlikun | 0:13413ea9a877 | 513 | { |
| ganlikun | 0:13413ea9a877 | 514 | if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 515 | { |
| ganlikun | 0:13413ea9a877 | 516 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 517 | } |
| ganlikun | 0:13413ea9a877 | 518 | } |
| ganlikun | 0:13413ea9a877 | 519 | |
| ganlikun | 0:13413ea9a877 | 520 | /* Disable the Over-drive */ |
| ganlikun | 0:13413ea9a877 | 521 | __HAL_PWR_OVERDRIVE_DISABLE(); |
| ganlikun | 0:13413ea9a877 | 522 | |
| ganlikun | 0:13413ea9a877 | 523 | /* Get tick */ |
| ganlikun | 0:13413ea9a877 | 524 | tickstart = HAL_GetTick(); |
| ganlikun | 0:13413ea9a877 | 525 | |
| ganlikun | 0:13413ea9a877 | 526 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) |
| ganlikun | 0:13413ea9a877 | 527 | { |
| ganlikun | 0:13413ea9a877 | 528 | if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| ganlikun | 0:13413ea9a877 | 529 | { |
| ganlikun | 0:13413ea9a877 | 530 | return HAL_TIMEOUT; |
| ganlikun | 0:13413ea9a877 | 531 | } |
| ganlikun | 0:13413ea9a877 | 532 | } |
| ganlikun | 0:13413ea9a877 | 533 | |
| ganlikun | 0:13413ea9a877 | 534 | return HAL_OK; |
| ganlikun | 0:13413ea9a877 | 535 | } |
| ganlikun | 0:13413ea9a877 | 536 | |
| ganlikun | 0:13413ea9a877 | 537 | /** |
| ganlikun | 0:13413ea9a877 | 538 | * @brief Enters in Under-Drive STOP mode. |
| ganlikun | 0:13413ea9a877 | 539 | * |
| ganlikun | 0:13413ea9a877 | 540 | * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. |
| ganlikun | 0:13413ea9a877 | 541 | * |
| ganlikun | 0:13413ea9a877 | 542 | * @note This mode can be selected only when the Under-Drive is already active |
| ganlikun | 0:13413ea9a877 | 543 | * |
| ganlikun | 0:13413ea9a877 | 544 | * @note This mode is enabled only with STOP low power mode. |
| ganlikun | 0:13413ea9a877 | 545 | * In this mode, the 1.2V domain is preserved in reduced leakage mode. This |
| ganlikun | 0:13413ea9a877 | 546 | * mode is only available when the main regulator or the low power regulator |
| ganlikun | 0:13413ea9a877 | 547 | * is in low voltage mode |
| ganlikun | 0:13413ea9a877 | 548 | * |
| ganlikun | 0:13413ea9a877 | 549 | * @note If the Under-drive mode was enabled, it is automatically disabled after |
| ganlikun | 0:13413ea9a877 | 550 | * exiting Stop mode. |
| ganlikun | 0:13413ea9a877 | 551 | * When the voltage regulator operates in Under-drive mode, an additional |
| ganlikun | 0:13413ea9a877 | 552 | * startup delay is induced when waking up from Stop mode. |
| ganlikun | 0:13413ea9a877 | 553 | * |
| ganlikun | 0:13413ea9a877 | 554 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
| ganlikun | 0:13413ea9a877 | 555 | * |
| ganlikun | 0:13413ea9a877 | 556 | * @note When exiting Stop mode by issuing an interrupt or a wake-up event, |
| ganlikun | 0:13413ea9a877 | 557 | * the HSI RC oscillator is selected as system clock. |
| ganlikun | 0:13413ea9a877 | 558 | * |
| ganlikun | 0:13413ea9a877 | 559 | * @note When the voltage regulator operates in low power mode, an additional |
| ganlikun | 0:13413ea9a877 | 560 | * startup delay is incurred when waking up from Stop mode. |
| ganlikun | 0:13413ea9a877 | 561 | * By keeping the internal regulator ON during Stop mode, the consumption |
| ganlikun | 0:13413ea9a877 | 562 | * is higher although the startup time is reduced. |
| ganlikun | 0:13413ea9a877 | 563 | * |
| ganlikun | 0:13413ea9a877 | 564 | * @param Regulator: specifies the regulator state in STOP mode. |
| ganlikun | 0:13413ea9a877 | 565 | * This parameter can be one of the following values: |
| ganlikun | 0:13413ea9a877 | 566 | * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode |
| ganlikun | 0:13413ea9a877 | 567 | * and Flash memory in power-down when the device is in Stop under-drive mode |
| ganlikun | 0:13413ea9a877 | 568 | * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode |
| ganlikun | 0:13413ea9a877 | 569 | * and Flash memory in power-down when the device is in Stop under-drive mode |
| ganlikun | 0:13413ea9a877 | 570 | * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. |
| ganlikun | 0:13413ea9a877 | 571 | * This parameter can be one of the following values: |
| ganlikun | 0:13413ea9a877 | 572 | * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction |
| ganlikun | 0:13413ea9a877 | 573 | * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction |
| ganlikun | 0:13413ea9a877 | 574 | * @retval None |
| ganlikun | 0:13413ea9a877 | 575 | */ |
| ganlikun | 0:13413ea9a877 | 576 | HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
| ganlikun | 0:13413ea9a877 | 577 | { |
| ganlikun | 0:13413ea9a877 | 578 | uint32_t tmpreg1 = 0U; |
| ganlikun | 0:13413ea9a877 | 579 | |
| ganlikun | 0:13413ea9a877 | 580 | /* Check the parameters */ |
| ganlikun | 0:13413ea9a877 | 581 | assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); |
| ganlikun | 0:13413ea9a877 | 582 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
| ganlikun | 0:13413ea9a877 | 583 | |
| ganlikun | 0:13413ea9a877 | 584 | /* Enable Power ctrl clock */ |
| ganlikun | 0:13413ea9a877 | 585 | __HAL_RCC_PWR_CLK_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 586 | /* Enable the Under-drive Mode ---------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 587 | /* Clear Under-drive flag */ |
| ganlikun | 0:13413ea9a877 | 588 | __HAL_PWR_CLEAR_ODRUDR_FLAG(); |
| ganlikun | 0:13413ea9a877 | 589 | |
| ganlikun | 0:13413ea9a877 | 590 | /* Enable the Under-drive */ |
| ganlikun | 0:13413ea9a877 | 591 | __HAL_PWR_UNDERDRIVE_ENABLE(); |
| ganlikun | 0:13413ea9a877 | 592 | |
| ganlikun | 0:13413ea9a877 | 593 | /* Select the regulator state in STOP mode ---------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 594 | tmpreg1 = PWR->CR; |
| ganlikun | 0:13413ea9a877 | 595 | /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ |
| ganlikun | 0:13413ea9a877 | 596 | tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); |
| ganlikun | 0:13413ea9a877 | 597 | |
| ganlikun | 0:13413ea9a877 | 598 | /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ |
| ganlikun | 0:13413ea9a877 | 599 | tmpreg1 |= Regulator; |
| ganlikun | 0:13413ea9a877 | 600 | |
| ganlikun | 0:13413ea9a877 | 601 | /* Store the new value */ |
| ganlikun | 0:13413ea9a877 | 602 | PWR->CR = tmpreg1; |
| ganlikun | 0:13413ea9a877 | 603 | |
| ganlikun | 0:13413ea9a877 | 604 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| ganlikun | 0:13413ea9a877 | 605 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
| ganlikun | 0:13413ea9a877 | 606 | |
| ganlikun | 0:13413ea9a877 | 607 | /* Select STOP mode entry --------------------------------------------------*/ |
| ganlikun | 0:13413ea9a877 | 608 | if(STOPEntry == PWR_SLEEPENTRY_WFI) |
| ganlikun | 0:13413ea9a877 | 609 | { |
| ganlikun | 0:13413ea9a877 | 610 | /* Request Wait For Interrupt */ |
| ganlikun | 0:13413ea9a877 | 611 | __WFI(); |
| ganlikun | 0:13413ea9a877 | 612 | } |
| ganlikun | 0:13413ea9a877 | 613 | else |
| ganlikun | 0:13413ea9a877 | 614 | { |
| ganlikun | 0:13413ea9a877 | 615 | /* Request Wait For Event */ |
| ganlikun | 0:13413ea9a877 | 616 | __WFE(); |
| ganlikun | 0:13413ea9a877 | 617 | } |
| ganlikun | 0:13413ea9a877 | 618 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
| ganlikun | 0:13413ea9a877 | 619 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
| ganlikun | 0:13413ea9a877 | 620 | |
| ganlikun | 0:13413ea9a877 | 621 | return HAL_OK; |
| ganlikun | 0:13413ea9a877 | 622 | } |
| ganlikun | 0:13413ea9a877 | 623 | |
| ganlikun | 0:13413ea9a877 | 624 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| ganlikun | 0:13413ea9a877 | 625 | /** |
| ganlikun | 0:13413ea9a877 | 626 | * @} |
| ganlikun | 0:13413ea9a877 | 627 | */ |
| ganlikun | 0:13413ea9a877 | 628 | |
| ganlikun | 0:13413ea9a877 | 629 | /** |
| ganlikun | 0:13413ea9a877 | 630 | * @} |
| ganlikun | 0:13413ea9a877 | 631 | */ |
| ganlikun | 0:13413ea9a877 | 632 | |
| ganlikun | 0:13413ea9a877 | 633 | #endif /* HAL_PWR_MODULE_ENABLED */ |
| ganlikun | 0:13413ea9a877 | 634 | /** |
| ganlikun | 0:13413ea9a877 | 635 | * @} |
| ganlikun | 0:13413ea9a877 | 636 | */ |
| ganlikun | 0:13413ea9a877 | 637 | |
| ganlikun | 0:13413ea9a877 | 638 | /** |
| ganlikun | 0:13413ea9a877 | 639 | * @} |
| ganlikun | 0:13413ea9a877 | 640 | */ |
| ganlikun | 0:13413ea9a877 | 641 | |
| ganlikun | 0:13413ea9a877 | 642 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| ganlikun | 0:13413ea9a877 | 643 |