Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

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ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_hal_pwr.h
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief Header file of PWR HAL module.
ganlikun 0:13413ea9a877 8 ******************************************************************************
ganlikun 0:13413ea9a877 9 * @attention
ganlikun 0:13413ea9a877 10 *
ganlikun 0:13413ea9a877 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 12 *
ganlikun 0:13413ea9a877 13 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 14 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 15 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 16 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 18 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 19 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 21 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 22 * without specific prior written permission.
ganlikun 0:13413ea9a877 23 *
ganlikun 0:13413ea9a877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 34 *
ganlikun 0:13413ea9a877 35 ******************************************************************************
ganlikun 0:13413ea9a877 36 */
ganlikun 0:13413ea9a877 37
ganlikun 0:13413ea9a877 38 /* Define to prevent recursive inclusion -------------------------------------*/
ganlikun 0:13413ea9a877 39 #ifndef __STM32F4xx_HAL_PWR_H
ganlikun 0:13413ea9a877 40 #define __STM32F4xx_HAL_PWR_H
ganlikun 0:13413ea9a877 41
ganlikun 0:13413ea9a877 42 #ifdef __cplusplus
ganlikun 0:13413ea9a877 43 extern "C" {
ganlikun 0:13413ea9a877 44 #endif
ganlikun 0:13413ea9a877 45
ganlikun 0:13413ea9a877 46 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 47 #include "stm32f4xx_hal_def.h"
ganlikun 0:13413ea9a877 48
ganlikun 0:13413ea9a877 49 /** @addtogroup STM32F4xx_HAL_Driver
ganlikun 0:13413ea9a877 50 * @{
ganlikun 0:13413ea9a877 51 */
ganlikun 0:13413ea9a877 52
ganlikun 0:13413ea9a877 53 /** @addtogroup PWR
ganlikun 0:13413ea9a877 54 * @{
ganlikun 0:13413ea9a877 55 */
ganlikun 0:13413ea9a877 56
ganlikun 0:13413ea9a877 57 /* Exported types ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 58
ganlikun 0:13413ea9a877 59 /** @defgroup PWR_Exported_Types PWR Exported Types
ganlikun 0:13413ea9a877 60 * @{
ganlikun 0:13413ea9a877 61 */
ganlikun 0:13413ea9a877 62
ganlikun 0:13413ea9a877 63 /**
ganlikun 0:13413ea9a877 64 * @brief PWR PVD configuration structure definition
ganlikun 0:13413ea9a877 65 */
ganlikun 0:13413ea9a877 66 typedef struct
ganlikun 0:13413ea9a877 67 {
ganlikun 0:13413ea9a877 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
ganlikun 0:13413ea9a877 69 This parameter can be a value of @ref PWR_PVD_detection_level */
ganlikun 0:13413ea9a877 70
ganlikun 0:13413ea9a877 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
ganlikun 0:13413ea9a877 72 This parameter can be a value of @ref PWR_PVD_Mode */
ganlikun 0:13413ea9a877 73 }PWR_PVDTypeDef;
ganlikun 0:13413ea9a877 74
ganlikun 0:13413ea9a877 75 /**
ganlikun 0:13413ea9a877 76 * @}
ganlikun 0:13413ea9a877 77 */
ganlikun 0:13413ea9a877 78
ganlikun 0:13413ea9a877 79 /* Exported constants --------------------------------------------------------*/
ganlikun 0:13413ea9a877 80 /** @defgroup PWR_Exported_Constants PWR Exported Constants
ganlikun 0:13413ea9a877 81 * @{
ganlikun 0:13413ea9a877 82 */
ganlikun 0:13413ea9a877 83
ganlikun 0:13413ea9a877 84 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
ganlikun 0:13413ea9a877 85 * @{
ganlikun 0:13413ea9a877 86 */
ganlikun 0:13413ea9a877 87 #define PWR_WAKEUP_PIN1 0x00000100U
ganlikun 0:13413ea9a877 88 /**
ganlikun 0:13413ea9a877 89 * @}
ganlikun 0:13413ea9a877 90 */
ganlikun 0:13413ea9a877 91
ganlikun 0:13413ea9a877 92 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
ganlikun 0:13413ea9a877 93 * @{
ganlikun 0:13413ea9a877 94 */
ganlikun 0:13413ea9a877 95 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
ganlikun 0:13413ea9a877 96 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
ganlikun 0:13413ea9a877 97 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
ganlikun 0:13413ea9a877 98 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
ganlikun 0:13413ea9a877 99 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
ganlikun 0:13413ea9a877 100 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
ganlikun 0:13413ea9a877 101 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
ganlikun 0:13413ea9a877 102 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
ganlikun 0:13413ea9a877 103 (Compare internally to VREFINT) */
ganlikun 0:13413ea9a877 104 /**
ganlikun 0:13413ea9a877 105 * @}
ganlikun 0:13413ea9a877 106 */
ganlikun 0:13413ea9a877 107
ganlikun 0:13413ea9a877 108 /** @defgroup PWR_PVD_Mode PWR PVD Mode
ganlikun 0:13413ea9a877 109 * @{
ganlikun 0:13413ea9a877 110 */
ganlikun 0:13413ea9a877 111 #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
ganlikun 0:13413ea9a877 112 #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
ganlikun 0:13413ea9a877 113 #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
ganlikun 0:13413ea9a877 114 #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
ganlikun 0:13413ea9a877 115 #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
ganlikun 0:13413ea9a877 116 #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
ganlikun 0:13413ea9a877 117 #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
ganlikun 0:13413ea9a877 118 /**
ganlikun 0:13413ea9a877 119 * @}
ganlikun 0:13413ea9a877 120 */
ganlikun 0:13413ea9a877 121
ganlikun 0:13413ea9a877 122
ganlikun 0:13413ea9a877 123 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
ganlikun 0:13413ea9a877 124 * @{
ganlikun 0:13413ea9a877 125 */
ganlikun 0:13413ea9a877 126 #define PWR_MAINREGULATOR_ON 0x00000000U
ganlikun 0:13413ea9a877 127 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
ganlikun 0:13413ea9a877 128 /**
ganlikun 0:13413ea9a877 129 * @}
ganlikun 0:13413ea9a877 130 */
ganlikun 0:13413ea9a877 131
ganlikun 0:13413ea9a877 132 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
ganlikun 0:13413ea9a877 133 * @{
ganlikun 0:13413ea9a877 134 */
ganlikun 0:13413ea9a877 135 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
ganlikun 0:13413ea9a877 136 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
ganlikun 0:13413ea9a877 137 /**
ganlikun 0:13413ea9a877 138 * @}
ganlikun 0:13413ea9a877 139 */
ganlikun 0:13413ea9a877 140
ganlikun 0:13413ea9a877 141 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
ganlikun 0:13413ea9a877 142 * @{
ganlikun 0:13413ea9a877 143 */
ganlikun 0:13413ea9a877 144 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
ganlikun 0:13413ea9a877 145 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
ganlikun 0:13413ea9a877 146 /**
ganlikun 0:13413ea9a877 147 * @}
ganlikun 0:13413ea9a877 148 */
ganlikun 0:13413ea9a877 149
ganlikun 0:13413ea9a877 150 /** @defgroup PWR_Flag PWR Flag
ganlikun 0:13413ea9a877 151 * @{
ganlikun 0:13413ea9a877 152 */
ganlikun 0:13413ea9a877 153 #define PWR_FLAG_WU PWR_CSR_WUF
ganlikun 0:13413ea9a877 154 #define PWR_FLAG_SB PWR_CSR_SBF
ganlikun 0:13413ea9a877 155 #define PWR_FLAG_PVDO PWR_CSR_PVDO
ganlikun 0:13413ea9a877 156 #define PWR_FLAG_BRR PWR_CSR_BRR
ganlikun 0:13413ea9a877 157 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
ganlikun 0:13413ea9a877 158 /**
ganlikun 0:13413ea9a877 159 * @}
ganlikun 0:13413ea9a877 160 */
ganlikun 0:13413ea9a877 161
ganlikun 0:13413ea9a877 162 /**
ganlikun 0:13413ea9a877 163 * @}
ganlikun 0:13413ea9a877 164 */
ganlikun 0:13413ea9a877 165
ganlikun 0:13413ea9a877 166 /* Exported macro ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 167 /** @defgroup PWR_Exported_Macro PWR Exported Macro
ganlikun 0:13413ea9a877 168 * @{
ganlikun 0:13413ea9a877 169 */
ganlikun 0:13413ea9a877 170
ganlikun 0:13413ea9a877 171 /** @brief Check PWR flag is set or not.
ganlikun 0:13413ea9a877 172 * @param __FLAG__: specifies the flag to check.
ganlikun 0:13413ea9a877 173 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 174 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
ganlikun 0:13413ea9a877 175 * was received from the WKUP pin or from the RTC alarm (Alarm A
ganlikun 0:13413ea9a877 176 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
ganlikun 0:13413ea9a877 177 * An additional wakeup event is detected if the WKUP pin is enabled
ganlikun 0:13413ea9a877 178 * (by setting the EWUP bit) when the WKUP pin level is already high.
ganlikun 0:13413ea9a877 179 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
ganlikun 0:13413ea9a877 180 * resumed from StandBy mode.
ganlikun 0:13413ea9a877 181 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
ganlikun 0:13413ea9a877 182 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
ganlikun 0:13413ea9a877 183 * For this reason, this bit is equal to 0 after Standby or reset
ganlikun 0:13413ea9a877 184 * until the PVDE bit is set.
ganlikun 0:13413ea9a877 185 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
ganlikun 0:13413ea9a877 186 * when the device wakes up from Standby mode or by a system reset
ganlikun 0:13413ea9a877 187 * or power reset.
ganlikun 0:13413ea9a877 188 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
ganlikun 0:13413ea9a877 189 * scaling output selection is ready.
ganlikun 0:13413ea9a877 190 * @retval The new state of __FLAG__ (TRUE or FALSE).
ganlikun 0:13413ea9a877 191 */
ganlikun 0:13413ea9a877 192 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
ganlikun 0:13413ea9a877 193
ganlikun 0:13413ea9a877 194 /** @brief Clear the PWR's pending flags.
ganlikun 0:13413ea9a877 195 * @param __FLAG__: specifies the flag to clear.
ganlikun 0:13413ea9a877 196 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 197 * @arg PWR_FLAG_WU: Wake Up flag
ganlikun 0:13413ea9a877 198 * @arg PWR_FLAG_SB: StandBy flag
ganlikun 0:13413ea9a877 199 */
ganlikun 0:13413ea9a877 200 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
ganlikun 0:13413ea9a877 201
ganlikun 0:13413ea9a877 202 /**
ganlikun 0:13413ea9a877 203 * @brief Enable the PVD Exti Line 16.
ganlikun 0:13413ea9a877 204 * @retval None.
ganlikun 0:13413ea9a877 205 */
ganlikun 0:13413ea9a877 206 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
ganlikun 0:13413ea9a877 207
ganlikun 0:13413ea9a877 208 /**
ganlikun 0:13413ea9a877 209 * @brief Disable the PVD EXTI Line 16.
ganlikun 0:13413ea9a877 210 * @retval None.
ganlikun 0:13413ea9a877 211 */
ganlikun 0:13413ea9a877 212 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
ganlikun 0:13413ea9a877 213
ganlikun 0:13413ea9a877 214 /**
ganlikun 0:13413ea9a877 215 * @brief Enable event on PVD Exti Line 16.
ganlikun 0:13413ea9a877 216 * @retval None.
ganlikun 0:13413ea9a877 217 */
ganlikun 0:13413ea9a877 218 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
ganlikun 0:13413ea9a877 219
ganlikun 0:13413ea9a877 220 /**
ganlikun 0:13413ea9a877 221 * @brief Disable event on PVD Exti Line 16.
ganlikun 0:13413ea9a877 222 * @retval None.
ganlikun 0:13413ea9a877 223 */
ganlikun 0:13413ea9a877 224 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
ganlikun 0:13413ea9a877 225
ganlikun 0:13413ea9a877 226 /**
ganlikun 0:13413ea9a877 227 * @brief Enable the PVD Extended Interrupt Rising Trigger.
ganlikun 0:13413ea9a877 228 * @retval None.
ganlikun 0:13413ea9a877 229 */
ganlikun 0:13413ea9a877 230 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
ganlikun 0:13413ea9a877 231
ganlikun 0:13413ea9a877 232 /**
ganlikun 0:13413ea9a877 233 * @brief Disable the PVD Extended Interrupt Rising Trigger.
ganlikun 0:13413ea9a877 234 * @retval None.
ganlikun 0:13413ea9a877 235 */
ganlikun 0:13413ea9a877 236 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
ganlikun 0:13413ea9a877 237
ganlikun 0:13413ea9a877 238 /**
ganlikun 0:13413ea9a877 239 * @brief Enable the PVD Extended Interrupt Falling Trigger.
ganlikun 0:13413ea9a877 240 * @retval None.
ganlikun 0:13413ea9a877 241 */
ganlikun 0:13413ea9a877 242 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
ganlikun 0:13413ea9a877 243
ganlikun 0:13413ea9a877 244
ganlikun 0:13413ea9a877 245 /**
ganlikun 0:13413ea9a877 246 * @brief Disable the PVD Extended Interrupt Falling Trigger.
ganlikun 0:13413ea9a877 247 * @retval None.
ganlikun 0:13413ea9a877 248 */
ganlikun 0:13413ea9a877 249 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
ganlikun 0:13413ea9a877 250
ganlikun 0:13413ea9a877 251
ganlikun 0:13413ea9a877 252 /**
ganlikun 0:13413ea9a877 253 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
ganlikun 0:13413ea9a877 254 * @retval None.
ganlikun 0:13413ea9a877 255 */
ganlikun 0:13413ea9a877 256 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
ganlikun 0:13413ea9a877 257 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
ganlikun 0:13413ea9a877 258 }while(0U)
ganlikun 0:13413ea9a877 259
ganlikun 0:13413ea9a877 260 /**
ganlikun 0:13413ea9a877 261 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
ganlikun 0:13413ea9a877 262 * This parameter can be:
ganlikun 0:13413ea9a877 263 * @retval None.
ganlikun 0:13413ea9a877 264 */
ganlikun 0:13413ea9a877 265 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
ganlikun 0:13413ea9a877 266 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
ganlikun 0:13413ea9a877 267 }while(0U)
ganlikun 0:13413ea9a877 268
ganlikun 0:13413ea9a877 269 /**
ganlikun 0:13413ea9a877 270 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
ganlikun 0:13413ea9a877 271 * @retval EXTI PVD Line Status.
ganlikun 0:13413ea9a877 272 */
ganlikun 0:13413ea9a877 273 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
ganlikun 0:13413ea9a877 274
ganlikun 0:13413ea9a877 275 /**
ganlikun 0:13413ea9a877 276 * @brief Clear the PVD Exti flag.
ganlikun 0:13413ea9a877 277 * @retval None.
ganlikun 0:13413ea9a877 278 */
ganlikun 0:13413ea9a877 279 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
ganlikun 0:13413ea9a877 280
ganlikun 0:13413ea9a877 281 /**
ganlikun 0:13413ea9a877 282 * @brief Generates a Software interrupt on PVD EXTI line.
ganlikun 0:13413ea9a877 283 * @retval None
ganlikun 0:13413ea9a877 284 */
ganlikun 0:13413ea9a877 285 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
ganlikun 0:13413ea9a877 286
ganlikun 0:13413ea9a877 287 /**
ganlikun 0:13413ea9a877 288 * @}
ganlikun 0:13413ea9a877 289 */
ganlikun 0:13413ea9a877 290
ganlikun 0:13413ea9a877 291 /* Include PWR HAL Extension module */
ganlikun 0:13413ea9a877 292 #include "stm32f4xx_hal_pwr_ex.h"
ganlikun 0:13413ea9a877 293
ganlikun 0:13413ea9a877 294 /* Exported functions --------------------------------------------------------*/
ganlikun 0:13413ea9a877 295 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
ganlikun 0:13413ea9a877 296 * @{
ganlikun 0:13413ea9a877 297 */
ganlikun 0:13413ea9a877 298
ganlikun 0:13413ea9a877 299 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
ganlikun 0:13413ea9a877 300 * @{
ganlikun 0:13413ea9a877 301 */
ganlikun 0:13413ea9a877 302 /* Initialization and de-initialization functions *****************************/
ganlikun 0:13413ea9a877 303 void HAL_PWR_DeInit(void);
ganlikun 0:13413ea9a877 304 void HAL_PWR_EnableBkUpAccess(void);
ganlikun 0:13413ea9a877 305 void HAL_PWR_DisableBkUpAccess(void);
ganlikun 0:13413ea9a877 306 /**
ganlikun 0:13413ea9a877 307 * @}
ganlikun 0:13413ea9a877 308 */
ganlikun 0:13413ea9a877 309
ganlikun 0:13413ea9a877 310 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
ganlikun 0:13413ea9a877 311 * @{
ganlikun 0:13413ea9a877 312 */
ganlikun 0:13413ea9a877 313 /* Peripheral Control functions **********************************************/
ganlikun 0:13413ea9a877 314 /* PVD configuration */
ganlikun 0:13413ea9a877 315 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
ganlikun 0:13413ea9a877 316 void HAL_PWR_EnablePVD(void);
ganlikun 0:13413ea9a877 317 void HAL_PWR_DisablePVD(void);
ganlikun 0:13413ea9a877 318
ganlikun 0:13413ea9a877 319 /* WakeUp pins configuration */
ganlikun 0:13413ea9a877 320 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
ganlikun 0:13413ea9a877 321 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
ganlikun 0:13413ea9a877 322
ganlikun 0:13413ea9a877 323 /* Low Power modes entry */
ganlikun 0:13413ea9a877 324 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
ganlikun 0:13413ea9a877 325 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
ganlikun 0:13413ea9a877 326 void HAL_PWR_EnterSTANDBYMode(void);
ganlikun 0:13413ea9a877 327
ganlikun 0:13413ea9a877 328 /* Power PVD IRQ Handler */
ganlikun 0:13413ea9a877 329 void HAL_PWR_PVD_IRQHandler(void);
ganlikun 0:13413ea9a877 330 void HAL_PWR_PVDCallback(void);
ganlikun 0:13413ea9a877 331
ganlikun 0:13413ea9a877 332 /* Cortex System Control functions *******************************************/
ganlikun 0:13413ea9a877 333 void HAL_PWR_EnableSleepOnExit(void);
ganlikun 0:13413ea9a877 334 void HAL_PWR_DisableSleepOnExit(void);
ganlikun 0:13413ea9a877 335 void HAL_PWR_EnableSEVOnPend(void);
ganlikun 0:13413ea9a877 336 void HAL_PWR_DisableSEVOnPend(void);
ganlikun 0:13413ea9a877 337 /**
ganlikun 0:13413ea9a877 338 * @}
ganlikun 0:13413ea9a877 339 */
ganlikun 0:13413ea9a877 340
ganlikun 0:13413ea9a877 341 /**
ganlikun 0:13413ea9a877 342 * @}
ganlikun 0:13413ea9a877 343 */
ganlikun 0:13413ea9a877 344
ganlikun 0:13413ea9a877 345 /* Private types -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 346 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 347 /* Private constants ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 348 /** @defgroup PWR_Private_Constants PWR Private Constants
ganlikun 0:13413ea9a877 349 * @{
ganlikun 0:13413ea9a877 350 */
ganlikun 0:13413ea9a877 351
ganlikun 0:13413ea9a877 352 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
ganlikun 0:13413ea9a877 353 * @{
ganlikun 0:13413ea9a877 354 */
ganlikun 0:13413ea9a877 355 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
ganlikun 0:13413ea9a877 356 /**
ganlikun 0:13413ea9a877 357 * @}
ganlikun 0:13413ea9a877 358 */
ganlikun 0:13413ea9a877 359
ganlikun 0:13413ea9a877 360 /** @defgroup PWR_register_alias_address PWR Register alias address
ganlikun 0:13413ea9a877 361 * @{
ganlikun 0:13413ea9a877 362 */
ganlikun 0:13413ea9a877 363 /* ------------- PWR registers bit address in the alias region ---------------*/
ganlikun 0:13413ea9a877 364 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
ganlikun 0:13413ea9a877 365 #define PWR_CR_OFFSET 0x00U
ganlikun 0:13413ea9a877 366 #define PWR_CSR_OFFSET 0x04U
ganlikun 0:13413ea9a877 367 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
ganlikun 0:13413ea9a877 368 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
ganlikun 0:13413ea9a877 369 /**
ganlikun 0:13413ea9a877 370 * @}
ganlikun 0:13413ea9a877 371 */
ganlikun 0:13413ea9a877 372
ganlikun 0:13413ea9a877 373 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
ganlikun 0:13413ea9a877 374 * @{
ganlikun 0:13413ea9a877 375 */
ganlikun 0:13413ea9a877 376 /* --- CR Register ---*/
ganlikun 0:13413ea9a877 377 /* Alias word address of DBP bit */
ganlikun 0:13413ea9a877 378 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
ganlikun 0:13413ea9a877 379 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 380
ganlikun 0:13413ea9a877 381 /* Alias word address of PVDE bit */
ganlikun 0:13413ea9a877 382 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
ganlikun 0:13413ea9a877 383 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 384
ganlikun 0:13413ea9a877 385 /* Alias word address of PMODE bit */
ganlikun 0:13413ea9a877 386 #define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
ganlikun 0:13413ea9a877 387 #define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 388 /**
ganlikun 0:13413ea9a877 389 * @}
ganlikun 0:13413ea9a877 390 */
ganlikun 0:13413ea9a877 391
ganlikun 0:13413ea9a877 392 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
ganlikun 0:13413ea9a877 393 * @{
ganlikun 0:13413ea9a877 394 */
ganlikun 0:13413ea9a877 395 /* --- CSR Register ---*/
ganlikun 0:13413ea9a877 396 /* Alias word address of EWUP bit */
ganlikun 0:13413ea9a877 397 #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
ganlikun 0:13413ea9a877 398 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
ganlikun 0:13413ea9a877 399 /**
ganlikun 0:13413ea9a877 400 * @}
ganlikun 0:13413ea9a877 401 */
ganlikun 0:13413ea9a877 402
ganlikun 0:13413ea9a877 403 /**
ganlikun 0:13413ea9a877 404 * @}
ganlikun 0:13413ea9a877 405 */
ganlikun 0:13413ea9a877 406 /* Private macros ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 407 /** @defgroup PWR_Private_Macros PWR Private Macros
ganlikun 0:13413ea9a877 408 * @{
ganlikun 0:13413ea9a877 409 */
ganlikun 0:13413ea9a877 410
ganlikun 0:13413ea9a877 411 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
ganlikun 0:13413ea9a877 412 * @{
ganlikun 0:13413ea9a877 413 */
ganlikun 0:13413ea9a877 414 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
ganlikun 0:13413ea9a877 415 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
ganlikun 0:13413ea9a877 416 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
ganlikun 0:13413ea9a877 417 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
ganlikun 0:13413ea9a877 418 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
ganlikun 0:13413ea9a877 419 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
ganlikun 0:13413ea9a877 420 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
ganlikun 0:13413ea9a877 421 ((MODE) == PWR_PVD_MODE_NORMAL))
ganlikun 0:13413ea9a877 422 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
ganlikun 0:13413ea9a877 423 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
ganlikun 0:13413ea9a877 424 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
ganlikun 0:13413ea9a877 425 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
ganlikun 0:13413ea9a877 426 /**
ganlikun 0:13413ea9a877 427 * @}
ganlikun 0:13413ea9a877 428 */
ganlikun 0:13413ea9a877 429
ganlikun 0:13413ea9a877 430 /**
ganlikun 0:13413ea9a877 431 * @}
ganlikun 0:13413ea9a877 432 */
ganlikun 0:13413ea9a877 433
ganlikun 0:13413ea9a877 434 /**
ganlikun 0:13413ea9a877 435 * @}
ganlikun 0:13413ea9a877 436 */
ganlikun 0:13413ea9a877 437
ganlikun 0:13413ea9a877 438 /**
ganlikun 0:13413ea9a877 439 * @}
ganlikun 0:13413ea9a877 440 */
ganlikun 0:13413ea9a877 441
ganlikun 0:13413ea9a877 442 #ifdef __cplusplus
ganlikun 0:13413ea9a877 443 }
ganlikun 0:13413ea9a877 444 #endif
ganlikun 0:13413ea9a877 445
ganlikun 0:13413ea9a877 446
ganlikun 0:13413ea9a877 447 #endif /* __STM32F4xx_HAL_PWR_H */
ganlikun 0:13413ea9a877 448
ganlikun 0:13413ea9a877 449 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 450