Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_hal_eth.c
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief ETH HAL module driver.
ganlikun 0:13413ea9a877 8 * This file provides firmware functions to manage the following
ganlikun 0:13413ea9a877 9 * functionalities of the Ethernet (ETH) peripheral:
ganlikun 0:13413ea9a877 10 * + Initialization and de-initialization functions
ganlikun 0:13413ea9a877 11 * + IO operation functions
ganlikun 0:13413ea9a877 12 * + Peripheral Control functions
ganlikun 0:13413ea9a877 13 * + Peripheral State and Errors functions
ganlikun 0:13413ea9a877 14 *
ganlikun 0:13413ea9a877 15 @verbatim
ganlikun 0:13413ea9a877 16 ==============================================================================
ganlikun 0:13413ea9a877 17 ##### How to use this driver #####
ganlikun 0:13413ea9a877 18 ==============================================================================
ganlikun 0:13413ea9a877 19 [..]
ganlikun 0:13413ea9a877 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
ganlikun 0:13413ea9a877 21 ETH_HandleTypeDef heth;
ganlikun 0:13413ea9a877 22
ganlikun 0:13413ea9a877 23 (#)Fill parameters of Init structure in heth handle
ganlikun 0:13413ea9a877 24
ganlikun 0:13413ea9a877 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
ganlikun 0:13413ea9a877 26
ganlikun 0:13413ea9a877 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
ganlikun 0:13413ea9a877 28 (##) Enable the Ethernet interface clock using
ganlikun 0:13413ea9a877 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
ganlikun 0:13413ea9a877 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
ganlikun 0:13413ea9a877 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
ganlikun 0:13413ea9a877 32
ganlikun 0:13413ea9a877 33 (##) Initialize the related GPIO clocks
ganlikun 0:13413ea9a877 34 (##) Configure Ethernet pin-out
ganlikun 0:13413ea9a877 35 (##) Configure Ethernet NVIC interrupt (IT mode)
ganlikun 0:13413ea9a877 36
ganlikun 0:13413ea9a877 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
ganlikun 0:13413ea9a877 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
ganlikun 0:13413ea9a877 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
ganlikun 0:13413ea9a877 40
ganlikun 0:13413ea9a877 41 (#)Enable MAC and DMA transmission and reception:
ganlikun 0:13413ea9a877 42 (##) HAL_ETH_Start();
ganlikun 0:13413ea9a877 43
ganlikun 0:13413ea9a877 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
ganlikun 0:13413ea9a877 45 the frame to MAC TX FIFO:
ganlikun 0:13413ea9a877 46 (##) HAL_ETH_TransmitFrame();
ganlikun 0:13413ea9a877 47
ganlikun 0:13413ea9a877 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
ganlikun 0:13413ea9a877 49 frame parameters
ganlikun 0:13413ea9a877 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
ganlikun 0:13413ea9a877 51
ganlikun 0:13413ea9a877 52 (#) Get a received frame when an ETH RX interrupt occurs:
ganlikun 0:13413ea9a877 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
ganlikun 0:13413ea9a877 54
ganlikun 0:13413ea9a877 55 (#) Communicate with external PHY device:
ganlikun 0:13413ea9a877 56 (##) Read a specific register from the PHY
ganlikun 0:13413ea9a877 57 HAL_ETH_ReadPHYRegister();
ganlikun 0:13413ea9a877 58 (##) Write data to a specific RHY register:
ganlikun 0:13413ea9a877 59 HAL_ETH_WritePHYRegister();
ganlikun 0:13413ea9a877 60
ganlikun 0:13413ea9a877 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
ganlikun 0:13413ea9a877 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
ganlikun 0:13413ea9a877 63
ganlikun 0:13413ea9a877 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
ganlikun 0:13413ea9a877 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
ganlikun 0:13413ea9a877 66
ganlikun 0:13413ea9a877 67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
ganlikun 0:13413ea9a877 68 in this driver
ganlikun 0:13413ea9a877 69
ganlikun 0:13413ea9a877 70 @endverbatim
ganlikun 0:13413ea9a877 71 ******************************************************************************
ganlikun 0:13413ea9a877 72 * @attention
ganlikun 0:13413ea9a877 73 *
ganlikun 0:13413ea9a877 74 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 75 *
ganlikun 0:13413ea9a877 76 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 77 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 78 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 79 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 81 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 82 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 84 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 85 * without specific prior written permission.
ganlikun 0:13413ea9a877 86 *
ganlikun 0:13413ea9a877 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 97 *
ganlikun 0:13413ea9a877 98 ******************************************************************************
ganlikun 0:13413ea9a877 99 */
ganlikun 0:13413ea9a877 100
ganlikun 0:13413ea9a877 101 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 102 #include "stm32f4xx_hal.h"
ganlikun 0:13413ea9a877 103
ganlikun 0:13413ea9a877 104 /** @addtogroup STM32F4xx_HAL_Driver
ganlikun 0:13413ea9a877 105 * @{
ganlikun 0:13413ea9a877 106 */
ganlikun 0:13413ea9a877 107
ganlikun 0:13413ea9a877 108 /** @defgroup ETH ETH
ganlikun 0:13413ea9a877 109 * @brief ETH HAL module driver
ganlikun 0:13413ea9a877 110 * @{
ganlikun 0:13413ea9a877 111 */
ganlikun 0:13413ea9a877 112
ganlikun 0:13413ea9a877 113 #ifdef HAL_ETH_MODULE_ENABLED
ganlikun 0:13413ea9a877 114
ganlikun 0:13413ea9a877 115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
ganlikun 0:13413ea9a877 116 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
ganlikun 0:13413ea9a877 117
ganlikun 0:13413ea9a877 118 /* Private typedef -----------------------------------------------------------*/
ganlikun 0:13413ea9a877 119 /* Private define ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 120 /** @defgroup ETH_Private_Constants ETH Private Constants
ganlikun 0:13413ea9a877 121 * @{
ganlikun 0:13413ea9a877 122 */
ganlikun 0:13413ea9a877 123 #define ETH_TIMEOUT_SWRESET 500U
ganlikun 0:13413ea9a877 124 #define ETH_TIMEOUT_LINKED_STATE 5000U
ganlikun 0:13413ea9a877 125 #define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
ganlikun 0:13413ea9a877 126
ganlikun 0:13413ea9a877 127 /**
ganlikun 0:13413ea9a877 128 * @}
ganlikun 0:13413ea9a877 129 */
ganlikun 0:13413ea9a877 130 /* Private macro -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 131 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 132 /* Private function prototypes -----------------------------------------------*/
ganlikun 0:13413ea9a877 133 /** @defgroup ETH_Private_Functions ETH Private Functions
ganlikun 0:13413ea9a877 134 * @{
ganlikun 0:13413ea9a877 135 */
ganlikun 0:13413ea9a877 136 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
ganlikun 0:13413ea9a877 137 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
ganlikun 0:13413ea9a877 138 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 139 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 140 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 141 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 142 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 143 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 144 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 145 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 146 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
ganlikun 0:13413ea9a877 147 static void ETH_Delay(uint32_t mdelay);
ganlikun 0:13413ea9a877 148
ganlikun 0:13413ea9a877 149 /**
ganlikun 0:13413ea9a877 150 * @}
ganlikun 0:13413ea9a877 151 */
ganlikun 0:13413ea9a877 152 /* Private functions ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 153
ganlikun 0:13413ea9a877 154 /** @defgroup ETH_Exported_Functions ETH Exported Functions
ganlikun 0:13413ea9a877 155 * @{
ganlikun 0:13413ea9a877 156 */
ganlikun 0:13413ea9a877 157
ganlikun 0:13413ea9a877 158 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
ganlikun 0:13413ea9a877 159 * @brief Initialization and Configuration functions
ganlikun 0:13413ea9a877 160 *
ganlikun 0:13413ea9a877 161 @verbatim
ganlikun 0:13413ea9a877 162 ===============================================================================
ganlikun 0:13413ea9a877 163 ##### Initialization and de-initialization functions #####
ganlikun 0:13413ea9a877 164 ===============================================================================
ganlikun 0:13413ea9a877 165 [..] This section provides functions allowing to:
ganlikun 0:13413ea9a877 166 (+) Initialize and configure the Ethernet peripheral
ganlikun 0:13413ea9a877 167 (+) De-initialize the Ethernet peripheral
ganlikun 0:13413ea9a877 168
ganlikun 0:13413ea9a877 169 @endverbatim
ganlikun 0:13413ea9a877 170 * @{
ganlikun 0:13413ea9a877 171 */
ganlikun 0:13413ea9a877 172
ganlikun 0:13413ea9a877 173 /**
ganlikun 0:13413ea9a877 174 * @brief Initializes the Ethernet MAC and DMA according to default
ganlikun 0:13413ea9a877 175 * parameters.
ganlikun 0:13413ea9a877 176 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 177 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 178 * @retval HAL status
ganlikun 0:13413ea9a877 179 */
ganlikun 0:13413ea9a877 180 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 181 {
ganlikun 0:13413ea9a877 182 uint32_t tmpreg1 = 0U, phyreg = 0U;
ganlikun 0:13413ea9a877 183 uint32_t hclk = 60000000U;
ganlikun 0:13413ea9a877 184 uint32_t tickstart = 0U;
ganlikun 0:13413ea9a877 185 uint32_t err = ETH_SUCCESS;
ganlikun 0:13413ea9a877 186
ganlikun 0:13413ea9a877 187 /* Check the ETH peripheral state */
ganlikun 0:13413ea9a877 188 if(heth == NULL)
ganlikun 0:13413ea9a877 189 {
ganlikun 0:13413ea9a877 190 return HAL_ERROR;
ganlikun 0:13413ea9a877 191 }
ganlikun 0:13413ea9a877 192
ganlikun 0:13413ea9a877 193 /* Check parameters */
ganlikun 0:13413ea9a877 194 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
ganlikun 0:13413ea9a877 195 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
ganlikun 0:13413ea9a877 196 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
ganlikun 0:13413ea9a877 197 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
ganlikun 0:13413ea9a877 198
ganlikun 0:13413ea9a877 199 if(heth->State == HAL_ETH_STATE_RESET)
ganlikun 0:13413ea9a877 200 {
ganlikun 0:13413ea9a877 201 /* Allocate lock resource and initialize it */
ganlikun 0:13413ea9a877 202 heth->Lock = HAL_UNLOCKED;
ganlikun 0:13413ea9a877 203 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
ganlikun 0:13413ea9a877 204 HAL_ETH_MspInit(heth);
ganlikun 0:13413ea9a877 205 }
ganlikun 0:13413ea9a877 206
ganlikun 0:13413ea9a877 207 /* Enable SYSCFG Clock */
ganlikun 0:13413ea9a877 208 __HAL_RCC_SYSCFG_CLK_ENABLE();
ganlikun 0:13413ea9a877 209
ganlikun 0:13413ea9a877 210 /* Select MII or RMII Mode*/
ganlikun 0:13413ea9a877 211 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
ganlikun 0:13413ea9a877 212 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
ganlikun 0:13413ea9a877 213
ganlikun 0:13413ea9a877 214 /* Ethernet Software reset */
ganlikun 0:13413ea9a877 215 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
ganlikun 0:13413ea9a877 216 /* After reset all the registers holds their respective reset values */
ganlikun 0:13413ea9a877 217 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
ganlikun 0:13413ea9a877 218
ganlikun 0:13413ea9a877 219 /* Get tick */
ganlikun 0:13413ea9a877 220 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 221
ganlikun 0:13413ea9a877 222 /* Wait for software reset */
ganlikun 0:13413ea9a877 223 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
ganlikun 0:13413ea9a877 224 {
ganlikun 0:13413ea9a877 225 /* Check for the Timeout */
ganlikun 0:13413ea9a877 226 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
ganlikun 0:13413ea9a877 227 {
ganlikun 0:13413ea9a877 228 heth->State= HAL_ETH_STATE_TIMEOUT;
ganlikun 0:13413ea9a877 229
ganlikun 0:13413ea9a877 230 /* Process Unlocked */
ganlikun 0:13413ea9a877 231 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 232
ganlikun 0:13413ea9a877 233 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
ganlikun 0:13413ea9a877 234 not available, please check your external PHY or the IO configuration */
ganlikun 0:13413ea9a877 235 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 236 }
ganlikun 0:13413ea9a877 237 }
ganlikun 0:13413ea9a877 238
ganlikun 0:13413ea9a877 239 /*-------------------------------- MAC Initialization ----------------------*/
ganlikun 0:13413ea9a877 240 /* Get the ETHERNET MACMIIAR value */
ganlikun 0:13413ea9a877 241 tmpreg1 = (heth->Instance)->MACMIIAR;
ganlikun 0:13413ea9a877 242 /* Clear CSR Clock Range CR[2:0] bits */
ganlikun 0:13413ea9a877 243 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
ganlikun 0:13413ea9a877 244
ganlikun 0:13413ea9a877 245 /* Get hclk frequency value */
ganlikun 0:13413ea9a877 246 hclk = HAL_RCC_GetHCLKFreq();
ganlikun 0:13413ea9a877 247
ganlikun 0:13413ea9a877 248 /* Set CR bits depending on hclk value */
ganlikun 0:13413ea9a877 249 if((hclk >= 20000000U)&&(hclk < 35000000U))
ganlikun 0:13413ea9a877 250 {
ganlikun 0:13413ea9a877 251 /* CSR Clock Range between 20-35 MHz */
ganlikun 0:13413ea9a877 252 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
ganlikun 0:13413ea9a877 253 }
ganlikun 0:13413ea9a877 254 else if((hclk >= 35000000U)&&(hclk < 60000000U))
ganlikun 0:13413ea9a877 255 {
ganlikun 0:13413ea9a877 256 /* CSR Clock Range between 35-60 MHz */
ganlikun 0:13413ea9a877 257 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
ganlikun 0:13413ea9a877 258 }
ganlikun 0:13413ea9a877 259 else if((hclk >= 60000000U)&&(hclk < 100000000U))
ganlikun 0:13413ea9a877 260 {
ganlikun 0:13413ea9a877 261 /* CSR Clock Range between 60-100 MHz */
ganlikun 0:13413ea9a877 262 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
ganlikun 0:13413ea9a877 263 }
ganlikun 0:13413ea9a877 264 else if((hclk >= 100000000U)&&(hclk < 150000000U))
ganlikun 0:13413ea9a877 265 {
ganlikun 0:13413ea9a877 266 /* CSR Clock Range between 100-150 MHz */
ganlikun 0:13413ea9a877 267 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
ganlikun 0:13413ea9a877 268 }
ganlikun 0:13413ea9a877 269 else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
ganlikun 0:13413ea9a877 270 {
ganlikun 0:13413ea9a877 271 /* CSR Clock Range between 150-183 MHz */
ganlikun 0:13413ea9a877 272 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
ganlikun 0:13413ea9a877 273 }
ganlikun 0:13413ea9a877 274
ganlikun 0:13413ea9a877 275 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
ganlikun 0:13413ea9a877 276 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 277
ganlikun 0:13413ea9a877 278 /*-------------------- PHY initialization and configuration ----------------*/
ganlikun 0:13413ea9a877 279 /* Put the PHY in reset mode */
ganlikun 0:13413ea9a877 280 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
ganlikun 0:13413ea9a877 281 {
ganlikun 0:13413ea9a877 282 /* In case of write timeout */
ganlikun 0:13413ea9a877 283 err = ETH_ERROR;
ganlikun 0:13413ea9a877 284
ganlikun 0:13413ea9a877 285 /* Config MAC and DMA */
ganlikun 0:13413ea9a877 286 ETH_MACDMAConfig(heth, err);
ganlikun 0:13413ea9a877 287
ganlikun 0:13413ea9a877 288 /* Set the ETH peripheral state to READY */
ganlikun 0:13413ea9a877 289 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 290
ganlikun 0:13413ea9a877 291 /* Return HAL_ERROR */
ganlikun 0:13413ea9a877 292 return HAL_ERROR;
ganlikun 0:13413ea9a877 293 }
ganlikun 0:13413ea9a877 294
ganlikun 0:13413ea9a877 295 /* Delay to assure PHY reset */
ganlikun 0:13413ea9a877 296 HAL_Delay(PHY_RESET_DELAY);
ganlikun 0:13413ea9a877 297
ganlikun 0:13413ea9a877 298 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
ganlikun 0:13413ea9a877 299 {
ganlikun 0:13413ea9a877 300 /* Get tick */
ganlikun 0:13413ea9a877 301 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 302
ganlikun 0:13413ea9a877 303 /* We wait for linked status */
ganlikun 0:13413ea9a877 304 do
ganlikun 0:13413ea9a877 305 {
ganlikun 0:13413ea9a877 306 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
ganlikun 0:13413ea9a877 307
ganlikun 0:13413ea9a877 308 /* Check for the Timeout */
ganlikun 0:13413ea9a877 309 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
ganlikun 0:13413ea9a877 310 {
ganlikun 0:13413ea9a877 311 /* In case of write timeout */
ganlikun 0:13413ea9a877 312 err = ETH_ERROR;
ganlikun 0:13413ea9a877 313
ganlikun 0:13413ea9a877 314 /* Config MAC and DMA */
ganlikun 0:13413ea9a877 315 ETH_MACDMAConfig(heth, err);
ganlikun 0:13413ea9a877 316
ganlikun 0:13413ea9a877 317 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 318
ganlikun 0:13413ea9a877 319 /* Process Unlocked */
ganlikun 0:13413ea9a877 320 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 321
ganlikun 0:13413ea9a877 322 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 323 }
ganlikun 0:13413ea9a877 324 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
ganlikun 0:13413ea9a877 325
ganlikun 0:13413ea9a877 326
ganlikun 0:13413ea9a877 327 /* Enable Auto-Negotiation */
ganlikun 0:13413ea9a877 328 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
ganlikun 0:13413ea9a877 329 {
ganlikun 0:13413ea9a877 330 /* In case of write timeout */
ganlikun 0:13413ea9a877 331 err = ETH_ERROR;
ganlikun 0:13413ea9a877 332
ganlikun 0:13413ea9a877 333 /* Config MAC and DMA */
ganlikun 0:13413ea9a877 334 ETH_MACDMAConfig(heth, err);
ganlikun 0:13413ea9a877 335
ganlikun 0:13413ea9a877 336 /* Set the ETH peripheral state to READY */
ganlikun 0:13413ea9a877 337 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 338
ganlikun 0:13413ea9a877 339 /* Return HAL_ERROR */
ganlikun 0:13413ea9a877 340 return HAL_ERROR;
ganlikun 0:13413ea9a877 341 }
ganlikun 0:13413ea9a877 342
ganlikun 0:13413ea9a877 343 /* Get tick */
ganlikun 0:13413ea9a877 344 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 345
ganlikun 0:13413ea9a877 346 /* Wait until the auto-negotiation will be completed */
ganlikun 0:13413ea9a877 347 do
ganlikun 0:13413ea9a877 348 {
ganlikun 0:13413ea9a877 349 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
ganlikun 0:13413ea9a877 350
ganlikun 0:13413ea9a877 351 /* Check for the Timeout */
ganlikun 0:13413ea9a877 352 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
ganlikun 0:13413ea9a877 353 {
ganlikun 0:13413ea9a877 354 /* In case of write timeout */
ganlikun 0:13413ea9a877 355 err = ETH_ERROR;
ganlikun 0:13413ea9a877 356
ganlikun 0:13413ea9a877 357 /* Config MAC and DMA */
ganlikun 0:13413ea9a877 358 ETH_MACDMAConfig(heth, err);
ganlikun 0:13413ea9a877 359
ganlikun 0:13413ea9a877 360 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 361
ganlikun 0:13413ea9a877 362 /* Process Unlocked */
ganlikun 0:13413ea9a877 363 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 364
ganlikun 0:13413ea9a877 365 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 366 }
ganlikun 0:13413ea9a877 367
ganlikun 0:13413ea9a877 368 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
ganlikun 0:13413ea9a877 369
ganlikun 0:13413ea9a877 370 /* Read the result of the auto-negotiation */
ganlikun 0:13413ea9a877 371 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
ganlikun 0:13413ea9a877 372 {
ganlikun 0:13413ea9a877 373 /* In case of write timeout */
ganlikun 0:13413ea9a877 374 err = ETH_ERROR;
ganlikun 0:13413ea9a877 375
ganlikun 0:13413ea9a877 376 /* Config MAC and DMA */
ganlikun 0:13413ea9a877 377 ETH_MACDMAConfig(heth, err);
ganlikun 0:13413ea9a877 378
ganlikun 0:13413ea9a877 379 /* Set the ETH peripheral state to READY */
ganlikun 0:13413ea9a877 380 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 381
ganlikun 0:13413ea9a877 382 /* Return HAL_ERROR */
ganlikun 0:13413ea9a877 383 return HAL_ERROR;
ganlikun 0:13413ea9a877 384 }
ganlikun 0:13413ea9a877 385
ganlikun 0:13413ea9a877 386 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
ganlikun 0:13413ea9a877 387 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
ganlikun 0:13413ea9a877 388 {
ganlikun 0:13413ea9a877 389 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
ganlikun 0:13413ea9a877 390 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
ganlikun 0:13413ea9a877 391 }
ganlikun 0:13413ea9a877 392 else
ganlikun 0:13413ea9a877 393 {
ganlikun 0:13413ea9a877 394 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
ganlikun 0:13413ea9a877 395 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
ganlikun 0:13413ea9a877 396 }
ganlikun 0:13413ea9a877 397 /* Configure the MAC with the speed fixed by the auto-negotiation process */
ganlikun 0:13413ea9a877 398 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
ganlikun 0:13413ea9a877 399 {
ganlikun 0:13413ea9a877 400 /* Set Ethernet speed to 10M following the auto-negotiation */
ganlikun 0:13413ea9a877 401 (heth->Init).Speed = ETH_SPEED_10M;
ganlikun 0:13413ea9a877 402 }
ganlikun 0:13413ea9a877 403 else
ganlikun 0:13413ea9a877 404 {
ganlikun 0:13413ea9a877 405 /* Set Ethernet speed to 100M following the auto-negotiation */
ganlikun 0:13413ea9a877 406 (heth->Init).Speed = ETH_SPEED_100M;
ganlikun 0:13413ea9a877 407 }
ganlikun 0:13413ea9a877 408 }
ganlikun 0:13413ea9a877 409 else /* AutoNegotiation Disable */
ganlikun 0:13413ea9a877 410 {
ganlikun 0:13413ea9a877 411 /* Check parameters */
ganlikun 0:13413ea9a877 412 assert_param(IS_ETH_SPEED(heth->Init.Speed));
ganlikun 0:13413ea9a877 413 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
ganlikun 0:13413ea9a877 414
ganlikun 0:13413ea9a877 415 /* Set MAC Speed and Duplex Mode */
ganlikun 0:13413ea9a877 416 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
ganlikun 0:13413ea9a877 417 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
ganlikun 0:13413ea9a877 418 {
ganlikun 0:13413ea9a877 419 /* In case of write timeout */
ganlikun 0:13413ea9a877 420 err = ETH_ERROR;
ganlikun 0:13413ea9a877 421
ganlikun 0:13413ea9a877 422 /* Config MAC and DMA */
ganlikun 0:13413ea9a877 423 ETH_MACDMAConfig(heth, err);
ganlikun 0:13413ea9a877 424
ganlikun 0:13413ea9a877 425 /* Set the ETH peripheral state to READY */
ganlikun 0:13413ea9a877 426 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 427
ganlikun 0:13413ea9a877 428 /* Return HAL_ERROR */
ganlikun 0:13413ea9a877 429 return HAL_ERROR;
ganlikun 0:13413ea9a877 430 }
ganlikun 0:13413ea9a877 431
ganlikun 0:13413ea9a877 432 /* Delay to assure PHY configuration */
ganlikun 0:13413ea9a877 433 HAL_Delay(PHY_CONFIG_DELAY);
ganlikun 0:13413ea9a877 434 }
ganlikun 0:13413ea9a877 435
ganlikun 0:13413ea9a877 436 /* Config MAC and DMA */
ganlikun 0:13413ea9a877 437 ETH_MACDMAConfig(heth, err);
ganlikun 0:13413ea9a877 438
ganlikun 0:13413ea9a877 439 /* Set ETH HAL State to Ready */
ganlikun 0:13413ea9a877 440 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 441
ganlikun 0:13413ea9a877 442 /* Return function status */
ganlikun 0:13413ea9a877 443 return HAL_OK;
ganlikun 0:13413ea9a877 444 }
ganlikun 0:13413ea9a877 445
ganlikun 0:13413ea9a877 446 /**
ganlikun 0:13413ea9a877 447 * @brief De-Initializes the ETH peripheral.
ganlikun 0:13413ea9a877 448 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 449 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 450 * @retval HAL status
ganlikun 0:13413ea9a877 451 */
ganlikun 0:13413ea9a877 452 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 453 {
ganlikun 0:13413ea9a877 454 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 455 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 456
ganlikun 0:13413ea9a877 457 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
ganlikun 0:13413ea9a877 458 HAL_ETH_MspDeInit(heth);
ganlikun 0:13413ea9a877 459
ganlikun 0:13413ea9a877 460 /* Set ETH HAL state to Disabled */
ganlikun 0:13413ea9a877 461 heth->State= HAL_ETH_STATE_RESET;
ganlikun 0:13413ea9a877 462
ganlikun 0:13413ea9a877 463 /* Release Lock */
ganlikun 0:13413ea9a877 464 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 465
ganlikun 0:13413ea9a877 466 /* Return function status */
ganlikun 0:13413ea9a877 467 return HAL_OK;
ganlikun 0:13413ea9a877 468 }
ganlikun 0:13413ea9a877 469
ganlikun 0:13413ea9a877 470 /**
ganlikun 0:13413ea9a877 471 * @brief Initializes the DMA Tx descriptors in chain mode.
ganlikun 0:13413ea9a877 472 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 473 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 474 * @param DMATxDescTab: Pointer to the first Tx desc list
ganlikun 0:13413ea9a877 475 * @param TxBuff: Pointer to the first TxBuffer list
ganlikun 0:13413ea9a877 476 * @param TxBuffCount: Number of the used Tx desc in the list
ganlikun 0:13413ea9a877 477 * @retval HAL status
ganlikun 0:13413ea9a877 478 */
ganlikun 0:13413ea9a877 479 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
ganlikun 0:13413ea9a877 480 {
ganlikun 0:13413ea9a877 481 uint32_t i = 0U;
ganlikun 0:13413ea9a877 482 ETH_DMADescTypeDef *dmatxdesc;
ganlikun 0:13413ea9a877 483
ganlikun 0:13413ea9a877 484 /* Process Locked */
ganlikun 0:13413ea9a877 485 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 486
ganlikun 0:13413ea9a877 487 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 488 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 489
ganlikun 0:13413ea9a877 490 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
ganlikun 0:13413ea9a877 491 heth->TxDesc = DMATxDescTab;
ganlikun 0:13413ea9a877 492
ganlikun 0:13413ea9a877 493 /* Fill each DMATxDesc descriptor with the right values */
ganlikun 0:13413ea9a877 494 for(i=0U; i < TxBuffCount; i++)
ganlikun 0:13413ea9a877 495 {
ganlikun 0:13413ea9a877 496 /* Get the pointer on the ith member of the Tx Desc list */
ganlikun 0:13413ea9a877 497 dmatxdesc = DMATxDescTab + i;
ganlikun 0:13413ea9a877 498
ganlikun 0:13413ea9a877 499 /* Set Second Address Chained bit */
ganlikun 0:13413ea9a877 500 dmatxdesc->Status = ETH_DMATXDESC_TCH;
ganlikun 0:13413ea9a877 501
ganlikun 0:13413ea9a877 502 /* Set Buffer1 address pointer */
ganlikun 0:13413ea9a877 503 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
ganlikun 0:13413ea9a877 504
ganlikun 0:13413ea9a877 505 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
ganlikun 0:13413ea9a877 506 {
ganlikun 0:13413ea9a877 507 /* Set the DMA Tx descriptors checksum insertion */
ganlikun 0:13413ea9a877 508 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
ganlikun 0:13413ea9a877 509 }
ganlikun 0:13413ea9a877 510
ganlikun 0:13413ea9a877 511 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
ganlikun 0:13413ea9a877 512 if(i < (TxBuffCount-1U))
ganlikun 0:13413ea9a877 513 {
ganlikun 0:13413ea9a877 514 /* Set next descriptor address register with next descriptor base address */
ganlikun 0:13413ea9a877 515 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
ganlikun 0:13413ea9a877 516 }
ganlikun 0:13413ea9a877 517 else
ganlikun 0:13413ea9a877 518 {
ganlikun 0:13413ea9a877 519 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
ganlikun 0:13413ea9a877 520 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
ganlikun 0:13413ea9a877 521 }
ganlikun 0:13413ea9a877 522 }
ganlikun 0:13413ea9a877 523
ganlikun 0:13413ea9a877 524 /* Set Transmit Descriptor List Address Register */
ganlikun 0:13413ea9a877 525 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
ganlikun 0:13413ea9a877 526
ganlikun 0:13413ea9a877 527 /* Set ETH HAL State to Ready */
ganlikun 0:13413ea9a877 528 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 529
ganlikun 0:13413ea9a877 530 /* Process Unlocked */
ganlikun 0:13413ea9a877 531 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 532
ganlikun 0:13413ea9a877 533 /* Return function status */
ganlikun 0:13413ea9a877 534 return HAL_OK;
ganlikun 0:13413ea9a877 535 }
ganlikun 0:13413ea9a877 536
ganlikun 0:13413ea9a877 537 /**
ganlikun 0:13413ea9a877 538 * @brief Initializes the DMA Rx descriptors in chain mode.
ganlikun 0:13413ea9a877 539 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 540 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 541 * @param DMARxDescTab: Pointer to the first Rx desc list
ganlikun 0:13413ea9a877 542 * @param RxBuff: Pointer to the first RxBuffer list
ganlikun 0:13413ea9a877 543 * @param RxBuffCount: Number of the used Rx desc in the list
ganlikun 0:13413ea9a877 544 * @retval HAL status
ganlikun 0:13413ea9a877 545 */
ganlikun 0:13413ea9a877 546 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
ganlikun 0:13413ea9a877 547 {
ganlikun 0:13413ea9a877 548 uint32_t i = 0U;
ganlikun 0:13413ea9a877 549 ETH_DMADescTypeDef *DMARxDesc;
ganlikun 0:13413ea9a877 550
ganlikun 0:13413ea9a877 551 /* Process Locked */
ganlikun 0:13413ea9a877 552 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 553
ganlikun 0:13413ea9a877 554 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 555 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 556
ganlikun 0:13413ea9a877 557 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
ganlikun 0:13413ea9a877 558 heth->RxDesc = DMARxDescTab;
ganlikun 0:13413ea9a877 559
ganlikun 0:13413ea9a877 560 /* Fill each DMARxDesc descriptor with the right values */
ganlikun 0:13413ea9a877 561 for(i=0U; i < RxBuffCount; i++)
ganlikun 0:13413ea9a877 562 {
ganlikun 0:13413ea9a877 563 /* Get the pointer on the ith member of the Rx Desc list */
ganlikun 0:13413ea9a877 564 DMARxDesc = DMARxDescTab+i;
ganlikun 0:13413ea9a877 565
ganlikun 0:13413ea9a877 566 /* Set Own bit of the Rx descriptor Status */
ganlikun 0:13413ea9a877 567 DMARxDesc->Status = ETH_DMARXDESC_OWN;
ganlikun 0:13413ea9a877 568
ganlikun 0:13413ea9a877 569 /* Set Buffer1 size and Second Address Chained bit */
ganlikun 0:13413ea9a877 570 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
ganlikun 0:13413ea9a877 571
ganlikun 0:13413ea9a877 572 /* Set Buffer1 address pointer */
ganlikun 0:13413ea9a877 573 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
ganlikun 0:13413ea9a877 574
ganlikun 0:13413ea9a877 575 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
ganlikun 0:13413ea9a877 576 {
ganlikun 0:13413ea9a877 577 /* Enable Ethernet DMA Rx Descriptor interrupt */
ganlikun 0:13413ea9a877 578 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
ganlikun 0:13413ea9a877 579 }
ganlikun 0:13413ea9a877 580
ganlikun 0:13413ea9a877 581 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
ganlikun 0:13413ea9a877 582 if(i < (RxBuffCount-1U))
ganlikun 0:13413ea9a877 583 {
ganlikun 0:13413ea9a877 584 /* Set next descriptor address register with next descriptor base address */
ganlikun 0:13413ea9a877 585 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
ganlikun 0:13413ea9a877 586 }
ganlikun 0:13413ea9a877 587 else
ganlikun 0:13413ea9a877 588 {
ganlikun 0:13413ea9a877 589 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
ganlikun 0:13413ea9a877 590 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
ganlikun 0:13413ea9a877 591 }
ganlikun 0:13413ea9a877 592 }
ganlikun 0:13413ea9a877 593
ganlikun 0:13413ea9a877 594 /* Set Receive Descriptor List Address Register */
ganlikun 0:13413ea9a877 595 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
ganlikun 0:13413ea9a877 596
ganlikun 0:13413ea9a877 597 /* Set ETH HAL State to Ready */
ganlikun 0:13413ea9a877 598 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 599
ganlikun 0:13413ea9a877 600 /* Process Unlocked */
ganlikun 0:13413ea9a877 601 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 602
ganlikun 0:13413ea9a877 603 /* Return function status */
ganlikun 0:13413ea9a877 604 return HAL_OK;
ganlikun 0:13413ea9a877 605 }
ganlikun 0:13413ea9a877 606
ganlikun 0:13413ea9a877 607 /**
ganlikun 0:13413ea9a877 608 * @brief Initializes the ETH MSP.
ganlikun 0:13413ea9a877 609 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 610 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 611 * @retval None
ganlikun 0:13413ea9a877 612 */
ganlikun 0:13413ea9a877 613 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 614 {
ganlikun 0:13413ea9a877 615 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 616 UNUSED(heth);
ganlikun 0:13413ea9a877 617 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 618 the HAL_ETH_MspInit could be implemented in the user file
ganlikun 0:13413ea9a877 619 */
ganlikun 0:13413ea9a877 620 }
ganlikun 0:13413ea9a877 621
ganlikun 0:13413ea9a877 622 /**
ganlikun 0:13413ea9a877 623 * @brief DeInitializes ETH MSP.
ganlikun 0:13413ea9a877 624 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 625 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 626 * @retval None
ganlikun 0:13413ea9a877 627 */
ganlikun 0:13413ea9a877 628 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 629 {
ganlikun 0:13413ea9a877 630 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 631 UNUSED(heth);
ganlikun 0:13413ea9a877 632 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 633 the HAL_ETH_MspDeInit could be implemented in the user file
ganlikun 0:13413ea9a877 634 */
ganlikun 0:13413ea9a877 635 }
ganlikun 0:13413ea9a877 636
ganlikun 0:13413ea9a877 637 /**
ganlikun 0:13413ea9a877 638 * @}
ganlikun 0:13413ea9a877 639 */
ganlikun 0:13413ea9a877 640
ganlikun 0:13413ea9a877 641 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
ganlikun 0:13413ea9a877 642 * @brief Data transfers functions
ganlikun 0:13413ea9a877 643 *
ganlikun 0:13413ea9a877 644 @verbatim
ganlikun 0:13413ea9a877 645 ==============================================================================
ganlikun 0:13413ea9a877 646 ##### IO operation functions #####
ganlikun 0:13413ea9a877 647 ==============================================================================
ganlikun 0:13413ea9a877 648 [..] This section provides functions allowing to:
ganlikun 0:13413ea9a877 649 (+) Transmit a frame
ganlikun 0:13413ea9a877 650 HAL_ETH_TransmitFrame();
ganlikun 0:13413ea9a877 651 (+) Receive a frame
ganlikun 0:13413ea9a877 652 HAL_ETH_GetReceivedFrame();
ganlikun 0:13413ea9a877 653 HAL_ETH_GetReceivedFrame_IT();
ganlikun 0:13413ea9a877 654 (+) Read from an External PHY register
ganlikun 0:13413ea9a877 655 HAL_ETH_ReadPHYRegister();
ganlikun 0:13413ea9a877 656 (+) Write to an External PHY register
ganlikun 0:13413ea9a877 657 HAL_ETH_WritePHYRegister();
ganlikun 0:13413ea9a877 658
ganlikun 0:13413ea9a877 659 @endverbatim
ganlikun 0:13413ea9a877 660
ganlikun 0:13413ea9a877 661 * @{
ganlikun 0:13413ea9a877 662 */
ganlikun 0:13413ea9a877 663
ganlikun 0:13413ea9a877 664 /**
ganlikun 0:13413ea9a877 665 * @brief Sends an Ethernet frame.
ganlikun 0:13413ea9a877 666 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 667 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 668 * @param FrameLength: Amount of data to be sent
ganlikun 0:13413ea9a877 669 * @retval HAL status
ganlikun 0:13413ea9a877 670 */
ganlikun 0:13413ea9a877 671 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
ganlikun 0:13413ea9a877 672 {
ganlikun 0:13413ea9a877 673 uint32_t bufcount = 0U, size = 0U, i = 0U;
ganlikun 0:13413ea9a877 674
ganlikun 0:13413ea9a877 675 /* Process Locked */
ganlikun 0:13413ea9a877 676 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 677
ganlikun 0:13413ea9a877 678 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 679 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 680
ganlikun 0:13413ea9a877 681 if (FrameLength == 0U)
ganlikun 0:13413ea9a877 682 {
ganlikun 0:13413ea9a877 683 /* Set ETH HAL state to READY */
ganlikun 0:13413ea9a877 684 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 685
ganlikun 0:13413ea9a877 686 /* Process Unlocked */
ganlikun 0:13413ea9a877 687 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 688
ganlikun 0:13413ea9a877 689 return HAL_ERROR;
ganlikun 0:13413ea9a877 690 }
ganlikun 0:13413ea9a877 691
ganlikun 0:13413ea9a877 692 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
ganlikun 0:13413ea9a877 693 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
ganlikun 0:13413ea9a877 694 {
ganlikun 0:13413ea9a877 695 /* OWN bit set */
ganlikun 0:13413ea9a877 696 heth->State = HAL_ETH_STATE_BUSY_TX;
ganlikun 0:13413ea9a877 697
ganlikun 0:13413ea9a877 698 /* Process Unlocked */
ganlikun 0:13413ea9a877 699 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 700
ganlikun 0:13413ea9a877 701 return HAL_ERROR;
ganlikun 0:13413ea9a877 702 }
ganlikun 0:13413ea9a877 703
ganlikun 0:13413ea9a877 704 /* Get the number of needed Tx buffers for the current frame */
ganlikun 0:13413ea9a877 705 if (FrameLength > ETH_TX_BUF_SIZE)
ganlikun 0:13413ea9a877 706 {
ganlikun 0:13413ea9a877 707 bufcount = FrameLength/ETH_TX_BUF_SIZE;
ganlikun 0:13413ea9a877 708 if (FrameLength % ETH_TX_BUF_SIZE)
ganlikun 0:13413ea9a877 709 {
ganlikun 0:13413ea9a877 710 bufcount++;
ganlikun 0:13413ea9a877 711 }
ganlikun 0:13413ea9a877 712 }
ganlikun 0:13413ea9a877 713 else
ganlikun 0:13413ea9a877 714 {
ganlikun 0:13413ea9a877 715 bufcount = 1U;
ganlikun 0:13413ea9a877 716 }
ganlikun 0:13413ea9a877 717 if (bufcount == 1U)
ganlikun 0:13413ea9a877 718 {
ganlikun 0:13413ea9a877 719 /* Set LAST and FIRST segment */
ganlikun 0:13413ea9a877 720 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
ganlikun 0:13413ea9a877 721 /* Set frame size */
ganlikun 0:13413ea9a877 722 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
ganlikun 0:13413ea9a877 723 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
ganlikun 0:13413ea9a877 724 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
ganlikun 0:13413ea9a877 725 /* Point to next descriptor */
ganlikun 0:13413ea9a877 726 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 727 }
ganlikun 0:13413ea9a877 728 else
ganlikun 0:13413ea9a877 729 {
ganlikun 0:13413ea9a877 730 for (i=0U; i< bufcount; i++)
ganlikun 0:13413ea9a877 731 {
ganlikun 0:13413ea9a877 732 /* Clear FIRST and LAST segment bits */
ganlikun 0:13413ea9a877 733 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
ganlikun 0:13413ea9a877 734
ganlikun 0:13413ea9a877 735 if (i == 0U)
ganlikun 0:13413ea9a877 736 {
ganlikun 0:13413ea9a877 737 /* Setting the first segment bit */
ganlikun 0:13413ea9a877 738 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
ganlikun 0:13413ea9a877 739 }
ganlikun 0:13413ea9a877 740
ganlikun 0:13413ea9a877 741 /* Program size */
ganlikun 0:13413ea9a877 742 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
ganlikun 0:13413ea9a877 743
ganlikun 0:13413ea9a877 744 if (i == (bufcount-1U))
ganlikun 0:13413ea9a877 745 {
ganlikun 0:13413ea9a877 746 /* Setting the last segment bit */
ganlikun 0:13413ea9a877 747 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
ganlikun 0:13413ea9a877 748 size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
ganlikun 0:13413ea9a877 749 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
ganlikun 0:13413ea9a877 750 }
ganlikun 0:13413ea9a877 751
ganlikun 0:13413ea9a877 752 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
ganlikun 0:13413ea9a877 753 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
ganlikun 0:13413ea9a877 754 /* point to next descriptor */
ganlikun 0:13413ea9a877 755 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 756 }
ganlikun 0:13413ea9a877 757 }
ganlikun 0:13413ea9a877 758
ganlikun 0:13413ea9a877 759 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
ganlikun 0:13413ea9a877 760 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
ganlikun 0:13413ea9a877 761 {
ganlikun 0:13413ea9a877 762 /* Clear TBUS ETHERNET DMA flag */
ganlikun 0:13413ea9a877 763 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
ganlikun 0:13413ea9a877 764 /* Resume DMA transmission*/
ganlikun 0:13413ea9a877 765 (heth->Instance)->DMATPDR = 0U;
ganlikun 0:13413ea9a877 766 }
ganlikun 0:13413ea9a877 767
ganlikun 0:13413ea9a877 768 /* Set ETH HAL State to Ready */
ganlikun 0:13413ea9a877 769 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 770
ganlikun 0:13413ea9a877 771 /* Process Unlocked */
ganlikun 0:13413ea9a877 772 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 773
ganlikun 0:13413ea9a877 774 /* Return function status */
ganlikun 0:13413ea9a877 775 return HAL_OK;
ganlikun 0:13413ea9a877 776 }
ganlikun 0:13413ea9a877 777
ganlikun 0:13413ea9a877 778 /**
ganlikun 0:13413ea9a877 779 * @brief Checks for received frames.
ganlikun 0:13413ea9a877 780 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 781 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 782 * @retval HAL status
ganlikun 0:13413ea9a877 783 */
ganlikun 0:13413ea9a877 784 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 785 {
ganlikun 0:13413ea9a877 786 uint32_t framelength = 0U;
ganlikun 0:13413ea9a877 787
ganlikun 0:13413ea9a877 788 /* Process Locked */
ganlikun 0:13413ea9a877 789 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 790
ganlikun 0:13413ea9a877 791 /* Check the ETH state to BUSY */
ganlikun 0:13413ea9a877 792 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 793
ganlikun 0:13413ea9a877 794 /* Check if segment is not owned by DMA */
ganlikun 0:13413ea9a877 795 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
ganlikun 0:13413ea9a877 796 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
ganlikun 0:13413ea9a877 797 {
ganlikun 0:13413ea9a877 798 /* Check if last segment */
ganlikun 0:13413ea9a877 799 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
ganlikun 0:13413ea9a877 800 {
ganlikun 0:13413ea9a877 801 /* increment segment count */
ganlikun 0:13413ea9a877 802 (heth->RxFrameInfos).SegCount++;
ganlikun 0:13413ea9a877 803
ganlikun 0:13413ea9a877 804 /* Check if last segment is first segment: one segment contains the frame */
ganlikun 0:13413ea9a877 805 if ((heth->RxFrameInfos).SegCount == 1U)
ganlikun 0:13413ea9a877 806 {
ganlikun 0:13413ea9a877 807 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
ganlikun 0:13413ea9a877 808 }
ganlikun 0:13413ea9a877 809
ganlikun 0:13413ea9a877 810 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
ganlikun 0:13413ea9a877 811
ganlikun 0:13413ea9a877 812 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
ganlikun 0:13413ea9a877 813 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
ganlikun 0:13413ea9a877 814 heth->RxFrameInfos.length = framelength;
ganlikun 0:13413ea9a877 815
ganlikun 0:13413ea9a877 816 /* Get the address of the buffer start address */
ganlikun 0:13413ea9a877 817 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
ganlikun 0:13413ea9a877 818 /* point to next descriptor */
ganlikun 0:13413ea9a877 819 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 820
ganlikun 0:13413ea9a877 821 /* Set HAL State to Ready */
ganlikun 0:13413ea9a877 822 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 823
ganlikun 0:13413ea9a877 824 /* Process Unlocked */
ganlikun 0:13413ea9a877 825 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 826
ganlikun 0:13413ea9a877 827 /* Return function status */
ganlikun 0:13413ea9a877 828 return HAL_OK;
ganlikun 0:13413ea9a877 829 }
ganlikun 0:13413ea9a877 830 /* Check if first segment */
ganlikun 0:13413ea9a877 831 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
ganlikun 0:13413ea9a877 832 {
ganlikun 0:13413ea9a877 833 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
ganlikun 0:13413ea9a877 834 (heth->RxFrameInfos).LSRxDesc = NULL;
ganlikun 0:13413ea9a877 835 (heth->RxFrameInfos).SegCount = 1U;
ganlikun 0:13413ea9a877 836 /* Point to next descriptor */
ganlikun 0:13413ea9a877 837 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 838 }
ganlikun 0:13413ea9a877 839 /* Check if intermediate segment */
ganlikun 0:13413ea9a877 840 else
ganlikun 0:13413ea9a877 841 {
ganlikun 0:13413ea9a877 842 (heth->RxFrameInfos).SegCount++;
ganlikun 0:13413ea9a877 843 /* Point to next descriptor */
ganlikun 0:13413ea9a877 844 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 845 }
ganlikun 0:13413ea9a877 846 }
ganlikun 0:13413ea9a877 847
ganlikun 0:13413ea9a877 848 /* Set ETH HAL State to Ready */
ganlikun 0:13413ea9a877 849 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 850
ganlikun 0:13413ea9a877 851 /* Process Unlocked */
ganlikun 0:13413ea9a877 852 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 853
ganlikun 0:13413ea9a877 854 /* Return function status */
ganlikun 0:13413ea9a877 855 return HAL_ERROR;
ganlikun 0:13413ea9a877 856 }
ganlikun 0:13413ea9a877 857
ganlikun 0:13413ea9a877 858 /**
ganlikun 0:13413ea9a877 859 * @brief Gets the Received frame in interrupt mode.
ganlikun 0:13413ea9a877 860 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 861 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 862 * @retval HAL status
ganlikun 0:13413ea9a877 863 */
ganlikun 0:13413ea9a877 864 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 865 {
ganlikun 0:13413ea9a877 866 uint32_t descriptorscancounter = 0U;
ganlikun 0:13413ea9a877 867
ganlikun 0:13413ea9a877 868 /* Process Locked */
ganlikun 0:13413ea9a877 869 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 870
ganlikun 0:13413ea9a877 871 /* Set ETH HAL State to BUSY */
ganlikun 0:13413ea9a877 872 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 873
ganlikun 0:13413ea9a877 874 /* Scan descriptors owned by CPU */
ganlikun 0:13413ea9a877 875 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
ganlikun 0:13413ea9a877 876 {
ganlikun 0:13413ea9a877 877 /* Just for security */
ganlikun 0:13413ea9a877 878 descriptorscancounter++;
ganlikun 0:13413ea9a877 879
ganlikun 0:13413ea9a877 880 /* Check if first segment in frame */
ganlikun 0:13413ea9a877 881 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
ganlikun 0:13413ea9a877 882 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
ganlikun 0:13413ea9a877 883 {
ganlikun 0:13413ea9a877 884 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
ganlikun 0:13413ea9a877 885 heth->RxFrameInfos.SegCount = 1U;
ganlikun 0:13413ea9a877 886 /* Point to next descriptor */
ganlikun 0:13413ea9a877 887 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 888 }
ganlikun 0:13413ea9a877 889 /* Check if intermediate segment */
ganlikun 0:13413ea9a877 890 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
ganlikun 0:13413ea9a877 891 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
ganlikun 0:13413ea9a877 892 {
ganlikun 0:13413ea9a877 893 /* Increment segment count */
ganlikun 0:13413ea9a877 894 (heth->RxFrameInfos.SegCount)++;
ganlikun 0:13413ea9a877 895 /* Point to next descriptor */
ganlikun 0:13413ea9a877 896 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 897 }
ganlikun 0:13413ea9a877 898 /* Should be last segment */
ganlikun 0:13413ea9a877 899 else
ganlikun 0:13413ea9a877 900 {
ganlikun 0:13413ea9a877 901 /* Last segment */
ganlikun 0:13413ea9a877 902 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
ganlikun 0:13413ea9a877 903
ganlikun 0:13413ea9a877 904 /* Increment segment count */
ganlikun 0:13413ea9a877 905 (heth->RxFrameInfos.SegCount)++;
ganlikun 0:13413ea9a877 906
ganlikun 0:13413ea9a877 907 /* Check if last segment is first segment: one segment contains the frame */
ganlikun 0:13413ea9a877 908 if ((heth->RxFrameInfos.SegCount) == 1U)
ganlikun 0:13413ea9a877 909 {
ganlikun 0:13413ea9a877 910 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
ganlikun 0:13413ea9a877 911 }
ganlikun 0:13413ea9a877 912
ganlikun 0:13413ea9a877 913 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
ganlikun 0:13413ea9a877 914 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
ganlikun 0:13413ea9a877 915
ganlikun 0:13413ea9a877 916 /* Get the address of the buffer start address */
ganlikun 0:13413ea9a877 917 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
ganlikun 0:13413ea9a877 918
ganlikun 0:13413ea9a877 919 /* Point to next descriptor */
ganlikun 0:13413ea9a877 920 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
ganlikun 0:13413ea9a877 921
ganlikun 0:13413ea9a877 922 /* Set HAL State to Ready */
ganlikun 0:13413ea9a877 923 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 924
ganlikun 0:13413ea9a877 925 /* Process Unlocked */
ganlikun 0:13413ea9a877 926 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 927
ganlikun 0:13413ea9a877 928 /* Return function status */
ganlikun 0:13413ea9a877 929 return HAL_OK;
ganlikun 0:13413ea9a877 930 }
ganlikun 0:13413ea9a877 931 }
ganlikun 0:13413ea9a877 932
ganlikun 0:13413ea9a877 933 /* Set HAL State to Ready */
ganlikun 0:13413ea9a877 934 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 935
ganlikun 0:13413ea9a877 936 /* Process Unlocked */
ganlikun 0:13413ea9a877 937 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 938
ganlikun 0:13413ea9a877 939 /* Return function status */
ganlikun 0:13413ea9a877 940 return HAL_ERROR;
ganlikun 0:13413ea9a877 941 }
ganlikun 0:13413ea9a877 942
ganlikun 0:13413ea9a877 943 /**
ganlikun 0:13413ea9a877 944 * @brief This function handles ETH interrupt request.
ganlikun 0:13413ea9a877 945 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 946 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 947 * @retval HAL status
ganlikun 0:13413ea9a877 948 */
ganlikun 0:13413ea9a877 949 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 950 {
ganlikun 0:13413ea9a877 951 /* Frame received */
ganlikun 0:13413ea9a877 952 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
ganlikun 0:13413ea9a877 953 {
ganlikun 0:13413ea9a877 954 /* Receive complete callback */
ganlikun 0:13413ea9a877 955 HAL_ETH_RxCpltCallback(heth);
ganlikun 0:13413ea9a877 956
ganlikun 0:13413ea9a877 957 /* Clear the Eth DMA Rx IT pending bits */
ganlikun 0:13413ea9a877 958 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
ganlikun 0:13413ea9a877 959
ganlikun 0:13413ea9a877 960 /* Set HAL State to Ready */
ganlikun 0:13413ea9a877 961 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 962
ganlikun 0:13413ea9a877 963 /* Process Unlocked */
ganlikun 0:13413ea9a877 964 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 965
ganlikun 0:13413ea9a877 966 }
ganlikun 0:13413ea9a877 967 /* Frame transmitted */
ganlikun 0:13413ea9a877 968 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
ganlikun 0:13413ea9a877 969 {
ganlikun 0:13413ea9a877 970 /* Transfer complete callback */
ganlikun 0:13413ea9a877 971 HAL_ETH_TxCpltCallback(heth);
ganlikun 0:13413ea9a877 972
ganlikun 0:13413ea9a877 973 /* Clear the Eth DMA Tx IT pending bits */
ganlikun 0:13413ea9a877 974 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
ganlikun 0:13413ea9a877 975
ganlikun 0:13413ea9a877 976 /* Set HAL State to Ready */
ganlikun 0:13413ea9a877 977 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 978
ganlikun 0:13413ea9a877 979 /* Process Unlocked */
ganlikun 0:13413ea9a877 980 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 981 }
ganlikun 0:13413ea9a877 982
ganlikun 0:13413ea9a877 983 /* Clear the interrupt flags */
ganlikun 0:13413ea9a877 984 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
ganlikun 0:13413ea9a877 985
ganlikun 0:13413ea9a877 986 /* ETH DMA Error */
ganlikun 0:13413ea9a877 987 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
ganlikun 0:13413ea9a877 988 {
ganlikun 0:13413ea9a877 989 /* Ethernet Error callback */
ganlikun 0:13413ea9a877 990 HAL_ETH_ErrorCallback(heth);
ganlikun 0:13413ea9a877 991
ganlikun 0:13413ea9a877 992 /* Clear the interrupt flags */
ganlikun 0:13413ea9a877 993 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
ganlikun 0:13413ea9a877 994
ganlikun 0:13413ea9a877 995 /* Set HAL State to Ready */
ganlikun 0:13413ea9a877 996 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 997
ganlikun 0:13413ea9a877 998 /* Process Unlocked */
ganlikun 0:13413ea9a877 999 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 1000 }
ganlikun 0:13413ea9a877 1001 }
ganlikun 0:13413ea9a877 1002
ganlikun 0:13413ea9a877 1003 /**
ganlikun 0:13413ea9a877 1004 * @brief Tx Transfer completed callbacks.
ganlikun 0:13413ea9a877 1005 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1006 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1007 * @retval None
ganlikun 0:13413ea9a877 1008 */
ganlikun 0:13413ea9a877 1009 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1010 {
ganlikun 0:13413ea9a877 1011 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1012 UNUSED(heth);
ganlikun 0:13413ea9a877 1013 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1014 the HAL_ETH_TxCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1015 */
ganlikun 0:13413ea9a877 1016 }
ganlikun 0:13413ea9a877 1017
ganlikun 0:13413ea9a877 1018 /**
ganlikun 0:13413ea9a877 1019 * @brief Rx Transfer completed callbacks.
ganlikun 0:13413ea9a877 1020 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1021 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1022 * @retval None
ganlikun 0:13413ea9a877 1023 */
ganlikun 0:13413ea9a877 1024 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1025 {
ganlikun 0:13413ea9a877 1026 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1027 UNUSED(heth);
ganlikun 0:13413ea9a877 1028 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1029 the HAL_ETH_TxCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1030 */
ganlikun 0:13413ea9a877 1031 }
ganlikun 0:13413ea9a877 1032
ganlikun 0:13413ea9a877 1033 /**
ganlikun 0:13413ea9a877 1034 * @brief Ethernet transfer error callbacks
ganlikun 0:13413ea9a877 1035 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1036 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1037 * @retval None
ganlikun 0:13413ea9a877 1038 */
ganlikun 0:13413ea9a877 1039 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1040 {
ganlikun 0:13413ea9a877 1041 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1042 UNUSED(heth);
ganlikun 0:13413ea9a877 1043 /* NOTE : This function Should not be modified, when the callback is needed,
ganlikun 0:13413ea9a877 1044 the HAL_ETH_TxCpltCallback could be implemented in the user file
ganlikun 0:13413ea9a877 1045 */
ganlikun 0:13413ea9a877 1046 }
ganlikun 0:13413ea9a877 1047
ganlikun 0:13413ea9a877 1048 /**
ganlikun 0:13413ea9a877 1049 * @brief Reads a PHY register
ganlikun 0:13413ea9a877 1050 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1051 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1052 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
ganlikun 0:13413ea9a877 1053 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 1054 * PHY_BCR: Transceiver Basic Control Register,
ganlikun 0:13413ea9a877 1055 * PHY_BSR: Transceiver Basic Status Register.
ganlikun 0:13413ea9a877 1056 * More PHY register could be read depending on the used PHY
ganlikun 0:13413ea9a877 1057 * @param RegValue: PHY register value
ganlikun 0:13413ea9a877 1058 * @retval HAL status
ganlikun 0:13413ea9a877 1059 */
ganlikun 0:13413ea9a877 1060 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
ganlikun 0:13413ea9a877 1061 {
ganlikun 0:13413ea9a877 1062 uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1063 uint32_t tickstart = 0U;
ganlikun 0:13413ea9a877 1064
ganlikun 0:13413ea9a877 1065 /* Check parameters */
ganlikun 0:13413ea9a877 1066 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
ganlikun 0:13413ea9a877 1067
ganlikun 0:13413ea9a877 1068 /* Check the ETH peripheral state */
ganlikun 0:13413ea9a877 1069 if(heth->State == HAL_ETH_STATE_BUSY_RD)
ganlikun 0:13413ea9a877 1070 {
ganlikun 0:13413ea9a877 1071 return HAL_BUSY;
ganlikun 0:13413ea9a877 1072 }
ganlikun 0:13413ea9a877 1073 /* Set ETH HAL State to BUSY_RD */
ganlikun 0:13413ea9a877 1074 heth->State = HAL_ETH_STATE_BUSY_RD;
ganlikun 0:13413ea9a877 1075
ganlikun 0:13413ea9a877 1076 /* Get the ETHERNET MACMIIAR value */
ganlikun 0:13413ea9a877 1077 tmpreg1 = heth->Instance->MACMIIAR;
ganlikun 0:13413ea9a877 1078
ganlikun 0:13413ea9a877 1079 /* Keep only the CSR Clock Range CR[2:0] bits value */
ganlikun 0:13413ea9a877 1080 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
ganlikun 0:13413ea9a877 1081
ganlikun 0:13413ea9a877 1082 /* Prepare the MII address register value */
ganlikun 0:13413ea9a877 1083 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
ganlikun 0:13413ea9a877 1084 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
ganlikun 0:13413ea9a877 1085 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
ganlikun 0:13413ea9a877 1086 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
ganlikun 0:13413ea9a877 1087
ganlikun 0:13413ea9a877 1088 /* Write the result value into the MII Address register */
ganlikun 0:13413ea9a877 1089 heth->Instance->MACMIIAR = tmpreg1;
ganlikun 0:13413ea9a877 1090
ganlikun 0:13413ea9a877 1091 /* Get tick */
ganlikun 0:13413ea9a877 1092 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 1093
ganlikun 0:13413ea9a877 1094 /* Check for the Busy flag */
ganlikun 0:13413ea9a877 1095 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
ganlikun 0:13413ea9a877 1096 {
ganlikun 0:13413ea9a877 1097 /* Check for the Timeout */
ganlikun 0:13413ea9a877 1098 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
ganlikun 0:13413ea9a877 1099 {
ganlikun 0:13413ea9a877 1100 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1101
ganlikun 0:13413ea9a877 1102 /* Process Unlocked */
ganlikun 0:13413ea9a877 1103 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 1104
ganlikun 0:13413ea9a877 1105 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 1106 }
ganlikun 0:13413ea9a877 1107
ganlikun 0:13413ea9a877 1108 tmpreg1 = heth->Instance->MACMIIAR;
ganlikun 0:13413ea9a877 1109 }
ganlikun 0:13413ea9a877 1110
ganlikun 0:13413ea9a877 1111 /* Get MACMIIDR value */
ganlikun 0:13413ea9a877 1112 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
ganlikun 0:13413ea9a877 1113
ganlikun 0:13413ea9a877 1114 /* Set ETH HAL State to READY */
ganlikun 0:13413ea9a877 1115 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1116
ganlikun 0:13413ea9a877 1117 /* Return function status */
ganlikun 0:13413ea9a877 1118 return HAL_OK;
ganlikun 0:13413ea9a877 1119 }
ganlikun 0:13413ea9a877 1120
ganlikun 0:13413ea9a877 1121 /**
ganlikun 0:13413ea9a877 1122 * @brief Writes to a PHY register.
ganlikun 0:13413ea9a877 1123 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1124 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1125 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
ganlikun 0:13413ea9a877 1126 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 1127 * PHY_BCR: Transceiver Control Register.
ganlikun 0:13413ea9a877 1128 * More PHY register could be written depending on the used PHY
ganlikun 0:13413ea9a877 1129 * @param RegValue: the value to write
ganlikun 0:13413ea9a877 1130 * @retval HAL status
ganlikun 0:13413ea9a877 1131 */
ganlikun 0:13413ea9a877 1132 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
ganlikun 0:13413ea9a877 1133 {
ganlikun 0:13413ea9a877 1134 uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1135 uint32_t tickstart = 0U;
ganlikun 0:13413ea9a877 1136
ganlikun 0:13413ea9a877 1137 /* Check parameters */
ganlikun 0:13413ea9a877 1138 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
ganlikun 0:13413ea9a877 1139
ganlikun 0:13413ea9a877 1140 /* Check the ETH peripheral state */
ganlikun 0:13413ea9a877 1141 if(heth->State == HAL_ETH_STATE_BUSY_WR)
ganlikun 0:13413ea9a877 1142 {
ganlikun 0:13413ea9a877 1143 return HAL_BUSY;
ganlikun 0:13413ea9a877 1144 }
ganlikun 0:13413ea9a877 1145 /* Set ETH HAL State to BUSY_WR */
ganlikun 0:13413ea9a877 1146 heth->State = HAL_ETH_STATE_BUSY_WR;
ganlikun 0:13413ea9a877 1147
ganlikun 0:13413ea9a877 1148 /* Get the ETHERNET MACMIIAR value */
ganlikun 0:13413ea9a877 1149 tmpreg1 = heth->Instance->MACMIIAR;
ganlikun 0:13413ea9a877 1150
ganlikun 0:13413ea9a877 1151 /* Keep only the CSR Clock Range CR[2:0] bits value */
ganlikun 0:13413ea9a877 1152 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
ganlikun 0:13413ea9a877 1153
ganlikun 0:13413ea9a877 1154 /* Prepare the MII register address value */
ganlikun 0:13413ea9a877 1155 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
ganlikun 0:13413ea9a877 1156 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
ganlikun 0:13413ea9a877 1157 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
ganlikun 0:13413ea9a877 1158 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
ganlikun 0:13413ea9a877 1159
ganlikun 0:13413ea9a877 1160 /* Give the value to the MII data register */
ganlikun 0:13413ea9a877 1161 heth->Instance->MACMIIDR = (uint16_t)RegValue;
ganlikun 0:13413ea9a877 1162
ganlikun 0:13413ea9a877 1163 /* Write the result value into the MII Address register */
ganlikun 0:13413ea9a877 1164 heth->Instance->MACMIIAR = tmpreg1;
ganlikun 0:13413ea9a877 1165
ganlikun 0:13413ea9a877 1166 /* Get tick */
ganlikun 0:13413ea9a877 1167 tickstart = HAL_GetTick();
ganlikun 0:13413ea9a877 1168
ganlikun 0:13413ea9a877 1169 /* Check for the Busy flag */
ganlikun 0:13413ea9a877 1170 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
ganlikun 0:13413ea9a877 1171 {
ganlikun 0:13413ea9a877 1172 /* Check for the Timeout */
ganlikun 0:13413ea9a877 1173 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
ganlikun 0:13413ea9a877 1174 {
ganlikun 0:13413ea9a877 1175 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1176
ganlikun 0:13413ea9a877 1177 /* Process Unlocked */
ganlikun 0:13413ea9a877 1178 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 1179
ganlikun 0:13413ea9a877 1180 return HAL_TIMEOUT;
ganlikun 0:13413ea9a877 1181 }
ganlikun 0:13413ea9a877 1182
ganlikun 0:13413ea9a877 1183 tmpreg1 = heth->Instance->MACMIIAR;
ganlikun 0:13413ea9a877 1184 }
ganlikun 0:13413ea9a877 1185
ganlikun 0:13413ea9a877 1186 /* Set ETH HAL State to READY */
ganlikun 0:13413ea9a877 1187 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1188
ganlikun 0:13413ea9a877 1189 /* Return function status */
ganlikun 0:13413ea9a877 1190 return HAL_OK;
ganlikun 0:13413ea9a877 1191 }
ganlikun 0:13413ea9a877 1192
ganlikun 0:13413ea9a877 1193 /**
ganlikun 0:13413ea9a877 1194 * @}
ganlikun 0:13413ea9a877 1195 */
ganlikun 0:13413ea9a877 1196
ganlikun 0:13413ea9a877 1197 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
ganlikun 0:13413ea9a877 1198 * @brief Peripheral Control functions
ganlikun 0:13413ea9a877 1199 *
ganlikun 0:13413ea9a877 1200 @verbatim
ganlikun 0:13413ea9a877 1201 ===============================================================================
ganlikun 0:13413ea9a877 1202 ##### Peripheral Control functions #####
ganlikun 0:13413ea9a877 1203 ===============================================================================
ganlikun 0:13413ea9a877 1204 [..] This section provides functions allowing to:
ganlikun 0:13413ea9a877 1205 (+) Enable MAC and DMA transmission and reception.
ganlikun 0:13413ea9a877 1206 HAL_ETH_Start();
ganlikun 0:13413ea9a877 1207 (+) Disable MAC and DMA transmission and reception.
ganlikun 0:13413ea9a877 1208 HAL_ETH_Stop();
ganlikun 0:13413ea9a877 1209 (+) Set the MAC configuration in runtime mode
ganlikun 0:13413ea9a877 1210 HAL_ETH_ConfigMAC();
ganlikun 0:13413ea9a877 1211 (+) Set the DMA configuration in runtime mode
ganlikun 0:13413ea9a877 1212 HAL_ETH_ConfigDMA();
ganlikun 0:13413ea9a877 1213
ganlikun 0:13413ea9a877 1214 @endverbatim
ganlikun 0:13413ea9a877 1215 * @{
ganlikun 0:13413ea9a877 1216 */
ganlikun 0:13413ea9a877 1217
ganlikun 0:13413ea9a877 1218 /**
ganlikun 0:13413ea9a877 1219 * @brief Enables Ethernet MAC and DMA reception/transmission
ganlikun 0:13413ea9a877 1220 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1221 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1222 * @retval HAL status
ganlikun 0:13413ea9a877 1223 */
ganlikun 0:13413ea9a877 1224 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1225 {
ganlikun 0:13413ea9a877 1226 /* Process Locked */
ganlikun 0:13413ea9a877 1227 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 1228
ganlikun 0:13413ea9a877 1229 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 1230 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 1231
ganlikun 0:13413ea9a877 1232 /* Enable transmit state machine of the MAC for transmission on the MII */
ganlikun 0:13413ea9a877 1233 ETH_MACTransmissionEnable(heth);
ganlikun 0:13413ea9a877 1234
ganlikun 0:13413ea9a877 1235 /* Enable receive state machine of the MAC for reception from the MII */
ganlikun 0:13413ea9a877 1236 ETH_MACReceptionEnable(heth);
ganlikun 0:13413ea9a877 1237
ganlikun 0:13413ea9a877 1238 /* Flush Transmit FIFO */
ganlikun 0:13413ea9a877 1239 ETH_FlushTransmitFIFO(heth);
ganlikun 0:13413ea9a877 1240
ganlikun 0:13413ea9a877 1241 /* Start DMA transmission */
ganlikun 0:13413ea9a877 1242 ETH_DMATransmissionEnable(heth);
ganlikun 0:13413ea9a877 1243
ganlikun 0:13413ea9a877 1244 /* Start DMA reception */
ganlikun 0:13413ea9a877 1245 ETH_DMAReceptionEnable(heth);
ganlikun 0:13413ea9a877 1246
ganlikun 0:13413ea9a877 1247 /* Set the ETH state to READY*/
ganlikun 0:13413ea9a877 1248 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1249
ganlikun 0:13413ea9a877 1250 /* Process Unlocked */
ganlikun 0:13413ea9a877 1251 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 1252
ganlikun 0:13413ea9a877 1253 /* Return function status */
ganlikun 0:13413ea9a877 1254 return HAL_OK;
ganlikun 0:13413ea9a877 1255 }
ganlikun 0:13413ea9a877 1256
ganlikun 0:13413ea9a877 1257 /**
ganlikun 0:13413ea9a877 1258 * @brief Stop Ethernet MAC and DMA reception/transmission
ganlikun 0:13413ea9a877 1259 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1260 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1261 * @retval HAL status
ganlikun 0:13413ea9a877 1262 */
ganlikun 0:13413ea9a877 1263 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1264 {
ganlikun 0:13413ea9a877 1265 /* Process Locked */
ganlikun 0:13413ea9a877 1266 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 1267
ganlikun 0:13413ea9a877 1268 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 1269 heth->State = HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 1270
ganlikun 0:13413ea9a877 1271 /* Stop DMA transmission */
ganlikun 0:13413ea9a877 1272 ETH_DMATransmissionDisable(heth);
ganlikun 0:13413ea9a877 1273
ganlikun 0:13413ea9a877 1274 /* Stop DMA reception */
ganlikun 0:13413ea9a877 1275 ETH_DMAReceptionDisable(heth);
ganlikun 0:13413ea9a877 1276
ganlikun 0:13413ea9a877 1277 /* Disable receive state machine of the MAC for reception from the MII */
ganlikun 0:13413ea9a877 1278 ETH_MACReceptionDisable(heth);
ganlikun 0:13413ea9a877 1279
ganlikun 0:13413ea9a877 1280 /* Flush Transmit FIFO */
ganlikun 0:13413ea9a877 1281 ETH_FlushTransmitFIFO(heth);
ganlikun 0:13413ea9a877 1282
ganlikun 0:13413ea9a877 1283 /* Disable transmit state machine of the MAC for transmission on the MII */
ganlikun 0:13413ea9a877 1284 ETH_MACTransmissionDisable(heth);
ganlikun 0:13413ea9a877 1285
ganlikun 0:13413ea9a877 1286 /* Set the ETH state*/
ganlikun 0:13413ea9a877 1287 heth->State = HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1288
ganlikun 0:13413ea9a877 1289 /* Process Unlocked */
ganlikun 0:13413ea9a877 1290 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 1291
ganlikun 0:13413ea9a877 1292 /* Return function status */
ganlikun 0:13413ea9a877 1293 return HAL_OK;
ganlikun 0:13413ea9a877 1294 }
ganlikun 0:13413ea9a877 1295
ganlikun 0:13413ea9a877 1296 /**
ganlikun 0:13413ea9a877 1297 * @brief Set ETH MAC Configuration.
ganlikun 0:13413ea9a877 1298 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1299 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1300 * @param macconf: MAC Configuration structure
ganlikun 0:13413ea9a877 1301 * @retval HAL status
ganlikun 0:13413ea9a877 1302 */
ganlikun 0:13413ea9a877 1303 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
ganlikun 0:13413ea9a877 1304 {
ganlikun 0:13413ea9a877 1305 uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1306
ganlikun 0:13413ea9a877 1307 /* Process Locked */
ganlikun 0:13413ea9a877 1308 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 1309
ganlikun 0:13413ea9a877 1310 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 1311 heth->State= HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 1312
ganlikun 0:13413ea9a877 1313 assert_param(IS_ETH_SPEED(heth->Init.Speed));
ganlikun 0:13413ea9a877 1314 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
ganlikun 0:13413ea9a877 1315
ganlikun 0:13413ea9a877 1316 if (macconf != NULL)
ganlikun 0:13413ea9a877 1317 {
ganlikun 0:13413ea9a877 1318 /* Check the parameters */
ganlikun 0:13413ea9a877 1319 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
ganlikun 0:13413ea9a877 1320 assert_param(IS_ETH_JABBER(macconf->Jabber));
ganlikun 0:13413ea9a877 1321 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
ganlikun 0:13413ea9a877 1322 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
ganlikun 0:13413ea9a877 1323 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
ganlikun 0:13413ea9a877 1324 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
ganlikun 0:13413ea9a877 1325 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
ganlikun 0:13413ea9a877 1326 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
ganlikun 0:13413ea9a877 1327 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
ganlikun 0:13413ea9a877 1328 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
ganlikun 0:13413ea9a877 1329 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
ganlikun 0:13413ea9a877 1330 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
ganlikun 0:13413ea9a877 1331 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
ganlikun 0:13413ea9a877 1332 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
ganlikun 0:13413ea9a877 1333 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
ganlikun 0:13413ea9a877 1334 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
ganlikun 0:13413ea9a877 1335 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
ganlikun 0:13413ea9a877 1336 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
ganlikun 0:13413ea9a877 1337 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
ganlikun 0:13413ea9a877 1338 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
ganlikun 0:13413ea9a877 1339 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
ganlikun 0:13413ea9a877 1340 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
ganlikun 0:13413ea9a877 1341 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
ganlikun 0:13413ea9a877 1342 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
ganlikun 0:13413ea9a877 1343 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
ganlikun 0:13413ea9a877 1344 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
ganlikun 0:13413ea9a877 1345 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
ganlikun 0:13413ea9a877 1346
ganlikun 0:13413ea9a877 1347 /*------------------------ ETHERNET MACCR Configuration --------------------*/
ganlikun 0:13413ea9a877 1348 /* Get the ETHERNET MACCR value */
ganlikun 0:13413ea9a877 1349 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1350 /* Clear WD, PCE, PS, TE and RE bits */
ganlikun 0:13413ea9a877 1351 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
ganlikun 0:13413ea9a877 1352
ganlikun 0:13413ea9a877 1353 tmpreg1 |= (uint32_t)(macconf->Watchdog |
ganlikun 0:13413ea9a877 1354 macconf->Jabber |
ganlikun 0:13413ea9a877 1355 macconf->InterFrameGap |
ganlikun 0:13413ea9a877 1356 macconf->CarrierSense |
ganlikun 0:13413ea9a877 1357 (heth->Init).Speed |
ganlikun 0:13413ea9a877 1358 macconf->ReceiveOwn |
ganlikun 0:13413ea9a877 1359 macconf->LoopbackMode |
ganlikun 0:13413ea9a877 1360 (heth->Init).DuplexMode |
ganlikun 0:13413ea9a877 1361 macconf->ChecksumOffload |
ganlikun 0:13413ea9a877 1362 macconf->RetryTransmission |
ganlikun 0:13413ea9a877 1363 macconf->AutomaticPadCRCStrip |
ganlikun 0:13413ea9a877 1364 macconf->BackOffLimit |
ganlikun 0:13413ea9a877 1365 macconf->DeferralCheck);
ganlikun 0:13413ea9a877 1366
ganlikun 0:13413ea9a877 1367 /* Write to ETHERNET MACCR */
ganlikun 0:13413ea9a877 1368 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 1369
ganlikun 0:13413ea9a877 1370 /* Wait until the write operation will be taken into account :
ganlikun 0:13413ea9a877 1371 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1372 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1373 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1374 (heth->Instance)->MACCR = tmpreg1;
ganlikun 0:13413ea9a877 1375
ganlikun 0:13413ea9a877 1376 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
ganlikun 0:13413ea9a877 1377 /* Write to ETHERNET MACFFR */
ganlikun 0:13413ea9a877 1378 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
ganlikun 0:13413ea9a877 1379 macconf->SourceAddrFilter |
ganlikun 0:13413ea9a877 1380 macconf->PassControlFrames |
ganlikun 0:13413ea9a877 1381 macconf->BroadcastFramesReception |
ganlikun 0:13413ea9a877 1382 macconf->DestinationAddrFilter |
ganlikun 0:13413ea9a877 1383 macconf->PromiscuousMode |
ganlikun 0:13413ea9a877 1384 macconf->MulticastFramesFilter |
ganlikun 0:13413ea9a877 1385 macconf->UnicastFramesFilter);
ganlikun 0:13413ea9a877 1386
ganlikun 0:13413ea9a877 1387 /* Wait until the write operation will be taken into account :
ganlikun 0:13413ea9a877 1388 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1389 tmpreg1 = (heth->Instance)->MACFFR;
ganlikun 0:13413ea9a877 1390 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1391 (heth->Instance)->MACFFR = tmpreg1;
ganlikun 0:13413ea9a877 1392
ganlikun 0:13413ea9a877 1393 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
ganlikun 0:13413ea9a877 1394 /* Write to ETHERNET MACHTHR */
ganlikun 0:13413ea9a877 1395 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
ganlikun 0:13413ea9a877 1396
ganlikun 0:13413ea9a877 1397 /* Write to ETHERNET MACHTLR */
ganlikun 0:13413ea9a877 1398 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
ganlikun 0:13413ea9a877 1399 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
ganlikun 0:13413ea9a877 1400
ganlikun 0:13413ea9a877 1401 /* Get the ETHERNET MACFCR value */
ganlikun 0:13413ea9a877 1402 tmpreg1 = (heth->Instance)->MACFCR;
ganlikun 0:13413ea9a877 1403 /* Clear xx bits */
ganlikun 0:13413ea9a877 1404 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
ganlikun 0:13413ea9a877 1405
ganlikun 0:13413ea9a877 1406 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
ganlikun 0:13413ea9a877 1407 macconf->ZeroQuantaPause |
ganlikun 0:13413ea9a877 1408 macconf->PauseLowThreshold |
ganlikun 0:13413ea9a877 1409 macconf->UnicastPauseFrameDetect |
ganlikun 0:13413ea9a877 1410 macconf->ReceiveFlowControl |
ganlikun 0:13413ea9a877 1411 macconf->TransmitFlowControl);
ganlikun 0:13413ea9a877 1412
ganlikun 0:13413ea9a877 1413 /* Write to ETHERNET MACFCR */
ganlikun 0:13413ea9a877 1414 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 1415
ganlikun 0:13413ea9a877 1416 /* Wait until the write operation will be taken into account :
ganlikun 0:13413ea9a877 1417 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1418 tmpreg1 = (heth->Instance)->MACFCR;
ganlikun 0:13413ea9a877 1419 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1420 (heth->Instance)->MACFCR = tmpreg1;
ganlikun 0:13413ea9a877 1421
ganlikun 0:13413ea9a877 1422 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
ganlikun 0:13413ea9a877 1423 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
ganlikun 0:13413ea9a877 1424 macconf->VLANTagIdentifier);
ganlikun 0:13413ea9a877 1425
ganlikun 0:13413ea9a877 1426 /* Wait until the write operation will be taken into account :
ganlikun 0:13413ea9a877 1427 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1428 tmpreg1 = (heth->Instance)->MACVLANTR;
ganlikun 0:13413ea9a877 1429 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1430 (heth->Instance)->MACVLANTR = tmpreg1;
ganlikun 0:13413ea9a877 1431 }
ganlikun 0:13413ea9a877 1432 else /* macconf == NULL : here we just configure Speed and Duplex mode */
ganlikun 0:13413ea9a877 1433 {
ganlikun 0:13413ea9a877 1434 /*------------------------ ETHERNET MACCR Configuration --------------------*/
ganlikun 0:13413ea9a877 1435 /* Get the ETHERNET MACCR value */
ganlikun 0:13413ea9a877 1436 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1437
ganlikun 0:13413ea9a877 1438 /* Clear FES and DM bits */
ganlikun 0:13413ea9a877 1439 tmpreg1 &= ~(0x00004800U);
ganlikun 0:13413ea9a877 1440
ganlikun 0:13413ea9a877 1441 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
ganlikun 0:13413ea9a877 1442
ganlikun 0:13413ea9a877 1443 /* Write to ETHERNET MACCR */
ganlikun 0:13413ea9a877 1444 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 1445
ganlikun 0:13413ea9a877 1446 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1447 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1448 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1449 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1450 (heth->Instance)->MACCR = tmpreg1;
ganlikun 0:13413ea9a877 1451 }
ganlikun 0:13413ea9a877 1452
ganlikun 0:13413ea9a877 1453 /* Set the ETH state to Ready */
ganlikun 0:13413ea9a877 1454 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1455
ganlikun 0:13413ea9a877 1456 /* Process Unlocked */
ganlikun 0:13413ea9a877 1457 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 1458
ganlikun 0:13413ea9a877 1459 /* Return function status */
ganlikun 0:13413ea9a877 1460 return HAL_OK;
ganlikun 0:13413ea9a877 1461 }
ganlikun 0:13413ea9a877 1462
ganlikun 0:13413ea9a877 1463 /**
ganlikun 0:13413ea9a877 1464 * @brief Sets ETH DMA Configuration.
ganlikun 0:13413ea9a877 1465 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1466 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1467 * @param dmaconf: DMA Configuration structure
ganlikun 0:13413ea9a877 1468 * @retval HAL status
ganlikun 0:13413ea9a877 1469 */
ganlikun 0:13413ea9a877 1470 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
ganlikun 0:13413ea9a877 1471 {
ganlikun 0:13413ea9a877 1472 uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1473
ganlikun 0:13413ea9a877 1474 /* Process Locked */
ganlikun 0:13413ea9a877 1475 __HAL_LOCK(heth);
ganlikun 0:13413ea9a877 1476
ganlikun 0:13413ea9a877 1477 /* Set the ETH peripheral state to BUSY */
ganlikun 0:13413ea9a877 1478 heth->State= HAL_ETH_STATE_BUSY;
ganlikun 0:13413ea9a877 1479
ganlikun 0:13413ea9a877 1480 /* Check parameters */
ganlikun 0:13413ea9a877 1481 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
ganlikun 0:13413ea9a877 1482 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
ganlikun 0:13413ea9a877 1483 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
ganlikun 0:13413ea9a877 1484 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
ganlikun 0:13413ea9a877 1485 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
ganlikun 0:13413ea9a877 1486 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
ganlikun 0:13413ea9a877 1487 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
ganlikun 0:13413ea9a877 1488 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
ganlikun 0:13413ea9a877 1489 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
ganlikun 0:13413ea9a877 1490 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
ganlikun 0:13413ea9a877 1491 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
ganlikun 0:13413ea9a877 1492 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
ganlikun 0:13413ea9a877 1493 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
ganlikun 0:13413ea9a877 1494 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
ganlikun 0:13413ea9a877 1495 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
ganlikun 0:13413ea9a877 1496 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
ganlikun 0:13413ea9a877 1497
ganlikun 0:13413ea9a877 1498 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
ganlikun 0:13413ea9a877 1499 /* Get the ETHERNET DMAOMR value */
ganlikun 0:13413ea9a877 1500 tmpreg1 = (heth->Instance)->DMAOMR;
ganlikun 0:13413ea9a877 1501 /* Clear xx bits */
ganlikun 0:13413ea9a877 1502 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
ganlikun 0:13413ea9a877 1503
ganlikun 0:13413ea9a877 1504 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
ganlikun 0:13413ea9a877 1505 dmaconf->ReceiveStoreForward |
ganlikun 0:13413ea9a877 1506 dmaconf->FlushReceivedFrame |
ganlikun 0:13413ea9a877 1507 dmaconf->TransmitStoreForward |
ganlikun 0:13413ea9a877 1508 dmaconf->TransmitThresholdControl |
ganlikun 0:13413ea9a877 1509 dmaconf->ForwardErrorFrames |
ganlikun 0:13413ea9a877 1510 dmaconf->ForwardUndersizedGoodFrames |
ganlikun 0:13413ea9a877 1511 dmaconf->ReceiveThresholdControl |
ganlikun 0:13413ea9a877 1512 dmaconf->SecondFrameOperate);
ganlikun 0:13413ea9a877 1513
ganlikun 0:13413ea9a877 1514 /* Write to ETHERNET DMAOMR */
ganlikun 0:13413ea9a877 1515 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 1516
ganlikun 0:13413ea9a877 1517 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1518 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1519 tmpreg1 = (heth->Instance)->DMAOMR;
ganlikun 0:13413ea9a877 1520 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1521 (heth->Instance)->DMAOMR = tmpreg1;
ganlikun 0:13413ea9a877 1522
ganlikun 0:13413ea9a877 1523 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
ganlikun 0:13413ea9a877 1524 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
ganlikun 0:13413ea9a877 1525 dmaconf->FixedBurst |
ganlikun 0:13413ea9a877 1526 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
ganlikun 0:13413ea9a877 1527 dmaconf->TxDMABurstLength |
ganlikun 0:13413ea9a877 1528 dmaconf->EnhancedDescriptorFormat |
ganlikun 0:13413ea9a877 1529 (dmaconf->DescriptorSkipLength << 2U) |
ganlikun 0:13413ea9a877 1530 dmaconf->DMAArbitration |
ganlikun 0:13413ea9a877 1531 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
ganlikun 0:13413ea9a877 1532
ganlikun 0:13413ea9a877 1533 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1534 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1535 tmpreg1 = (heth->Instance)->DMABMR;
ganlikun 0:13413ea9a877 1536 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1537 (heth->Instance)->DMABMR = tmpreg1;
ganlikun 0:13413ea9a877 1538
ganlikun 0:13413ea9a877 1539 /* Set the ETH state to Ready */
ganlikun 0:13413ea9a877 1540 heth->State= HAL_ETH_STATE_READY;
ganlikun 0:13413ea9a877 1541
ganlikun 0:13413ea9a877 1542 /* Process Unlocked */
ganlikun 0:13413ea9a877 1543 __HAL_UNLOCK(heth);
ganlikun 0:13413ea9a877 1544
ganlikun 0:13413ea9a877 1545 /* Return function status */
ganlikun 0:13413ea9a877 1546 return HAL_OK;
ganlikun 0:13413ea9a877 1547 }
ganlikun 0:13413ea9a877 1548
ganlikun 0:13413ea9a877 1549 /**
ganlikun 0:13413ea9a877 1550 * @}
ganlikun 0:13413ea9a877 1551 */
ganlikun 0:13413ea9a877 1552
ganlikun 0:13413ea9a877 1553 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
ganlikun 0:13413ea9a877 1554 * @brief Peripheral State functions
ganlikun 0:13413ea9a877 1555 *
ganlikun 0:13413ea9a877 1556 @verbatim
ganlikun 0:13413ea9a877 1557 ===============================================================================
ganlikun 0:13413ea9a877 1558 ##### Peripheral State functions #####
ganlikun 0:13413ea9a877 1559 ===============================================================================
ganlikun 0:13413ea9a877 1560 [..]
ganlikun 0:13413ea9a877 1561 This subsection permits to get in run-time the status of the peripheral
ganlikun 0:13413ea9a877 1562 and the data flow.
ganlikun 0:13413ea9a877 1563 (+) Get the ETH handle state:
ganlikun 0:13413ea9a877 1564 HAL_ETH_GetState();
ganlikun 0:13413ea9a877 1565
ganlikun 0:13413ea9a877 1566
ganlikun 0:13413ea9a877 1567 @endverbatim
ganlikun 0:13413ea9a877 1568 * @{
ganlikun 0:13413ea9a877 1569 */
ganlikun 0:13413ea9a877 1570
ganlikun 0:13413ea9a877 1571 /**
ganlikun 0:13413ea9a877 1572 * @brief Return the ETH HAL state
ganlikun 0:13413ea9a877 1573 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1574 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1575 * @retval HAL state
ganlikun 0:13413ea9a877 1576 */
ganlikun 0:13413ea9a877 1577 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1578 {
ganlikun 0:13413ea9a877 1579 /* Return ETH state */
ganlikun 0:13413ea9a877 1580 return heth->State;
ganlikun 0:13413ea9a877 1581 }
ganlikun 0:13413ea9a877 1582
ganlikun 0:13413ea9a877 1583 /**
ganlikun 0:13413ea9a877 1584 * @}
ganlikun 0:13413ea9a877 1585 */
ganlikun 0:13413ea9a877 1586
ganlikun 0:13413ea9a877 1587 /**
ganlikun 0:13413ea9a877 1588 * @}
ganlikun 0:13413ea9a877 1589 */
ganlikun 0:13413ea9a877 1590
ganlikun 0:13413ea9a877 1591 /** @addtogroup ETH_Private_Functions
ganlikun 0:13413ea9a877 1592 * @{
ganlikun 0:13413ea9a877 1593 */
ganlikun 0:13413ea9a877 1594
ganlikun 0:13413ea9a877 1595 /**
ganlikun 0:13413ea9a877 1596 * @brief Configures Ethernet MAC and DMA with default parameters.
ganlikun 0:13413ea9a877 1597 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1598 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1599 * @param err: Ethernet Init error
ganlikun 0:13413ea9a877 1600 * @retval HAL status
ganlikun 0:13413ea9a877 1601 */
ganlikun 0:13413ea9a877 1602 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
ganlikun 0:13413ea9a877 1603 {
ganlikun 0:13413ea9a877 1604 ETH_MACInitTypeDef macinit;
ganlikun 0:13413ea9a877 1605 ETH_DMAInitTypeDef dmainit;
ganlikun 0:13413ea9a877 1606 uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1607
ganlikun 0:13413ea9a877 1608 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
ganlikun 0:13413ea9a877 1609 {
ganlikun 0:13413ea9a877 1610 /* Set Ethernet duplex mode to Full-duplex */
ganlikun 0:13413ea9a877 1611 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
ganlikun 0:13413ea9a877 1612
ganlikun 0:13413ea9a877 1613 /* Set Ethernet speed to 100M */
ganlikun 0:13413ea9a877 1614 (heth->Init).Speed = ETH_SPEED_100M;
ganlikun 0:13413ea9a877 1615 }
ganlikun 0:13413ea9a877 1616
ganlikun 0:13413ea9a877 1617 /* Ethernet MAC default initialization **************************************/
ganlikun 0:13413ea9a877 1618 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
ganlikun 0:13413ea9a877 1619 macinit.Jabber = ETH_JABBER_ENABLE;
ganlikun 0:13413ea9a877 1620 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
ganlikun 0:13413ea9a877 1621 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
ganlikun 0:13413ea9a877 1622 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
ganlikun 0:13413ea9a877 1623 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
ganlikun 0:13413ea9a877 1624 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
ganlikun 0:13413ea9a877 1625 {
ganlikun 0:13413ea9a877 1626 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
ganlikun 0:13413ea9a877 1627 }
ganlikun 0:13413ea9a877 1628 else
ganlikun 0:13413ea9a877 1629 {
ganlikun 0:13413ea9a877 1630 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
ganlikun 0:13413ea9a877 1631 }
ganlikun 0:13413ea9a877 1632 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
ganlikun 0:13413ea9a877 1633 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
ganlikun 0:13413ea9a877 1634 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
ganlikun 0:13413ea9a877 1635 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
ganlikun 0:13413ea9a877 1636 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
ganlikun 0:13413ea9a877 1637 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
ganlikun 0:13413ea9a877 1638 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
ganlikun 0:13413ea9a877 1639 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
ganlikun 0:13413ea9a877 1640 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
ganlikun 0:13413ea9a877 1641 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
ganlikun 0:13413ea9a877 1642 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
ganlikun 0:13413ea9a877 1643 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
ganlikun 0:13413ea9a877 1644 macinit.HashTableHigh = 0x0U;
ganlikun 0:13413ea9a877 1645 macinit.HashTableLow = 0x0U;
ganlikun 0:13413ea9a877 1646 macinit.PauseTime = 0x0U;
ganlikun 0:13413ea9a877 1647 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
ganlikun 0:13413ea9a877 1648 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
ganlikun 0:13413ea9a877 1649 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
ganlikun 0:13413ea9a877 1650 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
ganlikun 0:13413ea9a877 1651 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
ganlikun 0:13413ea9a877 1652 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
ganlikun 0:13413ea9a877 1653 macinit.VLANTagIdentifier = 0x0U;
ganlikun 0:13413ea9a877 1654
ganlikun 0:13413ea9a877 1655 /*------------------------ ETHERNET MACCR Configuration --------------------*/
ganlikun 0:13413ea9a877 1656 /* Get the ETHERNET MACCR value */
ganlikun 0:13413ea9a877 1657 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1658 /* Clear WD, PCE, PS, TE and RE bits */
ganlikun 0:13413ea9a877 1659 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
ganlikun 0:13413ea9a877 1660 /* Set the WD bit according to ETH Watchdog value */
ganlikun 0:13413ea9a877 1661 /* Set the JD: bit according to ETH Jabber value */
ganlikun 0:13413ea9a877 1662 /* Set the IFG bit according to ETH InterFrameGap value */
ganlikun 0:13413ea9a877 1663 /* Set the DCRS bit according to ETH CarrierSense value */
ganlikun 0:13413ea9a877 1664 /* Set the FES bit according to ETH Speed value */
ganlikun 0:13413ea9a877 1665 /* Set the DO bit according to ETH ReceiveOwn value */
ganlikun 0:13413ea9a877 1666 /* Set the LM bit according to ETH LoopbackMode value */
ganlikun 0:13413ea9a877 1667 /* Set the DM bit according to ETH Mode value */
ganlikun 0:13413ea9a877 1668 /* Set the IPCO bit according to ETH ChecksumOffload value */
ganlikun 0:13413ea9a877 1669 /* Set the DR bit according to ETH RetryTransmission value */
ganlikun 0:13413ea9a877 1670 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
ganlikun 0:13413ea9a877 1671 /* Set the BL bit according to ETH BackOffLimit value */
ganlikun 0:13413ea9a877 1672 /* Set the DC bit according to ETH DeferralCheck value */
ganlikun 0:13413ea9a877 1673 tmpreg1 |= (uint32_t)(macinit.Watchdog |
ganlikun 0:13413ea9a877 1674 macinit.Jabber |
ganlikun 0:13413ea9a877 1675 macinit.InterFrameGap |
ganlikun 0:13413ea9a877 1676 macinit.CarrierSense |
ganlikun 0:13413ea9a877 1677 (heth->Init).Speed |
ganlikun 0:13413ea9a877 1678 macinit.ReceiveOwn |
ganlikun 0:13413ea9a877 1679 macinit.LoopbackMode |
ganlikun 0:13413ea9a877 1680 (heth->Init).DuplexMode |
ganlikun 0:13413ea9a877 1681 macinit.ChecksumOffload |
ganlikun 0:13413ea9a877 1682 macinit.RetryTransmission |
ganlikun 0:13413ea9a877 1683 macinit.AutomaticPadCRCStrip |
ganlikun 0:13413ea9a877 1684 macinit.BackOffLimit |
ganlikun 0:13413ea9a877 1685 macinit.DeferralCheck);
ganlikun 0:13413ea9a877 1686
ganlikun 0:13413ea9a877 1687 /* Write to ETHERNET MACCR */
ganlikun 0:13413ea9a877 1688 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 1689
ganlikun 0:13413ea9a877 1690 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1691 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1692 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1693 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1694 (heth->Instance)->MACCR = tmpreg1;
ganlikun 0:13413ea9a877 1695
ganlikun 0:13413ea9a877 1696 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
ganlikun 0:13413ea9a877 1697 /* Set the RA bit according to ETH ReceiveAll value */
ganlikun 0:13413ea9a877 1698 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
ganlikun 0:13413ea9a877 1699 /* Set the PCF bit according to ETH PassControlFrames value */
ganlikun 0:13413ea9a877 1700 /* Set the DBF bit according to ETH BroadcastFramesReception value */
ganlikun 0:13413ea9a877 1701 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
ganlikun 0:13413ea9a877 1702 /* Set the PR bit according to ETH PromiscuousMode value */
ganlikun 0:13413ea9a877 1703 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
ganlikun 0:13413ea9a877 1704 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
ganlikun 0:13413ea9a877 1705 /* Write to ETHERNET MACFFR */
ganlikun 0:13413ea9a877 1706 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
ganlikun 0:13413ea9a877 1707 macinit.SourceAddrFilter |
ganlikun 0:13413ea9a877 1708 macinit.PassControlFrames |
ganlikun 0:13413ea9a877 1709 macinit.BroadcastFramesReception |
ganlikun 0:13413ea9a877 1710 macinit.DestinationAddrFilter |
ganlikun 0:13413ea9a877 1711 macinit.PromiscuousMode |
ganlikun 0:13413ea9a877 1712 macinit.MulticastFramesFilter |
ganlikun 0:13413ea9a877 1713 macinit.UnicastFramesFilter);
ganlikun 0:13413ea9a877 1714
ganlikun 0:13413ea9a877 1715 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1716 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1717 tmpreg1 = (heth->Instance)->MACFFR;
ganlikun 0:13413ea9a877 1718 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1719 (heth->Instance)->MACFFR = tmpreg1;
ganlikun 0:13413ea9a877 1720
ganlikun 0:13413ea9a877 1721 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
ganlikun 0:13413ea9a877 1722 /* Write to ETHERNET MACHTHR */
ganlikun 0:13413ea9a877 1723 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
ganlikun 0:13413ea9a877 1724
ganlikun 0:13413ea9a877 1725 /* Write to ETHERNET MACHTLR */
ganlikun 0:13413ea9a877 1726 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
ganlikun 0:13413ea9a877 1727 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
ganlikun 0:13413ea9a877 1728
ganlikun 0:13413ea9a877 1729 /* Get the ETHERNET MACFCR value */
ganlikun 0:13413ea9a877 1730 tmpreg1 = (heth->Instance)->MACFCR;
ganlikun 0:13413ea9a877 1731 /* Clear xx bits */
ganlikun 0:13413ea9a877 1732 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
ganlikun 0:13413ea9a877 1733
ganlikun 0:13413ea9a877 1734 /* Set the PT bit according to ETH PauseTime value */
ganlikun 0:13413ea9a877 1735 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
ganlikun 0:13413ea9a877 1736 /* Set the PLT bit according to ETH PauseLowThreshold value */
ganlikun 0:13413ea9a877 1737 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
ganlikun 0:13413ea9a877 1738 /* Set the RFE bit according to ETH ReceiveFlowControl value */
ganlikun 0:13413ea9a877 1739 /* Set the TFE bit according to ETH TransmitFlowControl value */
ganlikun 0:13413ea9a877 1740 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
ganlikun 0:13413ea9a877 1741 macinit.ZeroQuantaPause |
ganlikun 0:13413ea9a877 1742 macinit.PauseLowThreshold |
ganlikun 0:13413ea9a877 1743 macinit.UnicastPauseFrameDetect |
ganlikun 0:13413ea9a877 1744 macinit.ReceiveFlowControl |
ganlikun 0:13413ea9a877 1745 macinit.TransmitFlowControl);
ganlikun 0:13413ea9a877 1746
ganlikun 0:13413ea9a877 1747 /* Write to ETHERNET MACFCR */
ganlikun 0:13413ea9a877 1748 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 1749
ganlikun 0:13413ea9a877 1750 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1751 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1752 tmpreg1 = (heth->Instance)->MACFCR;
ganlikun 0:13413ea9a877 1753 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1754 (heth->Instance)->MACFCR = tmpreg1;
ganlikun 0:13413ea9a877 1755
ganlikun 0:13413ea9a877 1756 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
ganlikun 0:13413ea9a877 1757 /* Set the ETV bit according to ETH VLANTagComparison value */
ganlikun 0:13413ea9a877 1758 /* Set the VL bit according to ETH VLANTagIdentifier value */
ganlikun 0:13413ea9a877 1759 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
ganlikun 0:13413ea9a877 1760 macinit.VLANTagIdentifier);
ganlikun 0:13413ea9a877 1761
ganlikun 0:13413ea9a877 1762 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1763 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1764 tmpreg1 = (heth->Instance)->MACVLANTR;
ganlikun 0:13413ea9a877 1765 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1766 (heth->Instance)->MACVLANTR = tmpreg1;
ganlikun 0:13413ea9a877 1767
ganlikun 0:13413ea9a877 1768 /* Ethernet DMA default initialization ************************************/
ganlikun 0:13413ea9a877 1769 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
ganlikun 0:13413ea9a877 1770 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
ganlikun 0:13413ea9a877 1771 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
ganlikun 0:13413ea9a877 1772 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
ganlikun 0:13413ea9a877 1773 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
ganlikun 0:13413ea9a877 1774 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
ganlikun 0:13413ea9a877 1775 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
ganlikun 0:13413ea9a877 1776 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
ganlikun 0:13413ea9a877 1777 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
ganlikun 0:13413ea9a877 1778 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
ganlikun 0:13413ea9a877 1779 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
ganlikun 0:13413ea9a877 1780 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
ganlikun 0:13413ea9a877 1781 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
ganlikun 0:13413ea9a877 1782 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
ganlikun 0:13413ea9a877 1783 dmainit.DescriptorSkipLength = 0x0U;
ganlikun 0:13413ea9a877 1784 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
ganlikun 0:13413ea9a877 1785
ganlikun 0:13413ea9a877 1786 /* Get the ETHERNET DMAOMR value */
ganlikun 0:13413ea9a877 1787 tmpreg1 = (heth->Instance)->DMAOMR;
ganlikun 0:13413ea9a877 1788 /* Clear xx bits */
ganlikun 0:13413ea9a877 1789 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
ganlikun 0:13413ea9a877 1790
ganlikun 0:13413ea9a877 1791 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
ganlikun 0:13413ea9a877 1792 /* Set the RSF bit according to ETH ReceiveStoreForward value */
ganlikun 0:13413ea9a877 1793 /* Set the DFF bit according to ETH FlushReceivedFrame value */
ganlikun 0:13413ea9a877 1794 /* Set the TSF bit according to ETH TransmitStoreForward value */
ganlikun 0:13413ea9a877 1795 /* Set the TTC bit according to ETH TransmitThresholdControl value */
ganlikun 0:13413ea9a877 1796 /* Set the FEF bit according to ETH ForwardErrorFrames value */
ganlikun 0:13413ea9a877 1797 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
ganlikun 0:13413ea9a877 1798 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
ganlikun 0:13413ea9a877 1799 /* Set the OSF bit according to ETH SecondFrameOperate value */
ganlikun 0:13413ea9a877 1800 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
ganlikun 0:13413ea9a877 1801 dmainit.ReceiveStoreForward |
ganlikun 0:13413ea9a877 1802 dmainit.FlushReceivedFrame |
ganlikun 0:13413ea9a877 1803 dmainit.TransmitStoreForward |
ganlikun 0:13413ea9a877 1804 dmainit.TransmitThresholdControl |
ganlikun 0:13413ea9a877 1805 dmainit.ForwardErrorFrames |
ganlikun 0:13413ea9a877 1806 dmainit.ForwardUndersizedGoodFrames |
ganlikun 0:13413ea9a877 1807 dmainit.ReceiveThresholdControl |
ganlikun 0:13413ea9a877 1808 dmainit.SecondFrameOperate);
ganlikun 0:13413ea9a877 1809
ganlikun 0:13413ea9a877 1810 /* Write to ETHERNET DMAOMR */
ganlikun 0:13413ea9a877 1811 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
ganlikun 0:13413ea9a877 1812
ganlikun 0:13413ea9a877 1813 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1814 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1815 tmpreg1 = (heth->Instance)->DMAOMR;
ganlikun 0:13413ea9a877 1816 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1817 (heth->Instance)->DMAOMR = tmpreg1;
ganlikun 0:13413ea9a877 1818
ganlikun 0:13413ea9a877 1819 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
ganlikun 0:13413ea9a877 1820 /* Set the AAL bit according to ETH AddressAlignedBeats value */
ganlikun 0:13413ea9a877 1821 /* Set the FB bit according to ETH FixedBurst value */
ganlikun 0:13413ea9a877 1822 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
ganlikun 0:13413ea9a877 1823 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
ganlikun 0:13413ea9a877 1824 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
ganlikun 0:13413ea9a877 1825 /* Set the DSL bit according to ETH DesciptorSkipLength value */
ganlikun 0:13413ea9a877 1826 /* Set the PR and DA bits according to ETH DMAArbitration value */
ganlikun 0:13413ea9a877 1827 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
ganlikun 0:13413ea9a877 1828 dmainit.FixedBurst |
ganlikun 0:13413ea9a877 1829 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
ganlikun 0:13413ea9a877 1830 dmainit.TxDMABurstLength |
ganlikun 0:13413ea9a877 1831 dmainit.EnhancedDescriptorFormat |
ganlikun 0:13413ea9a877 1832 (dmainit.DescriptorSkipLength << 2U) |
ganlikun 0:13413ea9a877 1833 dmainit.DMAArbitration |
ganlikun 0:13413ea9a877 1834 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
ganlikun 0:13413ea9a877 1835
ganlikun 0:13413ea9a877 1836 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1837 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1838 tmpreg1 = (heth->Instance)->DMABMR;
ganlikun 0:13413ea9a877 1839 HAL_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1840 (heth->Instance)->DMABMR = tmpreg1;
ganlikun 0:13413ea9a877 1841
ganlikun 0:13413ea9a877 1842 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
ganlikun 0:13413ea9a877 1843 {
ganlikun 0:13413ea9a877 1844 /* Enable the Ethernet Rx Interrupt */
ganlikun 0:13413ea9a877 1845 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
ganlikun 0:13413ea9a877 1846 }
ganlikun 0:13413ea9a877 1847
ganlikun 0:13413ea9a877 1848 /* Initialize MAC address in ethernet MAC */
ganlikun 0:13413ea9a877 1849 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
ganlikun 0:13413ea9a877 1850 }
ganlikun 0:13413ea9a877 1851
ganlikun 0:13413ea9a877 1852 /**
ganlikun 0:13413ea9a877 1853 * @brief Configures the selected MAC address.
ganlikun 0:13413ea9a877 1854 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1855 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1856 * @param MacAddr: The MAC address to configure
ganlikun 0:13413ea9a877 1857 * This parameter can be one of the following values:
ganlikun 0:13413ea9a877 1858 * @arg ETH_MAC_Address0: MAC Address0
ganlikun 0:13413ea9a877 1859 * @arg ETH_MAC_Address1: MAC Address1
ganlikun 0:13413ea9a877 1860 * @arg ETH_MAC_Address2: MAC Address2
ganlikun 0:13413ea9a877 1861 * @arg ETH_MAC_Address3: MAC Address3
ganlikun 0:13413ea9a877 1862 * @param Addr: Pointer to MAC address buffer data (6 bytes)
ganlikun 0:13413ea9a877 1863 * @retval HAL status
ganlikun 0:13413ea9a877 1864 */
ganlikun 0:13413ea9a877 1865 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
ganlikun 0:13413ea9a877 1866 {
ganlikun 0:13413ea9a877 1867 uint32_t tmpreg1;
ganlikun 0:13413ea9a877 1868
ganlikun 0:13413ea9a877 1869 /* Prevent unused argument(s) compilation warning */
ganlikun 0:13413ea9a877 1870 UNUSED(heth);
ganlikun 0:13413ea9a877 1871
ganlikun 0:13413ea9a877 1872 /* Check the parameters */
ganlikun 0:13413ea9a877 1873 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
ganlikun 0:13413ea9a877 1874
ganlikun 0:13413ea9a877 1875 /* Calculate the selected MAC address high register */
ganlikun 0:13413ea9a877 1876 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
ganlikun 0:13413ea9a877 1877 /* Load the selected MAC address high register */
ganlikun 0:13413ea9a877 1878 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
ganlikun 0:13413ea9a877 1879 /* Calculate the selected MAC address low register */
ganlikun 0:13413ea9a877 1880 tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
ganlikun 0:13413ea9a877 1881
ganlikun 0:13413ea9a877 1882 /* Load the selected MAC address low register */
ganlikun 0:13413ea9a877 1883 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
ganlikun 0:13413ea9a877 1884 }
ganlikun 0:13413ea9a877 1885
ganlikun 0:13413ea9a877 1886 /**
ganlikun 0:13413ea9a877 1887 * @brief Enables the MAC transmission.
ganlikun 0:13413ea9a877 1888 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1889 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1890 * @retval None
ganlikun 0:13413ea9a877 1891 */
ganlikun 0:13413ea9a877 1892 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1893 {
ganlikun 0:13413ea9a877 1894 __IO uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1895
ganlikun 0:13413ea9a877 1896 /* Enable the MAC transmission */
ganlikun 0:13413ea9a877 1897 (heth->Instance)->MACCR |= ETH_MACCR_TE;
ganlikun 0:13413ea9a877 1898
ganlikun 0:13413ea9a877 1899 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1900 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1901 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1902 ETH_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1903 (heth->Instance)->MACCR = tmpreg1;
ganlikun 0:13413ea9a877 1904 }
ganlikun 0:13413ea9a877 1905
ganlikun 0:13413ea9a877 1906 /**
ganlikun 0:13413ea9a877 1907 * @brief Disables the MAC transmission.
ganlikun 0:13413ea9a877 1908 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1909 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1910 * @retval None
ganlikun 0:13413ea9a877 1911 */
ganlikun 0:13413ea9a877 1912 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1913 {
ganlikun 0:13413ea9a877 1914 __IO uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1915
ganlikun 0:13413ea9a877 1916 /* Disable the MAC transmission */
ganlikun 0:13413ea9a877 1917 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
ganlikun 0:13413ea9a877 1918
ganlikun 0:13413ea9a877 1919 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1920 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1921 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1922 ETH_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1923 (heth->Instance)->MACCR = tmpreg1;
ganlikun 0:13413ea9a877 1924 }
ganlikun 0:13413ea9a877 1925
ganlikun 0:13413ea9a877 1926 /**
ganlikun 0:13413ea9a877 1927 * @brief Enables the MAC reception.
ganlikun 0:13413ea9a877 1928 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1929 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1930 * @retval None
ganlikun 0:13413ea9a877 1931 */
ganlikun 0:13413ea9a877 1932 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1933 {
ganlikun 0:13413ea9a877 1934 __IO uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1935
ganlikun 0:13413ea9a877 1936 /* Enable the MAC reception */
ganlikun 0:13413ea9a877 1937 (heth->Instance)->MACCR |= ETH_MACCR_RE;
ganlikun 0:13413ea9a877 1938
ganlikun 0:13413ea9a877 1939 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1940 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1941 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1942 ETH_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1943 (heth->Instance)->MACCR = tmpreg1;
ganlikun 0:13413ea9a877 1944 }
ganlikun 0:13413ea9a877 1945
ganlikun 0:13413ea9a877 1946 /**
ganlikun 0:13413ea9a877 1947 * @brief Disables the MAC reception.
ganlikun 0:13413ea9a877 1948 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1949 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1950 * @retval None
ganlikun 0:13413ea9a877 1951 */
ganlikun 0:13413ea9a877 1952 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1953 {
ganlikun 0:13413ea9a877 1954 __IO uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 1955
ganlikun 0:13413ea9a877 1956 /* Disable the MAC reception */
ganlikun 0:13413ea9a877 1957 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
ganlikun 0:13413ea9a877 1958
ganlikun 0:13413ea9a877 1959 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 1960 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 1961 tmpreg1 = (heth->Instance)->MACCR;
ganlikun 0:13413ea9a877 1962 ETH_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 1963 (heth->Instance)->MACCR = tmpreg1;
ganlikun 0:13413ea9a877 1964 }
ganlikun 0:13413ea9a877 1965
ganlikun 0:13413ea9a877 1966 /**
ganlikun 0:13413ea9a877 1967 * @brief Enables the DMA transmission.
ganlikun 0:13413ea9a877 1968 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1969 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1970 * @retval None
ganlikun 0:13413ea9a877 1971 */
ganlikun 0:13413ea9a877 1972 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1973 {
ganlikun 0:13413ea9a877 1974 /* Enable the DMA transmission */
ganlikun 0:13413ea9a877 1975 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
ganlikun 0:13413ea9a877 1976 }
ganlikun 0:13413ea9a877 1977
ganlikun 0:13413ea9a877 1978 /**
ganlikun 0:13413ea9a877 1979 * @brief Disables the DMA transmission.
ganlikun 0:13413ea9a877 1980 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1981 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1982 * @retval None
ganlikun 0:13413ea9a877 1983 */
ganlikun 0:13413ea9a877 1984 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1985 {
ganlikun 0:13413ea9a877 1986 /* Disable the DMA transmission */
ganlikun 0:13413ea9a877 1987 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
ganlikun 0:13413ea9a877 1988 }
ganlikun 0:13413ea9a877 1989
ganlikun 0:13413ea9a877 1990 /**
ganlikun 0:13413ea9a877 1991 * @brief Enables the DMA reception.
ganlikun 0:13413ea9a877 1992 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 1993 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 1994 * @retval None
ganlikun 0:13413ea9a877 1995 */
ganlikun 0:13413ea9a877 1996 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 1997 {
ganlikun 0:13413ea9a877 1998 /* Enable the DMA reception */
ganlikun 0:13413ea9a877 1999 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
ganlikun 0:13413ea9a877 2000 }
ganlikun 0:13413ea9a877 2001
ganlikun 0:13413ea9a877 2002 /**
ganlikun 0:13413ea9a877 2003 * @brief Disables the DMA reception.
ganlikun 0:13413ea9a877 2004 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 2005 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 2006 * @retval None
ganlikun 0:13413ea9a877 2007 */
ganlikun 0:13413ea9a877 2008 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 2009 {
ganlikun 0:13413ea9a877 2010 /* Disable the DMA reception */
ganlikun 0:13413ea9a877 2011 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
ganlikun 0:13413ea9a877 2012 }
ganlikun 0:13413ea9a877 2013
ganlikun 0:13413ea9a877 2014 /**
ganlikun 0:13413ea9a877 2015 * @brief Clears the ETHERNET transmit FIFO.
ganlikun 0:13413ea9a877 2016 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
ganlikun 0:13413ea9a877 2017 * the configuration information for ETHERNET module
ganlikun 0:13413ea9a877 2018 * @retval None
ganlikun 0:13413ea9a877 2019 */
ganlikun 0:13413ea9a877 2020 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
ganlikun 0:13413ea9a877 2021 {
ganlikun 0:13413ea9a877 2022 __IO uint32_t tmpreg1 = 0U;
ganlikun 0:13413ea9a877 2023
ganlikun 0:13413ea9a877 2024 /* Set the Flush Transmit FIFO bit */
ganlikun 0:13413ea9a877 2025 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
ganlikun 0:13413ea9a877 2026
ganlikun 0:13413ea9a877 2027 /* Wait until the write operation will be taken into account:
ganlikun 0:13413ea9a877 2028 at least four TX_CLK/RX_CLK clock cycles */
ganlikun 0:13413ea9a877 2029 tmpreg1 = (heth->Instance)->DMAOMR;
ganlikun 0:13413ea9a877 2030 ETH_Delay(ETH_REG_WRITE_DELAY);
ganlikun 0:13413ea9a877 2031 (heth->Instance)->DMAOMR = tmpreg1;
ganlikun 0:13413ea9a877 2032 }
ganlikun 0:13413ea9a877 2033
ganlikun 0:13413ea9a877 2034 /**
ganlikun 0:13413ea9a877 2035 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
ganlikun 0:13413ea9a877 2036 * @param mdelay: specifies the delay time length, in milliseconds.
ganlikun 0:13413ea9a877 2037 * @retval None
ganlikun 0:13413ea9a877 2038 */
ganlikun 0:13413ea9a877 2039 static void ETH_Delay(uint32_t mdelay)
ganlikun 0:13413ea9a877 2040 {
ganlikun 0:13413ea9a877 2041 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
ganlikun 0:13413ea9a877 2042 do
ganlikun 0:13413ea9a877 2043 {
ganlikun 0:13413ea9a877 2044 __NOP();
ganlikun 0:13413ea9a877 2045 }
ganlikun 0:13413ea9a877 2046 while (Delay --);
ganlikun 0:13413ea9a877 2047 }
ganlikun 0:13413ea9a877 2048
ganlikun 0:13413ea9a877 2049 /**
ganlikun 0:13413ea9a877 2050 * @}
ganlikun 0:13413ea9a877 2051 */
ganlikun 0:13413ea9a877 2052
ganlikun 0:13413ea9a877 2053 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
ganlikun 0:13413ea9a877 2054 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
ganlikun 0:13413ea9a877 2055 #endif /* HAL_ETH_MODULE_ENABLED */
ganlikun 0:13413ea9a877 2056 /**
ganlikun 0:13413ea9a877 2057 * @}
ganlikun 0:13413ea9a877 2058 */
ganlikun 0:13413ea9a877 2059
ganlikun 0:13413ea9a877 2060 /**
ganlikun 0:13413ea9a877 2061 * @}
ganlikun 0:13413ea9a877 2062 */
ganlikun 0:13413ea9a877 2063
ganlikun 0:13413ea9a877 2064 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 2065