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cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

Who changed what in which revision?

User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/************************************************************************//
ganlikun	0:13413ea9a877	2	* @file cmsis_armclang.h
ganlikun	0:13413ea9a877	3	* @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
ganlikun	0:13413ea9a877	4	* @version V5.0.3
ganlikun	0:13413ea9a877	5	* @date 27. March 2017
ganlikun	0:13413ea9a877	6	******************************************************************************/
ganlikun	0:13413ea9a877	7	/*
ganlikun	0:13413ea9a877	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
ganlikun	0:13413ea9a877	9	*
ganlikun	0:13413ea9a877	10	* SPDX-License-Identifier: Apache-2.0
ganlikun	0:13413ea9a877	11	*
ganlikun	0:13413ea9a877	12	* Licensed under the Apache License, Version 2.0 (the License); you may
ganlikun	0:13413ea9a877	13	* not use this file except in compliance with the License.
ganlikun	0:13413ea9a877	14	* You may obtain a copy of the License at
ganlikun	0:13413ea9a877	15	*
ganlikun	0:13413ea9a877	16	* www.apache.org/licenses/LICENSE-2.0
ganlikun	0:13413ea9a877	17	*
ganlikun	0:13413ea9a877	18	* Unless required by applicable law or agreed to in writing, software
ganlikun	0:13413ea9a877	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
ganlikun	0:13413ea9a877	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ganlikun	0:13413ea9a877	21	* See the License for the specific language governing permissions and
ganlikun	0:13413ea9a877	22	* limitations under the License.
ganlikun	0:13413ea9a877	23	*/
ganlikun	0:13413ea9a877	24
ganlikun	0:13413ea9a877	25	//lint -esym(9058, IRQn) disable MISRA 2012 Rule 2.4 for IRQn
ganlikun	0:13413ea9a877	26
ganlikun	0:13413ea9a877	27	#ifndef __CMSIS_ARMCLANG_H
ganlikun	0:13413ea9a877	28	#define __CMSIS_ARMCLANG_H
ganlikun	0:13413ea9a877	29
ganlikun	0:13413ea9a877	30	#ifndef __ARM_COMPAT_H
ganlikun	0:13413ea9a877	31	#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
ganlikun	0:13413ea9a877	32	#endif
ganlikun	0:13413ea9a877	33
ganlikun	0:13413ea9a877	34	/* CMSIS compiler specific defines */
ganlikun	0:13413ea9a877	35	#ifndef __ASM
ganlikun	0:13413ea9a877	36	#define __ASM __asm
ganlikun	0:13413ea9a877	37	#endif
ganlikun	0:13413ea9a877	38	#ifndef __INLINE
ganlikun	0:13413ea9a877	39	#define __INLINE __inline
ganlikun	0:13413ea9a877	40	#endif
ganlikun	0:13413ea9a877	41	#ifndef __STATIC_INLINE
ganlikun	0:13413ea9a877	42	#define __STATIC_INLINE static __inline
ganlikun	0:13413ea9a877	43	#endif
ganlikun	0:13413ea9a877	44	#ifndef __NO_RETURN
ganlikun	0:13413ea9a877	45	#define __NO_RETURN __attribute__((noreturn))
ganlikun	0:13413ea9a877	46	#endif
ganlikun	0:13413ea9a877	47	#ifndef __USED
ganlikun	0:13413ea9a877	48	#define __USED __attribute__((used))
ganlikun	0:13413ea9a877	49	#endif
ganlikun	0:13413ea9a877	50	#ifndef __WEAK
ganlikun	0:13413ea9a877	51	#define __WEAK __attribute__((weak))
ganlikun	0:13413ea9a877	52	#endif
ganlikun	0:13413ea9a877	53	#ifndef __PACKED
ganlikun	0:13413ea9a877	54	#define __PACKED __attribute__((packed, aligned(1)))
ganlikun	0:13413ea9a877	55	#endif
ganlikun	0:13413ea9a877	56	#ifndef __PACKED_STRUCT
ganlikun	0:13413ea9a877	57	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
ganlikun	0:13413ea9a877	58	#endif
ganlikun	0:13413ea9a877	59	#ifndef __UNALIGNED_UINT32 /* deprecated */
ganlikun	0:13413ea9a877	60	#pragma clang diagnostic push
ganlikun	0:13413ea9a877	61	#pragma clang diagnostic ignored "-Wpacked"
ganlikun	0:13413ea9a877	62	//lint -esym(9058, T_UINT32) disable MISRA 2012 Rule 2.4 for T_UINT32
ganlikun	0:13413ea9a877	63	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
ganlikun	0:13413ea9a877	64	#pragma clang diagnostic pop
ganlikun	0:13413ea9a877	65	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
ganlikun	0:13413ea9a877	66	#endif
ganlikun	0:13413ea9a877	67	#ifndef __UNALIGNED_UINT16_WRITE
ganlikun	0:13413ea9a877	68	#pragma clang diagnostic push
ganlikun	0:13413ea9a877	69	#pragma clang diagnostic ignored "-Wpacked"
ganlikun	0:13413ea9a877	70	//lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
ganlikun	0:13413ea9a877	71	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
ganlikun	0:13413ea9a877	72	#pragma clang diagnostic pop
ganlikun	0:13413ea9a877	73	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
ganlikun	0:13413ea9a877	74	#endif
ganlikun	0:13413ea9a877	75	#ifndef __UNALIGNED_UINT16_READ
ganlikun	0:13413ea9a877	76	#pragma clang diagnostic push
ganlikun	0:13413ea9a877	77	#pragma clang diagnostic ignored "-Wpacked"
ganlikun	0:13413ea9a877	78	//lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ
ganlikun	0:13413ea9a877	79	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
ganlikun	0:13413ea9a877	80	#pragma clang diagnostic pop
ganlikun	0:13413ea9a877	81	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
ganlikun	0:13413ea9a877	82	#endif
ganlikun	0:13413ea9a877	83	#ifndef __UNALIGNED_UINT32_WRITE
ganlikun	0:13413ea9a877	84	#pragma clang diagnostic push
ganlikun	0:13413ea9a877	85	#pragma clang diagnostic ignored "-Wpacked"
ganlikun	0:13413ea9a877	86	//lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
ganlikun	0:13413ea9a877	87	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
ganlikun	0:13413ea9a877	88	#pragma clang diagnostic pop
ganlikun	0:13413ea9a877	89	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
ganlikun	0:13413ea9a877	90	#endif
ganlikun	0:13413ea9a877	91	#ifndef __UNALIGNED_UINT32_READ
ganlikun	0:13413ea9a877	92	#pragma clang diagnostic push
ganlikun	0:13413ea9a877	93	#pragma clang diagnostic ignored "-Wpacked"
ganlikun	0:13413ea9a877	94	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
ganlikun	0:13413ea9a877	95	#pragma clang diagnostic pop
ganlikun	0:13413ea9a877	96	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
ganlikun	0:13413ea9a877	97	#endif
ganlikun	0:13413ea9a877	98	#ifndef __ALIGNED
ganlikun	0:13413ea9a877	99	#define __ALIGNED(x) __attribute__((aligned(x)))
ganlikun	0:13413ea9a877	100	#endif
ganlikun	0:13413ea9a877	101
ganlikun	0:13413ea9a877	102
ganlikun	0:13413ea9a877	103	/* ########################### Core Function Access ########################### */
ganlikun	0:13413ea9a877	104	/** \ingroup CMSIS_Core_FunctionInterface
ganlikun	0:13413ea9a877	105	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
ganlikun	0:13413ea9a877	106	@{
ganlikun	0:13413ea9a877	107	*/
ganlikun	0:13413ea9a877	108
ganlikun	0:13413ea9a877	109	/**
ganlikun	0:13413ea9a877	110	\brief Enable IRQ Interrupts
ganlikun	0:13413ea9a877	111	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
ganlikun	0:13413ea9a877	112	Can only be executed in Privileged modes.
ganlikun	0:13413ea9a877	113	*/
ganlikun	0:13413ea9a877	114	/* intrinsic void __enable_irq(); see arm_compat.h */
ganlikun	0:13413ea9a877	115
ganlikun	0:13413ea9a877	116
ganlikun	0:13413ea9a877	117	/**
ganlikun	0:13413ea9a877	118	\brief Disable IRQ Interrupts
ganlikun	0:13413ea9a877	119	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
ganlikun	0:13413ea9a877	120	Can only be executed in Privileged modes.
ganlikun	0:13413ea9a877	121	*/
ganlikun	0:13413ea9a877	122	/* intrinsic void __disable_irq(); see arm_compat.h */
ganlikun	0:13413ea9a877	123
ganlikun	0:13413ea9a877	124
ganlikun	0:13413ea9a877	125	/**
ganlikun	0:13413ea9a877	126	\brief Get Control Register
ganlikun	0:13413ea9a877	127	\details Returns the content of the Control Register.
ganlikun	0:13413ea9a877	128	\return Control Register value
ganlikun	0:13413ea9a877	129	*/
ganlikun	0:13413ea9a877	130	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
ganlikun	0:13413ea9a877	131	{
ganlikun	0:13413ea9a877	132	uint32_t result;
ganlikun	0:13413ea9a877	133
ganlikun	0:13413ea9a877	134	__ASM volatile ("MRS %0, control" : "=r" (result) );
ganlikun	0:13413ea9a877	135	return(result);
ganlikun	0:13413ea9a877	136	}
ganlikun	0:13413ea9a877	137
ganlikun	0:13413ea9a877	138
ganlikun	0:13413ea9a877	139	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	140	/**
ganlikun	0:13413ea9a877	141	\brief Get Control Register (non-secure)
ganlikun	0:13413ea9a877	142	\details Returns the content of the non-secure Control Register when in secure mode.
ganlikun	0:13413ea9a877	143	\return non-secure Control Register value
ganlikun	0:13413ea9a877	144	*/
ganlikun	0:13413ea9a877	145	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
ganlikun	0:13413ea9a877	146	{
ganlikun	0:13413ea9a877	147	uint32_t result;
ganlikun	0:13413ea9a877	148
ganlikun	0:13413ea9a877	149	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	150	return(result);
ganlikun	0:13413ea9a877	151	}
ganlikun	0:13413ea9a877	152	#endif
ganlikun	0:13413ea9a877	153
ganlikun	0:13413ea9a877	154
ganlikun	0:13413ea9a877	155	/**
ganlikun	0:13413ea9a877	156	\brief Set Control Register
ganlikun	0:13413ea9a877	157	\details Writes the given value to the Control Register.
ganlikun	0:13413ea9a877	158	\param [in] control Control Register value to set
ganlikun	0:13413ea9a877	159	*/
ganlikun	0:13413ea9a877	160	__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
ganlikun	0:13413ea9a877	161	{
ganlikun	0:13413ea9a877	162	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
ganlikun	0:13413ea9a877	163	}
ganlikun	0:13413ea9a877	164
ganlikun	0:13413ea9a877	165
ganlikun	0:13413ea9a877	166	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	167	/**
ganlikun	0:13413ea9a877	168	\brief Set Control Register (non-secure)
ganlikun	0:13413ea9a877	169	\details Writes the given value to the non-secure Control Register when in secure state.
ganlikun	0:13413ea9a877	170	\param [in] control Control Register value to set
ganlikun	0:13413ea9a877	171	*/
ganlikun	0:13413ea9a877	172	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
ganlikun	0:13413ea9a877	173	{
ganlikun	0:13413ea9a877	174	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
ganlikun	0:13413ea9a877	175	}
ganlikun	0:13413ea9a877	176	#endif
ganlikun	0:13413ea9a877	177
ganlikun	0:13413ea9a877	178
ganlikun	0:13413ea9a877	179	/**
ganlikun	0:13413ea9a877	180	\brief Get IPSR Register
ganlikun	0:13413ea9a877	181	\details Returns the content of the IPSR Register.
ganlikun	0:13413ea9a877	182	\return IPSR Register value
ganlikun	0:13413ea9a877	183	*/
ganlikun	0:13413ea9a877	184	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
ganlikun	0:13413ea9a877	185	{
ganlikun	0:13413ea9a877	186	uint32_t result;
ganlikun	0:13413ea9a877	187
ganlikun	0:13413ea9a877	188	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
ganlikun	0:13413ea9a877	189	return(result);
ganlikun	0:13413ea9a877	190	}
ganlikun	0:13413ea9a877	191
ganlikun	0:13413ea9a877	192
ganlikun	0:13413ea9a877	193	/**
ganlikun	0:13413ea9a877	194	\brief Get APSR Register
ganlikun	0:13413ea9a877	195	\details Returns the content of the APSR Register.
ganlikun	0:13413ea9a877	196	\return APSR Register value
ganlikun	0:13413ea9a877	197	*/
ganlikun	0:13413ea9a877	198	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
ganlikun	0:13413ea9a877	199	{
ganlikun	0:13413ea9a877	200	uint32_t result;
ganlikun	0:13413ea9a877	201
ganlikun	0:13413ea9a877	202	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
ganlikun	0:13413ea9a877	203	return(result);
ganlikun	0:13413ea9a877	204	}
ganlikun	0:13413ea9a877	205
ganlikun	0:13413ea9a877	206
ganlikun	0:13413ea9a877	207	/**
ganlikun	0:13413ea9a877	208	\brief Get xPSR Register
ganlikun	0:13413ea9a877	209	\details Returns the content of the xPSR Register.
ganlikun	0:13413ea9a877	210	\return xPSR Register value
ganlikun	0:13413ea9a877	211	*/
ganlikun	0:13413ea9a877	212	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
ganlikun	0:13413ea9a877	213	{
ganlikun	0:13413ea9a877	214	uint32_t result;
ganlikun	0:13413ea9a877	215
ganlikun	0:13413ea9a877	216	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
ganlikun	0:13413ea9a877	217	return(result);
ganlikun	0:13413ea9a877	218	}
ganlikun	0:13413ea9a877	219
ganlikun	0:13413ea9a877	220
ganlikun	0:13413ea9a877	221	/**
ganlikun	0:13413ea9a877	222	\brief Get Process Stack Pointer
ganlikun	0:13413ea9a877	223	\details Returns the current value of the Process Stack Pointer (PSP).
ganlikun	0:13413ea9a877	224	\return PSP Register value
ganlikun	0:13413ea9a877	225	*/
ganlikun	0:13413ea9a877	226	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
ganlikun	0:13413ea9a877	227	{
ganlikun	0:13413ea9a877	228	register uint32_t result;
ganlikun	0:13413ea9a877	229
ganlikun	0:13413ea9a877	230	__ASM volatile ("MRS %0, psp" : "=r" (result) );
ganlikun	0:13413ea9a877	231	return(result);
ganlikun	0:13413ea9a877	232	}
ganlikun	0:13413ea9a877	233
ganlikun	0:13413ea9a877	234
ganlikun	0:13413ea9a877	235	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	236	/**
ganlikun	0:13413ea9a877	237	\brief Get Process Stack Pointer (non-secure)
ganlikun	0:13413ea9a877	238	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
ganlikun	0:13413ea9a877	239	\return PSP Register value
ganlikun	0:13413ea9a877	240	*/
ganlikun	0:13413ea9a877	241	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
ganlikun	0:13413ea9a877	242	{
ganlikun	0:13413ea9a877	243	register uint32_t result;
ganlikun	0:13413ea9a877	244
ganlikun	0:13413ea9a877	245	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	246	return(result);
ganlikun	0:13413ea9a877	247	}
ganlikun	0:13413ea9a877	248	#endif
ganlikun	0:13413ea9a877	249
ganlikun	0:13413ea9a877	250
ganlikun	0:13413ea9a877	251	/**
ganlikun	0:13413ea9a877	252	\brief Set Process Stack Pointer
ganlikun	0:13413ea9a877	253	\details Assigns the given value to the Process Stack Pointer (PSP).
ganlikun	0:13413ea9a877	254	\param [in] topOfProcStack Process Stack Pointer value to set
ganlikun	0:13413ea9a877	255	*/
ganlikun	0:13413ea9a877	256	__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
ganlikun	0:13413ea9a877	257	{
ganlikun	0:13413ea9a877	258	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
ganlikun	0:13413ea9a877	259	}
ganlikun	0:13413ea9a877	260
ganlikun	0:13413ea9a877	261
ganlikun	0:13413ea9a877	262	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	263	/**
ganlikun	0:13413ea9a877	264	\brief Set Process Stack Pointer (non-secure)
ganlikun	0:13413ea9a877	265	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
ganlikun	0:13413ea9a877	266	\param [in] topOfProcStack Process Stack Pointer value to set
ganlikun	0:13413ea9a877	267	*/
ganlikun	0:13413ea9a877	268	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
ganlikun	0:13413ea9a877	269	{
ganlikun	0:13413ea9a877	270	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
ganlikun	0:13413ea9a877	271	}
ganlikun	0:13413ea9a877	272	#endif
ganlikun	0:13413ea9a877	273
ganlikun	0:13413ea9a877	274
ganlikun	0:13413ea9a877	275	/**
ganlikun	0:13413ea9a877	276	\brief Get Main Stack Pointer
ganlikun	0:13413ea9a877	277	\details Returns the current value of the Main Stack Pointer (MSP).
ganlikun	0:13413ea9a877	278	\return MSP Register value
ganlikun	0:13413ea9a877	279	*/
ganlikun	0:13413ea9a877	280	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
ganlikun	0:13413ea9a877	281	{
ganlikun	0:13413ea9a877	282	register uint32_t result;
ganlikun	0:13413ea9a877	283
ganlikun	0:13413ea9a877	284	__ASM volatile ("MRS %0, msp" : "=r" (result) );
ganlikun	0:13413ea9a877	285	return(result);
ganlikun	0:13413ea9a877	286	}
ganlikun	0:13413ea9a877	287
ganlikun	0:13413ea9a877	288
ganlikun	0:13413ea9a877	289	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	290	/**
ganlikun	0:13413ea9a877	291	\brief Get Main Stack Pointer (non-secure)
ganlikun	0:13413ea9a877	292	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
ganlikun	0:13413ea9a877	293	\return MSP Register value
ganlikun	0:13413ea9a877	294	*/
ganlikun	0:13413ea9a877	295	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
ganlikun	0:13413ea9a877	296	{
ganlikun	0:13413ea9a877	297	register uint32_t result;
ganlikun	0:13413ea9a877	298
ganlikun	0:13413ea9a877	299	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	300	return(result);
ganlikun	0:13413ea9a877	301	}
ganlikun	0:13413ea9a877	302	#endif
ganlikun	0:13413ea9a877	303
ganlikun	0:13413ea9a877	304
ganlikun	0:13413ea9a877	305	/**
ganlikun	0:13413ea9a877	306	\brief Set Main Stack Pointer
ganlikun	0:13413ea9a877	307	\details Assigns the given value to the Main Stack Pointer (MSP).
ganlikun	0:13413ea9a877	308	\param [in] topOfMainStack Main Stack Pointer value to set
ganlikun	0:13413ea9a877	309	*/
ganlikun	0:13413ea9a877	310	__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
ganlikun	0:13413ea9a877	311	{
ganlikun	0:13413ea9a877	312	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
ganlikun	0:13413ea9a877	313	}
ganlikun	0:13413ea9a877	314
ganlikun	0:13413ea9a877	315
ganlikun	0:13413ea9a877	316	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	317	/**
ganlikun	0:13413ea9a877	318	\brief Set Main Stack Pointer (non-secure)
ganlikun	0:13413ea9a877	319	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
ganlikun	0:13413ea9a877	320	\param [in] topOfMainStack Main Stack Pointer value to set
ganlikun	0:13413ea9a877	321	*/
ganlikun	0:13413ea9a877	322	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
ganlikun	0:13413ea9a877	323	{
ganlikun	0:13413ea9a877	324	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
ganlikun	0:13413ea9a877	325	}
ganlikun	0:13413ea9a877	326	#endif
ganlikun	0:13413ea9a877	327
ganlikun	0:13413ea9a877	328
ganlikun	0:13413ea9a877	329	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	330	/**
ganlikun	0:13413ea9a877	331	\brief Get Stack Pointer (non-secure)
ganlikun	0:13413ea9a877	332	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
ganlikun	0:13413ea9a877	333	\return SP Register value
ganlikun	0:13413ea9a877	334	*/
ganlikun	0:13413ea9a877	335	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
ganlikun	0:13413ea9a877	336	{
ganlikun	0:13413ea9a877	337	register uint32_t result;
ganlikun	0:13413ea9a877	338
ganlikun	0:13413ea9a877	339	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	340	return(result);
ganlikun	0:13413ea9a877	341	}
ganlikun	0:13413ea9a877	342
ganlikun	0:13413ea9a877	343
ganlikun	0:13413ea9a877	344	/**
ganlikun	0:13413ea9a877	345	\brief Set Stack Pointer (non-secure)
ganlikun	0:13413ea9a877	346	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
ganlikun	0:13413ea9a877	347	\param [in] topOfStack Stack Pointer value to set
ganlikun	0:13413ea9a877	348	*/
ganlikun	0:13413ea9a877	349	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
ganlikun	0:13413ea9a877	350	{
ganlikun	0:13413ea9a877	351	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
ganlikun	0:13413ea9a877	352	}
ganlikun	0:13413ea9a877	353	#endif
ganlikun	0:13413ea9a877	354
ganlikun	0:13413ea9a877	355
ganlikun	0:13413ea9a877	356	/**
ganlikun	0:13413ea9a877	357	\brief Get Priority Mask
ganlikun	0:13413ea9a877	358	\details Returns the current state of the priority mask bit from the Priority Mask Register.
ganlikun	0:13413ea9a877	359	\return Priority Mask value
ganlikun	0:13413ea9a877	360	*/
ganlikun	0:13413ea9a877	361	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
ganlikun	0:13413ea9a877	362	{
ganlikun	0:13413ea9a877	363	uint32_t result;
ganlikun	0:13413ea9a877	364
ganlikun	0:13413ea9a877	365	__ASM volatile ("MRS %0, primask" : "=r" (result) );
ganlikun	0:13413ea9a877	366	return(result);
ganlikun	0:13413ea9a877	367	}
ganlikun	0:13413ea9a877	368
ganlikun	0:13413ea9a877	369
ganlikun	0:13413ea9a877	370	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	371	/**
ganlikun	0:13413ea9a877	372	\brief Get Priority Mask (non-secure)
ganlikun	0:13413ea9a877	373	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
ganlikun	0:13413ea9a877	374	\return Priority Mask value
ganlikun	0:13413ea9a877	375	*/
ganlikun	0:13413ea9a877	376	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
ganlikun	0:13413ea9a877	377	{
ganlikun	0:13413ea9a877	378	uint32_t result;
ganlikun	0:13413ea9a877	379
ganlikun	0:13413ea9a877	380	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	381	return(result);
ganlikun	0:13413ea9a877	382	}
ganlikun	0:13413ea9a877	383	#endif
ganlikun	0:13413ea9a877	384
ganlikun	0:13413ea9a877	385
ganlikun	0:13413ea9a877	386	/**
ganlikun	0:13413ea9a877	387	\brief Set Priority Mask
ganlikun	0:13413ea9a877	388	\details Assigns the given value to the Priority Mask Register.
ganlikun	0:13413ea9a877	389	\param [in] priMask Priority Mask
ganlikun	0:13413ea9a877	390	*/
ganlikun	0:13413ea9a877	391	__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
ganlikun	0:13413ea9a877	392	{
ganlikun	0:13413ea9a877	393	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
ganlikun	0:13413ea9a877	394	}
ganlikun	0:13413ea9a877	395
ganlikun	0:13413ea9a877	396
ganlikun	0:13413ea9a877	397	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	398	/**
ganlikun	0:13413ea9a877	399	\brief Set Priority Mask (non-secure)
ganlikun	0:13413ea9a877	400	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
ganlikun	0:13413ea9a877	401	\param [in] priMask Priority Mask
ganlikun	0:13413ea9a877	402	*/
ganlikun	0:13413ea9a877	403	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
ganlikun	0:13413ea9a877	404	{
ganlikun	0:13413ea9a877	405	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
ganlikun	0:13413ea9a877	406	}
ganlikun	0:13413ea9a877	407	#endif
ganlikun	0:13413ea9a877	408
ganlikun	0:13413ea9a877	409
ganlikun	0:13413ea9a877	410	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
ganlikun	0:13413ea9a877	411	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	412	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	413	/**
ganlikun	0:13413ea9a877	414	\brief Enable FIQ
ganlikun	0:13413ea9a877	415	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
ganlikun	0:13413ea9a877	416	Can only be executed in Privileged modes.
ganlikun	0:13413ea9a877	417	*/
ganlikun	0:13413ea9a877	418	#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
ganlikun	0:13413ea9a877	419
ganlikun	0:13413ea9a877	420
ganlikun	0:13413ea9a877	421	/**
ganlikun	0:13413ea9a877	422	\brief Disable FIQ
ganlikun	0:13413ea9a877	423	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
ganlikun	0:13413ea9a877	424	Can only be executed in Privileged modes.
ganlikun	0:13413ea9a877	425	*/
ganlikun	0:13413ea9a877	426	#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
ganlikun	0:13413ea9a877	427
ganlikun	0:13413ea9a877	428
ganlikun	0:13413ea9a877	429	/**
ganlikun	0:13413ea9a877	430	\brief Get Base Priority
ganlikun	0:13413ea9a877	431	\details Returns the current value of the Base Priority register.
ganlikun	0:13413ea9a877	432	\return Base Priority register value
ganlikun	0:13413ea9a877	433	*/
ganlikun	0:13413ea9a877	434	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
ganlikun	0:13413ea9a877	435	{
ganlikun	0:13413ea9a877	436	uint32_t result;
ganlikun	0:13413ea9a877	437
ganlikun	0:13413ea9a877	438	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
ganlikun	0:13413ea9a877	439	return(result);
ganlikun	0:13413ea9a877	440	}
ganlikun	0:13413ea9a877	441
ganlikun	0:13413ea9a877	442
ganlikun	0:13413ea9a877	443	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	444	/**
ganlikun	0:13413ea9a877	445	\brief Get Base Priority (non-secure)
ganlikun	0:13413ea9a877	446	\details Returns the current value of the non-secure Base Priority register when in secure state.
ganlikun	0:13413ea9a877	447	\return Base Priority register value
ganlikun	0:13413ea9a877	448	*/
ganlikun	0:13413ea9a877	449	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
ganlikun	0:13413ea9a877	450	{
ganlikun	0:13413ea9a877	451	uint32_t result;
ganlikun	0:13413ea9a877	452
ganlikun	0:13413ea9a877	453	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	454	return(result);
ganlikun	0:13413ea9a877	455	}
ganlikun	0:13413ea9a877	456	#endif
ganlikun	0:13413ea9a877	457
ganlikun	0:13413ea9a877	458
ganlikun	0:13413ea9a877	459	/**
ganlikun	0:13413ea9a877	460	\brief Set Base Priority
ganlikun	0:13413ea9a877	461	\details Assigns the given value to the Base Priority register.
ganlikun	0:13413ea9a877	462	\param [in] basePri Base Priority value to set
ganlikun	0:13413ea9a877	463	*/
ganlikun	0:13413ea9a877	464	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
ganlikun	0:13413ea9a877	465	{
ganlikun	0:13413ea9a877	466	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
ganlikun	0:13413ea9a877	467	}
ganlikun	0:13413ea9a877	468
ganlikun	0:13413ea9a877	469
ganlikun	0:13413ea9a877	470	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	471	/**
ganlikun	0:13413ea9a877	472	\brief Set Base Priority (non-secure)
ganlikun	0:13413ea9a877	473	\details Assigns the given value to the non-secure Base Priority register when in secure state.
ganlikun	0:13413ea9a877	474	\param [in] basePri Base Priority value to set
ganlikun	0:13413ea9a877	475	*/
ganlikun	0:13413ea9a877	476	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
ganlikun	0:13413ea9a877	477	{
ganlikun	0:13413ea9a877	478	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
ganlikun	0:13413ea9a877	479	}
ganlikun	0:13413ea9a877	480	#endif
ganlikun	0:13413ea9a877	481
ganlikun	0:13413ea9a877	482
ganlikun	0:13413ea9a877	483	/**
ganlikun	0:13413ea9a877	484	\brief Set Base Priority with condition
ganlikun	0:13413ea9a877	485	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
ganlikun	0:13413ea9a877	486	or the new value increases the BASEPRI priority level.
ganlikun	0:13413ea9a877	487	\param [in] basePri Base Priority value to set
ganlikun	0:13413ea9a877	488	*/
ganlikun	0:13413ea9a877	489	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
ganlikun	0:13413ea9a877	490	{
ganlikun	0:13413ea9a877	491	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
ganlikun	0:13413ea9a877	492	}
ganlikun	0:13413ea9a877	493
ganlikun	0:13413ea9a877	494
ganlikun	0:13413ea9a877	495	/**
ganlikun	0:13413ea9a877	496	\brief Get Fault Mask
ganlikun	0:13413ea9a877	497	\details Returns the current value of the Fault Mask register.
ganlikun	0:13413ea9a877	498	\return Fault Mask register value
ganlikun	0:13413ea9a877	499	*/
ganlikun	0:13413ea9a877	500	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
ganlikun	0:13413ea9a877	501	{
ganlikun	0:13413ea9a877	502	uint32_t result;
ganlikun	0:13413ea9a877	503
ganlikun	0:13413ea9a877	504	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
ganlikun	0:13413ea9a877	505	return(result);
ganlikun	0:13413ea9a877	506	}
ganlikun	0:13413ea9a877	507
ganlikun	0:13413ea9a877	508
ganlikun	0:13413ea9a877	509	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	510	/**
ganlikun	0:13413ea9a877	511	\brief Get Fault Mask (non-secure)
ganlikun	0:13413ea9a877	512	\details Returns the current value of the non-secure Fault Mask register when in secure state.
ganlikun	0:13413ea9a877	513	\return Fault Mask register value
ganlikun	0:13413ea9a877	514	*/
ganlikun	0:13413ea9a877	515	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
ganlikun	0:13413ea9a877	516	{
ganlikun	0:13413ea9a877	517	uint32_t result;
ganlikun	0:13413ea9a877	518
ganlikun	0:13413ea9a877	519	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	520	return(result);
ganlikun	0:13413ea9a877	521	}
ganlikun	0:13413ea9a877	522	#endif
ganlikun	0:13413ea9a877	523
ganlikun	0:13413ea9a877	524
ganlikun	0:13413ea9a877	525	/**
ganlikun	0:13413ea9a877	526	\brief Set Fault Mask
ganlikun	0:13413ea9a877	527	\details Assigns the given value to the Fault Mask register.
ganlikun	0:13413ea9a877	528	\param [in] faultMask Fault Mask value to set
ganlikun	0:13413ea9a877	529	*/
ganlikun	0:13413ea9a877	530	__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
ganlikun	0:13413ea9a877	531	{
ganlikun	0:13413ea9a877	532	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
ganlikun	0:13413ea9a877	533	}
ganlikun	0:13413ea9a877	534
ganlikun	0:13413ea9a877	535
ganlikun	0:13413ea9a877	536	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ganlikun	0:13413ea9a877	537	/**
ganlikun	0:13413ea9a877	538	\brief Set Fault Mask (non-secure)
ganlikun	0:13413ea9a877	539	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
ganlikun	0:13413ea9a877	540	\param [in] faultMask Fault Mask value to set
ganlikun	0:13413ea9a877	541	*/
ganlikun	0:13413ea9a877	542	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
ganlikun	0:13413ea9a877	543	{
ganlikun	0:13413ea9a877	544	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
ganlikun	0:13413ea9a877	545	}
ganlikun	0:13413ea9a877	546	#endif
ganlikun	0:13413ea9a877	547
ganlikun	0:13413ea9a877	548	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
ganlikun	0:13413ea9a877	549	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	550	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
ganlikun	0:13413ea9a877	551
ganlikun	0:13413ea9a877	552
ganlikun	0:13413ea9a877	553	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
ganlikun	0:13413ea9a877	554	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
ganlikun	0:13413ea9a877	555
ganlikun	0:13413ea9a877	556	/**
ganlikun	0:13413ea9a877	557	\brief Get Process Stack Pointer Limit
ganlikun	0:13413ea9a877	558	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
ganlikun	0:13413ea9a877	559	\return PSPLIM Register value
ganlikun	0:13413ea9a877	560	*/
ganlikun	0:13413ea9a877	561	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
ganlikun	0:13413ea9a877	562	{
ganlikun	0:13413ea9a877	563	register uint32_t result;
ganlikun	0:13413ea9a877	564
ganlikun	0:13413ea9a877	565	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
ganlikun	0:13413ea9a877	566	return(result);
ganlikun	0:13413ea9a877	567	}
ganlikun	0:13413ea9a877	568
ganlikun	0:13413ea9a877	569
ganlikun	0:13413ea9a877	570	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
ganlikun	0:13413ea9a877	571	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	572	/**
ganlikun	0:13413ea9a877	573	\brief Get Process Stack Pointer Limit (non-secure)
ganlikun	0:13413ea9a877	574	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
ganlikun	0:13413ea9a877	575	\return PSPLIM Register value
ganlikun	0:13413ea9a877	576	*/
ganlikun	0:13413ea9a877	577	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
ganlikun	0:13413ea9a877	578	{
ganlikun	0:13413ea9a877	579	register uint32_t result;
ganlikun	0:13413ea9a877	580
ganlikun	0:13413ea9a877	581	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	582	return(result);
ganlikun	0:13413ea9a877	583	}
ganlikun	0:13413ea9a877	584	#endif
ganlikun	0:13413ea9a877	585
ganlikun	0:13413ea9a877	586
ganlikun	0:13413ea9a877	587	/**
ganlikun	0:13413ea9a877	588	\brief Set Process Stack Pointer Limit
ganlikun	0:13413ea9a877	589	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
ganlikun	0:13413ea9a877	590	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
ganlikun	0:13413ea9a877	591	*/
ganlikun	0:13413ea9a877	592	__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
ganlikun	0:13413ea9a877	593	{
ganlikun	0:13413ea9a877	594	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
ganlikun	0:13413ea9a877	595	}
ganlikun	0:13413ea9a877	596
ganlikun	0:13413ea9a877	597
ganlikun	0:13413ea9a877	598	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
ganlikun	0:13413ea9a877	599	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	600	/**
ganlikun	0:13413ea9a877	601	\brief Set Process Stack Pointer (non-secure)
ganlikun	0:13413ea9a877	602	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
ganlikun	0:13413ea9a877	603	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
ganlikun	0:13413ea9a877	604	*/
ganlikun	0:13413ea9a877	605	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
ganlikun	0:13413ea9a877	606	{
ganlikun	0:13413ea9a877	607	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
ganlikun	0:13413ea9a877	608	}
ganlikun	0:13413ea9a877	609	#endif
ganlikun	0:13413ea9a877	610
ganlikun	0:13413ea9a877	611
ganlikun	0:13413ea9a877	612	/**
ganlikun	0:13413ea9a877	613	\brief Get Main Stack Pointer Limit
ganlikun	0:13413ea9a877	614	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
ganlikun	0:13413ea9a877	615	\return MSPLIM Register value
ganlikun	0:13413ea9a877	616	*/
ganlikun	0:13413ea9a877	617	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
ganlikun	0:13413ea9a877	618	{
ganlikun	0:13413ea9a877	619	register uint32_t result;
ganlikun	0:13413ea9a877	620
ganlikun	0:13413ea9a877	621	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
ganlikun	0:13413ea9a877	622
ganlikun	0:13413ea9a877	623	return(result);
ganlikun	0:13413ea9a877	624	}
ganlikun	0:13413ea9a877	625
ganlikun	0:13413ea9a877	626
ganlikun	0:13413ea9a877	627	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
ganlikun	0:13413ea9a877	628	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	629	/**
ganlikun	0:13413ea9a877	630	\brief Get Main Stack Pointer Limit (non-secure)
ganlikun	0:13413ea9a877	631	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
ganlikun	0:13413ea9a877	632	\return MSPLIM Register value
ganlikun	0:13413ea9a877	633	*/
ganlikun	0:13413ea9a877	634	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
ganlikun	0:13413ea9a877	635	{
ganlikun	0:13413ea9a877	636	register uint32_t result;
ganlikun	0:13413ea9a877	637
ganlikun	0:13413ea9a877	638	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
ganlikun	0:13413ea9a877	639	return(result);
ganlikun	0:13413ea9a877	640	}
ganlikun	0:13413ea9a877	641	#endif
ganlikun	0:13413ea9a877	642
ganlikun	0:13413ea9a877	643
ganlikun	0:13413ea9a877	644	/**
ganlikun	0:13413ea9a877	645	\brief Set Main Stack Pointer Limit
ganlikun	0:13413ea9a877	646	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
ganlikun	0:13413ea9a877	647	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
ganlikun	0:13413ea9a877	648	*/
ganlikun	0:13413ea9a877	649	__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
ganlikun	0:13413ea9a877	650	{
ganlikun	0:13413ea9a877	651	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
ganlikun	0:13413ea9a877	652	}
ganlikun	0:13413ea9a877	653
ganlikun	0:13413ea9a877	654
ganlikun	0:13413ea9a877	655	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
ganlikun	0:13413ea9a877	656	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	657	/**
ganlikun	0:13413ea9a877	658	\brief Set Main Stack Pointer Limit (non-secure)
ganlikun	0:13413ea9a877	659	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
ganlikun	0:13413ea9a877	660	\param [in] MainStackPtrLimit Main Stack Pointer value to set
ganlikun	0:13413ea9a877	661	*/
ganlikun	0:13413ea9a877	662	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
ganlikun	0:13413ea9a877	663	{
ganlikun	0:13413ea9a877	664	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
ganlikun	0:13413ea9a877	665	}
ganlikun	0:13413ea9a877	666	#endif
ganlikun	0:13413ea9a877	667
ganlikun	0:13413ea9a877	668	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
ganlikun	0:13413ea9a877	669	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
ganlikun	0:13413ea9a877	670
ganlikun	0:13413ea9a877	671
ganlikun	0:13413ea9a877	672	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	673	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	674
ganlikun	0:13413ea9a877	675	/**
ganlikun	0:13413ea9a877	676	\brief Get FPSCR
ganlikun	0:13413ea9a877	677	\details Returns the current value of the Floating Point Status/Control register.
ganlikun	0:13413ea9a877	678	\return Floating Point Status/Control register value
ganlikun	0:13413ea9a877	679	*/
ganlikun	0:13413ea9a877	680	/* #define __get_FPSCR __builtin_arm_get_fpscr */
ganlikun	0:13413ea9a877	681	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
ganlikun	0:13413ea9a877	682	{
ganlikun	0:13413ea9a877	683	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
ganlikun	0:13413ea9a877	684	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
ganlikun	0:13413ea9a877	685	uint32_t result;
ganlikun	0:13413ea9a877	686
ganlikun	0:13413ea9a877	687	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
ganlikun	0:13413ea9a877	688	return(result);
ganlikun	0:13413ea9a877	689	#else
ganlikun	0:13413ea9a877	690	return(0U);
ganlikun	0:13413ea9a877	691	#endif
ganlikun	0:13413ea9a877	692	}
ganlikun	0:13413ea9a877	693
ganlikun	0:13413ea9a877	694
ganlikun	0:13413ea9a877	695	/**
ganlikun	0:13413ea9a877	696	\brief Set FPSCR
ganlikun	0:13413ea9a877	697	\details Assigns the given value to the Floating Point Status/Control register.
ganlikun	0:13413ea9a877	698	\param [in] fpscr Floating Point Status/Control value to set
ganlikun	0:13413ea9a877	699	*/
ganlikun	0:13413ea9a877	700	/* #define __set_FPSCR __builtin_arm_set_fpscr */
ganlikun	0:13413ea9a877	701	__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
ganlikun	0:13413ea9a877	702	{
ganlikun	0:13413ea9a877	703	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
ganlikun	0:13413ea9a877	704	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
ganlikun	0:13413ea9a877	705	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
ganlikun	0:13413ea9a877	706	#else
ganlikun	0:13413ea9a877	707	(void)fpscr;
ganlikun	0:13413ea9a877	708	#endif
ganlikun	0:13413ea9a877	709	}
ganlikun	0:13413ea9a877	710
ganlikun	0:13413ea9a877	711	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	712	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
ganlikun	0:13413ea9a877	713
ganlikun	0:13413ea9a877	714
ganlikun	0:13413ea9a877	715
ganlikun	0:13413ea9a877	716	/@} end of CMSIS_Core_RegAccFunctions /
ganlikun	0:13413ea9a877	717
ganlikun	0:13413ea9a877	718
ganlikun	0:13413ea9a877	719	/* ########################## Core Instruction Access ######################### */
ganlikun	0:13413ea9a877	720	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
ganlikun	0:13413ea9a877	721	Access to dedicated instructions
ganlikun	0:13413ea9a877	722	@{
ganlikun	0:13413ea9a877	723	*/
ganlikun	0:13413ea9a877	724
ganlikun	0:13413ea9a877	725	/* Define macros for porting to both thumb1 and thumb2.
ganlikun	0:13413ea9a877	726	* For thumb1, use low register (r0-r7), specified by constraint "l"
ganlikun	0:13413ea9a877	727	* Otherwise, use general registers, specified by constraint "r" */
ganlikun	0:13413ea9a877	728	#if defined (__thumb__) && !defined (__thumb2__)
ganlikun	0:13413ea9a877	729	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
ganlikun	0:13413ea9a877	730	#define __CMSIS_GCC_USE_REG(r) "l" (r)
ganlikun	0:13413ea9a877	731	#else
ganlikun	0:13413ea9a877	732	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
ganlikun	0:13413ea9a877	733	#define __CMSIS_GCC_USE_REG(r) "r" (r)
ganlikun	0:13413ea9a877	734	#endif
ganlikun	0:13413ea9a877	735
ganlikun	0:13413ea9a877	736	/**
ganlikun	0:13413ea9a877	737	\brief No Operation
ganlikun	0:13413ea9a877	738	\details No Operation does nothing. This instruction can be used for code alignment purposes.
ganlikun	0:13413ea9a877	739	*/
ganlikun	0:13413ea9a877	740	#define __NOP __builtin_arm_nop
ganlikun	0:13413ea9a877	741
ganlikun	0:13413ea9a877	742	/**
ganlikun	0:13413ea9a877	743	\brief Wait For Interrupt
ganlikun	0:13413ea9a877	744	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
ganlikun	0:13413ea9a877	745	*/
ganlikun	0:13413ea9a877	746	#define __WFI __builtin_arm_wfi
ganlikun	0:13413ea9a877	747
ganlikun	0:13413ea9a877	748
ganlikun	0:13413ea9a877	749	/**
ganlikun	0:13413ea9a877	750	\brief Wait For Event
ganlikun	0:13413ea9a877	751	\details Wait For Event is a hint instruction that permits the processor to enter
ganlikun	0:13413ea9a877	752	a low-power state until one of a number of events occurs.
ganlikun	0:13413ea9a877	753	*/
ganlikun	0:13413ea9a877	754	#define __WFE __builtin_arm_wfe
ganlikun	0:13413ea9a877	755
ganlikun	0:13413ea9a877	756
ganlikun	0:13413ea9a877	757	/**
ganlikun	0:13413ea9a877	758	\brief Send Event
ganlikun	0:13413ea9a877	759	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
ganlikun	0:13413ea9a877	760	*/
ganlikun	0:13413ea9a877	761	#define __SEV __builtin_arm_sev
ganlikun	0:13413ea9a877	762
ganlikun	0:13413ea9a877	763
ganlikun	0:13413ea9a877	764	/**
ganlikun	0:13413ea9a877	765	\brief Instruction Synchronization Barrier
ganlikun	0:13413ea9a877	766	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
ganlikun	0:13413ea9a877	767	so that all instructions following the ISB are fetched from cache or memory,
ganlikun	0:13413ea9a877	768	after the instruction has been completed.
ganlikun	0:13413ea9a877	769	*/
ganlikun	0:13413ea9a877	770	#define __ISB() __builtin_arm_isb(0xF);
ganlikun	0:13413ea9a877	771
ganlikun	0:13413ea9a877	772	/**
ganlikun	0:13413ea9a877	773	\brief Data Synchronization Barrier
ganlikun	0:13413ea9a877	774	\details Acts as a special kind of Data Memory Barrier.
ganlikun	0:13413ea9a877	775	It completes when all explicit memory accesses before this instruction complete.
ganlikun	0:13413ea9a877	776	*/
ganlikun	0:13413ea9a877	777	#define __DSB() __builtin_arm_dsb(0xF);
ganlikun	0:13413ea9a877	778
ganlikun	0:13413ea9a877	779
ganlikun	0:13413ea9a877	780	/**
ganlikun	0:13413ea9a877	781	\brief Data Memory Barrier
ganlikun	0:13413ea9a877	782	\details Ensures the apparent order of the explicit memory operations before
ganlikun	0:13413ea9a877	783	and after the instruction, without ensuring their completion.
ganlikun	0:13413ea9a877	784	*/
ganlikun	0:13413ea9a877	785	#define __DMB() __builtin_arm_dmb(0xF);
ganlikun	0:13413ea9a877	786
ganlikun	0:13413ea9a877	787
ganlikun	0:13413ea9a877	788	/**
ganlikun	0:13413ea9a877	789	\brief Reverse byte order (32 bit)
ganlikun	0:13413ea9a877	790	\details Reverses the byte order in integer value.
ganlikun	0:13413ea9a877	791	\param [in] value Value to reverse
ganlikun	0:13413ea9a877	792	\return Reversed value
ganlikun	0:13413ea9a877	793	*/
ganlikun	0:13413ea9a877	794	#define __REV __builtin_bswap32
ganlikun	0:13413ea9a877	795
ganlikun	0:13413ea9a877	796
ganlikun	0:13413ea9a877	797	/**
ganlikun	0:13413ea9a877	798	\brief Reverse byte order (16 bit)
ganlikun	0:13413ea9a877	799	\details Reverses the byte order in two unsigned short values.
ganlikun	0:13413ea9a877	800	\param [in] value Value to reverse
ganlikun	0:13413ea9a877	801	\return Reversed value
ganlikun	0:13413ea9a877	802	*/
ganlikun	0:13413ea9a877	803	#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
ganlikun	0:13413ea9a877	804	#if 0
ganlikun	0:13413ea9a877	805	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
ganlikun	0:13413ea9a877	806	{
ganlikun	0:13413ea9a877	807	uint32_t result;
ganlikun	0:13413ea9a877	808
ganlikun	0:13413ea9a877	809	__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
ganlikun	0:13413ea9a877	810	return(result);
ganlikun	0:13413ea9a877	811	}
ganlikun	0:13413ea9a877	812	#endif
ganlikun	0:13413ea9a877	813
ganlikun	0:13413ea9a877	814
ganlikun	0:13413ea9a877	815	/**
ganlikun	0:13413ea9a877	816	\brief Reverse byte order in signed short value
ganlikun	0:13413ea9a877	817	\details Reverses the byte order in a signed short value with sign extension to integer.
ganlikun	0:13413ea9a877	818	\param [in] value Value to reverse
ganlikun	0:13413ea9a877	819	\return Reversed value
ganlikun	0:13413ea9a877	820	*/
ganlikun	0:13413ea9a877	821	/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
ganlikun	0:13413ea9a877	822	__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
ganlikun	0:13413ea9a877	823	{
ganlikun	0:13413ea9a877	824	int32_t result;
ganlikun	0:13413ea9a877	825
ganlikun	0:13413ea9a877	826	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
ganlikun	0:13413ea9a877	827	return(result);
ganlikun	0:13413ea9a877	828	}
ganlikun	0:13413ea9a877	829
ganlikun	0:13413ea9a877	830
ganlikun	0:13413ea9a877	831	/**
ganlikun	0:13413ea9a877	832	\brief Rotate Right in unsigned value (32 bit)
ganlikun	0:13413ea9a877	833	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
ganlikun	0:13413ea9a877	834	\param [in] op1 Value to rotate
ganlikun	0:13413ea9a877	835	\param [in] op2 Number of Bits to rotate
ganlikun	0:13413ea9a877	836	\return Rotated value
ganlikun	0:13413ea9a877	837	*/
ganlikun	0:13413ea9a877	838	__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	839	{
ganlikun	0:13413ea9a877	840	return (op1 >> op2) \| (op1 << (32U - op2));
ganlikun	0:13413ea9a877	841	}
ganlikun	0:13413ea9a877	842
ganlikun	0:13413ea9a877	843
ganlikun	0:13413ea9a877	844	/**
ganlikun	0:13413ea9a877	845	\brief Breakpoint
ganlikun	0:13413ea9a877	846	\details Causes the processor to enter Debug state.
ganlikun	0:13413ea9a877	847	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
ganlikun	0:13413ea9a877	848	\param [in] value is ignored by the processor.
ganlikun	0:13413ea9a877	849	If required, a debugger can use it to store additional information about the breakpoint.
ganlikun	0:13413ea9a877	850	*/
ganlikun	0:13413ea9a877	851	#define __BKPT(value) __ASM volatile ("bkpt "#value)
ganlikun	0:13413ea9a877	852
ganlikun	0:13413ea9a877	853
ganlikun	0:13413ea9a877	854	/**
ganlikun	0:13413ea9a877	855	\brief Reverse bit order of value
ganlikun	0:13413ea9a877	856	\details Reverses the bit order of the given value.
ganlikun	0:13413ea9a877	857	\param [in] value Value to reverse
ganlikun	0:13413ea9a877	858	\return Reversed value
ganlikun	0:13413ea9a877	859	*/
ganlikun	0:13413ea9a877	860	/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
ganlikun	0:13413ea9a877	861	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
ganlikun	0:13413ea9a877	862	{
ganlikun	0:13413ea9a877	863	uint32_t result;
ganlikun	0:13413ea9a877	864
ganlikun	0:13413ea9a877	865	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
ganlikun	0:13413ea9a877	866	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	867	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	868	__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
ganlikun	0:13413ea9a877	869	#else
ganlikun	0:13413ea9a877	870	int32_t s = (4 /sizeof(v)/ * 8) - 1; /* extra shift needed at end */
ganlikun	0:13413ea9a877	871
ganlikun	0:13413ea9a877	872	result = value; /* r will be reversed bits of v; first get LSB of v */
ganlikun	0:13413ea9a877	873	for (value >>= 1U; value; value >>= 1U)
ganlikun	0:13413ea9a877	874	{
ganlikun	0:13413ea9a877	875	result <<= 1U;
ganlikun	0:13413ea9a877	876	result \|= value & 1U;
ganlikun	0:13413ea9a877	877	s--;
ganlikun	0:13413ea9a877	878	}
ganlikun	0:13413ea9a877	879	result <<= s; /* shift when v's highest bits are zero */
ganlikun	0:13413ea9a877	880	#endif
ganlikun	0:13413ea9a877	881	return(result);
ganlikun	0:13413ea9a877	882	}
ganlikun	0:13413ea9a877	883
ganlikun	0:13413ea9a877	884
ganlikun	0:13413ea9a877	885	/**
ganlikun	0:13413ea9a877	886	\brief Count leading zeros
ganlikun	0:13413ea9a877	887	\details Counts the number of leading zeros of a data value.
ganlikun	0:13413ea9a877	888	\param [in] value Value to count the leading zeros
ganlikun	0:13413ea9a877	889	\return number of leading zeros in value
ganlikun	0:13413ea9a877	890	*/
ganlikun	0:13413ea9a877	891	#define __CLZ __builtin_clz
ganlikun	0:13413ea9a877	892
ganlikun	0:13413ea9a877	893
ganlikun	0:13413ea9a877	894	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
ganlikun	0:13413ea9a877	895	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	896	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
ganlikun	0:13413ea9a877	897	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
ganlikun	0:13413ea9a877	898	/**
ganlikun	0:13413ea9a877	899	\brief LDR Exclusive (8 bit)
ganlikun	0:13413ea9a877	900	\details Executes a exclusive LDR instruction for 8 bit value.
ganlikun	0:13413ea9a877	901	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	902	\return value of type uint8_t at (*ptr)
ganlikun	0:13413ea9a877	903	*/
ganlikun	0:13413ea9a877	904	#define __LDREXB (uint8_t)__builtin_arm_ldrex
ganlikun	0:13413ea9a877	905
ganlikun	0:13413ea9a877	906
ganlikun	0:13413ea9a877	907	/**
ganlikun	0:13413ea9a877	908	\brief LDR Exclusive (16 bit)
ganlikun	0:13413ea9a877	909	\details Executes a exclusive LDR instruction for 16 bit values.
ganlikun	0:13413ea9a877	910	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	911	\return value of type uint16_t at (*ptr)
ganlikun	0:13413ea9a877	912	*/
ganlikun	0:13413ea9a877	913	#define __LDREXH (uint16_t)__builtin_arm_ldrex
ganlikun	0:13413ea9a877	914
ganlikun	0:13413ea9a877	915
ganlikun	0:13413ea9a877	916	/**
ganlikun	0:13413ea9a877	917	\brief LDR Exclusive (32 bit)
ganlikun	0:13413ea9a877	918	\details Executes a exclusive LDR instruction for 32 bit values.
ganlikun	0:13413ea9a877	919	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	920	\return value of type uint32_t at (*ptr)
ganlikun	0:13413ea9a877	921	*/
ganlikun	0:13413ea9a877	922	#define __LDREXW (uint32_t)__builtin_arm_ldrex
ganlikun	0:13413ea9a877	923
ganlikun	0:13413ea9a877	924
ganlikun	0:13413ea9a877	925	/**
ganlikun	0:13413ea9a877	926	\brief STR Exclusive (8 bit)
ganlikun	0:13413ea9a877	927	\details Executes a exclusive STR instruction for 8 bit values.
ganlikun	0:13413ea9a877	928	\param [in] value Value to store
ganlikun	0:13413ea9a877	929	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	930	\return 0 Function succeeded
ganlikun	0:13413ea9a877	931	\return 1 Function failed
ganlikun	0:13413ea9a877	932	*/
ganlikun	0:13413ea9a877	933	#define __STREXB (uint32_t)__builtin_arm_strex
ganlikun	0:13413ea9a877	934
ganlikun	0:13413ea9a877	935
ganlikun	0:13413ea9a877	936	/**
ganlikun	0:13413ea9a877	937	\brief STR Exclusive (16 bit)
ganlikun	0:13413ea9a877	938	\details Executes a exclusive STR instruction for 16 bit values.
ganlikun	0:13413ea9a877	939	\param [in] value Value to store
ganlikun	0:13413ea9a877	940	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	941	\return 0 Function succeeded
ganlikun	0:13413ea9a877	942	\return 1 Function failed
ganlikun	0:13413ea9a877	943	*/
ganlikun	0:13413ea9a877	944	#define __STREXH (uint32_t)__builtin_arm_strex
ganlikun	0:13413ea9a877	945
ganlikun	0:13413ea9a877	946
ganlikun	0:13413ea9a877	947	/**
ganlikun	0:13413ea9a877	948	\brief STR Exclusive (32 bit)
ganlikun	0:13413ea9a877	949	\details Executes a exclusive STR instruction for 32 bit values.
ganlikun	0:13413ea9a877	950	\param [in] value Value to store
ganlikun	0:13413ea9a877	951	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	952	\return 0 Function succeeded
ganlikun	0:13413ea9a877	953	\return 1 Function failed
ganlikun	0:13413ea9a877	954	*/
ganlikun	0:13413ea9a877	955	#define __STREXW (uint32_t)__builtin_arm_strex
ganlikun	0:13413ea9a877	956
ganlikun	0:13413ea9a877	957
ganlikun	0:13413ea9a877	958	/**
ganlikun	0:13413ea9a877	959	\brief Remove the exclusive lock
ganlikun	0:13413ea9a877	960	\details Removes the exclusive lock which is created by LDREX.
ganlikun	0:13413ea9a877	961	*/
ganlikun	0:13413ea9a877	962	#define __CLREX __builtin_arm_clrex
ganlikun	0:13413ea9a877	963
ganlikun	0:13413ea9a877	964	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
ganlikun	0:13413ea9a877	965	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	966	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
ganlikun	0:13413ea9a877	967	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
ganlikun	0:13413ea9a877	968
ganlikun	0:13413ea9a877	969
ganlikun	0:13413ea9a877	970	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
ganlikun	0:13413ea9a877	971	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	972	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
ganlikun	0:13413ea9a877	973	/**
ganlikun	0:13413ea9a877	974	\brief Signed Saturate
ganlikun	0:13413ea9a877	975	\details Saturates a signed value.
ganlikun	0:13413ea9a877	976	\param [in] value Value to be saturated
ganlikun	0:13413ea9a877	977	\param [in] sat Bit position to saturate to (1..32)
ganlikun	0:13413ea9a877	978	\return Saturated value
ganlikun	0:13413ea9a877	979	*/
ganlikun	0:13413ea9a877	980	#define __SSAT __builtin_arm_ssat
ganlikun	0:13413ea9a877	981
ganlikun	0:13413ea9a877	982
ganlikun	0:13413ea9a877	983	/**
ganlikun	0:13413ea9a877	984	\brief Unsigned Saturate
ganlikun	0:13413ea9a877	985	\details Saturates an unsigned value.
ganlikun	0:13413ea9a877	986	\param [in] value Value to be saturated
ganlikun	0:13413ea9a877	987	\param [in] sat Bit position to saturate to (0..31)
ganlikun	0:13413ea9a877	988	\return Saturated value
ganlikun	0:13413ea9a877	989	*/
ganlikun	0:13413ea9a877	990	#define __USAT __builtin_arm_usat
ganlikun	0:13413ea9a877	991
ganlikun	0:13413ea9a877	992
ganlikun	0:13413ea9a877	993	/**
ganlikun	0:13413ea9a877	994	\brief Rotate Right with Extend (32 bit)
ganlikun	0:13413ea9a877	995	\details Moves each bit of a bitstring right by one bit.
ganlikun	0:13413ea9a877	996	The carry input is shifted in at the left end of the bitstring.
ganlikun	0:13413ea9a877	997	\param [in] value Value to rotate
ganlikun	0:13413ea9a877	998	\return Rotated value
ganlikun	0:13413ea9a877	999	*/
ganlikun	0:13413ea9a877	1000	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
ganlikun	0:13413ea9a877	1001	{
ganlikun	0:13413ea9a877	1002	uint32_t result;
ganlikun	0:13413ea9a877	1003
ganlikun	0:13413ea9a877	1004	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
ganlikun	0:13413ea9a877	1005	return(result);
ganlikun	0:13413ea9a877	1006	}
ganlikun	0:13413ea9a877	1007
ganlikun	0:13413ea9a877	1008
ganlikun	0:13413ea9a877	1009	/**
ganlikun	0:13413ea9a877	1010	\brief LDRT Unprivileged (8 bit)
ganlikun	0:13413ea9a877	1011	\details Executes a Unprivileged LDRT instruction for 8 bit value.
ganlikun	0:13413ea9a877	1012	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1013	\return value of type uint8_t at (*ptr)
ganlikun	0:13413ea9a877	1014	*/
ganlikun	0:13413ea9a877	1015	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
ganlikun	0:13413ea9a877	1016	{
ganlikun	0:13413ea9a877	1017	uint32_t result;
ganlikun	0:13413ea9a877	1018
ganlikun	0:13413ea9a877	1019	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
ganlikun	0:13413ea9a877	1020	return ((uint8_t) result); /* Add explicit type cast here */
ganlikun	0:13413ea9a877	1021	}
ganlikun	0:13413ea9a877	1022
ganlikun	0:13413ea9a877	1023
ganlikun	0:13413ea9a877	1024	/**
ganlikun	0:13413ea9a877	1025	\brief LDRT Unprivileged (16 bit)
ganlikun	0:13413ea9a877	1026	\details Executes a Unprivileged LDRT instruction for 16 bit values.
ganlikun	0:13413ea9a877	1027	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1028	\return value of type uint16_t at (*ptr)
ganlikun	0:13413ea9a877	1029	*/
ganlikun	0:13413ea9a877	1030	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
ganlikun	0:13413ea9a877	1031	{
ganlikun	0:13413ea9a877	1032	uint32_t result;
ganlikun	0:13413ea9a877	1033
ganlikun	0:13413ea9a877	1034	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
ganlikun	0:13413ea9a877	1035	return ((uint16_t) result); /* Add explicit type cast here */
ganlikun	0:13413ea9a877	1036	}
ganlikun	0:13413ea9a877	1037
ganlikun	0:13413ea9a877	1038
ganlikun	0:13413ea9a877	1039	/**
ganlikun	0:13413ea9a877	1040	\brief LDRT Unprivileged (32 bit)
ganlikun	0:13413ea9a877	1041	\details Executes a Unprivileged LDRT instruction for 32 bit values.
ganlikun	0:13413ea9a877	1042	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1043	\return value of type uint32_t at (*ptr)
ganlikun	0:13413ea9a877	1044	*/
ganlikun	0:13413ea9a877	1045	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
ganlikun	0:13413ea9a877	1046	{
ganlikun	0:13413ea9a877	1047	uint32_t result;
ganlikun	0:13413ea9a877	1048
ganlikun	0:13413ea9a877	1049	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
ganlikun	0:13413ea9a877	1050	return(result);
ganlikun	0:13413ea9a877	1051	}
ganlikun	0:13413ea9a877	1052
ganlikun	0:13413ea9a877	1053
ganlikun	0:13413ea9a877	1054	/**
ganlikun	0:13413ea9a877	1055	\brief STRT Unprivileged (8 bit)
ganlikun	0:13413ea9a877	1056	\details Executes a Unprivileged STRT instruction for 8 bit values.
ganlikun	0:13413ea9a877	1057	\param [in] value Value to store
ganlikun	0:13413ea9a877	1058	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1059	*/
ganlikun	0:13413ea9a877	1060	__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
ganlikun	0:13413ea9a877	1061	{
ganlikun	0:13413ea9a877	1062	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
ganlikun	0:13413ea9a877	1063	}
ganlikun	0:13413ea9a877	1064
ganlikun	0:13413ea9a877	1065
ganlikun	0:13413ea9a877	1066	/**
ganlikun	0:13413ea9a877	1067	\brief STRT Unprivileged (16 bit)
ganlikun	0:13413ea9a877	1068	\details Executes a Unprivileged STRT instruction for 16 bit values.
ganlikun	0:13413ea9a877	1069	\param [in] value Value to store
ganlikun	0:13413ea9a877	1070	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1071	*/
ganlikun	0:13413ea9a877	1072	__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
ganlikun	0:13413ea9a877	1073	{
ganlikun	0:13413ea9a877	1074	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
ganlikun	0:13413ea9a877	1075	}
ganlikun	0:13413ea9a877	1076
ganlikun	0:13413ea9a877	1077
ganlikun	0:13413ea9a877	1078	/**
ganlikun	0:13413ea9a877	1079	\brief STRT Unprivileged (32 bit)
ganlikun	0:13413ea9a877	1080	\details Executes a Unprivileged STRT instruction for 32 bit values.
ganlikun	0:13413ea9a877	1081	\param [in] value Value to store
ganlikun	0:13413ea9a877	1082	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1083	*/
ganlikun	0:13413ea9a877	1084	__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
ganlikun	0:13413ea9a877	1085	{
ganlikun	0:13413ea9a877	1086	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
ganlikun	0:13413ea9a877	1087	}
ganlikun	0:13413ea9a877	1088
ganlikun	0:13413ea9a877	1089	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
ganlikun	0:13413ea9a877	1090	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
ganlikun	0:13413ea9a877	1091	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
ganlikun	0:13413ea9a877	1092
ganlikun	0:13413ea9a877	1093
ganlikun	0:13413ea9a877	1094	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
ganlikun	0:13413ea9a877	1095	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
ganlikun	0:13413ea9a877	1096	/**
ganlikun	0:13413ea9a877	1097	\brief Load-Acquire (8 bit)
ganlikun	0:13413ea9a877	1098	\details Executes a LDAB instruction for 8 bit value.
ganlikun	0:13413ea9a877	1099	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1100	\return value of type uint8_t at (*ptr)
ganlikun	0:13413ea9a877	1101	*/
ganlikun	0:13413ea9a877	1102	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
ganlikun	0:13413ea9a877	1103	{
ganlikun	0:13413ea9a877	1104	uint32_t result;
ganlikun	0:13413ea9a877	1105
ganlikun	0:13413ea9a877	1106	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
ganlikun	0:13413ea9a877	1107	return ((uint8_t) result);
ganlikun	0:13413ea9a877	1108	}
ganlikun	0:13413ea9a877	1109
ganlikun	0:13413ea9a877	1110
ganlikun	0:13413ea9a877	1111	/**
ganlikun	0:13413ea9a877	1112	\brief Load-Acquire (16 bit)
ganlikun	0:13413ea9a877	1113	\details Executes a LDAH instruction for 16 bit values.
ganlikun	0:13413ea9a877	1114	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1115	\return value of type uint16_t at (*ptr)
ganlikun	0:13413ea9a877	1116	*/
ganlikun	0:13413ea9a877	1117	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
ganlikun	0:13413ea9a877	1118	{
ganlikun	0:13413ea9a877	1119	uint32_t result;
ganlikun	0:13413ea9a877	1120
ganlikun	0:13413ea9a877	1121	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
ganlikun	0:13413ea9a877	1122	return ((uint16_t) result);
ganlikun	0:13413ea9a877	1123	}
ganlikun	0:13413ea9a877	1124
ganlikun	0:13413ea9a877	1125
ganlikun	0:13413ea9a877	1126	/**
ganlikun	0:13413ea9a877	1127	\brief Load-Acquire (32 bit)
ganlikun	0:13413ea9a877	1128	\details Executes a LDA instruction for 32 bit values.
ganlikun	0:13413ea9a877	1129	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1130	\return value of type uint32_t at (*ptr)
ganlikun	0:13413ea9a877	1131	*/
ganlikun	0:13413ea9a877	1132	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
ganlikun	0:13413ea9a877	1133	{
ganlikun	0:13413ea9a877	1134	uint32_t result;
ganlikun	0:13413ea9a877	1135
ganlikun	0:13413ea9a877	1136	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
ganlikun	0:13413ea9a877	1137	return(result);
ganlikun	0:13413ea9a877	1138	}
ganlikun	0:13413ea9a877	1139
ganlikun	0:13413ea9a877	1140
ganlikun	0:13413ea9a877	1141	/**
ganlikun	0:13413ea9a877	1142	\brief Store-Release (8 bit)
ganlikun	0:13413ea9a877	1143	\details Executes a STLB instruction for 8 bit values.
ganlikun	0:13413ea9a877	1144	\param [in] value Value to store
ganlikun	0:13413ea9a877	1145	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1146	*/
ganlikun	0:13413ea9a877	1147	__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
ganlikun	0:13413ea9a877	1148	{
ganlikun	0:13413ea9a877	1149	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
ganlikun	0:13413ea9a877	1150	}
ganlikun	0:13413ea9a877	1151
ganlikun	0:13413ea9a877	1152
ganlikun	0:13413ea9a877	1153	/**
ganlikun	0:13413ea9a877	1154	\brief Store-Release (16 bit)
ganlikun	0:13413ea9a877	1155	\details Executes a STLH instruction for 16 bit values.
ganlikun	0:13413ea9a877	1156	\param [in] value Value to store
ganlikun	0:13413ea9a877	1157	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1158	*/
ganlikun	0:13413ea9a877	1159	__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
ganlikun	0:13413ea9a877	1160	{
ganlikun	0:13413ea9a877	1161	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
ganlikun	0:13413ea9a877	1162	}
ganlikun	0:13413ea9a877	1163
ganlikun	0:13413ea9a877	1164
ganlikun	0:13413ea9a877	1165	/**
ganlikun	0:13413ea9a877	1166	\brief Store-Release (32 bit)
ganlikun	0:13413ea9a877	1167	\details Executes a STL instruction for 32 bit values.
ganlikun	0:13413ea9a877	1168	\param [in] value Value to store
ganlikun	0:13413ea9a877	1169	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1170	*/
ganlikun	0:13413ea9a877	1171	__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
ganlikun	0:13413ea9a877	1172	{
ganlikun	0:13413ea9a877	1173	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
ganlikun	0:13413ea9a877	1174	}
ganlikun	0:13413ea9a877	1175
ganlikun	0:13413ea9a877	1176
ganlikun	0:13413ea9a877	1177	/**
ganlikun	0:13413ea9a877	1178	\brief Load-Acquire Exclusive (8 bit)
ganlikun	0:13413ea9a877	1179	\details Executes a LDAB exclusive instruction for 8 bit value.
ganlikun	0:13413ea9a877	1180	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1181	\return value of type uint8_t at (*ptr)
ganlikun	0:13413ea9a877	1182	*/
ganlikun	0:13413ea9a877	1183	#define __LDAEXB (uint8_t)__builtin_arm_ldaex
ganlikun	0:13413ea9a877	1184
ganlikun	0:13413ea9a877	1185
ganlikun	0:13413ea9a877	1186	/**
ganlikun	0:13413ea9a877	1187	\brief Load-Acquire Exclusive (16 bit)
ganlikun	0:13413ea9a877	1188	\details Executes a LDAH exclusive instruction for 16 bit values.
ganlikun	0:13413ea9a877	1189	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1190	\return value of type uint16_t at (*ptr)
ganlikun	0:13413ea9a877	1191	*/
ganlikun	0:13413ea9a877	1192	#define __LDAEXH (uint16_t)__builtin_arm_ldaex
ganlikun	0:13413ea9a877	1193
ganlikun	0:13413ea9a877	1194
ganlikun	0:13413ea9a877	1195	/**
ganlikun	0:13413ea9a877	1196	\brief Load-Acquire Exclusive (32 bit)
ganlikun	0:13413ea9a877	1197	\details Executes a LDA exclusive instruction for 32 bit values.
ganlikun	0:13413ea9a877	1198	\param [in] ptr Pointer to data
ganlikun	0:13413ea9a877	1199	\return value of type uint32_t at (*ptr)
ganlikun	0:13413ea9a877	1200	*/
ganlikun	0:13413ea9a877	1201	#define __LDAEX (uint32_t)__builtin_arm_ldaex
ganlikun	0:13413ea9a877	1202
ganlikun	0:13413ea9a877	1203
ganlikun	0:13413ea9a877	1204	/**
ganlikun	0:13413ea9a877	1205	\brief Store-Release Exclusive (8 bit)
ganlikun	0:13413ea9a877	1206	\details Executes a STLB exclusive instruction for 8 bit values.
ganlikun	0:13413ea9a877	1207	\param [in] value Value to store
ganlikun	0:13413ea9a877	1208	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1209	\return 0 Function succeeded
ganlikun	0:13413ea9a877	1210	\return 1 Function failed
ganlikun	0:13413ea9a877	1211	*/
ganlikun	0:13413ea9a877	1212	#define __STLEXB (uint32_t)__builtin_arm_stlex
ganlikun	0:13413ea9a877	1213
ganlikun	0:13413ea9a877	1214
ganlikun	0:13413ea9a877	1215	/**
ganlikun	0:13413ea9a877	1216	\brief Store-Release Exclusive (16 bit)
ganlikun	0:13413ea9a877	1217	\details Executes a STLH exclusive instruction for 16 bit values.
ganlikun	0:13413ea9a877	1218	\param [in] value Value to store
ganlikun	0:13413ea9a877	1219	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1220	\return 0 Function succeeded
ganlikun	0:13413ea9a877	1221	\return 1 Function failed
ganlikun	0:13413ea9a877	1222	*/
ganlikun	0:13413ea9a877	1223	#define __STLEXH (uint32_t)__builtin_arm_stlex
ganlikun	0:13413ea9a877	1224
ganlikun	0:13413ea9a877	1225
ganlikun	0:13413ea9a877	1226	/**
ganlikun	0:13413ea9a877	1227	\brief Store-Release Exclusive (32 bit)
ganlikun	0:13413ea9a877	1228	\details Executes a STL exclusive instruction for 32 bit values.
ganlikun	0:13413ea9a877	1229	\param [in] value Value to store
ganlikun	0:13413ea9a877	1230	\param [in] ptr Pointer to location
ganlikun	0:13413ea9a877	1231	\return 0 Function succeeded
ganlikun	0:13413ea9a877	1232	\return 1 Function failed
ganlikun	0:13413ea9a877	1233	*/
ganlikun	0:13413ea9a877	1234	#define __STLEX (uint32_t)__builtin_arm_stlex
ganlikun	0:13413ea9a877	1235
ganlikun	0:13413ea9a877	1236	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
ganlikun	0:13413ea9a877	1237	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
ganlikun	0:13413ea9a877	1238
ganlikun	0:13413ea9a877	1239	/@}/ /* end of group CMSIS_Core_InstructionInterface */
ganlikun	0:13413ea9a877	1240
ganlikun	0:13413ea9a877	1241
ganlikun	0:13413ea9a877	1242	/* ################### Compiler specific Intrinsics ########################### */
ganlikun	0:13413ea9a877	1243	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
ganlikun	0:13413ea9a877	1244	Access to dedicated SIMD instructions
ganlikun	0:13413ea9a877	1245	@{
ganlikun	0:13413ea9a877	1246	*/
ganlikun	0:13413ea9a877	1247
ganlikun	0:13413ea9a877	1248	#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
ganlikun	0:13413ea9a877	1249
ganlikun	0:13413ea9a877	1250	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1251	{
ganlikun	0:13413ea9a877	1252	uint32_t result;
ganlikun	0:13413ea9a877	1253
ganlikun	0:13413ea9a877	1254	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1255	return(result);
ganlikun	0:13413ea9a877	1256	}
ganlikun	0:13413ea9a877	1257
ganlikun	0:13413ea9a877	1258	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1259	{
ganlikun	0:13413ea9a877	1260	uint32_t result;
ganlikun	0:13413ea9a877	1261
ganlikun	0:13413ea9a877	1262	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1263	return(result);
ganlikun	0:13413ea9a877	1264	}
ganlikun	0:13413ea9a877	1265
ganlikun	0:13413ea9a877	1266	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1267	{
ganlikun	0:13413ea9a877	1268	uint32_t result;
ganlikun	0:13413ea9a877	1269
ganlikun	0:13413ea9a877	1270	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1271	return(result);
ganlikun	0:13413ea9a877	1272	}
ganlikun	0:13413ea9a877	1273
ganlikun	0:13413ea9a877	1274	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1275	{
ganlikun	0:13413ea9a877	1276	uint32_t result;
ganlikun	0:13413ea9a877	1277
ganlikun	0:13413ea9a877	1278	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1279	return(result);
ganlikun	0:13413ea9a877	1280	}
ganlikun	0:13413ea9a877	1281
ganlikun	0:13413ea9a877	1282	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1283	{
ganlikun	0:13413ea9a877	1284	uint32_t result;
ganlikun	0:13413ea9a877	1285
ganlikun	0:13413ea9a877	1286	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1287	return(result);
ganlikun	0:13413ea9a877	1288	}
ganlikun	0:13413ea9a877	1289
ganlikun	0:13413ea9a877	1290	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1291	{
ganlikun	0:13413ea9a877	1292	uint32_t result;
ganlikun	0:13413ea9a877	1293
ganlikun	0:13413ea9a877	1294	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1295	return(result);
ganlikun	0:13413ea9a877	1296	}
ganlikun	0:13413ea9a877	1297
ganlikun	0:13413ea9a877	1298
ganlikun	0:13413ea9a877	1299	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1300	{
ganlikun	0:13413ea9a877	1301	uint32_t result;
ganlikun	0:13413ea9a877	1302
ganlikun	0:13413ea9a877	1303	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1304	return(result);
ganlikun	0:13413ea9a877	1305	}
ganlikun	0:13413ea9a877	1306
ganlikun	0:13413ea9a877	1307	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1308	{
ganlikun	0:13413ea9a877	1309	uint32_t result;
ganlikun	0:13413ea9a877	1310
ganlikun	0:13413ea9a877	1311	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1312	return(result);
ganlikun	0:13413ea9a877	1313	}
ganlikun	0:13413ea9a877	1314
ganlikun	0:13413ea9a877	1315	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1316	{
ganlikun	0:13413ea9a877	1317	uint32_t result;
ganlikun	0:13413ea9a877	1318
ganlikun	0:13413ea9a877	1319	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1320	return(result);
ganlikun	0:13413ea9a877	1321	}
ganlikun	0:13413ea9a877	1322
ganlikun	0:13413ea9a877	1323	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1324	{
ganlikun	0:13413ea9a877	1325	uint32_t result;
ganlikun	0:13413ea9a877	1326
ganlikun	0:13413ea9a877	1327	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1328	return(result);
ganlikun	0:13413ea9a877	1329	}
ganlikun	0:13413ea9a877	1330
ganlikun	0:13413ea9a877	1331	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1332	{
ganlikun	0:13413ea9a877	1333	uint32_t result;
ganlikun	0:13413ea9a877	1334
ganlikun	0:13413ea9a877	1335	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1336	return(result);
ganlikun	0:13413ea9a877	1337	}
ganlikun	0:13413ea9a877	1338
ganlikun	0:13413ea9a877	1339	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1340	{
ganlikun	0:13413ea9a877	1341	uint32_t result;
ganlikun	0:13413ea9a877	1342
ganlikun	0:13413ea9a877	1343	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1344	return(result);
ganlikun	0:13413ea9a877	1345	}
ganlikun	0:13413ea9a877	1346
ganlikun	0:13413ea9a877	1347
ganlikun	0:13413ea9a877	1348	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1349	{
ganlikun	0:13413ea9a877	1350	uint32_t result;
ganlikun	0:13413ea9a877	1351
ganlikun	0:13413ea9a877	1352	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1353	return(result);
ganlikun	0:13413ea9a877	1354	}
ganlikun	0:13413ea9a877	1355
ganlikun	0:13413ea9a877	1356	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1357	{
ganlikun	0:13413ea9a877	1358	uint32_t result;
ganlikun	0:13413ea9a877	1359
ganlikun	0:13413ea9a877	1360	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1361	return(result);
ganlikun	0:13413ea9a877	1362	}
ganlikun	0:13413ea9a877	1363
ganlikun	0:13413ea9a877	1364	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1365	{
ganlikun	0:13413ea9a877	1366	uint32_t result;
ganlikun	0:13413ea9a877	1367
ganlikun	0:13413ea9a877	1368	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1369	return(result);
ganlikun	0:13413ea9a877	1370	}
ganlikun	0:13413ea9a877	1371
ganlikun	0:13413ea9a877	1372	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1373	{
ganlikun	0:13413ea9a877	1374	uint32_t result;
ganlikun	0:13413ea9a877	1375
ganlikun	0:13413ea9a877	1376	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1377	return(result);
ganlikun	0:13413ea9a877	1378	}
ganlikun	0:13413ea9a877	1379
ganlikun	0:13413ea9a877	1380	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1381	{
ganlikun	0:13413ea9a877	1382	uint32_t result;
ganlikun	0:13413ea9a877	1383
ganlikun	0:13413ea9a877	1384	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1385	return(result);
ganlikun	0:13413ea9a877	1386	}
ganlikun	0:13413ea9a877	1387
ganlikun	0:13413ea9a877	1388	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1389	{
ganlikun	0:13413ea9a877	1390	uint32_t result;
ganlikun	0:13413ea9a877	1391
ganlikun	0:13413ea9a877	1392	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1393	return(result);
ganlikun	0:13413ea9a877	1394	}
ganlikun	0:13413ea9a877	1395
ganlikun	0:13413ea9a877	1396	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1397	{
ganlikun	0:13413ea9a877	1398	uint32_t result;
ganlikun	0:13413ea9a877	1399
ganlikun	0:13413ea9a877	1400	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1401	return(result);
ganlikun	0:13413ea9a877	1402	}
ganlikun	0:13413ea9a877	1403
ganlikun	0:13413ea9a877	1404	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1405	{
ganlikun	0:13413ea9a877	1406	uint32_t result;
ganlikun	0:13413ea9a877	1407
ganlikun	0:13413ea9a877	1408	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1409	return(result);
ganlikun	0:13413ea9a877	1410	}
ganlikun	0:13413ea9a877	1411
ganlikun	0:13413ea9a877	1412	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1413	{
ganlikun	0:13413ea9a877	1414	uint32_t result;
ganlikun	0:13413ea9a877	1415
ganlikun	0:13413ea9a877	1416	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1417	return(result);
ganlikun	0:13413ea9a877	1418	}
ganlikun	0:13413ea9a877	1419
ganlikun	0:13413ea9a877	1420	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1421	{
ganlikun	0:13413ea9a877	1422	uint32_t result;
ganlikun	0:13413ea9a877	1423
ganlikun	0:13413ea9a877	1424	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1425	return(result);
ganlikun	0:13413ea9a877	1426	}
ganlikun	0:13413ea9a877	1427
ganlikun	0:13413ea9a877	1428	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1429	{
ganlikun	0:13413ea9a877	1430	uint32_t result;
ganlikun	0:13413ea9a877	1431
ganlikun	0:13413ea9a877	1432	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1433	return(result);
ganlikun	0:13413ea9a877	1434	}
ganlikun	0:13413ea9a877	1435
ganlikun	0:13413ea9a877	1436	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1437	{
ganlikun	0:13413ea9a877	1438	uint32_t result;
ganlikun	0:13413ea9a877	1439
ganlikun	0:13413ea9a877	1440	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1441	return(result);
ganlikun	0:13413ea9a877	1442	}
ganlikun	0:13413ea9a877	1443
ganlikun	0:13413ea9a877	1444	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1445	{
ganlikun	0:13413ea9a877	1446	uint32_t result;
ganlikun	0:13413ea9a877	1447
ganlikun	0:13413ea9a877	1448	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1449	return(result);
ganlikun	0:13413ea9a877	1450	}
ganlikun	0:13413ea9a877	1451
ganlikun	0:13413ea9a877	1452	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1453	{
ganlikun	0:13413ea9a877	1454	uint32_t result;
ganlikun	0:13413ea9a877	1455
ganlikun	0:13413ea9a877	1456	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1457	return(result);
ganlikun	0:13413ea9a877	1458	}
ganlikun	0:13413ea9a877	1459
ganlikun	0:13413ea9a877	1460	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1461	{
ganlikun	0:13413ea9a877	1462	uint32_t result;
ganlikun	0:13413ea9a877	1463
ganlikun	0:13413ea9a877	1464	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1465	return(result);
ganlikun	0:13413ea9a877	1466	}
ganlikun	0:13413ea9a877	1467
ganlikun	0:13413ea9a877	1468	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1469	{
ganlikun	0:13413ea9a877	1470	uint32_t result;
ganlikun	0:13413ea9a877	1471
ganlikun	0:13413ea9a877	1472	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1473	return(result);
ganlikun	0:13413ea9a877	1474	}
ganlikun	0:13413ea9a877	1475
ganlikun	0:13413ea9a877	1476	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1477	{
ganlikun	0:13413ea9a877	1478	uint32_t result;
ganlikun	0:13413ea9a877	1479
ganlikun	0:13413ea9a877	1480	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1481	return(result);
ganlikun	0:13413ea9a877	1482	}
ganlikun	0:13413ea9a877	1483
ganlikun	0:13413ea9a877	1484	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1485	{
ganlikun	0:13413ea9a877	1486	uint32_t result;
ganlikun	0:13413ea9a877	1487
ganlikun	0:13413ea9a877	1488	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1489	return(result);
ganlikun	0:13413ea9a877	1490	}
ganlikun	0:13413ea9a877	1491
ganlikun	0:13413ea9a877	1492	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1493	{
ganlikun	0:13413ea9a877	1494	uint32_t result;
ganlikun	0:13413ea9a877	1495
ganlikun	0:13413ea9a877	1496	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1497	return(result);
ganlikun	0:13413ea9a877	1498	}
ganlikun	0:13413ea9a877	1499
ganlikun	0:13413ea9a877	1500	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1501	{
ganlikun	0:13413ea9a877	1502	uint32_t result;
ganlikun	0:13413ea9a877	1503
ganlikun	0:13413ea9a877	1504	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1505	return(result);
ganlikun	0:13413ea9a877	1506	}
ganlikun	0:13413ea9a877	1507
ganlikun	0:13413ea9a877	1508	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1509	{
ganlikun	0:13413ea9a877	1510	uint32_t result;
ganlikun	0:13413ea9a877	1511
ganlikun	0:13413ea9a877	1512	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1513	return(result);
ganlikun	0:13413ea9a877	1514	}
ganlikun	0:13413ea9a877	1515
ganlikun	0:13413ea9a877	1516	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1517	{
ganlikun	0:13413ea9a877	1518	uint32_t result;
ganlikun	0:13413ea9a877	1519
ganlikun	0:13413ea9a877	1520	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1521	return(result);
ganlikun	0:13413ea9a877	1522	}
ganlikun	0:13413ea9a877	1523
ganlikun	0:13413ea9a877	1524	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1525	{
ganlikun	0:13413ea9a877	1526	uint32_t result;
ganlikun	0:13413ea9a877	1527
ganlikun	0:13413ea9a877	1528	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1529	return(result);
ganlikun	0:13413ea9a877	1530	}
ganlikun	0:13413ea9a877	1531
ganlikun	0:13413ea9a877	1532	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1533	{
ganlikun	0:13413ea9a877	1534	uint32_t result;
ganlikun	0:13413ea9a877	1535
ganlikun	0:13413ea9a877	1536	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1537	return(result);
ganlikun	0:13413ea9a877	1538	}
ganlikun	0:13413ea9a877	1539
ganlikun	0:13413ea9a877	1540	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1541	{
ganlikun	0:13413ea9a877	1542	uint32_t result;
ganlikun	0:13413ea9a877	1543
ganlikun	0:13413ea9a877	1544	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1545	return(result);
ganlikun	0:13413ea9a877	1546	}
ganlikun	0:13413ea9a877	1547
ganlikun	0:13413ea9a877	1548	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
ganlikun	0:13413ea9a877	1549	{
ganlikun	0:13413ea9a877	1550	uint32_t result;
ganlikun	0:13413ea9a877	1551
ganlikun	0:13413ea9a877	1552	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ganlikun	0:13413ea9a877	1553	return(result);
ganlikun	0:13413ea9a877	1554	}
ganlikun	0:13413ea9a877	1555
ganlikun	0:13413ea9a877	1556	#define __SSAT16(ARG1,ARG2) \
ganlikun	0:13413ea9a877	1557	({ \
ganlikun	0:13413ea9a877	1558	int32_t __RES, __ARG1 = (ARG1); \
ganlikun	0:13413ea9a877	1559	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
ganlikun	0:13413ea9a877	1560	__RES; \
ganlikun	0:13413ea9a877	1561	})
ganlikun	0:13413ea9a877	1562
ganlikun	0:13413ea9a877	1563	#define __USAT16(ARG1,ARG2) \
ganlikun	0:13413ea9a877	1564	({ \
ganlikun	0:13413ea9a877	1565	uint32_t __RES, __ARG1 = (ARG1); \
ganlikun	0:13413ea9a877	1566	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
ganlikun	0:13413ea9a877	1567	__RES; \
ganlikun	0:13413ea9a877	1568	})
ganlikun	0:13413ea9a877	1569
ganlikun	0:13413ea9a877	1570	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
ganlikun	0:13413ea9a877	1571	{
ganlikun	0:13413ea9a877	1572	uint32_t result;
ganlikun	0:13413ea9a877	1573
ganlikun	0:13413ea9a877	1574	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
ganlikun	0:13413ea9a877	1575	return(result);
ganlikun	0:13413ea9a877	1576	}
ganlikun	0:13413ea9a877	1577
ganlikun	0:13413ea9a877	1578	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1579	{
ganlikun	0:13413ea9a877	1580	uint32_t result;
ganlikun	0:13413ea9a877	1581
ganlikun	0:13413ea9a877	1582	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1583	return(result);
ganlikun	0:13413ea9a877	1584	}
ganlikun	0:13413ea9a877	1585
ganlikun	0:13413ea9a877	1586	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
ganlikun	0:13413ea9a877	1587	{
ganlikun	0:13413ea9a877	1588	uint32_t result;
ganlikun	0:13413ea9a877	1589
ganlikun	0:13413ea9a877	1590	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
ganlikun	0:13413ea9a877	1591	return(result);
ganlikun	0:13413ea9a877	1592	}
ganlikun	0:13413ea9a877	1593
ganlikun	0:13413ea9a877	1594	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1595	{
ganlikun	0:13413ea9a877	1596	uint32_t result;
ganlikun	0:13413ea9a877	1597
ganlikun	0:13413ea9a877	1598	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1599	return(result);
ganlikun	0:13413ea9a877	1600	}
ganlikun	0:13413ea9a877	1601
ganlikun	0:13413ea9a877	1602	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1603	{
ganlikun	0:13413ea9a877	1604	uint32_t result;
ganlikun	0:13413ea9a877	1605
ganlikun	0:13413ea9a877	1606	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1607	return(result);
ganlikun	0:13413ea9a877	1608	}
ganlikun	0:13413ea9a877	1609
ganlikun	0:13413ea9a877	1610	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1611	{
ganlikun	0:13413ea9a877	1612	uint32_t result;
ganlikun	0:13413ea9a877	1613
ganlikun	0:13413ea9a877	1614	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1615	return(result);
ganlikun	0:13413ea9a877	1616	}
ganlikun	0:13413ea9a877	1617
ganlikun	0:13413ea9a877	1618	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
ganlikun	0:13413ea9a877	1619	{
ganlikun	0:13413ea9a877	1620	uint32_t result;
ganlikun	0:13413ea9a877	1621
ganlikun	0:13413ea9a877	1622	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ganlikun	0:13413ea9a877	1623	return(result);
ganlikun	0:13413ea9a877	1624	}
ganlikun	0:13413ea9a877	1625
ganlikun	0:13413ea9a877	1626	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
ganlikun	0:13413ea9a877	1627	{
ganlikun	0:13413ea9a877	1628	uint32_t result;
ganlikun	0:13413ea9a877	1629
ganlikun	0:13413ea9a877	1630	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ganlikun	0:13413ea9a877	1631	return(result);
ganlikun	0:13413ea9a877	1632	}
ganlikun	0:13413ea9a877	1633
ganlikun	0:13413ea9a877	1634	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
ganlikun	0:13413ea9a877	1635	{
ganlikun	0:13413ea9a877	1636	union llreg_u{
ganlikun	0:13413ea9a877	1637	uint32_t w32[2];
ganlikun	0:13413ea9a877	1638	uint64_t w64;
ganlikun	0:13413ea9a877	1639	} llr;
ganlikun	0:13413ea9a877	1640	llr.w64 = acc;
ganlikun	0:13413ea9a877	1641
ganlikun	0:13413ea9a877	1642	#ifndef __ARMEB__ /* Little endian */
ganlikun	0:13413ea9a877	1643	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
ganlikun	0:13413ea9a877	1644	#else /* Big endian */
ganlikun	0:13413ea9a877	1645	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
ganlikun	0:13413ea9a877	1646	#endif
ganlikun	0:13413ea9a877	1647
ganlikun	0:13413ea9a877	1648	return(llr.w64);
ganlikun	0:13413ea9a877	1649	}
ganlikun	0:13413ea9a877	1650
ganlikun	0:13413ea9a877	1651	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
ganlikun	0:13413ea9a877	1652	{
ganlikun	0:13413ea9a877	1653	union llreg_u{
ganlikun	0:13413ea9a877	1654	uint32_t w32[2];
ganlikun	0:13413ea9a877	1655	uint64_t w64;
ganlikun	0:13413ea9a877	1656	} llr;
ganlikun	0:13413ea9a877	1657	llr.w64 = acc;
ganlikun	0:13413ea9a877	1658
ganlikun	0:13413ea9a877	1659	#ifndef __ARMEB__ /* Little endian */
ganlikun	0:13413ea9a877	1660	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
ganlikun	0:13413ea9a877	1661	#else /* Big endian */
ganlikun	0:13413ea9a877	1662	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
ganlikun	0:13413ea9a877	1663	#endif
ganlikun	0:13413ea9a877	1664
ganlikun	0:13413ea9a877	1665	return(llr.w64);
ganlikun	0:13413ea9a877	1666	}
ganlikun	0:13413ea9a877	1667
ganlikun	0:13413ea9a877	1668	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1669	{
ganlikun	0:13413ea9a877	1670	uint32_t result;
ganlikun	0:13413ea9a877	1671
ganlikun	0:13413ea9a877	1672	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1673	return(result);
ganlikun	0:13413ea9a877	1674	}
ganlikun	0:13413ea9a877	1675
ganlikun	0:13413ea9a877	1676	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1677	{
ganlikun	0:13413ea9a877	1678	uint32_t result;
ganlikun	0:13413ea9a877	1679
ganlikun	0:13413ea9a877	1680	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1681	return(result);
ganlikun	0:13413ea9a877	1682	}
ganlikun	0:13413ea9a877	1683
ganlikun	0:13413ea9a877	1684	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
ganlikun	0:13413ea9a877	1685	{
ganlikun	0:13413ea9a877	1686	uint32_t result;
ganlikun	0:13413ea9a877	1687
ganlikun	0:13413ea9a877	1688	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ganlikun	0:13413ea9a877	1689	return(result);
ganlikun	0:13413ea9a877	1690	}
ganlikun	0:13413ea9a877	1691
ganlikun	0:13413ea9a877	1692	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
ganlikun	0:13413ea9a877	1693	{
ganlikun	0:13413ea9a877	1694	uint32_t result;
ganlikun	0:13413ea9a877	1695
ganlikun	0:13413ea9a877	1696	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
ganlikun	0:13413ea9a877	1697	return(result);
ganlikun	0:13413ea9a877	1698	}
ganlikun	0:13413ea9a877	1699
ganlikun	0:13413ea9a877	1700	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
ganlikun	0:13413ea9a877	1701	{
ganlikun	0:13413ea9a877	1702	union llreg_u{
ganlikun	0:13413ea9a877	1703	uint32_t w32[2];
ganlikun	0:13413ea9a877	1704	uint64_t w64;
ganlikun	0:13413ea9a877	1705	} llr;
ganlikun	0:13413ea9a877	1706	llr.w64 = acc;
ganlikun	0:13413ea9a877	1707
ganlikun	0:13413ea9a877	1708	#ifndef __ARMEB__ /* Little endian */
ganlikun	0:13413ea9a877	1709	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
ganlikun	0:13413ea9a877	1710	#else /* Big endian */
ganlikun	0:13413ea9a877	1711	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
ganlikun	0:13413ea9a877	1712	#endif
ganlikun	0:13413ea9a877	1713
ganlikun	0:13413ea9a877	1714	return(llr.w64);
ganlikun	0:13413ea9a877	1715	}
ganlikun	0:13413ea9a877	1716
ganlikun	0:13413ea9a877	1717	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
ganlikun	0:13413ea9a877	1718	{
ganlikun	0:13413ea9a877	1719	union llreg_u{
ganlikun	0:13413ea9a877	1720	uint32_t w32[2];
ganlikun	0:13413ea9a877	1721	uint64_t w64;
ganlikun	0:13413ea9a877	1722	} llr;
ganlikun	0:13413ea9a877	1723	llr.w64 = acc;
ganlikun	0:13413ea9a877	1724
ganlikun	0:13413ea9a877	1725	#ifndef __ARMEB__ /* Little endian */
ganlikun	0:13413ea9a877	1726	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
ganlikun	0:13413ea9a877	1727	#else /* Big endian */
ganlikun	0:13413ea9a877	1728	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
ganlikun	0:13413ea9a877	1729	#endif
ganlikun	0:13413ea9a877	1730
ganlikun	0:13413ea9a877	1731	return(llr.w64);
ganlikun	0:13413ea9a877	1732	}
ganlikun	0:13413ea9a877	1733
ganlikun	0:13413ea9a877	1734	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
ganlikun	0:13413ea9a877	1735	{
ganlikun	0:13413ea9a877	1736	uint32_t result;
ganlikun	0:13413ea9a877	1737
ganlikun	0:13413ea9a877	1738	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1739	return(result);
ganlikun	0:13413ea9a877	1740	}
ganlikun	0:13413ea9a877	1741
ganlikun	0:13413ea9a877	1742	__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
ganlikun	0:13413ea9a877	1743	{
ganlikun	0:13413ea9a877	1744	int32_t result;
ganlikun	0:13413ea9a877	1745
ganlikun	0:13413ea9a877	1746	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1747	return(result);
ganlikun	0:13413ea9a877	1748	}
ganlikun	0:13413ea9a877	1749
ganlikun	0:13413ea9a877	1750	__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
ganlikun	0:13413ea9a877	1751	{
ganlikun	0:13413ea9a877	1752	int32_t result;
ganlikun	0:13413ea9a877	1753
ganlikun	0:13413ea9a877	1754	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
ganlikun	0:13413ea9a877	1755	return(result);
ganlikun	0:13413ea9a877	1756	}
ganlikun	0:13413ea9a877	1757
ganlikun	0:13413ea9a877	1758	#if 0
ganlikun	0:13413ea9a877	1759	#define __PKHBT(ARG1,ARG2,ARG3) \
ganlikun	0:13413ea9a877	1760	({ \
ganlikun	0:13413ea9a877	1761	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
ganlikun	0:13413ea9a877	1762	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
ganlikun	0:13413ea9a877	1763	__RES; \
ganlikun	0:13413ea9a877	1764	})
ganlikun	0:13413ea9a877	1765
ganlikun	0:13413ea9a877	1766	#define __PKHTB(ARG1,ARG2,ARG3) \
ganlikun	0:13413ea9a877	1767	({ \
ganlikun	0:13413ea9a877	1768	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
ganlikun	0:13413ea9a877	1769	if (ARG3 == 0) \
ganlikun	0:13413ea9a877	1770	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
ganlikun	0:13413ea9a877	1771	else \
ganlikun	0:13413ea9a877	1772	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
ganlikun	0:13413ea9a877	1773	__RES; \
ganlikun	0:13413ea9a877	1774	})
ganlikun	0:13413ea9a877	1775	#endif
ganlikun	0:13413ea9a877	1776
ganlikun	0:13413ea9a877	1777	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
ganlikun	0:13413ea9a877	1778	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
ganlikun	0:13413ea9a877	1779
ganlikun	0:13413ea9a877	1780	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
ganlikun	0:13413ea9a877	1781	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
ganlikun	0:13413ea9a877	1782
ganlikun	0:13413ea9a877	1783	__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
ganlikun	0:13413ea9a877	1784	{
ganlikun	0:13413ea9a877	1785	int32_t result;
ganlikun	0:13413ea9a877	1786
ganlikun	0:13413ea9a877	1787	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
ganlikun	0:13413ea9a877	1788	return(result);
ganlikun	0:13413ea9a877	1789	}
ganlikun	0:13413ea9a877	1790
ganlikun	0:13413ea9a877	1791	#endif /* (__ARM_FEATURE_DSP == 1) */
ganlikun	0:13413ea9a877	1792	/@} end of group CMSIS_SIMD_intrinsics /
ganlikun	0:13413ea9a877	1793
ganlikun	0:13413ea9a877	1794
ganlikun	0:13413ea9a877	1795	#endif /* __CMSIS_ARMCLANG_H */
ganlikun	0:13413ea9a877	1796

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h@0:13413ea9a877, 2022-06-12 (annotated)

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