Gan likun / mbed-dev11

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c@0:06036f8bee2d, 2022-10-24 (annotated)

Committer:
ganlikun
Date:
Mon Oct 24 15:19:39 2022 +0000
Revision:
0:06036f8bee2d
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:06036f8bee2d 1 /**
ganlikun 0:06036f8bee2d 2 ******************************************************************************
ganlikun 0:06036f8bee2d 3 * @file stm32f4xx_hal_dma.c
ganlikun 0:06036f8bee2d 4 * @author MCD Application Team
ganlikun 0:06036f8bee2d 5 * @version V1.7.1
ganlikun 0:06036f8bee2d 6 * @date 14-April-2017
ganlikun 0:06036f8bee2d 7 * @brief DMA HAL module driver.
ganlikun 0:06036f8bee2d 8 *
ganlikun 0:06036f8bee2d 9 * This file provides firmware functions to manage the following
ganlikun 0:06036f8bee2d 10 * functionalities of the Direct Memory Access (DMA) peripheral:
ganlikun 0:06036f8bee2d 11 * + Initialization and de-initialization functions
ganlikun 0:06036f8bee2d 12 * + IO operation functions
ganlikun 0:06036f8bee2d 13 * + Peripheral State and errors functions
ganlikun 0:06036f8bee2d 14 @verbatim
ganlikun 0:06036f8bee2d 15 ==============================================================================
ganlikun 0:06036f8bee2d 16 ##### How to use this driver #####
ganlikun 0:06036f8bee2d 17 ==============================================================================
ganlikun 0:06036f8bee2d 18 [..]
ganlikun 0:06036f8bee2d 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
ganlikun 0:06036f8bee2d 20 (except for internal SRAM/FLASH memories: no initialization is
ganlikun 0:06036f8bee2d 21 necessary) please refer to Reference manual for connection between peripherals
ganlikun 0:06036f8bee2d 22 and DMA requests.
ganlikun 0:06036f8bee2d 23
ganlikun 0:06036f8bee2d 24 (#) For a given Stream, program the required configuration through the following parameters:
ganlikun 0:06036f8bee2d 25 Transfer Direction, Source and Destination data formats,
ganlikun 0:06036f8bee2d 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
ganlikun 0:06036f8bee2d 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
ganlikun 0:06036f8bee2d 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
ganlikun 0:06036f8bee2d 29
ganlikun 0:06036f8bee2d 30 -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
ganlikun 0:06036f8bee2d 31 __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
ganlikun 0:06036f8bee2d 32
ganlikun 0:06036f8bee2d 33 *** Polling mode IO operation ***
ganlikun 0:06036f8bee2d 34 =================================
ganlikun 0:06036f8bee2d 35 [..]
ganlikun 0:06036f8bee2d 36 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
ganlikun 0:06036f8bee2d 37 address and destination address and the Length of data to be transferred.
ganlikun 0:06036f8bee2d 38 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
ganlikun 0:06036f8bee2d 39 case a fixed Timeout can be configured by User depending from his application.
ganlikun 0:06036f8bee2d 40 (+) Use HAL_DMA_Abort() function to abort the current transfer.
ganlikun 0:06036f8bee2d 41
ganlikun 0:06036f8bee2d 42 *** Interrupt mode IO operation ***
ganlikun 0:06036f8bee2d 43 ===================================
ganlikun 0:06036f8bee2d 44 [..]
ganlikun 0:06036f8bee2d 45 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
ganlikun 0:06036f8bee2d 46 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
ganlikun 0:06036f8bee2d 47 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
ganlikun 0:06036f8bee2d 48 Source address and destination address and the Length of data to be transferred. In this
ganlikun 0:06036f8bee2d 49 case the DMA interrupt is configured
ganlikun 0:06036f8bee2d 50 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
ganlikun 0:06036f8bee2d 51 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
ganlikun 0:06036f8bee2d 52 add his own function by customization of function pointer XferCpltCallback and
ganlikun 0:06036f8bee2d 53 XferErrorCallback (i.e a member of DMA handle structure).
ganlikun 0:06036f8bee2d 54 [..]
ganlikun 0:06036f8bee2d 55 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
ganlikun 0:06036f8bee2d 56 detection.
ganlikun 0:06036f8bee2d 57
ganlikun 0:06036f8bee2d 58 (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
ganlikun 0:06036f8bee2d 59
ganlikun 0:06036f8bee2d 60 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
ganlikun 0:06036f8bee2d 61
ganlikun 0:06036f8bee2d 62 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
ganlikun 0:06036f8bee2d 63 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
ganlikun 0:06036f8bee2d 64 Half-Word data size for the peripheral to access its data register and set Word data size
ganlikun 0:06036f8bee2d 65 for the Memory to gain in access time. Each two half words will be packed and written in
ganlikun 0:06036f8bee2d 66 a single access to a Word in the Memory).
ganlikun 0:06036f8bee2d 67
ganlikun 0:06036f8bee2d 68 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
ganlikun 0:06036f8bee2d 69 and Destination. In this case the Peripheral Data Size will be applied to both Source
ganlikun 0:06036f8bee2d 70 and Destination.
ganlikun 0:06036f8bee2d 71
ganlikun 0:06036f8bee2d 72 *** DMA HAL driver macros list ***
ganlikun 0:06036f8bee2d 73 =============================================
ganlikun 0:06036f8bee2d 74 [..]
ganlikun 0:06036f8bee2d 75 Below the list of most used macros in DMA HAL driver.
ganlikun 0:06036f8bee2d 76
ganlikun 0:06036f8bee2d 77 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
ganlikun 0:06036f8bee2d 78 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
ganlikun 0:06036f8bee2d 79 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
ganlikun 0:06036f8bee2d 80
ganlikun 0:06036f8bee2d 81 [..]
ganlikun 0:06036f8bee2d 82 (@) You can refer to the DMA HAL driver header file for more useful macros
ganlikun 0:06036f8bee2d 83
ganlikun 0:06036f8bee2d 84 @endverbatim
ganlikun 0:06036f8bee2d 85 ******************************************************************************
ganlikun 0:06036f8bee2d 86 * @attention
ganlikun 0:06036f8bee2d 87 *
ganlikun 0:06036f8bee2d 88 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:06036f8bee2d 89 *
ganlikun 0:06036f8bee2d 90 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:06036f8bee2d 91 * are permitted provided that the following conditions are met:
ganlikun 0:06036f8bee2d 92 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:06036f8bee2d 93 * this list of conditions and the following disclaimer.
ganlikun 0:06036f8bee2d 94 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:06036f8bee2d 95 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:06036f8bee2d 96 * and/or other materials provided with the distribution.
ganlikun 0:06036f8bee2d 97 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:06036f8bee2d 98 * may be used to endorse or promote products derived from this software
ganlikun 0:06036f8bee2d 99 * without specific prior written permission.
ganlikun 0:06036f8bee2d 100 *
ganlikun 0:06036f8bee2d 101 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:06036f8bee2d 102 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:06036f8bee2d 103 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:06036f8bee2d 104 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:06036f8bee2d 105 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:06036f8bee2d 106 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:06036f8bee2d 107 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:06036f8bee2d 108 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:06036f8bee2d 109 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:06036f8bee2d 110 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:06036f8bee2d 111 *
ganlikun 0:06036f8bee2d 112 ******************************************************************************
ganlikun 0:06036f8bee2d 113 */
ganlikun 0:06036f8bee2d 114
ganlikun 0:06036f8bee2d 115 /* Includes ------------------------------------------------------------------*/
ganlikun 0:06036f8bee2d 116 #include "stm32f4xx_hal.h"
ganlikun 0:06036f8bee2d 117
ganlikun 0:06036f8bee2d 118 /** @addtogroup STM32F4xx_HAL_Driver
ganlikun 0:06036f8bee2d 119 * @{
ganlikun 0:06036f8bee2d 120 */
ganlikun 0:06036f8bee2d 121
ganlikun 0:06036f8bee2d 122 /** @defgroup DMA DMA
ganlikun 0:06036f8bee2d 123 * @brief DMA HAL module driver
ganlikun 0:06036f8bee2d 124 * @{
ganlikun 0:06036f8bee2d 125 */
ganlikun 0:06036f8bee2d 126
ganlikun 0:06036f8bee2d 127 #ifdef HAL_DMA_MODULE_ENABLED
ganlikun 0:06036f8bee2d 128
ganlikun 0:06036f8bee2d 129 /* Private types -------------------------------------------------------------*/
ganlikun 0:06036f8bee2d 130 typedef struct
ganlikun 0:06036f8bee2d 131 {
ganlikun 0:06036f8bee2d 132 __IO uint32_t ISR; /*!< DMA interrupt status register */
ganlikun 0:06036f8bee2d 133 __IO uint32_t Reserved0;
ganlikun 0:06036f8bee2d 134 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
ganlikun 0:06036f8bee2d 135 } DMA_Base_Registers;
ganlikun 0:06036f8bee2d 136
ganlikun 0:06036f8bee2d 137 /* Private variables ---------------------------------------------------------*/
ganlikun 0:06036f8bee2d 138 /* Private constants ---------------------------------------------------------*/
ganlikun 0:06036f8bee2d 139 /** @addtogroup DMA_Private_Constants
ganlikun 0:06036f8bee2d 140 * @{
ganlikun 0:06036f8bee2d 141 */
ganlikun 0:06036f8bee2d 142 #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */
ganlikun 0:06036f8bee2d 143 /**
ganlikun 0:06036f8bee2d 144 * @}
ganlikun 0:06036f8bee2d 145 */
ganlikun 0:06036f8bee2d 146 /* Private macros ------------------------------------------------------------*/
ganlikun 0:06036f8bee2d 147 /* Private functions ---------------------------------------------------------*/
ganlikun 0:06036f8bee2d 148 /** @addtogroup DMA_Private_Functions
ganlikun 0:06036f8bee2d 149 * @{
ganlikun 0:06036f8bee2d 150 */
ganlikun 0:06036f8bee2d 151 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
ganlikun 0:06036f8bee2d 152 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
ganlikun 0:06036f8bee2d 153 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
ganlikun 0:06036f8bee2d 154
ganlikun 0:06036f8bee2d 155 /**
ganlikun 0:06036f8bee2d 156 * @}
ganlikun 0:06036f8bee2d 157 */
ganlikun 0:06036f8bee2d 158
ganlikun 0:06036f8bee2d 159 /* Exported functions ---------------------------------------------------------*/
ganlikun 0:06036f8bee2d 160 /** @addtogroup DMA_Exported_Functions
ganlikun 0:06036f8bee2d 161 * @{
ganlikun 0:06036f8bee2d 162 */
ganlikun 0:06036f8bee2d 163
ganlikun 0:06036f8bee2d 164 /** @addtogroup DMA_Exported_Functions_Group1
ganlikun 0:06036f8bee2d 165 *
ganlikun 0:06036f8bee2d 166 @verbatim
ganlikun 0:06036f8bee2d 167 ===============================================================================
ganlikun 0:06036f8bee2d 168 ##### Initialization and de-initialization functions #####
ganlikun 0:06036f8bee2d 169 ===============================================================================
ganlikun 0:06036f8bee2d 170 [..]
ganlikun 0:06036f8bee2d 171 This section provides functions allowing to initialize the DMA Stream source
ganlikun 0:06036f8bee2d 172 and destination addresses, incrementation and data sizes, transfer direction,
ganlikun 0:06036f8bee2d 173 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
ganlikun 0:06036f8bee2d 174 [..]
ganlikun 0:06036f8bee2d 175 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
ganlikun 0:06036f8bee2d 176 reference manual.
ganlikun 0:06036f8bee2d 177
ganlikun 0:06036f8bee2d 178 @endverbatim
ganlikun 0:06036f8bee2d 179 * @{
ganlikun 0:06036f8bee2d 180 */
ganlikun 0:06036f8bee2d 181
ganlikun 0:06036f8bee2d 182 /**
ganlikun 0:06036f8bee2d 183 * @brief Initialize the DMA according to the specified
ganlikun 0:06036f8bee2d 184 * parameters in the DMA_InitTypeDef and create the associated handle.
ganlikun 0:06036f8bee2d 185 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 186 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 187 * @retval HAL status
ganlikun 0:06036f8bee2d 188 */
ganlikun 0:06036f8bee2d 189 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 190 {
ganlikun 0:06036f8bee2d 191 uint32_t tmp = 0U;
ganlikun 0:06036f8bee2d 192 uint32_t tickstart = HAL_GetTick();
ganlikun 0:06036f8bee2d 193 DMA_Base_Registers *regs;
ganlikun 0:06036f8bee2d 194
ganlikun 0:06036f8bee2d 195 /* Check the DMA peripheral state */
ganlikun 0:06036f8bee2d 196 if(hdma == NULL)
ganlikun 0:06036f8bee2d 197 {
ganlikun 0:06036f8bee2d 198 return HAL_ERROR;
ganlikun 0:06036f8bee2d 199 }
ganlikun 0:06036f8bee2d 200
ganlikun 0:06036f8bee2d 201 /* Check the parameters */
ganlikun 0:06036f8bee2d 202 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
ganlikun 0:06036f8bee2d 203 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
ganlikun 0:06036f8bee2d 204 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
ganlikun 0:06036f8bee2d 205 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
ganlikun 0:06036f8bee2d 206 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
ganlikun 0:06036f8bee2d 207 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
ganlikun 0:06036f8bee2d 208 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
ganlikun 0:06036f8bee2d 209 assert_param(IS_DMA_MODE(hdma->Init.Mode));
ganlikun 0:06036f8bee2d 210 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
ganlikun 0:06036f8bee2d 211 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
ganlikun 0:06036f8bee2d 212 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
ganlikun 0:06036f8bee2d 213 when FIFO mode is enabled */
ganlikun 0:06036f8bee2d 214 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
ganlikun 0:06036f8bee2d 215 {
ganlikun 0:06036f8bee2d 216 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
ganlikun 0:06036f8bee2d 217 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
ganlikun 0:06036f8bee2d 218 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
ganlikun 0:06036f8bee2d 219 }
ganlikun 0:06036f8bee2d 220
ganlikun 0:06036f8bee2d 221 /* Allocate lock resource */
ganlikun 0:06036f8bee2d 222 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 223
ganlikun 0:06036f8bee2d 224 /* Change DMA peripheral state */
ganlikun 0:06036f8bee2d 225 hdma->State = HAL_DMA_STATE_BUSY;
ganlikun 0:06036f8bee2d 226
ganlikun 0:06036f8bee2d 227 /* Disable the peripheral */
ganlikun 0:06036f8bee2d 228 __HAL_DMA_DISABLE(hdma);
ganlikun 0:06036f8bee2d 229
ganlikun 0:06036f8bee2d 230 /* Check if the DMA Stream is effectively disabled */
ganlikun 0:06036f8bee2d 231 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
ganlikun 0:06036f8bee2d 232 {
ganlikun 0:06036f8bee2d 233 /* Check for the Timeout */
ganlikun 0:06036f8bee2d 234 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
ganlikun 0:06036f8bee2d 235 {
ganlikun 0:06036f8bee2d 236 /* Update error code */
ganlikun 0:06036f8bee2d 237 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
ganlikun 0:06036f8bee2d 238
ganlikun 0:06036f8bee2d 239 /* Change the DMA state */
ganlikun 0:06036f8bee2d 240 hdma->State = HAL_DMA_STATE_TIMEOUT;
ganlikun 0:06036f8bee2d 241
ganlikun 0:06036f8bee2d 242 return HAL_TIMEOUT;
ganlikun 0:06036f8bee2d 243 }
ganlikun 0:06036f8bee2d 244 }
ganlikun 0:06036f8bee2d 245
ganlikun 0:06036f8bee2d 246 /* Get the CR register value */
ganlikun 0:06036f8bee2d 247 tmp = hdma->Instance->CR;
ganlikun 0:06036f8bee2d 248
ganlikun 0:06036f8bee2d 249 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
ganlikun 0:06036f8bee2d 250 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
ganlikun 0:06036f8bee2d 251 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
ganlikun 0:06036f8bee2d 252 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
ganlikun 0:06036f8bee2d 253 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
ganlikun 0:06036f8bee2d 254
ganlikun 0:06036f8bee2d 255 /* Prepare the DMA Stream configuration */
ganlikun 0:06036f8bee2d 256 tmp |= hdma->Init.Channel | hdma->Init.Direction |
ganlikun 0:06036f8bee2d 257 hdma->Init.PeriphInc | hdma->Init.MemInc |
ganlikun 0:06036f8bee2d 258 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
ganlikun 0:06036f8bee2d 259 hdma->Init.Mode | hdma->Init.Priority;
ganlikun 0:06036f8bee2d 260
ganlikun 0:06036f8bee2d 261 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
ganlikun 0:06036f8bee2d 262 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
ganlikun 0:06036f8bee2d 263 {
ganlikun 0:06036f8bee2d 264 /* Get memory burst and peripheral burst */
ganlikun 0:06036f8bee2d 265 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
ganlikun 0:06036f8bee2d 266 }
ganlikun 0:06036f8bee2d 267
ganlikun 0:06036f8bee2d 268 /* Write to DMA Stream CR register */
ganlikun 0:06036f8bee2d 269 hdma->Instance->CR = tmp;
ganlikun 0:06036f8bee2d 270
ganlikun 0:06036f8bee2d 271 /* Get the FCR register value */
ganlikun 0:06036f8bee2d 272 tmp = hdma->Instance->FCR;
ganlikun 0:06036f8bee2d 273
ganlikun 0:06036f8bee2d 274 /* Clear Direct mode and FIFO threshold bits */
ganlikun 0:06036f8bee2d 275 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
ganlikun 0:06036f8bee2d 276
ganlikun 0:06036f8bee2d 277 /* Prepare the DMA Stream FIFO configuration */
ganlikun 0:06036f8bee2d 278 tmp |= hdma->Init.FIFOMode;
ganlikun 0:06036f8bee2d 279
ganlikun 0:06036f8bee2d 280 /* The FIFO threshold is not used when the FIFO mode is disabled */
ganlikun 0:06036f8bee2d 281 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
ganlikun 0:06036f8bee2d 282 {
ganlikun 0:06036f8bee2d 283 /* Get the FIFO threshold */
ganlikun 0:06036f8bee2d 284 tmp |= hdma->Init.FIFOThreshold;
ganlikun 0:06036f8bee2d 285
ganlikun 0:06036f8bee2d 286 /* Check compatibility between FIFO threshold level and size of the memory burst */
ganlikun 0:06036f8bee2d 287 /* for INCR4, INCR8, INCR16 bursts */
ganlikun 0:06036f8bee2d 288 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
ganlikun 0:06036f8bee2d 289 {
ganlikun 0:06036f8bee2d 290 if (DMA_CheckFifoParam(hdma) != HAL_OK)
ganlikun 0:06036f8bee2d 291 {
ganlikun 0:06036f8bee2d 292 /* Update error code */
ganlikun 0:06036f8bee2d 293 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
ganlikun 0:06036f8bee2d 294
ganlikun 0:06036f8bee2d 295 /* Change the DMA state */
ganlikun 0:06036f8bee2d 296 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 297
ganlikun 0:06036f8bee2d 298 return HAL_ERROR;
ganlikun 0:06036f8bee2d 299 }
ganlikun 0:06036f8bee2d 300 }
ganlikun 0:06036f8bee2d 301 }
ganlikun 0:06036f8bee2d 302
ganlikun 0:06036f8bee2d 303 /* Write to DMA Stream FCR */
ganlikun 0:06036f8bee2d 304 hdma->Instance->FCR = tmp;
ganlikun 0:06036f8bee2d 305
ganlikun 0:06036f8bee2d 306 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
ganlikun 0:06036f8bee2d 307 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
ganlikun 0:06036f8bee2d 308 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
ganlikun 0:06036f8bee2d 309
ganlikun 0:06036f8bee2d 310 /* Clear all interrupt flags */
ganlikun 0:06036f8bee2d 311 regs->IFCR = 0x3FU << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 312
ganlikun 0:06036f8bee2d 313 /* Initialize the error code */
ganlikun 0:06036f8bee2d 314 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
ganlikun 0:06036f8bee2d 315
ganlikun 0:06036f8bee2d 316 /* Initialize the DMA state */
ganlikun 0:06036f8bee2d 317 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 318
ganlikun 0:06036f8bee2d 319 return HAL_OK;
ganlikun 0:06036f8bee2d 320 }
ganlikun 0:06036f8bee2d 321
ganlikun 0:06036f8bee2d 322 /**
ganlikun 0:06036f8bee2d 323 * @brief DeInitializes the DMA peripheral
ganlikun 0:06036f8bee2d 324 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 325 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 326 * @retval HAL status
ganlikun 0:06036f8bee2d 327 */
ganlikun 0:06036f8bee2d 328 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 329 {
ganlikun 0:06036f8bee2d 330 DMA_Base_Registers *regs;
ganlikun 0:06036f8bee2d 331
ganlikun 0:06036f8bee2d 332 /* Check the DMA peripheral state */
ganlikun 0:06036f8bee2d 333 if(hdma == NULL)
ganlikun 0:06036f8bee2d 334 {
ganlikun 0:06036f8bee2d 335 return HAL_ERROR;
ganlikun 0:06036f8bee2d 336 }
ganlikun 0:06036f8bee2d 337
ganlikun 0:06036f8bee2d 338 /* Check the DMA peripheral state */
ganlikun 0:06036f8bee2d 339 if(hdma->State == HAL_DMA_STATE_BUSY)
ganlikun 0:06036f8bee2d 340 {
ganlikun 0:06036f8bee2d 341 /* Return error status */
ganlikun 0:06036f8bee2d 342 return HAL_BUSY;
ganlikun 0:06036f8bee2d 343 }
ganlikun 0:06036f8bee2d 344
ganlikun 0:06036f8bee2d 345 /* Check the parameters */
ganlikun 0:06036f8bee2d 346 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
ganlikun 0:06036f8bee2d 347
ganlikun 0:06036f8bee2d 348 /* Disable the selected DMA Streamx */
ganlikun 0:06036f8bee2d 349 __HAL_DMA_DISABLE(hdma);
ganlikun 0:06036f8bee2d 350
ganlikun 0:06036f8bee2d 351 /* Reset DMA Streamx control register */
ganlikun 0:06036f8bee2d 352 hdma->Instance->CR = 0U;
ganlikun 0:06036f8bee2d 353
ganlikun 0:06036f8bee2d 354 /* Reset DMA Streamx number of data to transfer register */
ganlikun 0:06036f8bee2d 355 hdma->Instance->NDTR = 0U;
ganlikun 0:06036f8bee2d 356
ganlikun 0:06036f8bee2d 357 /* Reset DMA Streamx peripheral address register */
ganlikun 0:06036f8bee2d 358 hdma->Instance->PAR = 0U;
ganlikun 0:06036f8bee2d 359
ganlikun 0:06036f8bee2d 360 /* Reset DMA Streamx memory 0 address register */
ganlikun 0:06036f8bee2d 361 hdma->Instance->M0AR = 0U;
ganlikun 0:06036f8bee2d 362
ganlikun 0:06036f8bee2d 363 /* Reset DMA Streamx memory 1 address register */
ganlikun 0:06036f8bee2d 364 hdma->Instance->M1AR = 0U;
ganlikun 0:06036f8bee2d 365
ganlikun 0:06036f8bee2d 366 /* Reset DMA Streamx FIFO control register */
ganlikun 0:06036f8bee2d 367 hdma->Instance->FCR = 0x00000021U;
ganlikun 0:06036f8bee2d 368
ganlikun 0:06036f8bee2d 369 /* Get DMA steam Base Address */
ganlikun 0:06036f8bee2d 370 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
ganlikun 0:06036f8bee2d 371
ganlikun 0:06036f8bee2d 372 /* Clear all interrupt flags at correct offset within the register */
ganlikun 0:06036f8bee2d 373 regs->IFCR = 0x3FU << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 374
ganlikun 0:06036f8bee2d 375 /* Initialize the error code */
ganlikun 0:06036f8bee2d 376 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
ganlikun 0:06036f8bee2d 377
ganlikun 0:06036f8bee2d 378 /* Initialize the DMA state */
ganlikun 0:06036f8bee2d 379 hdma->State = HAL_DMA_STATE_RESET;
ganlikun 0:06036f8bee2d 380
ganlikun 0:06036f8bee2d 381 /* Release Lock */
ganlikun 0:06036f8bee2d 382 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 383
ganlikun 0:06036f8bee2d 384 return HAL_OK;
ganlikun 0:06036f8bee2d 385 }
ganlikun 0:06036f8bee2d 386
ganlikun 0:06036f8bee2d 387 /**
ganlikun 0:06036f8bee2d 388 * @}
ganlikun 0:06036f8bee2d 389 */
ganlikun 0:06036f8bee2d 390
ganlikun 0:06036f8bee2d 391 /** @addtogroup DMA_Exported_Functions_Group2
ganlikun 0:06036f8bee2d 392 *
ganlikun 0:06036f8bee2d 393 @verbatim
ganlikun 0:06036f8bee2d 394 ===============================================================================
ganlikun 0:06036f8bee2d 395 ##### IO operation functions #####
ganlikun 0:06036f8bee2d 396 ===============================================================================
ganlikun 0:06036f8bee2d 397 [..] This section provides functions allowing to:
ganlikun 0:06036f8bee2d 398 (+) Configure the source, destination address and data length and Start DMA transfer
ganlikun 0:06036f8bee2d 399 (+) Configure the source, destination address and data length and
ganlikun 0:06036f8bee2d 400 Start DMA transfer with interrupt
ganlikun 0:06036f8bee2d 401 (+) Abort DMA transfer
ganlikun 0:06036f8bee2d 402 (+) Poll for transfer complete
ganlikun 0:06036f8bee2d 403 (+) Handle DMA interrupt request
ganlikun 0:06036f8bee2d 404
ganlikun 0:06036f8bee2d 405 @endverbatim
ganlikun 0:06036f8bee2d 406 * @{
ganlikun 0:06036f8bee2d 407 */
ganlikun 0:06036f8bee2d 408
ganlikun 0:06036f8bee2d 409 /**
ganlikun 0:06036f8bee2d 410 * @brief Starts the DMA Transfer.
ganlikun 0:06036f8bee2d 411 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 412 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 413 * @param SrcAddress: The source memory Buffer address
ganlikun 0:06036f8bee2d 414 * @param DstAddress: The destination memory Buffer address
ganlikun 0:06036f8bee2d 415 * @param DataLength: The length of data to be transferred from source to destination
ganlikun 0:06036f8bee2d 416 * @retval HAL status
ganlikun 0:06036f8bee2d 417 */
ganlikun 0:06036f8bee2d 418 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
ganlikun 0:06036f8bee2d 419 {
ganlikun 0:06036f8bee2d 420 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:06036f8bee2d 421
ganlikun 0:06036f8bee2d 422 /* Check the parameters */
ganlikun 0:06036f8bee2d 423 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
ganlikun 0:06036f8bee2d 424
ganlikun 0:06036f8bee2d 425 /* Process locked */
ganlikun 0:06036f8bee2d 426 __HAL_LOCK(hdma);
ganlikun 0:06036f8bee2d 427
ganlikun 0:06036f8bee2d 428 if(HAL_DMA_STATE_READY == hdma->State)
ganlikun 0:06036f8bee2d 429 {
ganlikun 0:06036f8bee2d 430 /* Change DMA peripheral state */
ganlikun 0:06036f8bee2d 431 hdma->State = HAL_DMA_STATE_BUSY;
ganlikun 0:06036f8bee2d 432
ganlikun 0:06036f8bee2d 433 /* Initialize the error code */
ganlikun 0:06036f8bee2d 434 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
ganlikun 0:06036f8bee2d 435
ganlikun 0:06036f8bee2d 436 /* Configure the source, destination address and the data length */
ganlikun 0:06036f8bee2d 437 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
ganlikun 0:06036f8bee2d 438
ganlikun 0:06036f8bee2d 439 /* Enable the Peripheral */
ganlikun 0:06036f8bee2d 440 __HAL_DMA_ENABLE(hdma);
ganlikun 0:06036f8bee2d 441 }
ganlikun 0:06036f8bee2d 442 else
ganlikun 0:06036f8bee2d 443 {
ganlikun 0:06036f8bee2d 444 /* Process unlocked */
ganlikun 0:06036f8bee2d 445 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 446
ganlikun 0:06036f8bee2d 447 /* Return error status */
ganlikun 0:06036f8bee2d 448 status = HAL_BUSY;
ganlikun 0:06036f8bee2d 449 }
ganlikun 0:06036f8bee2d 450 return status;
ganlikun 0:06036f8bee2d 451 }
ganlikun 0:06036f8bee2d 452
ganlikun 0:06036f8bee2d 453 /**
ganlikun 0:06036f8bee2d 454 * @brief Start the DMA Transfer with interrupt enabled.
ganlikun 0:06036f8bee2d 455 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 456 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 457 * @param SrcAddress: The source memory Buffer address
ganlikun 0:06036f8bee2d 458 * @param DstAddress: The destination memory Buffer address
ganlikun 0:06036f8bee2d 459 * @param DataLength: The length of data to be transferred from source to destination
ganlikun 0:06036f8bee2d 460 * @retval HAL status
ganlikun 0:06036f8bee2d 461 */
ganlikun 0:06036f8bee2d 462 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
ganlikun 0:06036f8bee2d 463 {
ganlikun 0:06036f8bee2d 464 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:06036f8bee2d 465
ganlikun 0:06036f8bee2d 466 /* calculate DMA base and stream number */
ganlikun 0:06036f8bee2d 467 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
ganlikun 0:06036f8bee2d 468
ganlikun 0:06036f8bee2d 469 /* Check the parameters */
ganlikun 0:06036f8bee2d 470 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
ganlikun 0:06036f8bee2d 471
ganlikun 0:06036f8bee2d 472 /* Process locked */
ganlikun 0:06036f8bee2d 473 __HAL_LOCK(hdma);
ganlikun 0:06036f8bee2d 474
ganlikun 0:06036f8bee2d 475 if(HAL_DMA_STATE_READY == hdma->State)
ganlikun 0:06036f8bee2d 476 {
ganlikun 0:06036f8bee2d 477 /* Change DMA peripheral state */
ganlikun 0:06036f8bee2d 478 hdma->State = HAL_DMA_STATE_BUSY;
ganlikun 0:06036f8bee2d 479
ganlikun 0:06036f8bee2d 480 /* Initialize the error code */
ganlikun 0:06036f8bee2d 481 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
ganlikun 0:06036f8bee2d 482
ganlikun 0:06036f8bee2d 483 /* Configure the source, destination address and the data length */
ganlikun 0:06036f8bee2d 484 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
ganlikun 0:06036f8bee2d 485
ganlikun 0:06036f8bee2d 486 /* Clear all interrupt flags at correct offset within the register */
ganlikun 0:06036f8bee2d 487 regs->IFCR = 0x3FU << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 488
ganlikun 0:06036f8bee2d 489 /* Enable Common interrupts*/
ganlikun 0:06036f8bee2d 490 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
ganlikun 0:06036f8bee2d 491 hdma->Instance->FCR |= DMA_IT_FE;
ganlikun 0:06036f8bee2d 492
ganlikun 0:06036f8bee2d 493 if(hdma->XferHalfCpltCallback != NULL)
ganlikun 0:06036f8bee2d 494 {
ganlikun 0:06036f8bee2d 495 hdma->Instance->CR |= DMA_IT_HT;
ganlikun 0:06036f8bee2d 496 }
ganlikun 0:06036f8bee2d 497
ganlikun 0:06036f8bee2d 498 /* Enable the Peripheral */
ganlikun 0:06036f8bee2d 499 __HAL_DMA_ENABLE(hdma);
ganlikun 0:06036f8bee2d 500 }
ganlikun 0:06036f8bee2d 501 else
ganlikun 0:06036f8bee2d 502 {
ganlikun 0:06036f8bee2d 503 /* Process unlocked */
ganlikun 0:06036f8bee2d 504 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 505
ganlikun 0:06036f8bee2d 506 /* Return error status */
ganlikun 0:06036f8bee2d 507 status = HAL_BUSY;
ganlikun 0:06036f8bee2d 508 }
ganlikun 0:06036f8bee2d 509
ganlikun 0:06036f8bee2d 510 return status;
ganlikun 0:06036f8bee2d 511 }
ganlikun 0:06036f8bee2d 512
ganlikun 0:06036f8bee2d 513 /**
ganlikun 0:06036f8bee2d 514 * @brief Aborts the DMA Transfer.
ganlikun 0:06036f8bee2d 515 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 516 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 517 *
ganlikun 0:06036f8bee2d 518 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
ganlikun 0:06036f8bee2d 519 * effectively disabled is added. If a Stream is disabled
ganlikun 0:06036f8bee2d 520 * while a data transfer is ongoing, the current data will be transferred
ganlikun 0:06036f8bee2d 521 * and the Stream will be effectively disabled only after the transfer of
ganlikun 0:06036f8bee2d 522 * this single data is finished.
ganlikun 0:06036f8bee2d 523 * @retval HAL status
ganlikun 0:06036f8bee2d 524 */
ganlikun 0:06036f8bee2d 525 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 526 {
ganlikun 0:06036f8bee2d 527 /* calculate DMA base and stream number */
ganlikun 0:06036f8bee2d 528 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
ganlikun 0:06036f8bee2d 529
ganlikun 0:06036f8bee2d 530 uint32_t tickstart = HAL_GetTick();
ganlikun 0:06036f8bee2d 531
ganlikun 0:06036f8bee2d 532 if(hdma->State != HAL_DMA_STATE_BUSY)
ganlikun 0:06036f8bee2d 533 {
ganlikun 0:06036f8bee2d 534 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
ganlikun 0:06036f8bee2d 535
ganlikun 0:06036f8bee2d 536 /* Process Unlocked */
ganlikun 0:06036f8bee2d 537 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 538
ganlikun 0:06036f8bee2d 539 return HAL_ERROR;
ganlikun 0:06036f8bee2d 540 }
ganlikun 0:06036f8bee2d 541 else
ganlikun 0:06036f8bee2d 542 {
ganlikun 0:06036f8bee2d 543 /* Disable all the transfer interrupts */
ganlikun 0:06036f8bee2d 544 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
ganlikun 0:06036f8bee2d 545 hdma->Instance->FCR &= ~(DMA_IT_FE);
ganlikun 0:06036f8bee2d 546
ganlikun 0:06036f8bee2d 547 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
ganlikun 0:06036f8bee2d 548 {
ganlikun 0:06036f8bee2d 549 hdma->Instance->CR &= ~(DMA_IT_HT);
ganlikun 0:06036f8bee2d 550 }
ganlikun 0:06036f8bee2d 551
ganlikun 0:06036f8bee2d 552 /* Disable the stream */
ganlikun 0:06036f8bee2d 553 __HAL_DMA_DISABLE(hdma);
ganlikun 0:06036f8bee2d 554
ganlikun 0:06036f8bee2d 555 /* Check if the DMA Stream is effectively disabled */
ganlikun 0:06036f8bee2d 556 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
ganlikun 0:06036f8bee2d 557 {
ganlikun 0:06036f8bee2d 558 /* Check for the Timeout */
ganlikun 0:06036f8bee2d 559 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
ganlikun 0:06036f8bee2d 560 {
ganlikun 0:06036f8bee2d 561 /* Update error code */
ganlikun 0:06036f8bee2d 562 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
ganlikun 0:06036f8bee2d 563
ganlikun 0:06036f8bee2d 564 /* Process Unlocked */
ganlikun 0:06036f8bee2d 565 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 566
ganlikun 0:06036f8bee2d 567 /* Change the DMA state */
ganlikun 0:06036f8bee2d 568 hdma->State = HAL_DMA_STATE_TIMEOUT;
ganlikun 0:06036f8bee2d 569
ganlikun 0:06036f8bee2d 570 return HAL_TIMEOUT;
ganlikun 0:06036f8bee2d 571 }
ganlikun 0:06036f8bee2d 572 }
ganlikun 0:06036f8bee2d 573
ganlikun 0:06036f8bee2d 574 /* Clear all interrupt flags at correct offset within the register */
ganlikun 0:06036f8bee2d 575 regs->IFCR = 0x3FU << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 576
ganlikun 0:06036f8bee2d 577 /* Process Unlocked */
ganlikun 0:06036f8bee2d 578 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 579
ganlikun 0:06036f8bee2d 580 /* Change the DMA state*/
ganlikun 0:06036f8bee2d 581 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 582 }
ganlikun 0:06036f8bee2d 583 return HAL_OK;
ganlikun 0:06036f8bee2d 584 }
ganlikun 0:06036f8bee2d 585
ganlikun 0:06036f8bee2d 586 /**
ganlikun 0:06036f8bee2d 587 * @brief Aborts the DMA Transfer in Interrupt mode.
ganlikun 0:06036f8bee2d 588 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 589 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 590 * @retval HAL status
ganlikun 0:06036f8bee2d 591 */
ganlikun 0:06036f8bee2d 592 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 593 {
ganlikun 0:06036f8bee2d 594 if(hdma->State != HAL_DMA_STATE_BUSY)
ganlikun 0:06036f8bee2d 595 {
ganlikun 0:06036f8bee2d 596 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
ganlikun 0:06036f8bee2d 597 return HAL_ERROR;
ganlikun 0:06036f8bee2d 598 }
ganlikun 0:06036f8bee2d 599 else
ganlikun 0:06036f8bee2d 600 {
ganlikun 0:06036f8bee2d 601 /* Set Abort State */
ganlikun 0:06036f8bee2d 602 hdma->State = HAL_DMA_STATE_ABORT;
ganlikun 0:06036f8bee2d 603
ganlikun 0:06036f8bee2d 604 /* Disable the stream */
ganlikun 0:06036f8bee2d 605 __HAL_DMA_DISABLE(hdma);
ganlikun 0:06036f8bee2d 606 }
ganlikun 0:06036f8bee2d 607
ganlikun 0:06036f8bee2d 608 return HAL_OK;
ganlikun 0:06036f8bee2d 609 }
ganlikun 0:06036f8bee2d 610
ganlikun 0:06036f8bee2d 611 /**
ganlikun 0:06036f8bee2d 612 * @brief Polling for transfer complete.
ganlikun 0:06036f8bee2d 613 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 614 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 615 * @param CompleteLevel: Specifies the DMA level complete.
ganlikun 0:06036f8bee2d 616 * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
ganlikun 0:06036f8bee2d 617 * This model could be used for debug purpose.
ganlikun 0:06036f8bee2d 618 * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
ganlikun 0:06036f8bee2d 619 * @param Timeout: Timeout duration.
ganlikun 0:06036f8bee2d 620 * @retval HAL status
ganlikun 0:06036f8bee2d 621 */
ganlikun 0:06036f8bee2d 622 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
ganlikun 0:06036f8bee2d 623 {
ganlikun 0:06036f8bee2d 624 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:06036f8bee2d 625 uint32_t mask_cpltlevel;
ganlikun 0:06036f8bee2d 626 uint32_t tickstart = HAL_GetTick();
ganlikun 0:06036f8bee2d 627 uint32_t tmpisr;
ganlikun 0:06036f8bee2d 628
ganlikun 0:06036f8bee2d 629 /* calculate DMA base and stream number */
ganlikun 0:06036f8bee2d 630 DMA_Base_Registers *regs;
ganlikun 0:06036f8bee2d 631
ganlikun 0:06036f8bee2d 632 if(HAL_DMA_STATE_BUSY != hdma->State)
ganlikun 0:06036f8bee2d 633 {
ganlikun 0:06036f8bee2d 634 /* No transfer ongoing */
ganlikun 0:06036f8bee2d 635 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
ganlikun 0:06036f8bee2d 636 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 637 return HAL_ERROR;
ganlikun 0:06036f8bee2d 638 }
ganlikun 0:06036f8bee2d 639
ganlikun 0:06036f8bee2d 640 /* Polling mode not supported in circular mode and double buffering mode */
ganlikun 0:06036f8bee2d 641 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
ganlikun 0:06036f8bee2d 642 {
ganlikun 0:06036f8bee2d 643 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
ganlikun 0:06036f8bee2d 644 return HAL_ERROR;
ganlikun 0:06036f8bee2d 645 }
ganlikun 0:06036f8bee2d 646
ganlikun 0:06036f8bee2d 647 /* Get the level transfer complete flag */
ganlikun 0:06036f8bee2d 648 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
ganlikun 0:06036f8bee2d 649 {
ganlikun 0:06036f8bee2d 650 /* Transfer Complete flag */
ganlikun 0:06036f8bee2d 651 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 652 }
ganlikun 0:06036f8bee2d 653 else
ganlikun 0:06036f8bee2d 654 {
ganlikun 0:06036f8bee2d 655 /* Half Transfer Complete flag */
ganlikun 0:06036f8bee2d 656 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 657 }
ganlikun 0:06036f8bee2d 658
ganlikun 0:06036f8bee2d 659 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
ganlikun 0:06036f8bee2d 660 tmpisr = regs->ISR;
ganlikun 0:06036f8bee2d 661
ganlikun 0:06036f8bee2d 662 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
ganlikun 0:06036f8bee2d 663 {
ganlikun 0:06036f8bee2d 664 /* Check for the Timeout (Not applicable in circular mode)*/
ganlikun 0:06036f8bee2d 665 if(Timeout != HAL_MAX_DELAY)
ganlikun 0:06036f8bee2d 666 {
ganlikun 0:06036f8bee2d 667 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
ganlikun 0:06036f8bee2d 668 {
ganlikun 0:06036f8bee2d 669 /* Update error code */
ganlikun 0:06036f8bee2d 670 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
ganlikun 0:06036f8bee2d 671
ganlikun 0:06036f8bee2d 672 /* Process Unlocked */
ganlikun 0:06036f8bee2d 673 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 674
ganlikun 0:06036f8bee2d 675 /* Change the DMA state */
ganlikun 0:06036f8bee2d 676 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 677
ganlikun 0:06036f8bee2d 678 return HAL_TIMEOUT;
ganlikun 0:06036f8bee2d 679 }
ganlikun 0:06036f8bee2d 680 }
ganlikun 0:06036f8bee2d 681
ganlikun 0:06036f8bee2d 682 /* Get the ISR register value */
ganlikun 0:06036f8bee2d 683 tmpisr = regs->ISR;
ganlikun 0:06036f8bee2d 684
ganlikun 0:06036f8bee2d 685 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 686 {
ganlikun 0:06036f8bee2d 687 /* Update error code */
ganlikun 0:06036f8bee2d 688 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
ganlikun 0:06036f8bee2d 689
ganlikun 0:06036f8bee2d 690 /* Clear the transfer error flag */
ganlikun 0:06036f8bee2d 691 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 692 }
ganlikun 0:06036f8bee2d 693
ganlikun 0:06036f8bee2d 694 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 695 {
ganlikun 0:06036f8bee2d 696 /* Update error code */
ganlikun 0:06036f8bee2d 697 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
ganlikun 0:06036f8bee2d 698
ganlikun 0:06036f8bee2d 699 /* Clear the FIFO error flag */
ganlikun 0:06036f8bee2d 700 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 701 }
ganlikun 0:06036f8bee2d 702
ganlikun 0:06036f8bee2d 703 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 704 {
ganlikun 0:06036f8bee2d 705 /* Update error code */
ganlikun 0:06036f8bee2d 706 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
ganlikun 0:06036f8bee2d 707
ganlikun 0:06036f8bee2d 708 /* Clear the Direct Mode error flag */
ganlikun 0:06036f8bee2d 709 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 710 }
ganlikun 0:06036f8bee2d 711 tmpisr = regs->ISR;
ganlikun 0:06036f8bee2d 712 }
ganlikun 0:06036f8bee2d 713
ganlikun 0:06036f8bee2d 714 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
ganlikun 0:06036f8bee2d 715 {
ganlikun 0:06036f8bee2d 716 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
ganlikun 0:06036f8bee2d 717 {
ganlikun 0:06036f8bee2d 718 HAL_DMA_Abort(hdma);
ganlikun 0:06036f8bee2d 719
ganlikun 0:06036f8bee2d 720 /* Clear the half transfer and transfer complete flags */
ganlikun 0:06036f8bee2d 721 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 722
ganlikun 0:06036f8bee2d 723 /* Process Unlocked */
ganlikun 0:06036f8bee2d 724 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 725
ganlikun 0:06036f8bee2d 726 /* Change the DMA state */
ganlikun 0:06036f8bee2d 727 hdma->State= HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 728
ganlikun 0:06036f8bee2d 729 return HAL_ERROR;
ganlikun 0:06036f8bee2d 730 }
ganlikun 0:06036f8bee2d 731 }
ganlikun 0:06036f8bee2d 732
ganlikun 0:06036f8bee2d 733 /* Get the level transfer complete flag */
ganlikun 0:06036f8bee2d 734 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
ganlikun 0:06036f8bee2d 735 {
ganlikun 0:06036f8bee2d 736 /* Clear the half transfer and transfer complete flags */
ganlikun 0:06036f8bee2d 737 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 738
ganlikun 0:06036f8bee2d 739 /* Process Unlocked */
ganlikun 0:06036f8bee2d 740 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 741
ganlikun 0:06036f8bee2d 742 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 743 }
ganlikun 0:06036f8bee2d 744 else
ganlikun 0:06036f8bee2d 745 {
ganlikun 0:06036f8bee2d 746 /* Clear the half transfer and transfer complete flags */
ganlikun 0:06036f8bee2d 747 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 748 }
ganlikun 0:06036f8bee2d 749
ganlikun 0:06036f8bee2d 750 return status;
ganlikun 0:06036f8bee2d 751 }
ganlikun 0:06036f8bee2d 752
ganlikun 0:06036f8bee2d 753 /**
ganlikun 0:06036f8bee2d 754 * @brief Handles DMA interrupt request.
ganlikun 0:06036f8bee2d 755 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 756 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 757 * @retval None
ganlikun 0:06036f8bee2d 758 */
ganlikun 0:06036f8bee2d 759 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 760 {
ganlikun 0:06036f8bee2d 761 uint32_t tmpisr;
ganlikun 0:06036f8bee2d 762 __IO uint32_t count = 0U;
ganlikun 0:06036f8bee2d 763 uint32_t timeout = SystemCoreClock / 9600U;
ganlikun 0:06036f8bee2d 764
ganlikun 0:06036f8bee2d 765 /* calculate DMA base and stream number */
ganlikun 0:06036f8bee2d 766 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
ganlikun 0:06036f8bee2d 767
ganlikun 0:06036f8bee2d 768 tmpisr = regs->ISR;
ganlikun 0:06036f8bee2d 769
ganlikun 0:06036f8bee2d 770 /* Transfer Error Interrupt management ***************************************/
ganlikun 0:06036f8bee2d 771 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 772 {
ganlikun 0:06036f8bee2d 773 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
ganlikun 0:06036f8bee2d 774 {
ganlikun 0:06036f8bee2d 775 /* Disable the transfer error interrupt */
ganlikun 0:06036f8bee2d 776 hdma->Instance->CR &= ~(DMA_IT_TE);
ganlikun 0:06036f8bee2d 777
ganlikun 0:06036f8bee2d 778 /* Clear the transfer error flag */
ganlikun 0:06036f8bee2d 779 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 780
ganlikun 0:06036f8bee2d 781 /* Update error code */
ganlikun 0:06036f8bee2d 782 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
ganlikun 0:06036f8bee2d 783 }
ganlikun 0:06036f8bee2d 784 }
ganlikun 0:06036f8bee2d 785 /* FIFO Error Interrupt management ******************************************/
ganlikun 0:06036f8bee2d 786 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 787 {
ganlikun 0:06036f8bee2d 788 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
ganlikun 0:06036f8bee2d 789 {
ganlikun 0:06036f8bee2d 790 /* Clear the FIFO error flag */
ganlikun 0:06036f8bee2d 791 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 792
ganlikun 0:06036f8bee2d 793 /* Update error code */
ganlikun 0:06036f8bee2d 794 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
ganlikun 0:06036f8bee2d 795 }
ganlikun 0:06036f8bee2d 796 }
ganlikun 0:06036f8bee2d 797 /* Direct Mode Error Interrupt management ***********************************/
ganlikun 0:06036f8bee2d 798 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 799 {
ganlikun 0:06036f8bee2d 800 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
ganlikun 0:06036f8bee2d 801 {
ganlikun 0:06036f8bee2d 802 /* Clear the direct mode error flag */
ganlikun 0:06036f8bee2d 803 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 804
ganlikun 0:06036f8bee2d 805 /* Update error code */
ganlikun 0:06036f8bee2d 806 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
ganlikun 0:06036f8bee2d 807 }
ganlikun 0:06036f8bee2d 808 }
ganlikun 0:06036f8bee2d 809 /* Half Transfer Complete Interrupt management ******************************/
ganlikun 0:06036f8bee2d 810 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 811 {
ganlikun 0:06036f8bee2d 812 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
ganlikun 0:06036f8bee2d 813 {
ganlikun 0:06036f8bee2d 814 /* Clear the half transfer complete flag */
ganlikun 0:06036f8bee2d 815 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 816
ganlikun 0:06036f8bee2d 817 /* Multi_Buffering mode enabled */
ganlikun 0:06036f8bee2d 818 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
ganlikun 0:06036f8bee2d 819 {
ganlikun 0:06036f8bee2d 820 /* Current memory buffer used is Memory 0 */
ganlikun 0:06036f8bee2d 821 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
ganlikun 0:06036f8bee2d 822 {
ganlikun 0:06036f8bee2d 823 if(hdma->XferHalfCpltCallback != NULL)
ganlikun 0:06036f8bee2d 824 {
ganlikun 0:06036f8bee2d 825 /* Half transfer callback */
ganlikun 0:06036f8bee2d 826 hdma->XferHalfCpltCallback(hdma);
ganlikun 0:06036f8bee2d 827 }
ganlikun 0:06036f8bee2d 828 }
ganlikun 0:06036f8bee2d 829 /* Current memory buffer used is Memory 1 */
ganlikun 0:06036f8bee2d 830 else
ganlikun 0:06036f8bee2d 831 {
ganlikun 0:06036f8bee2d 832 if(hdma->XferM1HalfCpltCallback != NULL)
ganlikun 0:06036f8bee2d 833 {
ganlikun 0:06036f8bee2d 834 /* Half transfer callback */
ganlikun 0:06036f8bee2d 835 hdma->XferM1HalfCpltCallback(hdma);
ganlikun 0:06036f8bee2d 836 }
ganlikun 0:06036f8bee2d 837 }
ganlikun 0:06036f8bee2d 838 }
ganlikun 0:06036f8bee2d 839 else
ganlikun 0:06036f8bee2d 840 {
ganlikun 0:06036f8bee2d 841 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
ganlikun 0:06036f8bee2d 842 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
ganlikun 0:06036f8bee2d 843 {
ganlikun 0:06036f8bee2d 844 /* Disable the half transfer interrupt */
ganlikun 0:06036f8bee2d 845 hdma->Instance->CR &= ~(DMA_IT_HT);
ganlikun 0:06036f8bee2d 846 }
ganlikun 0:06036f8bee2d 847
ganlikun 0:06036f8bee2d 848 if(hdma->XferHalfCpltCallback != NULL)
ganlikun 0:06036f8bee2d 849 {
ganlikun 0:06036f8bee2d 850 /* Half transfer callback */
ganlikun 0:06036f8bee2d 851 hdma->XferHalfCpltCallback(hdma);
ganlikun 0:06036f8bee2d 852 }
ganlikun 0:06036f8bee2d 853 }
ganlikun 0:06036f8bee2d 854 }
ganlikun 0:06036f8bee2d 855 }
ganlikun 0:06036f8bee2d 856 /* Transfer Complete Interrupt management ***********************************/
ganlikun 0:06036f8bee2d 857 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
ganlikun 0:06036f8bee2d 858 {
ganlikun 0:06036f8bee2d 859 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
ganlikun 0:06036f8bee2d 860 {
ganlikun 0:06036f8bee2d 861 /* Clear the transfer complete flag */
ganlikun 0:06036f8bee2d 862 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 863
ganlikun 0:06036f8bee2d 864 if(HAL_DMA_STATE_ABORT == hdma->State)
ganlikun 0:06036f8bee2d 865 {
ganlikun 0:06036f8bee2d 866 /* Disable all the transfer interrupts */
ganlikun 0:06036f8bee2d 867 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
ganlikun 0:06036f8bee2d 868 hdma->Instance->FCR &= ~(DMA_IT_FE);
ganlikun 0:06036f8bee2d 869
ganlikun 0:06036f8bee2d 870 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
ganlikun 0:06036f8bee2d 871 {
ganlikun 0:06036f8bee2d 872 hdma->Instance->CR &= ~(DMA_IT_HT);
ganlikun 0:06036f8bee2d 873 }
ganlikun 0:06036f8bee2d 874
ganlikun 0:06036f8bee2d 875 /* Clear all interrupt flags at correct offset within the register */
ganlikun 0:06036f8bee2d 876 regs->IFCR = 0x3FU << hdma->StreamIndex;
ganlikun 0:06036f8bee2d 877
ganlikun 0:06036f8bee2d 878 /* Process Unlocked */
ganlikun 0:06036f8bee2d 879 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 880
ganlikun 0:06036f8bee2d 881 /* Change the DMA state */
ganlikun 0:06036f8bee2d 882 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 883
ganlikun 0:06036f8bee2d 884 if(hdma->XferAbortCallback != NULL)
ganlikun 0:06036f8bee2d 885 {
ganlikun 0:06036f8bee2d 886 hdma->XferAbortCallback(hdma);
ganlikun 0:06036f8bee2d 887 }
ganlikun 0:06036f8bee2d 888 return;
ganlikun 0:06036f8bee2d 889 }
ganlikun 0:06036f8bee2d 890
ganlikun 0:06036f8bee2d 891 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
ganlikun 0:06036f8bee2d 892 {
ganlikun 0:06036f8bee2d 893 /* Current memory buffer used is Memory 0 */
ganlikun 0:06036f8bee2d 894 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
ganlikun 0:06036f8bee2d 895 {
ganlikun 0:06036f8bee2d 896 if(hdma->XferM1CpltCallback != NULL)
ganlikun 0:06036f8bee2d 897 {
ganlikun 0:06036f8bee2d 898 /* Transfer complete Callback for memory1 */
ganlikun 0:06036f8bee2d 899 hdma->XferM1CpltCallback(hdma);
ganlikun 0:06036f8bee2d 900 }
ganlikun 0:06036f8bee2d 901 }
ganlikun 0:06036f8bee2d 902 /* Current memory buffer used is Memory 1 */
ganlikun 0:06036f8bee2d 903 else
ganlikun 0:06036f8bee2d 904 {
ganlikun 0:06036f8bee2d 905 if(hdma->XferCpltCallback != NULL)
ganlikun 0:06036f8bee2d 906 {
ganlikun 0:06036f8bee2d 907 /* Transfer complete Callback for memory0 */
ganlikun 0:06036f8bee2d 908 hdma->XferCpltCallback(hdma);
ganlikun 0:06036f8bee2d 909 }
ganlikun 0:06036f8bee2d 910 }
ganlikun 0:06036f8bee2d 911 }
ganlikun 0:06036f8bee2d 912 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
ganlikun 0:06036f8bee2d 913 else
ganlikun 0:06036f8bee2d 914 {
ganlikun 0:06036f8bee2d 915 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
ganlikun 0:06036f8bee2d 916 {
ganlikun 0:06036f8bee2d 917 /* Disable the transfer complete interrupt */
ganlikun 0:06036f8bee2d 918 hdma->Instance->CR &= ~(DMA_IT_TC);
ganlikun 0:06036f8bee2d 919
ganlikun 0:06036f8bee2d 920 /* Process Unlocked */
ganlikun 0:06036f8bee2d 921 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 922
ganlikun 0:06036f8bee2d 923 /* Change the DMA state */
ganlikun 0:06036f8bee2d 924 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 925 }
ganlikun 0:06036f8bee2d 926
ganlikun 0:06036f8bee2d 927 if(hdma->XferCpltCallback != NULL)
ganlikun 0:06036f8bee2d 928 {
ganlikun 0:06036f8bee2d 929 /* Transfer complete callback */
ganlikun 0:06036f8bee2d 930 hdma->XferCpltCallback(hdma);
ganlikun 0:06036f8bee2d 931 }
ganlikun 0:06036f8bee2d 932 }
ganlikun 0:06036f8bee2d 933 }
ganlikun 0:06036f8bee2d 934 }
ganlikun 0:06036f8bee2d 935
ganlikun 0:06036f8bee2d 936 /* manage error case */
ganlikun 0:06036f8bee2d 937 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
ganlikun 0:06036f8bee2d 938 {
ganlikun 0:06036f8bee2d 939 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
ganlikun 0:06036f8bee2d 940 {
ganlikun 0:06036f8bee2d 941 hdma->State = HAL_DMA_STATE_ABORT;
ganlikun 0:06036f8bee2d 942
ganlikun 0:06036f8bee2d 943 /* Disable the stream */
ganlikun 0:06036f8bee2d 944 __HAL_DMA_DISABLE(hdma);
ganlikun 0:06036f8bee2d 945
ganlikun 0:06036f8bee2d 946 do
ganlikun 0:06036f8bee2d 947 {
ganlikun 0:06036f8bee2d 948 if (++count > timeout)
ganlikun 0:06036f8bee2d 949 {
ganlikun 0:06036f8bee2d 950 break;
ganlikun 0:06036f8bee2d 951 }
ganlikun 0:06036f8bee2d 952 }
ganlikun 0:06036f8bee2d 953 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
ganlikun 0:06036f8bee2d 954
ganlikun 0:06036f8bee2d 955 /* Process Unlocked */
ganlikun 0:06036f8bee2d 956 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 957
ganlikun 0:06036f8bee2d 958 /* Change the DMA state */
ganlikun 0:06036f8bee2d 959 hdma->State = HAL_DMA_STATE_READY;
ganlikun 0:06036f8bee2d 960 }
ganlikun 0:06036f8bee2d 961
ganlikun 0:06036f8bee2d 962 if(hdma->XferErrorCallback != NULL)
ganlikun 0:06036f8bee2d 963 {
ganlikun 0:06036f8bee2d 964 /* Transfer error callback */
ganlikun 0:06036f8bee2d 965 hdma->XferErrorCallback(hdma);
ganlikun 0:06036f8bee2d 966 }
ganlikun 0:06036f8bee2d 967 }
ganlikun 0:06036f8bee2d 968 }
ganlikun 0:06036f8bee2d 969
ganlikun 0:06036f8bee2d 970 /**
ganlikun 0:06036f8bee2d 971 * @brief Register callbacks
ganlikun 0:06036f8bee2d 972 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 973 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 974 * @param CallbackID: User Callback identifer
ganlikun 0:06036f8bee2d 975 * a DMA_HandleTypeDef structure as parameter.
ganlikun 0:06036f8bee2d 976 * @param pCallback: pointer to private callbacsk function which has pointer to
ganlikun 0:06036f8bee2d 977 * a DMA_HandleTypeDef structure as parameter.
ganlikun 0:06036f8bee2d 978 * @retval HAL status
ganlikun 0:06036f8bee2d 979 */
ganlikun 0:06036f8bee2d 980 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
ganlikun 0:06036f8bee2d 981 {
ganlikun 0:06036f8bee2d 982
ganlikun 0:06036f8bee2d 983 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:06036f8bee2d 984
ganlikun 0:06036f8bee2d 985 /* Process locked */
ganlikun 0:06036f8bee2d 986 __HAL_LOCK(hdma);
ganlikun 0:06036f8bee2d 987
ganlikun 0:06036f8bee2d 988 if(HAL_DMA_STATE_READY == hdma->State)
ganlikun 0:06036f8bee2d 989 {
ganlikun 0:06036f8bee2d 990 switch (CallbackID)
ganlikun 0:06036f8bee2d 991 {
ganlikun 0:06036f8bee2d 992 case HAL_DMA_XFER_CPLT_CB_ID:
ganlikun 0:06036f8bee2d 993 hdma->XferCpltCallback = pCallback;
ganlikun 0:06036f8bee2d 994 break;
ganlikun 0:06036f8bee2d 995
ganlikun 0:06036f8bee2d 996 case HAL_DMA_XFER_HALFCPLT_CB_ID:
ganlikun 0:06036f8bee2d 997 hdma->XferHalfCpltCallback = pCallback;
ganlikun 0:06036f8bee2d 998 break;
ganlikun 0:06036f8bee2d 999
ganlikun 0:06036f8bee2d 1000 case HAL_DMA_XFER_M1CPLT_CB_ID:
ganlikun 0:06036f8bee2d 1001 hdma->XferM1CpltCallback = pCallback;
ganlikun 0:06036f8bee2d 1002 break;
ganlikun 0:06036f8bee2d 1003
ganlikun 0:06036f8bee2d 1004 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
ganlikun 0:06036f8bee2d 1005 hdma->XferM1HalfCpltCallback = pCallback;
ganlikun 0:06036f8bee2d 1006 break;
ganlikun 0:06036f8bee2d 1007
ganlikun 0:06036f8bee2d 1008 case HAL_DMA_XFER_ERROR_CB_ID:
ganlikun 0:06036f8bee2d 1009 hdma->XferErrorCallback = pCallback;
ganlikun 0:06036f8bee2d 1010 break;
ganlikun 0:06036f8bee2d 1011
ganlikun 0:06036f8bee2d 1012 case HAL_DMA_XFER_ABORT_CB_ID:
ganlikun 0:06036f8bee2d 1013 hdma->XferAbortCallback = pCallback;
ganlikun 0:06036f8bee2d 1014 break;
ganlikun 0:06036f8bee2d 1015
ganlikun 0:06036f8bee2d 1016 default:
ganlikun 0:06036f8bee2d 1017 break;
ganlikun 0:06036f8bee2d 1018 }
ganlikun 0:06036f8bee2d 1019 }
ganlikun 0:06036f8bee2d 1020 else
ganlikun 0:06036f8bee2d 1021 {
ganlikun 0:06036f8bee2d 1022 /* Return error status */
ganlikun 0:06036f8bee2d 1023 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1024 }
ganlikun 0:06036f8bee2d 1025
ganlikun 0:06036f8bee2d 1026 /* Release Lock */
ganlikun 0:06036f8bee2d 1027 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 1028
ganlikun 0:06036f8bee2d 1029 return status;
ganlikun 0:06036f8bee2d 1030 }
ganlikun 0:06036f8bee2d 1031
ganlikun 0:06036f8bee2d 1032 /**
ganlikun 0:06036f8bee2d 1033 * @brief UnRegister callbacks
ganlikun 0:06036f8bee2d 1034 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 1035 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 1036 * @param CallbackID: User Callback identifer
ganlikun 0:06036f8bee2d 1037 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
ganlikun 0:06036f8bee2d 1038 * @retval HAL status
ganlikun 0:06036f8bee2d 1039 */
ganlikun 0:06036f8bee2d 1040 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
ganlikun 0:06036f8bee2d 1041 {
ganlikun 0:06036f8bee2d 1042 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:06036f8bee2d 1043
ganlikun 0:06036f8bee2d 1044 /* Process locked */
ganlikun 0:06036f8bee2d 1045 __HAL_LOCK(hdma);
ganlikun 0:06036f8bee2d 1046
ganlikun 0:06036f8bee2d 1047 if(HAL_DMA_STATE_READY == hdma->State)
ganlikun 0:06036f8bee2d 1048 {
ganlikun 0:06036f8bee2d 1049 switch (CallbackID)
ganlikun 0:06036f8bee2d 1050 {
ganlikun 0:06036f8bee2d 1051 case HAL_DMA_XFER_CPLT_CB_ID:
ganlikun 0:06036f8bee2d 1052 hdma->XferCpltCallback = NULL;
ganlikun 0:06036f8bee2d 1053 break;
ganlikun 0:06036f8bee2d 1054
ganlikun 0:06036f8bee2d 1055 case HAL_DMA_XFER_HALFCPLT_CB_ID:
ganlikun 0:06036f8bee2d 1056 hdma->XferHalfCpltCallback = NULL;
ganlikun 0:06036f8bee2d 1057 break;
ganlikun 0:06036f8bee2d 1058
ganlikun 0:06036f8bee2d 1059 case HAL_DMA_XFER_M1CPLT_CB_ID:
ganlikun 0:06036f8bee2d 1060 hdma->XferM1CpltCallback = NULL;
ganlikun 0:06036f8bee2d 1061 break;
ganlikun 0:06036f8bee2d 1062
ganlikun 0:06036f8bee2d 1063 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
ganlikun 0:06036f8bee2d 1064 hdma->XferM1HalfCpltCallback = NULL;
ganlikun 0:06036f8bee2d 1065 break;
ganlikun 0:06036f8bee2d 1066
ganlikun 0:06036f8bee2d 1067 case HAL_DMA_XFER_ERROR_CB_ID:
ganlikun 0:06036f8bee2d 1068 hdma->XferErrorCallback = NULL;
ganlikun 0:06036f8bee2d 1069 break;
ganlikun 0:06036f8bee2d 1070
ganlikun 0:06036f8bee2d 1071 case HAL_DMA_XFER_ABORT_CB_ID:
ganlikun 0:06036f8bee2d 1072 hdma->XferAbortCallback = NULL;
ganlikun 0:06036f8bee2d 1073 break;
ganlikun 0:06036f8bee2d 1074
ganlikun 0:06036f8bee2d 1075 case HAL_DMA_XFER_ALL_CB_ID:
ganlikun 0:06036f8bee2d 1076 hdma->XferCpltCallback = NULL;
ganlikun 0:06036f8bee2d 1077 hdma->XferHalfCpltCallback = NULL;
ganlikun 0:06036f8bee2d 1078 hdma->XferM1CpltCallback = NULL;
ganlikun 0:06036f8bee2d 1079 hdma->XferM1HalfCpltCallback = NULL;
ganlikun 0:06036f8bee2d 1080 hdma->XferErrorCallback = NULL;
ganlikun 0:06036f8bee2d 1081 hdma->XferAbortCallback = NULL;
ganlikun 0:06036f8bee2d 1082 break;
ganlikun 0:06036f8bee2d 1083
ganlikun 0:06036f8bee2d 1084 default:
ganlikun 0:06036f8bee2d 1085 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1086 break;
ganlikun 0:06036f8bee2d 1087 }
ganlikun 0:06036f8bee2d 1088 }
ganlikun 0:06036f8bee2d 1089 else
ganlikun 0:06036f8bee2d 1090 {
ganlikun 0:06036f8bee2d 1091 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1092 }
ganlikun 0:06036f8bee2d 1093
ganlikun 0:06036f8bee2d 1094 /* Release Lock */
ganlikun 0:06036f8bee2d 1095 __HAL_UNLOCK(hdma);
ganlikun 0:06036f8bee2d 1096
ganlikun 0:06036f8bee2d 1097 return status;
ganlikun 0:06036f8bee2d 1098 }
ganlikun 0:06036f8bee2d 1099
ganlikun 0:06036f8bee2d 1100 /**
ganlikun 0:06036f8bee2d 1101 * @}
ganlikun 0:06036f8bee2d 1102 */
ganlikun 0:06036f8bee2d 1103
ganlikun 0:06036f8bee2d 1104 /** @addtogroup DMA_Exported_Functions_Group3
ganlikun 0:06036f8bee2d 1105 *
ganlikun 0:06036f8bee2d 1106 @verbatim
ganlikun 0:06036f8bee2d 1107 ===============================================================================
ganlikun 0:06036f8bee2d 1108 ##### State and Errors functions #####
ganlikun 0:06036f8bee2d 1109 ===============================================================================
ganlikun 0:06036f8bee2d 1110 [..]
ganlikun 0:06036f8bee2d 1111 This subsection provides functions allowing to
ganlikun 0:06036f8bee2d 1112 (+) Check the DMA state
ganlikun 0:06036f8bee2d 1113 (+) Get error code
ganlikun 0:06036f8bee2d 1114
ganlikun 0:06036f8bee2d 1115 @endverbatim
ganlikun 0:06036f8bee2d 1116 * @{
ganlikun 0:06036f8bee2d 1117 */
ganlikun 0:06036f8bee2d 1118
ganlikun 0:06036f8bee2d 1119 /**
ganlikun 0:06036f8bee2d 1120 * @brief Returns the DMA state.
ganlikun 0:06036f8bee2d 1121 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 1122 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 1123 * @retval HAL state
ganlikun 0:06036f8bee2d 1124 */
ganlikun 0:06036f8bee2d 1125 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 1126 {
ganlikun 0:06036f8bee2d 1127 return hdma->State;
ganlikun 0:06036f8bee2d 1128 }
ganlikun 0:06036f8bee2d 1129
ganlikun 0:06036f8bee2d 1130 /**
ganlikun 0:06036f8bee2d 1131 * @brief Return the DMA error code
ganlikun 0:06036f8bee2d 1132 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 1133 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 1134 * @retval DMA Error Code
ganlikun 0:06036f8bee2d 1135 */
ganlikun 0:06036f8bee2d 1136 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 1137 {
ganlikun 0:06036f8bee2d 1138 return hdma->ErrorCode;
ganlikun 0:06036f8bee2d 1139 }
ganlikun 0:06036f8bee2d 1140
ganlikun 0:06036f8bee2d 1141 /**
ganlikun 0:06036f8bee2d 1142 * @}
ganlikun 0:06036f8bee2d 1143 */
ganlikun 0:06036f8bee2d 1144
ganlikun 0:06036f8bee2d 1145 /**
ganlikun 0:06036f8bee2d 1146 * @}
ganlikun 0:06036f8bee2d 1147 */
ganlikun 0:06036f8bee2d 1148
ganlikun 0:06036f8bee2d 1149 /** @addtogroup DMA_Private_Functions
ganlikun 0:06036f8bee2d 1150 * @{
ganlikun 0:06036f8bee2d 1151 */
ganlikun 0:06036f8bee2d 1152
ganlikun 0:06036f8bee2d 1153 /**
ganlikun 0:06036f8bee2d 1154 * @brief Sets the DMA Transfer parameter.
ganlikun 0:06036f8bee2d 1155 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 1156 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 1157 * @param SrcAddress: The source memory Buffer address
ganlikun 0:06036f8bee2d 1158 * @param DstAddress: The destination memory Buffer address
ganlikun 0:06036f8bee2d 1159 * @param DataLength: The length of data to be transferred from source to destination
ganlikun 0:06036f8bee2d 1160 * @retval HAL status
ganlikun 0:06036f8bee2d 1161 */
ganlikun 0:06036f8bee2d 1162 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
ganlikun 0:06036f8bee2d 1163 {
ganlikun 0:06036f8bee2d 1164 /* Clear DBM bit */
ganlikun 0:06036f8bee2d 1165 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
ganlikun 0:06036f8bee2d 1166
ganlikun 0:06036f8bee2d 1167 /* Configure DMA Stream data length */
ganlikun 0:06036f8bee2d 1168 hdma->Instance->NDTR = DataLength;
ganlikun 0:06036f8bee2d 1169
ganlikun 0:06036f8bee2d 1170 /* Peripheral to Memory */
ganlikun 0:06036f8bee2d 1171 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
ganlikun 0:06036f8bee2d 1172 {
ganlikun 0:06036f8bee2d 1173 /* Configure DMA Stream destination address */
ganlikun 0:06036f8bee2d 1174 hdma->Instance->PAR = DstAddress;
ganlikun 0:06036f8bee2d 1175
ganlikun 0:06036f8bee2d 1176 /* Configure DMA Stream source address */
ganlikun 0:06036f8bee2d 1177 hdma->Instance->M0AR = SrcAddress;
ganlikun 0:06036f8bee2d 1178 }
ganlikun 0:06036f8bee2d 1179 /* Memory to Peripheral */
ganlikun 0:06036f8bee2d 1180 else
ganlikun 0:06036f8bee2d 1181 {
ganlikun 0:06036f8bee2d 1182 /* Configure DMA Stream source address */
ganlikun 0:06036f8bee2d 1183 hdma->Instance->PAR = SrcAddress;
ganlikun 0:06036f8bee2d 1184
ganlikun 0:06036f8bee2d 1185 /* Configure DMA Stream destination address */
ganlikun 0:06036f8bee2d 1186 hdma->Instance->M0AR = DstAddress;
ganlikun 0:06036f8bee2d 1187 }
ganlikun 0:06036f8bee2d 1188 }
ganlikun 0:06036f8bee2d 1189
ganlikun 0:06036f8bee2d 1190 /**
ganlikun 0:06036f8bee2d 1191 * @brief Returns the DMA Stream base address depending on stream number
ganlikun 0:06036f8bee2d 1192 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 1193 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 1194 * @retval Stream base address
ganlikun 0:06036f8bee2d 1195 */
ganlikun 0:06036f8bee2d 1196 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 1197 {
ganlikun 0:06036f8bee2d 1198 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
ganlikun 0:06036f8bee2d 1199
ganlikun 0:06036f8bee2d 1200 /* lookup table for necessary bitshift of flags within status registers */
ganlikun 0:06036f8bee2d 1201 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
ganlikun 0:06036f8bee2d 1202 hdma->StreamIndex = flagBitshiftOffset[stream_number];
ganlikun 0:06036f8bee2d 1203
ganlikun 0:06036f8bee2d 1204 if (stream_number > 3U)
ganlikun 0:06036f8bee2d 1205 {
ganlikun 0:06036f8bee2d 1206 /* return pointer to HISR and HIFCR */
ganlikun 0:06036f8bee2d 1207 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
ganlikun 0:06036f8bee2d 1208 }
ganlikun 0:06036f8bee2d 1209 else
ganlikun 0:06036f8bee2d 1210 {
ganlikun 0:06036f8bee2d 1211 /* return pointer to LISR and LIFCR */
ganlikun 0:06036f8bee2d 1212 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
ganlikun 0:06036f8bee2d 1213 }
ganlikun 0:06036f8bee2d 1214
ganlikun 0:06036f8bee2d 1215 return hdma->StreamBaseAddress;
ganlikun 0:06036f8bee2d 1216 }
ganlikun 0:06036f8bee2d 1217
ganlikun 0:06036f8bee2d 1218 /**
ganlikun 0:06036f8bee2d 1219 * @brief Check compatibility between FIFO threshold level and size of the memory burst
ganlikun 0:06036f8bee2d 1220 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
ganlikun 0:06036f8bee2d 1221 * the configuration information for the specified DMA Stream.
ganlikun 0:06036f8bee2d 1222 * @retval HAL status
ganlikun 0:06036f8bee2d 1223 */
ganlikun 0:06036f8bee2d 1224 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
ganlikun 0:06036f8bee2d 1225 {
ganlikun 0:06036f8bee2d 1226 HAL_StatusTypeDef status = HAL_OK;
ganlikun 0:06036f8bee2d 1227 uint32_t tmp = hdma->Init.FIFOThreshold;
ganlikun 0:06036f8bee2d 1228
ganlikun 0:06036f8bee2d 1229 /* Memory Data size equal to Byte */
ganlikun 0:06036f8bee2d 1230 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
ganlikun 0:06036f8bee2d 1231 {
ganlikun 0:06036f8bee2d 1232 switch (tmp)
ganlikun 0:06036f8bee2d 1233 {
ganlikun 0:06036f8bee2d 1234 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
ganlikun 0:06036f8bee2d 1235 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
ganlikun 0:06036f8bee2d 1236 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
ganlikun 0:06036f8bee2d 1237 {
ganlikun 0:06036f8bee2d 1238 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1239 }
ganlikun 0:06036f8bee2d 1240 break;
ganlikun 0:06036f8bee2d 1241 case DMA_FIFO_THRESHOLD_HALFFULL:
ganlikun 0:06036f8bee2d 1242 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
ganlikun 0:06036f8bee2d 1243 {
ganlikun 0:06036f8bee2d 1244 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1245 }
ganlikun 0:06036f8bee2d 1246 break;
ganlikun 0:06036f8bee2d 1247 case DMA_FIFO_THRESHOLD_FULL:
ganlikun 0:06036f8bee2d 1248 break;
ganlikun 0:06036f8bee2d 1249 default:
ganlikun 0:06036f8bee2d 1250 break;
ganlikun 0:06036f8bee2d 1251 }
ganlikun 0:06036f8bee2d 1252 }
ganlikun 0:06036f8bee2d 1253
ganlikun 0:06036f8bee2d 1254 /* Memory Data size equal to Half-Word */
ganlikun 0:06036f8bee2d 1255 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
ganlikun 0:06036f8bee2d 1256 {
ganlikun 0:06036f8bee2d 1257 switch (tmp)
ganlikun 0:06036f8bee2d 1258 {
ganlikun 0:06036f8bee2d 1259 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
ganlikun 0:06036f8bee2d 1260 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
ganlikun 0:06036f8bee2d 1261 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1262 break;
ganlikun 0:06036f8bee2d 1263 case DMA_FIFO_THRESHOLD_HALFFULL:
ganlikun 0:06036f8bee2d 1264 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
ganlikun 0:06036f8bee2d 1265 {
ganlikun 0:06036f8bee2d 1266 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1267 }
ganlikun 0:06036f8bee2d 1268 break;
ganlikun 0:06036f8bee2d 1269 case DMA_FIFO_THRESHOLD_FULL:
ganlikun 0:06036f8bee2d 1270 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
ganlikun 0:06036f8bee2d 1271 {
ganlikun 0:06036f8bee2d 1272 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1273 }
ganlikun 0:06036f8bee2d 1274 break;
ganlikun 0:06036f8bee2d 1275 default:
ganlikun 0:06036f8bee2d 1276 break;
ganlikun 0:06036f8bee2d 1277 }
ganlikun 0:06036f8bee2d 1278 }
ganlikun 0:06036f8bee2d 1279
ganlikun 0:06036f8bee2d 1280 /* Memory Data size equal to Word */
ganlikun 0:06036f8bee2d 1281 else
ganlikun 0:06036f8bee2d 1282 {
ganlikun 0:06036f8bee2d 1283 switch (tmp)
ganlikun 0:06036f8bee2d 1284 {
ganlikun 0:06036f8bee2d 1285 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
ganlikun 0:06036f8bee2d 1286 case DMA_FIFO_THRESHOLD_HALFFULL:
ganlikun 0:06036f8bee2d 1287 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
ganlikun 0:06036f8bee2d 1288 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1289 break;
ganlikun 0:06036f8bee2d 1290 case DMA_FIFO_THRESHOLD_FULL:
ganlikun 0:06036f8bee2d 1291 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
ganlikun 0:06036f8bee2d 1292 {
ganlikun 0:06036f8bee2d 1293 status = HAL_ERROR;
ganlikun 0:06036f8bee2d 1294 }
ganlikun 0:06036f8bee2d 1295 break;
ganlikun 0:06036f8bee2d 1296 default:
ganlikun 0:06036f8bee2d 1297 break;
ganlikun 0:06036f8bee2d 1298 }
ganlikun 0:06036f8bee2d 1299 }
ganlikun 0:06036f8bee2d 1300
ganlikun 0:06036f8bee2d 1301 return status;
ganlikun 0:06036f8bee2d 1302 }
ganlikun 0:06036f8bee2d 1303
ganlikun 0:06036f8bee2d 1304 /**
ganlikun 0:06036f8bee2d 1305 * @}
ganlikun 0:06036f8bee2d 1306 */
ganlikun 0:06036f8bee2d 1307
ganlikun 0:06036f8bee2d 1308 #endif /* HAL_DMA_MODULE_ENABLED */
ganlikun 0:06036f8bee2d 1309 /**
ganlikun 0:06036f8bee2d 1310 * @}
ganlikun 0:06036f8bee2d 1311 */
ganlikun 0:06036f8bee2d 1312
ganlikun 0:06036f8bee2d 1313 /**
ganlikun 0:06036f8bee2d 1314 * @}
ganlikun 0:06036f8bee2d 1315 */
ganlikun 0:06036f8bee2d 1316
ganlikun 0:06036f8bee2d 1317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:06036f8bee2d 1318