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/**************************************************************************//**
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* @file core_cm0plus.h
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* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
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* @version V5.0.2
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* @date 13. February 2017
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef __CORE_CM0PLUS_H_GENERIC
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#define __CORE_CM0PLUS_H_GENERIC
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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CMSIS violates the following MISRA-C:2004 rules:
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\li Required Rule 8.5, object/function definition in header file.<br>
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Function definitions in header files are used to allow 'inlining'.
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\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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Unions are used for effective representation of core registers.
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\li Advisory Rule 19.7, Function-like macro defined.<br>
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Function-like macros are used to allow more efficient code.
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*/
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/*******************************************************************************
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* CMSIS definitions
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******************************************************************************/
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/**
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\ingroup Cortex-M0+
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@{
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*/
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/* CMSIS CM0+ definitions */
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#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
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#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
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#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
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__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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#define __CORTEX_M (0U) /*!< Cortex-M Core */
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/** __FPU_USED indicates whether an FPU is used or not.
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This core does not support an FPU at all
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*/
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#define __FPU_USED 0U
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#if defined ( __CC_ARM )
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#if defined __TARGET_FPU_VFP
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#if defined __ARM_PCS_VFP
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __GNUC__ )
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __ICCARM__ )
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#if defined __ARMVFP__
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __TI_ARM__ )
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#if defined __TI_VFP_SUPPORT__
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __TASKING__ )
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#if defined __FPU_VFP__
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __CSMC__ )
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#if ( __CSMC__ & 0x400U)
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#endif
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#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CORE_CM0PLUS_H_GENERIC */
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#ifndef __CMSIS_GENERIC
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#ifndef __CORE_CM0PLUS_H_DEPENDANT
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#define __CORE_CM0PLUS_H_DEPENDANT
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* check device defines and use defaults */
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#if defined __CHECK_DEVICE_DEFINES
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#ifndef __CM0PLUS_REV
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#define __CM0PLUS_REV 0x0000U
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#warning "__CM0PLUS_REV not defined in device header file; using default!"
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#endif
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#ifndef __MPU_PRESENT
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#define __MPU_PRESENT 0U
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#warning "__MPU_PRESENT not defined in device header file; using default!"
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#endif
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#ifndef __VTOR_PRESENT
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#define __VTOR_PRESENT 0U
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#warning "__VTOR_PRESENT not defined in device header file; using default!"
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#endif
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#ifndef __NVIC_PRIO_BITS
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#define __NVIC_PRIO_BITS 2U
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#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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#endif
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#ifndef __Vendor_SysTickConfig
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#define __Vendor_SysTickConfig 0U
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#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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#endif
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#endif
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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\defgroup CMSIS_glob_defs CMSIS Global Defines
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<strong>IO Type Qualifiers</strong> are used
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\li to specify the access to peripheral variables.
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\li for automatic generation of peripheral register debug information.
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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/*@} end of group Cortex-M0+ */
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/*******************************************************************************
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* Register Abstraction
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Core Register contain:
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- Core Register
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- Core NVIC Register
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- Core SCB Register
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- Core SysTick Register
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- Core MPU Register
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******************************************************************************/
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/**
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| ganlikun |
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\defgroup CMSIS_core_register Defines and Type Definitions
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| ganlikun |
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\brief Type definitions and defines for Cortex-M processor based devices.
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*/
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/**
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\ingroup CMSIS_core_register
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\defgroup CMSIS_CORE Status and Control Registers
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| ganlikun |
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\brief Core Register type definitions.
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@{
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*/
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/**
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| ganlikun |
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\brief Union type to access the Application Program Status Register (APSR).
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| ganlikun |
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*/
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typedef union
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{
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struct
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{
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uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
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uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} APSR_Type;
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/* APSR Register Definitions */
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#define APSR_N_Pos 31U /*!< APSR: N Position */
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#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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#define APSR_Z_Pos 30U /*!< APSR: Z Position */
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#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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#define APSR_C_Pos 29U /*!< APSR: C Position */
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#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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#define APSR_V_Pos 28U /*!< APSR: V Position */
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#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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/**
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\brief Union type to access the Interrupt Program Status Register (IPSR).
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*/
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typedef union
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{
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struct
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{
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uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} IPSR_Type;
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/* IPSR Register Definitions */
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#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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/**
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|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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*/
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typedef union
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| ganlikun |
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{
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|
struct
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| ganlikun |
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{
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| ganlikun |
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uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
| ganlikun |
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uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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| ganlikun |
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uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
| ganlikun |
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uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
| ganlikun |
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|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
| ganlikun |
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uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
| ganlikun |
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uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
| ganlikun |
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|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
| ganlikun |
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|
} b; /*!< Structure used for bit access */
|
| ganlikun |
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|
uint32_t w; /*!< Type used for word access */
|
| ganlikun |
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|
} xPSR_Type;
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| ganlikun |
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|
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| ganlikun |
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272
|
/* xPSR Register Definitions */
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| ganlikun |
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|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
| ganlikun |
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|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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|
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| ganlikun |
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|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
| ganlikun |
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|
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|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
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|
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|
|
| ganlikun |
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|
279
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
| ganlikun |
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|
280
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
| ganlikun |
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|
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|
|
| ganlikun |
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|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
| ganlikun |
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|
283
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
| ganlikun |
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|
284
|
|
| ganlikun |
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|
285
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
| ganlikun |
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|
286
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
| ganlikun |
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|
287
|
|
| ganlikun |
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|
288
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
| ganlikun |
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|
289
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
| ganlikun |
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|
290
|
|
| ganlikun |
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|
291
|
|
| ganlikun |
0:06036f8bee2d
|
292
|
/**
|
| ganlikun |
0:06036f8bee2d
|
293
|
\brief Union type to access the Control Registers (CONTROL).
|
| ganlikun |
0:06036f8bee2d
|
294
|
*/
|
| ganlikun |
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|
295
|
typedef union
|
| ganlikun |
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|
296
|
{
|
| ganlikun |
0:06036f8bee2d
|
297
|
struct
|
| ganlikun |
0:06036f8bee2d
|
298
|
{
|
| ganlikun |
0:06036f8bee2d
|
299
|
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
| ganlikun |
0:06036f8bee2d
|
300
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
| ganlikun |
0:06036f8bee2d
|
301
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
| ganlikun |
0:06036f8bee2d
|
302
|
} b; /*!< Structure used for bit access */
|
| ganlikun |
0:06036f8bee2d
|
303
|
uint32_t w; /*!< Type used for word access */
|
| ganlikun |
0:06036f8bee2d
|
304
|
} CONTROL_Type;
|
| ganlikun |
0:06036f8bee2d
|
305
|
|
| ganlikun |
0:06036f8bee2d
|
306
|
/* CONTROL Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
307
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
| ganlikun |
0:06036f8bee2d
|
308
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
| ganlikun |
0:06036f8bee2d
|
309
|
|
| ganlikun |
0:06036f8bee2d
|
310
|
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
|
| ganlikun |
0:06036f8bee2d
|
311
|
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
|
| ganlikun |
0:06036f8bee2d
|
312
|
|
| ganlikun |
0:06036f8bee2d
|
313
|
/*@} end of group CMSIS_CORE */
|
| ganlikun |
0:06036f8bee2d
|
314
|
|
| ganlikun |
0:06036f8bee2d
|
315
|
|
| ganlikun |
0:06036f8bee2d
|
316
|
/**
|
| ganlikun |
0:06036f8bee2d
|
317
|
\ingroup CMSIS_core_register
|
| ganlikun |
0:06036f8bee2d
|
318
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
| ganlikun |
0:06036f8bee2d
|
319
|
\brief Type definitions for the NVIC Registers
|
| ganlikun |
0:06036f8bee2d
|
320
|
@{
|
| ganlikun |
0:06036f8bee2d
|
321
|
*/
|
| ganlikun |
0:06036f8bee2d
|
322
|
|
| ganlikun |
0:06036f8bee2d
|
323
|
/**
|
| ganlikun |
0:06036f8bee2d
|
324
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
| ganlikun |
0:06036f8bee2d
|
325
|
*/
|
| ganlikun |
0:06036f8bee2d
|
326
|
typedef struct
|
| ganlikun |
0:06036f8bee2d
|
327
|
{
|
| ganlikun |
0:06036f8bee2d
|
328
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
| ganlikun |
0:06036f8bee2d
|
329
|
uint32_t RESERVED0[31U];
|
| ganlikun |
0:06036f8bee2d
|
330
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
| ganlikun |
0:06036f8bee2d
|
331
|
uint32_t RSERVED1[31U];
|
| ganlikun |
0:06036f8bee2d
|
332
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
| ganlikun |
0:06036f8bee2d
|
333
|
uint32_t RESERVED2[31U];
|
| ganlikun |
0:06036f8bee2d
|
334
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
| ganlikun |
0:06036f8bee2d
|
335
|
uint32_t RESERVED3[31U];
|
| ganlikun |
0:06036f8bee2d
|
336
|
uint32_t RESERVED4[64U];
|
| ganlikun |
0:06036f8bee2d
|
337
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
| ganlikun |
0:06036f8bee2d
|
338
|
} NVIC_Type;
|
| ganlikun |
0:06036f8bee2d
|
339
|
|
| ganlikun |
0:06036f8bee2d
|
340
|
/*@} end of group CMSIS_NVIC */
|
| ganlikun |
0:06036f8bee2d
|
341
|
|
| ganlikun |
0:06036f8bee2d
|
342
|
|
| ganlikun |
0:06036f8bee2d
|
343
|
/**
|
| ganlikun |
0:06036f8bee2d
|
344
|
\ingroup CMSIS_core_register
|
| ganlikun |
0:06036f8bee2d
|
345
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
| ganlikun |
0:06036f8bee2d
|
346
|
\brief Type definitions for the System Control Block Registers
|
| ganlikun |
0:06036f8bee2d
|
347
|
@{
|
| ganlikun |
0:06036f8bee2d
|
348
|
*/
|
| ganlikun |
0:06036f8bee2d
|
349
|
|
| ganlikun |
0:06036f8bee2d
|
350
|
/**
|
| ganlikun |
0:06036f8bee2d
|
351
|
\brief Structure type to access the System Control Block (SCB).
|
| ganlikun |
0:06036f8bee2d
|
352
|
*/
|
| ganlikun |
0:06036f8bee2d
|
353
|
typedef struct
|
| ganlikun |
0:06036f8bee2d
|
354
|
{
|
| ganlikun |
0:06036f8bee2d
|
355
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
| ganlikun |
0:06036f8bee2d
|
356
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
| ganlikun |
0:06036f8bee2d
|
357
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
| ganlikun |
0:06036f8bee2d
|
358
|
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
| ganlikun |
0:06036f8bee2d
|
359
|
#else
|
| ganlikun |
0:06036f8bee2d
|
360
|
uint32_t RESERVED0;
|
| ganlikun |
0:06036f8bee2d
|
361
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
362
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
| ganlikun |
0:06036f8bee2d
|
363
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
| ganlikun |
0:06036f8bee2d
|
364
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
| ganlikun |
0:06036f8bee2d
|
365
|
uint32_t RESERVED1;
|
| ganlikun |
0:06036f8bee2d
|
366
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
| ganlikun |
0:06036f8bee2d
|
367
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
| ganlikun |
0:06036f8bee2d
|
368
|
} SCB_Type;
|
| ganlikun |
0:06036f8bee2d
|
369
|
|
| ganlikun |
0:06036f8bee2d
|
370
|
/* SCB CPUID Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
371
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
| ganlikun |
0:06036f8bee2d
|
372
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
| ganlikun |
0:06036f8bee2d
|
373
|
|
| ganlikun |
0:06036f8bee2d
|
374
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
| ganlikun |
0:06036f8bee2d
|
375
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
| ganlikun |
0:06036f8bee2d
|
376
|
|
| ganlikun |
0:06036f8bee2d
|
377
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
| ganlikun |
0:06036f8bee2d
|
378
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
| ganlikun |
0:06036f8bee2d
|
379
|
|
| ganlikun |
0:06036f8bee2d
|
380
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
| ganlikun |
0:06036f8bee2d
|
381
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
| ganlikun |
0:06036f8bee2d
|
382
|
|
| ganlikun |
0:06036f8bee2d
|
383
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
| ganlikun |
0:06036f8bee2d
|
384
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
| ganlikun |
0:06036f8bee2d
|
385
|
|
| ganlikun |
0:06036f8bee2d
|
386
|
/* SCB Interrupt Control State Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
387
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
| ganlikun |
0:06036f8bee2d
|
388
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
| ganlikun |
0:06036f8bee2d
|
389
|
|
| ganlikun |
0:06036f8bee2d
|
390
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
| ganlikun |
0:06036f8bee2d
|
391
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
| ganlikun |
0:06036f8bee2d
|
392
|
|
| ganlikun |
0:06036f8bee2d
|
393
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
| ganlikun |
0:06036f8bee2d
|
394
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
| ganlikun |
0:06036f8bee2d
|
395
|
|
| ganlikun |
0:06036f8bee2d
|
396
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
| ganlikun |
0:06036f8bee2d
|
397
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
| ganlikun |
0:06036f8bee2d
|
398
|
|
| ganlikun |
0:06036f8bee2d
|
399
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
| ganlikun |
0:06036f8bee2d
|
400
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
| ganlikun |
0:06036f8bee2d
|
401
|
|
| ganlikun |
0:06036f8bee2d
|
402
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
| ganlikun |
0:06036f8bee2d
|
403
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
| ganlikun |
0:06036f8bee2d
|
404
|
|
| ganlikun |
0:06036f8bee2d
|
405
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
| ganlikun |
0:06036f8bee2d
|
406
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
| ganlikun |
0:06036f8bee2d
|
407
|
|
| ganlikun |
0:06036f8bee2d
|
408
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
| ganlikun |
0:06036f8bee2d
|
409
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
| ganlikun |
0:06036f8bee2d
|
410
|
|
| ganlikun |
0:06036f8bee2d
|
411
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
| ganlikun |
0:06036f8bee2d
|
412
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
| ganlikun |
0:06036f8bee2d
|
413
|
|
| ganlikun |
0:06036f8bee2d
|
414
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
| ganlikun |
0:06036f8bee2d
|
415
|
/* SCB Interrupt Control State Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
416
|
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
| ganlikun |
0:06036f8bee2d
|
417
|
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
| ganlikun |
0:06036f8bee2d
|
418
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
419
|
|
| ganlikun |
0:06036f8bee2d
|
420
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
421
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
| ganlikun |
0:06036f8bee2d
|
422
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
| ganlikun |
0:06036f8bee2d
|
423
|
|
| ganlikun |
0:06036f8bee2d
|
424
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
| ganlikun |
0:06036f8bee2d
|
425
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
| ganlikun |
0:06036f8bee2d
|
426
|
|
| ganlikun |
0:06036f8bee2d
|
427
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
| ganlikun |
0:06036f8bee2d
|
428
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
| ganlikun |
0:06036f8bee2d
|
429
|
|
| ganlikun |
0:06036f8bee2d
|
430
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
| ganlikun |
0:06036f8bee2d
|
431
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
| ganlikun |
0:06036f8bee2d
|
432
|
|
| ganlikun |
0:06036f8bee2d
|
433
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
| ganlikun |
0:06036f8bee2d
|
434
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
| ganlikun |
0:06036f8bee2d
|
435
|
|
| ganlikun |
0:06036f8bee2d
|
436
|
/* SCB System Control Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
437
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
| ganlikun |
0:06036f8bee2d
|
438
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
| ganlikun |
0:06036f8bee2d
|
439
|
|
| ganlikun |
0:06036f8bee2d
|
440
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
| ganlikun |
0:06036f8bee2d
|
441
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
| ganlikun |
0:06036f8bee2d
|
442
|
|
| ganlikun |
0:06036f8bee2d
|
443
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
| ganlikun |
0:06036f8bee2d
|
444
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
| ganlikun |
0:06036f8bee2d
|
445
|
|
| ganlikun |
0:06036f8bee2d
|
446
|
/* SCB Configuration Control Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
447
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
| ganlikun |
0:06036f8bee2d
|
448
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
| ganlikun |
0:06036f8bee2d
|
449
|
|
| ganlikun |
0:06036f8bee2d
|
450
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
| ganlikun |
0:06036f8bee2d
|
451
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
| ganlikun |
0:06036f8bee2d
|
452
|
|
| ganlikun |
0:06036f8bee2d
|
453
|
/* SCB System Handler Control and State Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
454
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
| ganlikun |
0:06036f8bee2d
|
455
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
| ganlikun |
0:06036f8bee2d
|
456
|
|
| ganlikun |
0:06036f8bee2d
|
457
|
/*@} end of group CMSIS_SCB */
|
| ganlikun |
0:06036f8bee2d
|
458
|
|
| ganlikun |
0:06036f8bee2d
|
459
|
|
| ganlikun |
0:06036f8bee2d
|
460
|
/**
|
| ganlikun |
0:06036f8bee2d
|
461
|
\ingroup CMSIS_core_register
|
| ganlikun |
0:06036f8bee2d
|
462
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
| ganlikun |
0:06036f8bee2d
|
463
|
\brief Type definitions for the System Timer Registers.
|
| ganlikun |
0:06036f8bee2d
|
464
|
@{
|
| ganlikun |
0:06036f8bee2d
|
465
|
*/
|
| ganlikun |
0:06036f8bee2d
|
466
|
|
| ganlikun |
0:06036f8bee2d
|
467
|
/**
|
| ganlikun |
0:06036f8bee2d
|
468
|
\brief Structure type to access the System Timer (SysTick).
|
| ganlikun |
0:06036f8bee2d
|
469
|
*/
|
| ganlikun |
0:06036f8bee2d
|
470
|
typedef struct
|
| ganlikun |
0:06036f8bee2d
|
471
|
{
|
| ganlikun |
0:06036f8bee2d
|
472
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
| ganlikun |
0:06036f8bee2d
|
473
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
| ganlikun |
0:06036f8bee2d
|
474
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
| ganlikun |
0:06036f8bee2d
|
475
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
| ganlikun |
0:06036f8bee2d
|
476
|
} SysTick_Type;
|
| ganlikun |
0:06036f8bee2d
|
477
|
|
| ganlikun |
0:06036f8bee2d
|
478
|
/* SysTick Control / Status Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
479
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
| ganlikun |
0:06036f8bee2d
|
480
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
| ganlikun |
0:06036f8bee2d
|
481
|
|
| ganlikun |
0:06036f8bee2d
|
482
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
| ganlikun |
0:06036f8bee2d
|
483
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
| ganlikun |
0:06036f8bee2d
|
484
|
|
| ganlikun |
0:06036f8bee2d
|
485
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
| ganlikun |
0:06036f8bee2d
|
486
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
| ganlikun |
0:06036f8bee2d
|
487
|
|
| ganlikun |
0:06036f8bee2d
|
488
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
| ganlikun |
0:06036f8bee2d
|
489
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
| ganlikun |
0:06036f8bee2d
|
490
|
|
| ganlikun |
0:06036f8bee2d
|
491
|
/* SysTick Reload Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
492
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
| ganlikun |
0:06036f8bee2d
|
493
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
| ganlikun |
0:06036f8bee2d
|
494
|
|
| ganlikun |
0:06036f8bee2d
|
495
|
/* SysTick Current Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
496
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
| ganlikun |
0:06036f8bee2d
|
497
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
| ganlikun |
0:06036f8bee2d
|
498
|
|
| ganlikun |
0:06036f8bee2d
|
499
|
/* SysTick Calibration Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
500
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
| ganlikun |
0:06036f8bee2d
|
501
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
| ganlikun |
0:06036f8bee2d
|
502
|
|
| ganlikun |
0:06036f8bee2d
|
503
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
| ganlikun |
0:06036f8bee2d
|
504
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
| ganlikun |
0:06036f8bee2d
|
505
|
|
| ganlikun |
0:06036f8bee2d
|
506
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
| ganlikun |
0:06036f8bee2d
|
507
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
| ganlikun |
0:06036f8bee2d
|
508
|
|
| ganlikun |
0:06036f8bee2d
|
509
|
/*@} end of group CMSIS_SysTick */
|
| ganlikun |
0:06036f8bee2d
|
510
|
|
| ganlikun |
0:06036f8bee2d
|
511
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
| ganlikun |
0:06036f8bee2d
|
512
|
/**
|
| ganlikun |
0:06036f8bee2d
|
513
|
\ingroup CMSIS_core_register
|
| ganlikun |
0:06036f8bee2d
|
514
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
| ganlikun |
0:06036f8bee2d
|
515
|
\brief Type definitions for the Memory Protection Unit (MPU)
|
| ganlikun |
0:06036f8bee2d
|
516
|
@{
|
| ganlikun |
0:06036f8bee2d
|
517
|
*/
|
| ganlikun |
0:06036f8bee2d
|
518
|
|
| ganlikun |
0:06036f8bee2d
|
519
|
/**
|
| ganlikun |
0:06036f8bee2d
|
520
|
\brief Structure type to access the Memory Protection Unit (MPU).
|
| ganlikun |
0:06036f8bee2d
|
521
|
*/
|
| ganlikun |
0:06036f8bee2d
|
522
|
typedef struct
|
| ganlikun |
0:06036f8bee2d
|
523
|
{
|
| ganlikun |
0:06036f8bee2d
|
524
|
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
| ganlikun |
0:06036f8bee2d
|
525
|
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
| ganlikun |
0:06036f8bee2d
|
526
|
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
| ganlikun |
0:06036f8bee2d
|
527
|
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
| ganlikun |
0:06036f8bee2d
|
528
|
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
| ganlikun |
0:06036f8bee2d
|
529
|
} MPU_Type;
|
| ganlikun |
0:06036f8bee2d
|
530
|
|
| ganlikun |
0:06036f8bee2d
|
531
|
/* MPU Type Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
532
|
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
| ganlikun |
0:06036f8bee2d
|
533
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
| ganlikun |
0:06036f8bee2d
|
534
|
|
| ganlikun |
0:06036f8bee2d
|
535
|
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
| ganlikun |
0:06036f8bee2d
|
536
|
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
| ganlikun |
0:06036f8bee2d
|
537
|
|
| ganlikun |
0:06036f8bee2d
|
538
|
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
| ganlikun |
0:06036f8bee2d
|
539
|
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
| ganlikun |
0:06036f8bee2d
|
540
|
|
| ganlikun |
0:06036f8bee2d
|
541
|
/* MPU Control Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
542
|
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
| ganlikun |
0:06036f8bee2d
|
543
|
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
| ganlikun |
0:06036f8bee2d
|
544
|
|
| ganlikun |
0:06036f8bee2d
|
545
|
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
| ganlikun |
0:06036f8bee2d
|
546
|
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
| ganlikun |
0:06036f8bee2d
|
547
|
|
| ganlikun |
0:06036f8bee2d
|
548
|
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
| ganlikun |
0:06036f8bee2d
|
549
|
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
| ganlikun |
0:06036f8bee2d
|
550
|
|
| ganlikun |
0:06036f8bee2d
|
551
|
/* MPU Region Number Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
552
|
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
| ganlikun |
0:06036f8bee2d
|
553
|
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
| ganlikun |
0:06036f8bee2d
|
554
|
|
| ganlikun |
0:06036f8bee2d
|
555
|
/* MPU Region Base Address Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
556
|
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
| ganlikun |
0:06036f8bee2d
|
557
|
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
| ganlikun |
0:06036f8bee2d
|
558
|
|
| ganlikun |
0:06036f8bee2d
|
559
|
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
| ganlikun |
0:06036f8bee2d
|
560
|
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
| ganlikun |
0:06036f8bee2d
|
561
|
|
| ganlikun |
0:06036f8bee2d
|
562
|
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
| ganlikun |
0:06036f8bee2d
|
563
|
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
| ganlikun |
0:06036f8bee2d
|
564
|
|
| ganlikun |
0:06036f8bee2d
|
565
|
/* MPU Region Attribute and Size Register Definitions */
|
| ganlikun |
0:06036f8bee2d
|
566
|
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
| ganlikun |
0:06036f8bee2d
|
567
|
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
| ganlikun |
0:06036f8bee2d
|
568
|
|
| ganlikun |
0:06036f8bee2d
|
569
|
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
| ganlikun |
0:06036f8bee2d
|
570
|
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
| ganlikun |
0:06036f8bee2d
|
571
|
|
| ganlikun |
0:06036f8bee2d
|
572
|
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
| ganlikun |
0:06036f8bee2d
|
573
|
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
| ganlikun |
0:06036f8bee2d
|
574
|
|
| ganlikun |
0:06036f8bee2d
|
575
|
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
| ganlikun |
0:06036f8bee2d
|
576
|
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
| ganlikun |
0:06036f8bee2d
|
577
|
|
| ganlikun |
0:06036f8bee2d
|
578
|
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
| ganlikun |
0:06036f8bee2d
|
579
|
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
| ganlikun |
0:06036f8bee2d
|
580
|
|
| ganlikun |
0:06036f8bee2d
|
581
|
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
| ganlikun |
0:06036f8bee2d
|
582
|
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
| ganlikun |
0:06036f8bee2d
|
583
|
|
| ganlikun |
0:06036f8bee2d
|
584
|
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
| ganlikun |
0:06036f8bee2d
|
585
|
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
| ganlikun |
0:06036f8bee2d
|
586
|
|
| ganlikun |
0:06036f8bee2d
|
587
|
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
| ganlikun |
0:06036f8bee2d
|
588
|
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
| ganlikun |
0:06036f8bee2d
|
589
|
|
| ganlikun |
0:06036f8bee2d
|
590
|
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
| ganlikun |
0:06036f8bee2d
|
591
|
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
| ganlikun |
0:06036f8bee2d
|
592
|
|
| ganlikun |
0:06036f8bee2d
|
593
|
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
| ganlikun |
0:06036f8bee2d
|
594
|
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
| ganlikun |
0:06036f8bee2d
|
595
|
|
| ganlikun |
0:06036f8bee2d
|
596
|
/*@} end of group CMSIS_MPU */
|
| ganlikun |
0:06036f8bee2d
|
597
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
598
|
|
| ganlikun |
0:06036f8bee2d
|
599
|
|
| ganlikun |
0:06036f8bee2d
|
600
|
/**
|
| ganlikun |
0:06036f8bee2d
|
601
|
\ingroup CMSIS_core_register
|
| ganlikun |
0:06036f8bee2d
|
602
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
| ganlikun |
0:06036f8bee2d
|
603
|
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
| ganlikun |
0:06036f8bee2d
|
604
|
Therefore they are not covered by the Cortex-M0+ header file.
|
| ganlikun |
0:06036f8bee2d
|
605
|
@{
|
| ganlikun |
0:06036f8bee2d
|
606
|
*/
|
| ganlikun |
0:06036f8bee2d
|
607
|
/*@} end of group CMSIS_CoreDebug */
|
| ganlikun |
0:06036f8bee2d
|
608
|
|
| ganlikun |
0:06036f8bee2d
|
609
|
|
| ganlikun |
0:06036f8bee2d
|
610
|
/**
|
| ganlikun |
0:06036f8bee2d
|
611
|
\ingroup CMSIS_core_register
|
| ganlikun |
0:06036f8bee2d
|
612
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
| ganlikun |
0:06036f8bee2d
|
613
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
| ganlikun |
0:06036f8bee2d
|
614
|
@{
|
| ganlikun |
0:06036f8bee2d
|
615
|
*/
|
| ganlikun |
0:06036f8bee2d
|
616
|
|
| ganlikun |
0:06036f8bee2d
|
617
|
/**
|
| ganlikun |
0:06036f8bee2d
|
618
|
\brief Mask and shift a bit field value for use in a register bit range.
|
| ganlikun |
0:06036f8bee2d
|
619
|
\param[in] field Name of the register bit field.
|
| ganlikun |
0:06036f8bee2d
|
620
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
| ganlikun |
0:06036f8bee2d
|
621
|
\return Masked and shifted value.
|
| ganlikun |
0:06036f8bee2d
|
622
|
*/
|
| ganlikun |
0:06036f8bee2d
|
623
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
| ganlikun |
0:06036f8bee2d
|
624
|
|
| ganlikun |
0:06036f8bee2d
|
625
|
/**
|
| ganlikun |
0:06036f8bee2d
|
626
|
\brief Mask and shift a register value to extract a bit filed value.
|
| ganlikun |
0:06036f8bee2d
|
627
|
\param[in] field Name of the register bit field.
|
| ganlikun |
0:06036f8bee2d
|
628
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
| ganlikun |
0:06036f8bee2d
|
629
|
\return Masked and shifted bit field value.
|
| ganlikun |
0:06036f8bee2d
|
630
|
*/
|
| ganlikun |
0:06036f8bee2d
|
631
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
| ganlikun |
0:06036f8bee2d
|
632
|
|
| ganlikun |
0:06036f8bee2d
|
633
|
/*@} end of group CMSIS_core_bitfield */
|
| ganlikun |
0:06036f8bee2d
|
634
|
|
| ganlikun |
0:06036f8bee2d
|
635
|
|
| ganlikun |
0:06036f8bee2d
|
636
|
/**
|
| ganlikun |
0:06036f8bee2d
|
637
|
\ingroup CMSIS_core_register
|
| ganlikun |
0:06036f8bee2d
|
638
|
\defgroup CMSIS_core_base Core Definitions
|
| ganlikun |
0:06036f8bee2d
|
639
|
\brief Definitions for base addresses, unions, and structures.
|
| ganlikun |
0:06036f8bee2d
|
640
|
@{
|
| ganlikun |
0:06036f8bee2d
|
641
|
*/
|
| ganlikun |
0:06036f8bee2d
|
642
|
|
| ganlikun |
0:06036f8bee2d
|
643
|
/* Memory mapping of Core Hardware */
|
| ganlikun |
0:06036f8bee2d
|
644
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
| ganlikun |
0:06036f8bee2d
|
645
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
| ganlikun |
0:06036f8bee2d
|
646
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
| ganlikun |
0:06036f8bee2d
|
647
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
| ganlikun |
0:06036f8bee2d
|
648
|
|
| ganlikun |
0:06036f8bee2d
|
649
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
| ganlikun |
0:06036f8bee2d
|
650
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
| ganlikun |
0:06036f8bee2d
|
651
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
| ganlikun |
0:06036f8bee2d
|
652
|
|
| ganlikun |
0:06036f8bee2d
|
653
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
| ganlikun |
0:06036f8bee2d
|
654
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
| ganlikun |
0:06036f8bee2d
|
655
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
| ganlikun |
0:06036f8bee2d
|
656
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
657
|
|
| ganlikun |
0:06036f8bee2d
|
658
|
/*@} */
|
| ganlikun |
0:06036f8bee2d
|
659
|
|
| ganlikun |
0:06036f8bee2d
|
660
|
|
| ganlikun |
0:06036f8bee2d
|
661
|
|
| ganlikun |
0:06036f8bee2d
|
662
|
/*******************************************************************************
|
| ganlikun |
0:06036f8bee2d
|
663
|
* Hardware Abstraction Layer
|
| ganlikun |
0:06036f8bee2d
|
664
|
Core Function Interface contains:
|
| ganlikun |
0:06036f8bee2d
|
665
|
- Core NVIC Functions
|
| ganlikun |
0:06036f8bee2d
|
666
|
- Core SysTick Functions
|
| ganlikun |
0:06036f8bee2d
|
667
|
- Core Register Access Functions
|
| ganlikun |
0:06036f8bee2d
|
668
|
******************************************************************************/
|
| ganlikun |
0:06036f8bee2d
|
669
|
/**
|
| ganlikun |
0:06036f8bee2d
|
670
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
| ganlikun |
0:06036f8bee2d
|
671
|
*/
|
| ganlikun |
0:06036f8bee2d
|
672
|
|
| ganlikun |
0:06036f8bee2d
|
673
|
|
| ganlikun |
0:06036f8bee2d
|
674
|
|
| ganlikun |
0:06036f8bee2d
|
675
|
/* ########################## NVIC functions #################################### */
|
| ganlikun |
0:06036f8bee2d
|
676
|
/**
|
| ganlikun |
0:06036f8bee2d
|
677
|
\ingroup CMSIS_Core_FunctionInterface
|
| ganlikun |
0:06036f8bee2d
|
678
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
| ganlikun |
0:06036f8bee2d
|
679
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
| ganlikun |
0:06036f8bee2d
|
680
|
@{
|
| ganlikun |
0:06036f8bee2d
|
681
|
*/
|
| ganlikun |
0:06036f8bee2d
|
682
|
|
| ganlikun |
0:06036f8bee2d
|
683
|
#ifdef CMSIS_NVIC_VIRTUAL
|
| ganlikun |
0:06036f8bee2d
|
684
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
| ganlikun |
0:06036f8bee2d
|
685
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
| ganlikun |
0:06036f8bee2d
|
686
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
687
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
| ganlikun |
0:06036f8bee2d
|
688
|
#else
|
| ganlikun |
0:06036f8bee2d
|
689
|
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
|
| ganlikun |
0:06036f8bee2d
|
690
|
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
|
| ganlikun |
0:06036f8bee2d
|
691
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
| ganlikun |
0:06036f8bee2d
|
692
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
| ganlikun |
0:06036f8bee2d
|
693
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
| ganlikun |
0:06036f8bee2d
|
694
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
| ganlikun |
0:06036f8bee2d
|
695
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
| ganlikun |
0:06036f8bee2d
|
696
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
| ganlikun |
0:06036f8bee2d
|
697
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
|
| ganlikun |
0:06036f8bee2d
|
698
|
#define NVIC_SetPriority __NVIC_SetPriority
|
| ganlikun |
0:06036f8bee2d
|
699
|
#define NVIC_GetPriority __NVIC_GetPriority
|
| ganlikun |
0:06036f8bee2d
|
700
|
#define NVIC_SystemReset __NVIC_SystemReset
|
| ganlikun |
0:06036f8bee2d
|
701
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
| ganlikun |
0:06036f8bee2d
|
702
|
|
| ganlikun |
0:06036f8bee2d
|
703
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
| ganlikun |
0:06036f8bee2d
|
704
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
| ganlikun |
0:06036f8bee2d
|
705
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
| ganlikun |
0:06036f8bee2d
|
706
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
707
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
| ganlikun |
0:06036f8bee2d
|
708
|
#else
|
| ganlikun |
0:06036f8bee2d
|
709
|
#define NVIC_SetVector __NVIC_SetVector
|
| ganlikun |
0:06036f8bee2d
|
710
|
#define NVIC_GetVector __NVIC_GetVector
|
| ganlikun |
0:06036f8bee2d
|
711
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
| ganlikun |
0:06036f8bee2d
|
712
|
|
| ganlikun |
0:06036f8bee2d
|
713
|
#define NVIC_USER_IRQ_OFFSET 16
|
| ganlikun |
0:06036f8bee2d
|
714
|
|
| ganlikun |
0:06036f8bee2d
|
715
|
|
| ganlikun |
0:06036f8bee2d
|
716
|
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
| ganlikun |
0:06036f8bee2d
|
717
|
/* The following MACROS handle generation of the register offset and byte masks */
|
| ganlikun |
0:06036f8bee2d
|
718
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
| ganlikun |
0:06036f8bee2d
|
719
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
| ganlikun |
0:06036f8bee2d
|
720
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
| ganlikun |
0:06036f8bee2d
|
721
|
|
| ganlikun |
0:06036f8bee2d
|
722
|
|
| ganlikun |
0:06036f8bee2d
|
723
|
/**
|
| ganlikun |
0:06036f8bee2d
|
724
|
\brief Enable Interrupt
|
| ganlikun |
0:06036f8bee2d
|
725
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
| ganlikun |
0:06036f8bee2d
|
726
|
\param [in] IRQn Device specific interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
727
|
\note IRQn must not be negative.
|
| ganlikun |
0:06036f8bee2d
|
728
|
*/
|
| ganlikun |
0:06036f8bee2d
|
729
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
730
|
{
|
| ganlikun |
0:06036f8bee2d
|
731
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
732
|
{
|
| ganlikun |
0:06036f8bee2d
|
733
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
| ganlikun |
0:06036f8bee2d
|
734
|
}
|
| ganlikun |
0:06036f8bee2d
|
735
|
}
|
| ganlikun |
0:06036f8bee2d
|
736
|
|
| ganlikun |
0:06036f8bee2d
|
737
|
|
| ganlikun |
0:06036f8bee2d
|
738
|
/**
|
| ganlikun |
0:06036f8bee2d
|
739
|
\brief Get Interrupt Enable status
|
| ganlikun |
0:06036f8bee2d
|
740
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
| ganlikun |
0:06036f8bee2d
|
741
|
\param [in] IRQn Device specific interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
742
|
\return 0 Interrupt is not enabled.
|
| ganlikun |
0:06036f8bee2d
|
743
|
\return 1 Interrupt is enabled.
|
| ganlikun |
0:06036f8bee2d
|
744
|
\note IRQn must not be negative.
|
| ganlikun |
0:06036f8bee2d
|
745
|
*/
|
| ganlikun |
0:06036f8bee2d
|
746
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
747
|
{
|
| ganlikun |
0:06036f8bee2d
|
748
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
749
|
{
|
| ganlikun |
0:06036f8bee2d
|
750
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
| ganlikun |
0:06036f8bee2d
|
751
|
}
|
| ganlikun |
0:06036f8bee2d
|
752
|
else
|
| ganlikun |
0:06036f8bee2d
|
753
|
{
|
| ganlikun |
0:06036f8bee2d
|
754
|
return(0U);
|
| ganlikun |
0:06036f8bee2d
|
755
|
}
|
| ganlikun |
0:06036f8bee2d
|
756
|
}
|
| ganlikun |
0:06036f8bee2d
|
757
|
|
| ganlikun |
0:06036f8bee2d
|
758
|
|
| ganlikun |
0:06036f8bee2d
|
759
|
/**
|
| ganlikun |
0:06036f8bee2d
|
760
|
\brief Disable Interrupt
|
| ganlikun |
0:06036f8bee2d
|
761
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
| ganlikun |
0:06036f8bee2d
|
762
|
\param [in] IRQn Device specific interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
763
|
\note IRQn must not be negative.
|
| ganlikun |
0:06036f8bee2d
|
764
|
*/
|
| ganlikun |
0:06036f8bee2d
|
765
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
766
|
{
|
| ganlikun |
0:06036f8bee2d
|
767
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
768
|
{
|
| ganlikun |
0:06036f8bee2d
|
769
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
| ganlikun |
0:06036f8bee2d
|
770
|
__DSB();
|
| ganlikun |
0:06036f8bee2d
|
771
|
__ISB();
|
| ganlikun |
0:06036f8bee2d
|
772
|
}
|
| ganlikun |
0:06036f8bee2d
|
773
|
}
|
| ganlikun |
0:06036f8bee2d
|
774
|
|
| ganlikun |
0:06036f8bee2d
|
775
|
|
| ganlikun |
0:06036f8bee2d
|
776
|
/**
|
| ganlikun |
0:06036f8bee2d
|
777
|
\brief Get Pending Interrupt
|
| ganlikun |
0:06036f8bee2d
|
778
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
| ganlikun |
0:06036f8bee2d
|
779
|
\param [in] IRQn Device specific interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
780
|
\return 0 Interrupt status is not pending.
|
| ganlikun |
0:06036f8bee2d
|
781
|
\return 1 Interrupt status is pending.
|
| ganlikun |
0:06036f8bee2d
|
782
|
\note IRQn must not be negative.
|
| ganlikun |
0:06036f8bee2d
|
783
|
*/
|
| ganlikun |
0:06036f8bee2d
|
784
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
785
|
{
|
| ganlikun |
0:06036f8bee2d
|
786
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
787
|
{
|
| ganlikun |
0:06036f8bee2d
|
788
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
| ganlikun |
0:06036f8bee2d
|
789
|
}
|
| ganlikun |
0:06036f8bee2d
|
790
|
else
|
| ganlikun |
0:06036f8bee2d
|
791
|
{
|
| ganlikun |
0:06036f8bee2d
|
792
|
return(0U);
|
| ganlikun |
0:06036f8bee2d
|
793
|
}
|
| ganlikun |
0:06036f8bee2d
|
794
|
}
|
| ganlikun |
0:06036f8bee2d
|
795
|
|
| ganlikun |
0:06036f8bee2d
|
796
|
|
| ganlikun |
0:06036f8bee2d
|
797
|
/**
|
| ganlikun |
0:06036f8bee2d
|
798
|
\brief Set Pending Interrupt
|
| ganlikun |
0:06036f8bee2d
|
799
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
| ganlikun |
0:06036f8bee2d
|
800
|
\param [in] IRQn Device specific interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
801
|
\note IRQn must not be negative.
|
| ganlikun |
0:06036f8bee2d
|
802
|
*/
|
| ganlikun |
0:06036f8bee2d
|
803
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
804
|
{
|
| ganlikun |
0:06036f8bee2d
|
805
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
806
|
{
|
| ganlikun |
0:06036f8bee2d
|
807
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
| ganlikun |
0:06036f8bee2d
|
808
|
}
|
| ganlikun |
0:06036f8bee2d
|
809
|
}
|
| ganlikun |
0:06036f8bee2d
|
810
|
|
| ganlikun |
0:06036f8bee2d
|
811
|
|
| ganlikun |
0:06036f8bee2d
|
812
|
/**
|
| ganlikun |
0:06036f8bee2d
|
813
|
\brief Clear Pending Interrupt
|
| ganlikun |
0:06036f8bee2d
|
814
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
| ganlikun |
0:06036f8bee2d
|
815
|
\param [in] IRQn Device specific interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
816
|
\note IRQn must not be negative.
|
| ganlikun |
0:06036f8bee2d
|
817
|
*/
|
| ganlikun |
0:06036f8bee2d
|
818
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
819
|
{
|
| ganlikun |
0:06036f8bee2d
|
820
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
821
|
{
|
| ganlikun |
0:06036f8bee2d
|
822
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
| ganlikun |
0:06036f8bee2d
|
823
|
}
|
| ganlikun |
0:06036f8bee2d
|
824
|
}
|
| ganlikun |
0:06036f8bee2d
|
825
|
|
| ganlikun |
0:06036f8bee2d
|
826
|
|
| ganlikun |
0:06036f8bee2d
|
827
|
/**
|
| ganlikun |
0:06036f8bee2d
|
828
|
\brief Set Interrupt Priority
|
| ganlikun |
0:06036f8bee2d
|
829
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
| ganlikun |
0:06036f8bee2d
|
830
|
The interrupt number can be positive to specify a device specific interrupt,
|
| ganlikun |
0:06036f8bee2d
|
831
|
or negative to specify a processor exception.
|
| ganlikun |
0:06036f8bee2d
|
832
|
\param [in] IRQn Interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
833
|
\param [in] priority Priority to set.
|
| ganlikun |
0:06036f8bee2d
|
834
|
\note The priority cannot be set for every processor exception.
|
| ganlikun |
0:06036f8bee2d
|
835
|
*/
|
| ganlikun |
0:06036f8bee2d
|
836
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
| ganlikun |
0:06036f8bee2d
|
837
|
{
|
| ganlikun |
0:06036f8bee2d
|
838
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
839
|
{
|
| ganlikun |
0:06036f8bee2d
|
840
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
| ganlikun |
0:06036f8bee2d
|
841
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
| ganlikun |
0:06036f8bee2d
|
842
|
}
|
| ganlikun |
0:06036f8bee2d
|
843
|
else
|
| ganlikun |
0:06036f8bee2d
|
844
|
{
|
| ganlikun |
0:06036f8bee2d
|
845
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
| ganlikun |
0:06036f8bee2d
|
846
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
| ganlikun |
0:06036f8bee2d
|
847
|
}
|
| ganlikun |
0:06036f8bee2d
|
848
|
}
|
| ganlikun |
0:06036f8bee2d
|
849
|
|
| ganlikun |
0:06036f8bee2d
|
850
|
|
| ganlikun |
0:06036f8bee2d
|
851
|
/**
|
| ganlikun |
0:06036f8bee2d
|
852
|
\brief Get Interrupt Priority
|
| ganlikun |
0:06036f8bee2d
|
853
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
| ganlikun |
0:06036f8bee2d
|
854
|
The interrupt number can be positive to specify a device specific interrupt,
|
| ganlikun |
0:06036f8bee2d
|
855
|
or negative to specify a processor exception.
|
| ganlikun |
0:06036f8bee2d
|
856
|
\param [in] IRQn Interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
857
|
\return Interrupt Priority.
|
| ganlikun |
0:06036f8bee2d
|
858
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
| ganlikun |
0:06036f8bee2d
|
859
|
*/
|
| ganlikun |
0:06036f8bee2d
|
860
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
861
|
{
|
| ganlikun |
0:06036f8bee2d
|
862
|
|
| ganlikun |
0:06036f8bee2d
|
863
|
if ((int32_t)(IRQn) >= 0)
|
| ganlikun |
0:06036f8bee2d
|
864
|
{
|
| ganlikun |
0:06036f8bee2d
|
865
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
| ganlikun |
0:06036f8bee2d
|
866
|
}
|
| ganlikun |
0:06036f8bee2d
|
867
|
else
|
| ganlikun |
0:06036f8bee2d
|
868
|
{
|
| ganlikun |
0:06036f8bee2d
|
869
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
| ganlikun |
0:06036f8bee2d
|
870
|
}
|
| ganlikun |
0:06036f8bee2d
|
871
|
}
|
| ganlikun |
0:06036f8bee2d
|
872
|
|
| ganlikun |
0:06036f8bee2d
|
873
|
|
| ganlikun |
0:06036f8bee2d
|
874
|
/**
|
| ganlikun |
0:06036f8bee2d
|
875
|
\brief Set Interrupt Vector
|
| ganlikun |
0:06036f8bee2d
|
876
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
| ganlikun |
0:06036f8bee2d
|
877
|
The interrupt number can be positive to specify a device specific interrupt,
|
| ganlikun |
0:06036f8bee2d
|
878
|
or negative to specify a processor exception.
|
| ganlikun |
0:06036f8bee2d
|
879
|
VTOR must been relocated to SRAM before.
|
| ganlikun |
0:06036f8bee2d
|
880
|
If VTOR is not present address 0 must be mapped to SRAM.
|
| ganlikun |
0:06036f8bee2d
|
881
|
\param [in] IRQn Interrupt number
|
| ganlikun |
0:06036f8bee2d
|
882
|
\param [in] vector Address of interrupt handler function
|
| ganlikun |
0:06036f8bee2d
|
883
|
*/
|
| ganlikun |
0:06036f8bee2d
|
884
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
| ganlikun |
0:06036f8bee2d
|
885
|
{
|
| ganlikun |
0:06036f8bee2d
|
886
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
| ganlikun |
0:06036f8bee2d
|
887
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
| ganlikun |
0:06036f8bee2d
|
888
|
#else
|
| ganlikun |
0:06036f8bee2d
|
889
|
uint32_t *vectors = (uint32_t *)0x0U;
|
| ganlikun |
0:06036f8bee2d
|
890
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
891
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
| ganlikun |
0:06036f8bee2d
|
892
|
}
|
| ganlikun |
0:06036f8bee2d
|
893
|
|
| ganlikun |
0:06036f8bee2d
|
894
|
|
| ganlikun |
0:06036f8bee2d
|
895
|
/**
|
| ganlikun |
0:06036f8bee2d
|
896
|
\brief Get Interrupt Vector
|
| ganlikun |
0:06036f8bee2d
|
897
|
\details Reads an interrupt vector from interrupt vector table.
|
| ganlikun |
0:06036f8bee2d
|
898
|
The interrupt number can be positive to specify a device specific interrupt,
|
| ganlikun |
0:06036f8bee2d
|
899
|
or negative to specify a processor exception.
|
| ganlikun |
0:06036f8bee2d
|
900
|
\param [in] IRQn Interrupt number.
|
| ganlikun |
0:06036f8bee2d
|
901
|
\return Address of interrupt handler function
|
| ganlikun |
0:06036f8bee2d
|
902
|
*/
|
| ganlikun |
0:06036f8bee2d
|
903
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
| ganlikun |
0:06036f8bee2d
|
904
|
{
|
| ganlikun |
0:06036f8bee2d
|
905
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
| ganlikun |
0:06036f8bee2d
|
906
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
| ganlikun |
0:06036f8bee2d
|
907
|
#else
|
| ganlikun |
0:06036f8bee2d
|
908
|
uint32_t *vectors = (uint32_t *)0x0U;
|
| ganlikun |
0:06036f8bee2d
|
909
|
#endif
|
| ganlikun |
0:06036f8bee2d
|
910
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
| ganlikun |
0:06036f8bee2d
|
911
|
|
| ganlikun |
0:06036f8bee2d
|
912
|
}
|
| ganlikun |
0:06036f8bee2d
|
913
|
|
| ganlikun |
0:06036f8bee2d
|
914
|
|
| ganlikun |
0:06036f8bee2d
|
915
|
/**
|
| ganlikun |
0:06036f8bee2d
|
916
|
\brief System Reset
|
| ganlikun |
0:06036f8bee2d
|
917
|
\details Initiates a system reset request to reset the MCU.
|
| ganlikun |
0:06036f8bee2d
|
918
|
*/
|
| ganlikun |
0:06036f8bee2d
|
919
|
__STATIC_INLINE void __NVIC_SystemReset(void)
|
| ganlikun |
0:06036f8bee2d
|
920
|
{
|
| ganlikun |
0:06036f8bee2d
|
921
|
__DSB(); /* Ensure all outstanding memory accesses included
|
| ganlikun |
0:06036f8bee2d
|
922
|
buffered write are completed before reset */
|
| ganlikun |
0:06036f8bee2d
|
923
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
| ganlikun |
0:06036f8bee2d
|
924
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
| ganlikun |
0:06036f8bee2d
|
925
|
__DSB(); /* Ensure completion of memory access */
|
| ganlikun |
0:06036f8bee2d
|
926
|
|
| ganlikun |
0:06036f8bee2d
|
927
|
for(;;) /* wait until reset */
|
| ganlikun |
0:06036f8bee2d
|
928
|
{
|
| ganlikun |
0:06036f8bee2d
|
929
|
__NOP();
|
| ganlikun |
0:06036f8bee2d
|
930
|
}
|
| ganlikun |
0:06036f8bee2d
|
931
|
}
|
| ganlikun |
0:06036f8bee2d
|
932
|
|
| ganlikun |
0:06036f8bee2d
|
933
|
/*@} end of CMSIS_Core_NVICFunctions */
|
| ganlikun |
0:06036f8bee2d
|
934
|
|
| ganlikun |
0:06036f8bee2d
|
935
|
|
| ganlikun |
0:06036f8bee2d
|
936
|
/* ########################## FPU functions #################################### */
|
| ganlikun |
0:06036f8bee2d
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937
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/**
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938
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\ingroup CMSIS_Core_FunctionInterface
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939
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\defgroup CMSIS_Core_FpuFunctions FPU Functions
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940
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\brief Function that provides FPU type.
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941
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@{
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942
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*/
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943
|
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944
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/**
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945
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\brief get FPU type
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946
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\details returns the FPU type
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947
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\returns
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948
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- \b 0: No FPU
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949
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- \b 1: Single precision FPU
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950
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- \b 2: Double + Single precision FPU
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951
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*/
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952
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__STATIC_INLINE uint32_t SCB_GetFPUType(void)
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953
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{
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954
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return 0U; /* No FPU */
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955
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}
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|
956
|
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|
957
|
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958
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/*@} end of CMSIS_Core_FpuFunctions */
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959
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0:06036f8bee2d
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960
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961
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962
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/* ################################## SysTick function ############################################ */
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963
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/**
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964
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\ingroup CMSIS_Core_FunctionInterface
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965
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\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
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966
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\brief Functions that configure the System.
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967
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@{
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968
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*/
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|
969
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970
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#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
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971
|
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972
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/**
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973
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\brief System Tick Configuration
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974
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\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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975
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Counter is in free running mode to generate periodic interrupts.
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976
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\param [in] ticks Number of ticks between two interrupts.
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977
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\return 0 Function succeeded.
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|
978
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\return 1 Function failed.
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|
979
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\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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| ganlikun |
0:06036f8bee2d
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980
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function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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| ganlikun |
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981
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must contain a vendor-specific implementation of this function.
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982
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*/
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983
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__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
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984
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{
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985
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if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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0:06036f8bee2d
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986
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{
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987
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return (1UL); /* Reload value impossible */
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0:06036f8bee2d
|
988
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}
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| ganlikun |
0:06036f8bee2d
|
989
|
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990
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SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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991
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NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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992
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SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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993
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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|
994
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SysTick_CTRL_TICKINT_Msk |
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995
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SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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| ganlikun |
0:06036f8bee2d
|
996
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return (0UL); /* Function successful */
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0:06036f8bee2d
|
997
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}
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| ganlikun |
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|
998
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| ganlikun |
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999
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#endif
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| ganlikun |
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|
1000
|
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| ganlikun |
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1001
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/*@} end of CMSIS_Core_SysTickFunctions */
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| ganlikun |
0:06036f8bee2d
|
1002
|
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| ganlikun |
0:06036f8bee2d
|
1003
|
|
| ganlikun |
0:06036f8bee2d
|
1004
|
|
| ganlikun |
0:06036f8bee2d
|
1005
|
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| ganlikun |
0:06036f8bee2d
|
1006
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#ifdef __cplusplus
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|
1007
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}
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| ganlikun |
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1008
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#endif
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| ganlikun |
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|
1009
|
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| ganlikun |
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1010
|
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
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|
1011
|
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| ganlikun |
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|
1012
|
#endif /* __CMSIS_GENERIC */ |