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cmsis/core_cm7.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/************************************************************************//
ganlikun	0:13413ea9a877	2	* @file core_cm7.h
ganlikun	0:13413ea9a877	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
ganlikun	0:13413ea9a877	4	* @version V5.0.2
ganlikun	0:13413ea9a877	5	* @date 13. February 2017
ganlikun	0:13413ea9a877	6	******************************************************************************/
ganlikun	0:13413ea9a877	7	/*
ganlikun	0:13413ea9a877	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
ganlikun	0:13413ea9a877	9	*
ganlikun	0:13413ea9a877	10	* SPDX-License-Identifier: Apache-2.0
ganlikun	0:13413ea9a877	11	*
ganlikun	0:13413ea9a877	12	* Licensed under the Apache License, Version 2.0 (the License); you may
ganlikun	0:13413ea9a877	13	* not use this file except in compliance with the License.
ganlikun	0:13413ea9a877	14	* You may obtain a copy of the License at
ganlikun	0:13413ea9a877	15	*
ganlikun	0:13413ea9a877	16	* www.apache.org/licenses/LICENSE-2.0
ganlikun	0:13413ea9a877	17	*
ganlikun	0:13413ea9a877	18	* Unless required by applicable law or agreed to in writing, software
ganlikun	0:13413ea9a877	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
ganlikun	0:13413ea9a877	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ganlikun	0:13413ea9a877	21	* See the License for the specific language governing permissions and
ganlikun	0:13413ea9a877	22	* limitations under the License.
ganlikun	0:13413ea9a877	23	*/
ganlikun	0:13413ea9a877	24
ganlikun	0:13413ea9a877	25	#if defined ( __ICCARM__ )
ganlikun	0:13413ea9a877	26	#pragma system_include /* treat file as system include file for MISRA check */
ganlikun	0:13413ea9a877	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun	0:13413ea9a877	28	#pragma clang system_header /* treat file as system include file */
ganlikun	0:13413ea9a877	29	#endif
ganlikun	0:13413ea9a877	30
ganlikun	0:13413ea9a877	31	#ifndef __CORE_CM7_H_GENERIC
ganlikun	0:13413ea9a877	32	#define __CORE_CM7_H_GENERIC
ganlikun	0:13413ea9a877	33
ganlikun	0:13413ea9a877	34	#include <stdint.h>
ganlikun	0:13413ea9a877	35
ganlikun	0:13413ea9a877	36	#ifdef __cplusplus
ganlikun	0:13413ea9a877	37	extern "C" {
ganlikun	0:13413ea9a877	38	#endif
ganlikun	0:13413ea9a877	39
ganlikun	0:13413ea9a877	40	/**
ganlikun	0:13413ea9a877	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
ganlikun	0:13413ea9a877	42	CMSIS violates the following MISRA-C:2004 rules:
ganlikun	0:13413ea9a877	43
ganlikun	0:13413ea9a877	44	\li Required Rule 8.5, object/function definition in header file.<br>
ganlikun	0:13413ea9a877	45	Function definitions in header files are used to allow 'inlining'.
ganlikun	0:13413ea9a877	46
ganlikun	0:13413ea9a877	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
ganlikun	0:13413ea9a877	48	Unions are used for effective representation of core registers.
ganlikun	0:13413ea9a877	49
ganlikun	0:13413ea9a877	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
ganlikun	0:13413ea9a877	51	Function-like macros are used to allow more efficient code.
ganlikun	0:13413ea9a877	52	*/
ganlikun	0:13413ea9a877	53
ganlikun	0:13413ea9a877	54
ganlikun	0:13413ea9a877	55	/*******************************************************************************
ganlikun	0:13413ea9a877	56	* CMSIS definitions
ganlikun	0:13413ea9a877	57	******************************************************************************/
ganlikun	0:13413ea9a877	58	/**
ganlikun	0:13413ea9a877	59	\ingroup Cortex_M7
ganlikun	0:13413ea9a877	60	@{
ganlikun	0:13413ea9a877	61	*/
ganlikun	0:13413ea9a877	62
ganlikun	0:13413ea9a877	63	/* CMSIS CM7 definitions */
ganlikun	0:13413ea9a877	64	#define __CM7_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
ganlikun	0:13413ea9a877	65	#define __CM7_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
ganlikun	0:13413ea9a877	66	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
ganlikun	0:13413ea9a877	67	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
ganlikun	0:13413ea9a877	68
ganlikun	0:13413ea9a877	69	#define __CORTEX_M (7U) /!< Cortex-M Core /
ganlikun	0:13413ea9a877	70
ganlikun	0:13413ea9a877	71	/** __FPU_USED indicates whether an FPU is used or not.
ganlikun	0:13413ea9a877	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
ganlikun	0:13413ea9a877	73	*/
ganlikun	0:13413ea9a877	74	#if defined ( __CC_ARM )
ganlikun	0:13413ea9a877	75	#if defined __TARGET_FPU_VFP
ganlikun	0:13413ea9a877	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	77	#define __FPU_USED 1U
ganlikun	0:13413ea9a877	78	#else
ganlikun	0:13413ea9a877	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun	0:13413ea9a877	80	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	81	#endif
ganlikun	0:13413ea9a877	82	#else
ganlikun	0:13413ea9a877	83	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	84	#endif
ganlikun	0:13413ea9a877	85
ganlikun	0:13413ea9a877	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun	0:13413ea9a877	87	#if defined __ARM_PCS_VFP
ganlikun	0:13413ea9a877	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	89	#define __FPU_USED 1U
ganlikun	0:13413ea9a877	90	#else
ganlikun	0:13413ea9a877	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun	0:13413ea9a877	92	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	93	#endif
ganlikun	0:13413ea9a877	94	#else
ganlikun	0:13413ea9a877	95	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	96	#endif
ganlikun	0:13413ea9a877	97
ganlikun	0:13413ea9a877	98	#elif defined ( __GNUC__ )
ganlikun	0:13413ea9a877	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
ganlikun	0:13413ea9a877	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	101	#define __FPU_USED 1U
ganlikun	0:13413ea9a877	102	#else
ganlikun	0:13413ea9a877	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun	0:13413ea9a877	104	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	105	#endif
ganlikun	0:13413ea9a877	106	#else
ganlikun	0:13413ea9a877	107	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	108	#endif
ganlikun	0:13413ea9a877	109
ganlikun	0:13413ea9a877	110	#elif defined ( __ICCARM__ )
ganlikun	0:13413ea9a877	111	#if defined __ARMVFP__
ganlikun	0:13413ea9a877	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	113	#define __FPU_USED 1U
ganlikun	0:13413ea9a877	114	#else
ganlikun	0:13413ea9a877	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun	0:13413ea9a877	116	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	117	#endif
ganlikun	0:13413ea9a877	118	#else
ganlikun	0:13413ea9a877	119	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	120	#endif
ganlikun	0:13413ea9a877	121
ganlikun	0:13413ea9a877	122	#elif defined ( __TI_ARM__ )
ganlikun	0:13413ea9a877	123	#if defined __TI_VFP_SUPPORT__
ganlikun	0:13413ea9a877	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	125	#define __FPU_USED 1U
ganlikun	0:13413ea9a877	126	#else
ganlikun	0:13413ea9a877	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun	0:13413ea9a877	128	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	129	#endif
ganlikun	0:13413ea9a877	130	#else
ganlikun	0:13413ea9a877	131	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	132	#endif
ganlikun	0:13413ea9a877	133
ganlikun	0:13413ea9a877	134	#elif defined ( __TASKING__ )
ganlikun	0:13413ea9a877	135	#if defined __FPU_VFP__
ganlikun	0:13413ea9a877	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	137	#define __FPU_USED 1U
ganlikun	0:13413ea9a877	138	#else
ganlikun	0:13413ea9a877	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun	0:13413ea9a877	140	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	141	#endif
ganlikun	0:13413ea9a877	142	#else
ganlikun	0:13413ea9a877	143	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	144	#endif
ganlikun	0:13413ea9a877	145
ganlikun	0:13413ea9a877	146	#elif defined ( __CSMC__ )
ganlikun	0:13413ea9a877	147	#if ( __CSMC__ & 0x400U)
ganlikun	0:13413ea9a877	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	149	#define __FPU_USED 1U
ganlikun	0:13413ea9a877	150	#else
ganlikun	0:13413ea9a877	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun	0:13413ea9a877	152	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	153	#endif
ganlikun	0:13413ea9a877	154	#else
ganlikun	0:13413ea9a877	155	#define __FPU_USED 0U
ganlikun	0:13413ea9a877	156	#endif
ganlikun	0:13413ea9a877	157
ganlikun	0:13413ea9a877	158	#endif
ganlikun	0:13413ea9a877	159
ganlikun	0:13413ea9a877	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
ganlikun	0:13413ea9a877	161
ganlikun	0:13413ea9a877	162
ganlikun	0:13413ea9a877	163	#ifdef __cplusplus
ganlikun	0:13413ea9a877	164	}
ganlikun	0:13413ea9a877	165	#endif
ganlikun	0:13413ea9a877	166
ganlikun	0:13413ea9a877	167	#endif /* __CORE_CM7_H_GENERIC */
ganlikun	0:13413ea9a877	168
ganlikun	0:13413ea9a877	169	#ifndef __CMSIS_GENERIC
ganlikun	0:13413ea9a877	170
ganlikun	0:13413ea9a877	171	#ifndef __CORE_CM7_H_DEPENDANT
ganlikun	0:13413ea9a877	172	#define __CORE_CM7_H_DEPENDANT
ganlikun	0:13413ea9a877	173
ganlikun	0:13413ea9a877	174	#ifdef __cplusplus
ganlikun	0:13413ea9a877	175	extern "C" {
ganlikun	0:13413ea9a877	176	#endif
ganlikun	0:13413ea9a877	177
ganlikun	0:13413ea9a877	178	/* check device defines and use defaults */
ganlikun	0:13413ea9a877	179	#if defined __CHECK_DEVICE_DEFINES
ganlikun	0:13413ea9a877	180	#ifndef __CM7_REV
ganlikun	0:13413ea9a877	181	#define __CM7_REV 0x0000U
ganlikun	0:13413ea9a877	182	#warning "__CM7_REV not defined in device header file; using default!"
ganlikun	0:13413ea9a877	183	#endif
ganlikun	0:13413ea9a877	184
ganlikun	0:13413ea9a877	185	#ifndef __FPU_PRESENT
ganlikun	0:13413ea9a877	186	#define __FPU_PRESENT 0U
ganlikun	0:13413ea9a877	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
ganlikun	0:13413ea9a877	188	#endif
ganlikun	0:13413ea9a877	189
ganlikun	0:13413ea9a877	190	#ifndef __MPU_PRESENT
ganlikun	0:13413ea9a877	191	#define __MPU_PRESENT 0U
ganlikun	0:13413ea9a877	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
ganlikun	0:13413ea9a877	193	#endif
ganlikun	0:13413ea9a877	194
ganlikun	0:13413ea9a877	195	#ifndef __ICACHE_PRESENT
ganlikun	0:13413ea9a877	196	#define __ICACHE_PRESENT 0U
ganlikun	0:13413ea9a877	197	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
ganlikun	0:13413ea9a877	198	#endif
ganlikun	0:13413ea9a877	199
ganlikun	0:13413ea9a877	200	#ifndef __DCACHE_PRESENT
ganlikun	0:13413ea9a877	201	#define __DCACHE_PRESENT 0U
ganlikun	0:13413ea9a877	202	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
ganlikun	0:13413ea9a877	203	#endif
ganlikun	0:13413ea9a877	204
ganlikun	0:13413ea9a877	205	#ifndef __DTCM_PRESENT
ganlikun	0:13413ea9a877	206	#define __DTCM_PRESENT 0U
ganlikun	0:13413ea9a877	207	#warning "__DTCM_PRESENT not defined in device header file; using default!"
ganlikun	0:13413ea9a877	208	#endif
ganlikun	0:13413ea9a877	209
ganlikun	0:13413ea9a877	210	#ifndef __NVIC_PRIO_BITS
ganlikun	0:13413ea9a877	211	#define __NVIC_PRIO_BITS 3U
ganlikun	0:13413ea9a877	212	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
ganlikun	0:13413ea9a877	213	#endif
ganlikun	0:13413ea9a877	214
ganlikun	0:13413ea9a877	215	#ifndef __Vendor_SysTickConfig
ganlikun	0:13413ea9a877	216	#define __Vendor_SysTickConfig 0U
ganlikun	0:13413ea9a877	217	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
ganlikun	0:13413ea9a877	218	#endif
ganlikun	0:13413ea9a877	219	#endif
ganlikun	0:13413ea9a877	220
ganlikun	0:13413ea9a877	221	/* IO definitions (access restrictions to peripheral registers) */
ganlikun	0:13413ea9a877	222	/**
ganlikun	0:13413ea9a877	223	\defgroup CMSIS_glob_defs CMSIS Global Defines
ganlikun	0:13413ea9a877	224
ganlikun	0:13413ea9a877	225	<strong>IO Type Qualifiers</strong> are used
ganlikun	0:13413ea9a877	226	\li to specify the access to peripheral variables.
ganlikun	0:13413ea9a877	227	\li for automatic generation of peripheral register debug information.
ganlikun	0:13413ea9a877	228	*/
ganlikun	0:13413ea9a877	229	#ifdef __cplusplus
ganlikun	0:13413ea9a877	230	#define __I volatile /!< Defines 'read only' permissions /
ganlikun	0:13413ea9a877	231	#else
ganlikun	0:13413ea9a877	232	#define __I volatile const /!< Defines 'read only' permissions /
ganlikun	0:13413ea9a877	233	#endif
ganlikun	0:13413ea9a877	234	#define __O volatile /!< Defines 'write only' permissions /
ganlikun	0:13413ea9a877	235	#define __IO volatile /!< Defines 'read / write' permissions /
ganlikun	0:13413ea9a877	236
ganlikun	0:13413ea9a877	237	/* following defines should be used for structure members */
ganlikun	0:13413ea9a877	238	#define __IM volatile const /! Defines 'read only' structure member permissions /
ganlikun	0:13413ea9a877	239	#define __OM volatile /! Defines 'write only' structure member permissions /
ganlikun	0:13413ea9a877	240	#define __IOM volatile /! Defines 'read / write' structure member permissions /
ganlikun	0:13413ea9a877	241
ganlikun	0:13413ea9a877	242	/@} end of group Cortex_M7 /
ganlikun	0:13413ea9a877	243
ganlikun	0:13413ea9a877	244
ganlikun	0:13413ea9a877	245
ganlikun	0:13413ea9a877	246	/*******************************************************************************
ganlikun	0:13413ea9a877	247	* Register Abstraction
ganlikun	0:13413ea9a877	248	Core Register contain:
ganlikun	0:13413ea9a877	249	- Core Register
ganlikun	0:13413ea9a877	250	- Core NVIC Register
ganlikun	0:13413ea9a877	251	- Core SCB Register
ganlikun	0:13413ea9a877	252	- Core SysTick Register
ganlikun	0:13413ea9a877	253	- Core Debug Register
ganlikun	0:13413ea9a877	254	- Core MPU Register
ganlikun	0:13413ea9a877	255	- Core FPU Register
ganlikun	0:13413ea9a877	256	******************************************************************************/
ganlikun	0:13413ea9a877	257	/**
ganlikun	0:13413ea9a877	258	\defgroup CMSIS_core_register Defines and Type Definitions
ganlikun	0:13413ea9a877	259	\brief Type definitions and defines for Cortex-M processor based devices.
ganlikun	0:13413ea9a877	260	*/
ganlikun	0:13413ea9a877	261
ganlikun	0:13413ea9a877	262	/**
ganlikun	0:13413ea9a877	263	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	264	\defgroup CMSIS_CORE Status and Control Registers
ganlikun	0:13413ea9a877	265	\brief Core Register type definitions.
ganlikun	0:13413ea9a877	266	@{
ganlikun	0:13413ea9a877	267	*/
ganlikun	0:13413ea9a877	268
ganlikun	0:13413ea9a877	269	/**
ganlikun	0:13413ea9a877	270	\brief Union type to access the Application Program Status Register (APSR).
ganlikun	0:13413ea9a877	271	*/
ganlikun	0:13413ea9a877	272	typedef union
ganlikun	0:13413ea9a877	273	{
ganlikun	0:13413ea9a877	274	struct
ganlikun	0:13413ea9a877	275	{
ganlikun	0:13413ea9a877	276	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
ganlikun	0:13413ea9a877	277	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
ganlikun	0:13413ea9a877	278	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
ganlikun	0:13413ea9a877	279	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
ganlikun	0:13413ea9a877	280	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
ganlikun	0:13413ea9a877	281	uint32_t C:1; /!< bit: 29 Carry condition code flag /
ganlikun	0:13413ea9a877	282	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
ganlikun	0:13413ea9a877	283	uint32_t N:1; /!< bit: 31 Negative condition code flag /
ganlikun	0:13413ea9a877	284	} b; /!< Structure used for bit access /
ganlikun	0:13413ea9a877	285	uint32_t w; /!< Type used for word access /
ganlikun	0:13413ea9a877	286	} APSR_Type;
ganlikun	0:13413ea9a877	287
ganlikun	0:13413ea9a877	288	/* APSR Register Definitions */
ganlikun	0:13413ea9a877	289	#define APSR_N_Pos 31U /!< APSR: N Position /
ganlikun	0:13413ea9a877	290	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
ganlikun	0:13413ea9a877	291
ganlikun	0:13413ea9a877	292	#define APSR_Z_Pos 30U /!< APSR: Z Position /
ganlikun	0:13413ea9a877	293	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
ganlikun	0:13413ea9a877	294
ganlikun	0:13413ea9a877	295	#define APSR_C_Pos 29U /!< APSR: C Position /
ganlikun	0:13413ea9a877	296	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
ganlikun	0:13413ea9a877	297
ganlikun	0:13413ea9a877	298	#define APSR_V_Pos 28U /!< APSR: V Position /
ganlikun	0:13413ea9a877	299	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
ganlikun	0:13413ea9a877	300
ganlikun	0:13413ea9a877	301	#define APSR_Q_Pos 27U /!< APSR: Q Position /
ganlikun	0:13413ea9a877	302	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
ganlikun	0:13413ea9a877	303
ganlikun	0:13413ea9a877	304	#define APSR_GE_Pos 16U /!< APSR: GE Position /
ganlikun	0:13413ea9a877	305	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
ganlikun	0:13413ea9a877	306
ganlikun	0:13413ea9a877	307
ganlikun	0:13413ea9a877	308	/**
ganlikun	0:13413ea9a877	309	\brief Union type to access the Interrupt Program Status Register (IPSR).
ganlikun	0:13413ea9a877	310	*/
ganlikun	0:13413ea9a877	311	typedef union
ganlikun	0:13413ea9a877	312	{
ganlikun	0:13413ea9a877	313	struct
ganlikun	0:13413ea9a877	314	{
ganlikun	0:13413ea9a877	315	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
ganlikun	0:13413ea9a877	316	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
ganlikun	0:13413ea9a877	317	} b; /!< Structure used for bit access /
ganlikun	0:13413ea9a877	318	uint32_t w; /!< Type used for word access /
ganlikun	0:13413ea9a877	319	} IPSR_Type;
ganlikun	0:13413ea9a877	320
ganlikun	0:13413ea9a877	321	/* IPSR Register Definitions */
ganlikun	0:13413ea9a877	322	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
ganlikun	0:13413ea9a877	323	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
ganlikun	0:13413ea9a877	324
ganlikun	0:13413ea9a877	325
ganlikun	0:13413ea9a877	326	/**
ganlikun	0:13413ea9a877	327	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ganlikun	0:13413ea9a877	328	*/
ganlikun	0:13413ea9a877	329	typedef union
ganlikun	0:13413ea9a877	330	{
ganlikun	0:13413ea9a877	331	struct
ganlikun	0:13413ea9a877	332	{
ganlikun	0:13413ea9a877	333	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
ganlikun	0:13413ea9a877	334	uint32_t _reserved0:1; /!< bit: 9 Reserved /
ganlikun	0:13413ea9a877	335	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
ganlikun	0:13413ea9a877	336	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
ganlikun	0:13413ea9a877	337	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
ganlikun	0:13413ea9a877	338	uint32_t T:1; /!< bit: 24 Thumb bit /
ganlikun	0:13413ea9a877	339	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
ganlikun	0:13413ea9a877	340	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
ganlikun	0:13413ea9a877	341	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
ganlikun	0:13413ea9a877	342	uint32_t C:1; /!< bit: 29 Carry condition code flag /
ganlikun	0:13413ea9a877	343	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
ganlikun	0:13413ea9a877	344	uint32_t N:1; /!< bit: 31 Negative condition code flag /
ganlikun	0:13413ea9a877	345	} b; /!< Structure used for bit access /
ganlikun	0:13413ea9a877	346	uint32_t w; /!< Type used for word access /
ganlikun	0:13413ea9a877	347	} xPSR_Type;
ganlikun	0:13413ea9a877	348
ganlikun	0:13413ea9a877	349	/* xPSR Register Definitions */
ganlikun	0:13413ea9a877	350	#define xPSR_N_Pos 31U /!< xPSR: N Position /
ganlikun	0:13413ea9a877	351	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
ganlikun	0:13413ea9a877	352
ganlikun	0:13413ea9a877	353	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
ganlikun	0:13413ea9a877	354	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
ganlikun	0:13413ea9a877	355
ganlikun	0:13413ea9a877	356	#define xPSR_C_Pos 29U /!< xPSR: C Position /
ganlikun	0:13413ea9a877	357	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
ganlikun	0:13413ea9a877	358
ganlikun	0:13413ea9a877	359	#define xPSR_V_Pos 28U /!< xPSR: V Position /
ganlikun	0:13413ea9a877	360	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
ganlikun	0:13413ea9a877	361
ganlikun	0:13413ea9a877	362	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
ganlikun	0:13413ea9a877	363	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
ganlikun	0:13413ea9a877	364
ganlikun	0:13413ea9a877	365	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
ganlikun	0:13413ea9a877	366	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
ganlikun	0:13413ea9a877	367
ganlikun	0:13413ea9a877	368	#define xPSR_T_Pos 24U /!< xPSR: T Position /
ganlikun	0:13413ea9a877	369	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
ganlikun	0:13413ea9a877	370
ganlikun	0:13413ea9a877	371	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
ganlikun	0:13413ea9a877	372	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
ganlikun	0:13413ea9a877	373
ganlikun	0:13413ea9a877	374	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
ganlikun	0:13413ea9a877	375	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
ganlikun	0:13413ea9a877	376
ganlikun	0:13413ea9a877	377	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
ganlikun	0:13413ea9a877	378	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
ganlikun	0:13413ea9a877	379
ganlikun	0:13413ea9a877	380
ganlikun	0:13413ea9a877	381	/**
ganlikun	0:13413ea9a877	382	\brief Union type to access the Control Registers (CONTROL).
ganlikun	0:13413ea9a877	383	*/
ganlikun	0:13413ea9a877	384	typedef union
ganlikun	0:13413ea9a877	385	{
ganlikun	0:13413ea9a877	386	struct
ganlikun	0:13413ea9a877	387	{
ganlikun	0:13413ea9a877	388	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
ganlikun	0:13413ea9a877	389	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
ganlikun	0:13413ea9a877	390	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
ganlikun	0:13413ea9a877	391	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
ganlikun	0:13413ea9a877	392	} b; /!< Structure used for bit access /
ganlikun	0:13413ea9a877	393	uint32_t w; /!< Type used for word access /
ganlikun	0:13413ea9a877	394	} CONTROL_Type;
ganlikun	0:13413ea9a877	395
ganlikun	0:13413ea9a877	396	/* CONTROL Register Definitions */
ganlikun	0:13413ea9a877	397	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
ganlikun	0:13413ea9a877	398	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
ganlikun	0:13413ea9a877	399
ganlikun	0:13413ea9a877	400	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
ganlikun	0:13413ea9a877	401	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
ganlikun	0:13413ea9a877	402
ganlikun	0:13413ea9a877	403	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
ganlikun	0:13413ea9a877	404	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
ganlikun	0:13413ea9a877	405
ganlikun	0:13413ea9a877	406	/@} end of group CMSIS_CORE /
ganlikun	0:13413ea9a877	407
ganlikun	0:13413ea9a877	408
ganlikun	0:13413ea9a877	409	/**
ganlikun	0:13413ea9a877	410	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	411	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
ganlikun	0:13413ea9a877	412	\brief Type definitions for the NVIC Registers
ganlikun	0:13413ea9a877	413	@{
ganlikun	0:13413ea9a877	414	*/
ganlikun	0:13413ea9a877	415
ganlikun	0:13413ea9a877	416	/**
ganlikun	0:13413ea9a877	417	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
ganlikun	0:13413ea9a877	418	*/
ganlikun	0:13413ea9a877	419	typedef struct
ganlikun	0:13413ea9a877	420	{
ganlikun	0:13413ea9a877	421	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
ganlikun	0:13413ea9a877	422	uint32_t RESERVED0[24U];
ganlikun	0:13413ea9a877	423	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
ganlikun	0:13413ea9a877	424	uint32_t RSERVED1[24U];
ganlikun	0:13413ea9a877	425	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
ganlikun	0:13413ea9a877	426	uint32_t RESERVED2[24U];
ganlikun	0:13413ea9a877	427	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
ganlikun	0:13413ea9a877	428	uint32_t RESERVED3[24U];
ganlikun	0:13413ea9a877	429	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
ganlikun	0:13413ea9a877	430	uint32_t RESERVED4[56U];
ganlikun	0:13413ea9a877	431	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
ganlikun	0:13413ea9a877	432	uint32_t RESERVED5[644U];
ganlikun	0:13413ea9a877	433	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
ganlikun	0:13413ea9a877	434	} NVIC_Type;
ganlikun	0:13413ea9a877	435
ganlikun	0:13413ea9a877	436	/* Software Triggered Interrupt Register Definitions */
ganlikun	0:13413ea9a877	437	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
ganlikun	0:13413ea9a877	438	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
ganlikun	0:13413ea9a877	439
ganlikun	0:13413ea9a877	440	/@} end of group CMSIS_NVIC /
ganlikun	0:13413ea9a877	441
ganlikun	0:13413ea9a877	442
ganlikun	0:13413ea9a877	443	/**
ganlikun	0:13413ea9a877	444	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	445	\defgroup CMSIS_SCB System Control Block (SCB)
ganlikun	0:13413ea9a877	446	\brief Type definitions for the System Control Block Registers
ganlikun	0:13413ea9a877	447	@{
ganlikun	0:13413ea9a877	448	*/
ganlikun	0:13413ea9a877	449
ganlikun	0:13413ea9a877	450	/**
ganlikun	0:13413ea9a877	451	\brief Structure type to access the System Control Block (SCB).
ganlikun	0:13413ea9a877	452	*/
ganlikun	0:13413ea9a877	453	typedef struct
ganlikun	0:13413ea9a877	454	{
ganlikun	0:13413ea9a877	455	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
ganlikun	0:13413ea9a877	456	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
ganlikun	0:13413ea9a877	457	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
ganlikun	0:13413ea9a877	458	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
ganlikun	0:13413ea9a877	459	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
ganlikun	0:13413ea9a877	460	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
ganlikun	0:13413ea9a877	461	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
ganlikun	0:13413ea9a877	462	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
ganlikun	0:13413ea9a877	463	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
ganlikun	0:13413ea9a877	464	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
ganlikun	0:13413ea9a877	465	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
ganlikun	0:13413ea9a877	466	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
ganlikun	0:13413ea9a877	467	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
ganlikun	0:13413ea9a877	468	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
ganlikun	0:13413ea9a877	469	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
ganlikun	0:13413ea9a877	470	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
ganlikun	0:13413ea9a877	471	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
ganlikun	0:13413ea9a877	472	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
ganlikun	0:13413ea9a877	473	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
ganlikun	0:13413ea9a877	474	uint32_t RESERVED0[1U];
ganlikun	0:13413ea9a877	475	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
ganlikun	0:13413ea9a877	476	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
ganlikun	0:13413ea9a877	477	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
ganlikun	0:13413ea9a877	478	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
ganlikun	0:13413ea9a877	479	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
ganlikun	0:13413ea9a877	480	uint32_t RESERVED3[93U];
ganlikun	0:13413ea9a877	481	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
ganlikun	0:13413ea9a877	482	uint32_t RESERVED4[15U];
ganlikun	0:13413ea9a877	483	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
ganlikun	0:13413ea9a877	484	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
ganlikun	0:13413ea9a877	485	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
ganlikun	0:13413ea9a877	486	uint32_t RESERVED5[1U];
ganlikun	0:13413ea9a877	487	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
ganlikun	0:13413ea9a877	488	uint32_t RESERVED6[1U];
ganlikun	0:13413ea9a877	489	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
ganlikun	0:13413ea9a877	490	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
ganlikun	0:13413ea9a877	491	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
ganlikun	0:13413ea9a877	492	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
ganlikun	0:13413ea9a877	493	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
ganlikun	0:13413ea9a877	494	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
ganlikun	0:13413ea9a877	495	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
ganlikun	0:13413ea9a877	496	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
ganlikun	0:13413ea9a877	497	uint32_t RESERVED7[6U];
ganlikun	0:13413ea9a877	498	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
ganlikun	0:13413ea9a877	499	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
ganlikun	0:13413ea9a877	500	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
ganlikun	0:13413ea9a877	501	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
ganlikun	0:13413ea9a877	502	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
ganlikun	0:13413ea9a877	503	uint32_t RESERVED8[1U];
ganlikun	0:13413ea9a877	504	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
ganlikun	0:13413ea9a877	505	} SCB_Type;
ganlikun	0:13413ea9a877	506
ganlikun	0:13413ea9a877	507	/* SCB CPUID Register Definitions */
ganlikun	0:13413ea9a877	508	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
ganlikun	0:13413ea9a877	509	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
ganlikun	0:13413ea9a877	510
ganlikun	0:13413ea9a877	511	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
ganlikun	0:13413ea9a877	512	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
ganlikun	0:13413ea9a877	513
ganlikun	0:13413ea9a877	514	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
ganlikun	0:13413ea9a877	515	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
ganlikun	0:13413ea9a877	516
ganlikun	0:13413ea9a877	517	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
ganlikun	0:13413ea9a877	518	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
ganlikun	0:13413ea9a877	519
ganlikun	0:13413ea9a877	520	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
ganlikun	0:13413ea9a877	521	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
ganlikun	0:13413ea9a877	522
ganlikun	0:13413ea9a877	523	/* SCB Interrupt Control State Register Definitions */
ganlikun	0:13413ea9a877	524	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
ganlikun	0:13413ea9a877	525	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
ganlikun	0:13413ea9a877	526
ganlikun	0:13413ea9a877	527	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
ganlikun	0:13413ea9a877	528	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
ganlikun	0:13413ea9a877	529
ganlikun	0:13413ea9a877	530	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
ganlikun	0:13413ea9a877	531	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
ganlikun	0:13413ea9a877	532
ganlikun	0:13413ea9a877	533	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
ganlikun	0:13413ea9a877	534	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
ganlikun	0:13413ea9a877	535
ganlikun	0:13413ea9a877	536	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
ganlikun	0:13413ea9a877	537	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
ganlikun	0:13413ea9a877	538
ganlikun	0:13413ea9a877	539	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
ganlikun	0:13413ea9a877	540	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
ganlikun	0:13413ea9a877	541
ganlikun	0:13413ea9a877	542	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
ganlikun	0:13413ea9a877	543	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
ganlikun	0:13413ea9a877	544
ganlikun	0:13413ea9a877	545	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
ganlikun	0:13413ea9a877	546	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
ganlikun	0:13413ea9a877	547
ganlikun	0:13413ea9a877	548	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
ganlikun	0:13413ea9a877	549	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
ganlikun	0:13413ea9a877	550
ganlikun	0:13413ea9a877	551	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
ganlikun	0:13413ea9a877	552	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
ganlikun	0:13413ea9a877	553
ganlikun	0:13413ea9a877	554	/* SCB Vector Table Offset Register Definitions */
ganlikun	0:13413ea9a877	555	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
ganlikun	0:13413ea9a877	556	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
ganlikun	0:13413ea9a877	557
ganlikun	0:13413ea9a877	558	/* SCB Application Interrupt and Reset Control Register Definitions */
ganlikun	0:13413ea9a877	559	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
ganlikun	0:13413ea9a877	560	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
ganlikun	0:13413ea9a877	561
ganlikun	0:13413ea9a877	562	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
ganlikun	0:13413ea9a877	563	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
ganlikun	0:13413ea9a877	564
ganlikun	0:13413ea9a877	565	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
ganlikun	0:13413ea9a877	566	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
ganlikun	0:13413ea9a877	567
ganlikun	0:13413ea9a877	568	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
ganlikun	0:13413ea9a877	569	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
ganlikun	0:13413ea9a877	570
ganlikun	0:13413ea9a877	571	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
ganlikun	0:13413ea9a877	572	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
ganlikun	0:13413ea9a877	573
ganlikun	0:13413ea9a877	574	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
ganlikun	0:13413ea9a877	575	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
ganlikun	0:13413ea9a877	576
ganlikun	0:13413ea9a877	577	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
ganlikun	0:13413ea9a877	578	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
ganlikun	0:13413ea9a877	579
ganlikun	0:13413ea9a877	580	/* SCB System Control Register Definitions */
ganlikun	0:13413ea9a877	581	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
ganlikun	0:13413ea9a877	582	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
ganlikun	0:13413ea9a877	583
ganlikun	0:13413ea9a877	584	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
ganlikun	0:13413ea9a877	585	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
ganlikun	0:13413ea9a877	586
ganlikun	0:13413ea9a877	587	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
ganlikun	0:13413ea9a877	588	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
ganlikun	0:13413ea9a877	589
ganlikun	0:13413ea9a877	590	/* SCB Configuration Control Register Definitions */
ganlikun	0:13413ea9a877	591	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
ganlikun	0:13413ea9a877	592	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
ganlikun	0:13413ea9a877	593
ganlikun	0:13413ea9a877	594	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
ganlikun	0:13413ea9a877	595	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
ganlikun	0:13413ea9a877	596
ganlikun	0:13413ea9a877	597	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
ganlikun	0:13413ea9a877	598	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
ganlikun	0:13413ea9a877	599
ganlikun	0:13413ea9a877	600	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
ganlikun	0:13413ea9a877	601	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
ganlikun	0:13413ea9a877	602
ganlikun	0:13413ea9a877	603	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
ganlikun	0:13413ea9a877	604	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
ganlikun	0:13413ea9a877	605
ganlikun	0:13413ea9a877	606	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
ganlikun	0:13413ea9a877	607	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
ganlikun	0:13413ea9a877	608
ganlikun	0:13413ea9a877	609	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
ganlikun	0:13413ea9a877	610	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
ganlikun	0:13413ea9a877	611
ganlikun	0:13413ea9a877	612	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
ganlikun	0:13413ea9a877	613	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
ganlikun	0:13413ea9a877	614
ganlikun	0:13413ea9a877	615	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
ganlikun	0:13413ea9a877	616	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
ganlikun	0:13413ea9a877	617
ganlikun	0:13413ea9a877	618	/* SCB System Handler Control and State Register Definitions */
ganlikun	0:13413ea9a877	619	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
ganlikun	0:13413ea9a877	620	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
ganlikun	0:13413ea9a877	621
ganlikun	0:13413ea9a877	622	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
ganlikun	0:13413ea9a877	623	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
ganlikun	0:13413ea9a877	624
ganlikun	0:13413ea9a877	625	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
ganlikun	0:13413ea9a877	626	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
ganlikun	0:13413ea9a877	627
ganlikun	0:13413ea9a877	628	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
ganlikun	0:13413ea9a877	629	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
ganlikun	0:13413ea9a877	630
ganlikun	0:13413ea9a877	631	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
ganlikun	0:13413ea9a877	632	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
ganlikun	0:13413ea9a877	633
ganlikun	0:13413ea9a877	634	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
ganlikun	0:13413ea9a877	635	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
ganlikun	0:13413ea9a877	636
ganlikun	0:13413ea9a877	637	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
ganlikun	0:13413ea9a877	638	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
ganlikun	0:13413ea9a877	639
ganlikun	0:13413ea9a877	640	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
ganlikun	0:13413ea9a877	641	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
ganlikun	0:13413ea9a877	642
ganlikun	0:13413ea9a877	643	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
ganlikun	0:13413ea9a877	644	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
ganlikun	0:13413ea9a877	645
ganlikun	0:13413ea9a877	646	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
ganlikun	0:13413ea9a877	647	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
ganlikun	0:13413ea9a877	648
ganlikun	0:13413ea9a877	649	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
ganlikun	0:13413ea9a877	650	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
ganlikun	0:13413ea9a877	651
ganlikun	0:13413ea9a877	652	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
ganlikun	0:13413ea9a877	653	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
ganlikun	0:13413ea9a877	654
ganlikun	0:13413ea9a877	655	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
ganlikun	0:13413ea9a877	656	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
ganlikun	0:13413ea9a877	657
ganlikun	0:13413ea9a877	658	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
ganlikun	0:13413ea9a877	659	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
ganlikun	0:13413ea9a877	660
ganlikun	0:13413ea9a877	661	/* SCB Configurable Fault Status Register Definitions */
ganlikun	0:13413ea9a877	662	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
ganlikun	0:13413ea9a877	663	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
ganlikun	0:13413ea9a877	664
ganlikun	0:13413ea9a877	665	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
ganlikun	0:13413ea9a877	666	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
ganlikun	0:13413ea9a877	667
ganlikun	0:13413ea9a877	668	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
ganlikun	0:13413ea9a877	669	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
ganlikun	0:13413ea9a877	670
ganlikun	0:13413ea9a877	671	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
ganlikun	0:13413ea9a877	672	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
ganlikun	0:13413ea9a877	673	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
ganlikun	0:13413ea9a877	674
ganlikun	0:13413ea9a877	675	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
ganlikun	0:13413ea9a877	676	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
ganlikun	0:13413ea9a877	677
ganlikun	0:13413ea9a877	678	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
ganlikun	0:13413ea9a877	679	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
ganlikun	0:13413ea9a877	680
ganlikun	0:13413ea9a877	681	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
ganlikun	0:13413ea9a877	682	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
ganlikun	0:13413ea9a877	683
ganlikun	0:13413ea9a877	684	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
ganlikun	0:13413ea9a877	685	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
ganlikun	0:13413ea9a877	686
ganlikun	0:13413ea9a877	687	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
ganlikun	0:13413ea9a877	688	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
ganlikun	0:13413ea9a877	689
ganlikun	0:13413ea9a877	690	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
ganlikun	0:13413ea9a877	691	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
ganlikun	0:13413ea9a877	692	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
ganlikun	0:13413ea9a877	693
ganlikun	0:13413ea9a877	694	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
ganlikun	0:13413ea9a877	695	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
ganlikun	0:13413ea9a877	696
ganlikun	0:13413ea9a877	697	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
ganlikun	0:13413ea9a877	698	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
ganlikun	0:13413ea9a877	699
ganlikun	0:13413ea9a877	700	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
ganlikun	0:13413ea9a877	701	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
ganlikun	0:13413ea9a877	702
ganlikun	0:13413ea9a877	703	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
ganlikun	0:13413ea9a877	704	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
ganlikun	0:13413ea9a877	705
ganlikun	0:13413ea9a877	706	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
ganlikun	0:13413ea9a877	707	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
ganlikun	0:13413ea9a877	708
ganlikun	0:13413ea9a877	709	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
ganlikun	0:13413ea9a877	710	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
ganlikun	0:13413ea9a877	711
ganlikun	0:13413ea9a877	712	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
ganlikun	0:13413ea9a877	713	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
ganlikun	0:13413ea9a877	714	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
ganlikun	0:13413ea9a877	715
ganlikun	0:13413ea9a877	716	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
ganlikun	0:13413ea9a877	717	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
ganlikun	0:13413ea9a877	718
ganlikun	0:13413ea9a877	719	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
ganlikun	0:13413ea9a877	720	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
ganlikun	0:13413ea9a877	721
ganlikun	0:13413ea9a877	722	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
ganlikun	0:13413ea9a877	723	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
ganlikun	0:13413ea9a877	724
ganlikun	0:13413ea9a877	725	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
ganlikun	0:13413ea9a877	726	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
ganlikun	0:13413ea9a877	727
ganlikun	0:13413ea9a877	728	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
ganlikun	0:13413ea9a877	729	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
ganlikun	0:13413ea9a877	730
ganlikun	0:13413ea9a877	731	/* SCB Hard Fault Status Register Definitions */
ganlikun	0:13413ea9a877	732	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
ganlikun	0:13413ea9a877	733	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
ganlikun	0:13413ea9a877	734
ganlikun	0:13413ea9a877	735	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
ganlikun	0:13413ea9a877	736	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
ganlikun	0:13413ea9a877	737
ganlikun	0:13413ea9a877	738	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
ganlikun	0:13413ea9a877	739	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
ganlikun	0:13413ea9a877	740
ganlikun	0:13413ea9a877	741	/* SCB Debug Fault Status Register Definitions */
ganlikun	0:13413ea9a877	742	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
ganlikun	0:13413ea9a877	743	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
ganlikun	0:13413ea9a877	744
ganlikun	0:13413ea9a877	745	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
ganlikun	0:13413ea9a877	746	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
ganlikun	0:13413ea9a877	747
ganlikun	0:13413ea9a877	748	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
ganlikun	0:13413ea9a877	749	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
ganlikun	0:13413ea9a877	750
ganlikun	0:13413ea9a877	751	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
ganlikun	0:13413ea9a877	752	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
ganlikun	0:13413ea9a877	753
ganlikun	0:13413ea9a877	754	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
ganlikun	0:13413ea9a877	755	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
ganlikun	0:13413ea9a877	756
ganlikun	0:13413ea9a877	757	/* SCB Cache Level ID Register Definitions */
ganlikun	0:13413ea9a877	758	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
ganlikun	0:13413ea9a877	759	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
ganlikun	0:13413ea9a877	760
ganlikun	0:13413ea9a877	761	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
ganlikun	0:13413ea9a877	762	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
ganlikun	0:13413ea9a877	763
ganlikun	0:13413ea9a877	764	/* SCB Cache Type Register Definitions */
ganlikun	0:13413ea9a877	765	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
ganlikun	0:13413ea9a877	766	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
ganlikun	0:13413ea9a877	767
ganlikun	0:13413ea9a877	768	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
ganlikun	0:13413ea9a877	769	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
ganlikun	0:13413ea9a877	770
ganlikun	0:13413ea9a877	771	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
ganlikun	0:13413ea9a877	772	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
ganlikun	0:13413ea9a877	773
ganlikun	0:13413ea9a877	774	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
ganlikun	0:13413ea9a877	775	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
ganlikun	0:13413ea9a877	776
ganlikun	0:13413ea9a877	777	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
ganlikun	0:13413ea9a877	778	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
ganlikun	0:13413ea9a877	779
ganlikun	0:13413ea9a877	780	/* SCB Cache Size ID Register Definitions */
ganlikun	0:13413ea9a877	781	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
ganlikun	0:13413ea9a877	782	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
ganlikun	0:13413ea9a877	783
ganlikun	0:13413ea9a877	784	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
ganlikun	0:13413ea9a877	785	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
ganlikun	0:13413ea9a877	786
ganlikun	0:13413ea9a877	787	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
ganlikun	0:13413ea9a877	788	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
ganlikun	0:13413ea9a877	789
ganlikun	0:13413ea9a877	790	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
ganlikun	0:13413ea9a877	791	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
ganlikun	0:13413ea9a877	792
ganlikun	0:13413ea9a877	793	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
ganlikun	0:13413ea9a877	794	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
ganlikun	0:13413ea9a877	795
ganlikun	0:13413ea9a877	796	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
ganlikun	0:13413ea9a877	797	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
ganlikun	0:13413ea9a877	798
ganlikun	0:13413ea9a877	799	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
ganlikun	0:13413ea9a877	800	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
ganlikun	0:13413ea9a877	801
ganlikun	0:13413ea9a877	802	/* SCB Cache Size Selection Register Definitions */
ganlikun	0:13413ea9a877	803	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
ganlikun	0:13413ea9a877	804	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
ganlikun	0:13413ea9a877	805
ganlikun	0:13413ea9a877	806	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
ganlikun	0:13413ea9a877	807	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
ganlikun	0:13413ea9a877	808
ganlikun	0:13413ea9a877	809	/* SCB Software Triggered Interrupt Register Definitions */
ganlikun	0:13413ea9a877	810	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
ganlikun	0:13413ea9a877	811	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
ganlikun	0:13413ea9a877	812
ganlikun	0:13413ea9a877	813	/* SCB D-Cache Invalidate by Set-way Register Definitions */
ganlikun	0:13413ea9a877	814	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
ganlikun	0:13413ea9a877	815	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
ganlikun	0:13413ea9a877	816
ganlikun	0:13413ea9a877	817	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
ganlikun	0:13413ea9a877	818	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
ganlikun	0:13413ea9a877	819
ganlikun	0:13413ea9a877	820	/* SCB D-Cache Clean by Set-way Register Definitions */
ganlikun	0:13413ea9a877	821	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
ganlikun	0:13413ea9a877	822	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
ganlikun	0:13413ea9a877	823
ganlikun	0:13413ea9a877	824	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
ganlikun	0:13413ea9a877	825	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
ganlikun	0:13413ea9a877	826
ganlikun	0:13413ea9a877	827	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
ganlikun	0:13413ea9a877	828	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
ganlikun	0:13413ea9a877	829	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
ganlikun	0:13413ea9a877	830
ganlikun	0:13413ea9a877	831	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
ganlikun	0:13413ea9a877	832	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
ganlikun	0:13413ea9a877	833
ganlikun	0:13413ea9a877	834	/* Instruction Tightly-Coupled Memory Control Register Definitions */
ganlikun	0:13413ea9a877	835	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
ganlikun	0:13413ea9a877	836	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
ganlikun	0:13413ea9a877	837
ganlikun	0:13413ea9a877	838	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
ganlikun	0:13413ea9a877	839	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
ganlikun	0:13413ea9a877	840
ganlikun	0:13413ea9a877	841	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
ganlikun	0:13413ea9a877	842	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
ganlikun	0:13413ea9a877	843
ganlikun	0:13413ea9a877	844	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
ganlikun	0:13413ea9a877	845	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
ganlikun	0:13413ea9a877	846
ganlikun	0:13413ea9a877	847	/* Data Tightly-Coupled Memory Control Register Definitions */
ganlikun	0:13413ea9a877	848	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
ganlikun	0:13413ea9a877	849	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
ganlikun	0:13413ea9a877	850
ganlikun	0:13413ea9a877	851	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
ganlikun	0:13413ea9a877	852	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
ganlikun	0:13413ea9a877	853
ganlikun	0:13413ea9a877	854	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
ganlikun	0:13413ea9a877	855	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
ganlikun	0:13413ea9a877	856
ganlikun	0:13413ea9a877	857	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
ganlikun	0:13413ea9a877	858	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
ganlikun	0:13413ea9a877	859
ganlikun	0:13413ea9a877	860	/* AHBP Control Register Definitions */
ganlikun	0:13413ea9a877	861	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
ganlikun	0:13413ea9a877	862	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
ganlikun	0:13413ea9a877	863
ganlikun	0:13413ea9a877	864	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
ganlikun	0:13413ea9a877	865	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
ganlikun	0:13413ea9a877	866
ganlikun	0:13413ea9a877	867	/* L1 Cache Control Register Definitions */
ganlikun	0:13413ea9a877	868	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
ganlikun	0:13413ea9a877	869	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
ganlikun	0:13413ea9a877	870
ganlikun	0:13413ea9a877	871	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
ganlikun	0:13413ea9a877	872	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
ganlikun	0:13413ea9a877	873
ganlikun	0:13413ea9a877	874	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
ganlikun	0:13413ea9a877	875	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
ganlikun	0:13413ea9a877	876
ganlikun	0:13413ea9a877	877	/* AHBS Control Register Definitions */
ganlikun	0:13413ea9a877	878	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
ganlikun	0:13413ea9a877	879	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
ganlikun	0:13413ea9a877	880
ganlikun	0:13413ea9a877	881	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
ganlikun	0:13413ea9a877	882	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
ganlikun	0:13413ea9a877	883
ganlikun	0:13413ea9a877	884	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
ganlikun	0:13413ea9a877	885	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
ganlikun	0:13413ea9a877	886
ganlikun	0:13413ea9a877	887	/* Auxiliary Bus Fault Status Register Definitions */
ganlikun	0:13413ea9a877	888	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
ganlikun	0:13413ea9a877	889	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
ganlikun	0:13413ea9a877	890
ganlikun	0:13413ea9a877	891	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
ganlikun	0:13413ea9a877	892	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
ganlikun	0:13413ea9a877	893
ganlikun	0:13413ea9a877	894	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
ganlikun	0:13413ea9a877	895	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
ganlikun	0:13413ea9a877	896
ganlikun	0:13413ea9a877	897	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
ganlikun	0:13413ea9a877	898	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
ganlikun	0:13413ea9a877	899
ganlikun	0:13413ea9a877	900	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
ganlikun	0:13413ea9a877	901	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
ganlikun	0:13413ea9a877	902
ganlikun	0:13413ea9a877	903	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
ganlikun	0:13413ea9a877	904	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
ganlikun	0:13413ea9a877	905
ganlikun	0:13413ea9a877	906	/@} end of group CMSIS_SCB /
ganlikun	0:13413ea9a877	907
ganlikun	0:13413ea9a877	908
ganlikun	0:13413ea9a877	909	/**
ganlikun	0:13413ea9a877	910	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	911	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
ganlikun	0:13413ea9a877	912	\brief Type definitions for the System Control and ID Register not in the SCB
ganlikun	0:13413ea9a877	913	@{
ganlikun	0:13413ea9a877	914	*/
ganlikun	0:13413ea9a877	915
ganlikun	0:13413ea9a877	916	/**
ganlikun	0:13413ea9a877	917	\brief Structure type to access the System Control and ID Register not in the SCB.
ganlikun	0:13413ea9a877	918	*/
ganlikun	0:13413ea9a877	919	typedef struct
ganlikun	0:13413ea9a877	920	{
ganlikun	0:13413ea9a877	921	uint32_t RESERVED0[1U];
ganlikun	0:13413ea9a877	922	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
ganlikun	0:13413ea9a877	923	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
ganlikun	0:13413ea9a877	924	} SCnSCB_Type;
ganlikun	0:13413ea9a877	925
ganlikun	0:13413ea9a877	926	/* Interrupt Controller Type Register Definitions */
ganlikun	0:13413ea9a877	927	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
ganlikun	0:13413ea9a877	928	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
ganlikun	0:13413ea9a877	929
ganlikun	0:13413ea9a877	930	/* Auxiliary Control Register Definitions */
ganlikun	0:13413ea9a877	931	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
ganlikun	0:13413ea9a877	932	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
ganlikun	0:13413ea9a877	933
ganlikun	0:13413ea9a877	934	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
ganlikun	0:13413ea9a877	935	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
ganlikun	0:13413ea9a877	936
ganlikun	0:13413ea9a877	937	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
ganlikun	0:13413ea9a877	938	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
ganlikun	0:13413ea9a877	939
ganlikun	0:13413ea9a877	940	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
ganlikun	0:13413ea9a877	941	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
ganlikun	0:13413ea9a877	942
ganlikun	0:13413ea9a877	943	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
ganlikun	0:13413ea9a877	944	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
ganlikun	0:13413ea9a877	945
ganlikun	0:13413ea9a877	946	/@} end of group CMSIS_SCnotSCB /
ganlikun	0:13413ea9a877	947
ganlikun	0:13413ea9a877	948
ganlikun	0:13413ea9a877	949	/**
ganlikun	0:13413ea9a877	950	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	951	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
ganlikun	0:13413ea9a877	952	\brief Type definitions for the System Timer Registers.
ganlikun	0:13413ea9a877	953	@{
ganlikun	0:13413ea9a877	954	*/
ganlikun	0:13413ea9a877	955
ganlikun	0:13413ea9a877	956	/**
ganlikun	0:13413ea9a877	957	\brief Structure type to access the System Timer (SysTick).
ganlikun	0:13413ea9a877	958	*/
ganlikun	0:13413ea9a877	959	typedef struct
ganlikun	0:13413ea9a877	960	{
ganlikun	0:13413ea9a877	961	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
ganlikun	0:13413ea9a877	962	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
ganlikun	0:13413ea9a877	963	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
ganlikun	0:13413ea9a877	964	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
ganlikun	0:13413ea9a877	965	} SysTick_Type;
ganlikun	0:13413ea9a877	966
ganlikun	0:13413ea9a877	967	/* SysTick Control / Status Register Definitions */
ganlikun	0:13413ea9a877	968	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
ganlikun	0:13413ea9a877	969	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
ganlikun	0:13413ea9a877	970
ganlikun	0:13413ea9a877	971	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
ganlikun	0:13413ea9a877	972	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
ganlikun	0:13413ea9a877	973
ganlikun	0:13413ea9a877	974	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
ganlikun	0:13413ea9a877	975	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
ganlikun	0:13413ea9a877	976
ganlikun	0:13413ea9a877	977	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
ganlikun	0:13413ea9a877	978	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
ganlikun	0:13413ea9a877	979
ganlikun	0:13413ea9a877	980	/* SysTick Reload Register Definitions */
ganlikun	0:13413ea9a877	981	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
ganlikun	0:13413ea9a877	982	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
ganlikun	0:13413ea9a877	983
ganlikun	0:13413ea9a877	984	/* SysTick Current Register Definitions */
ganlikun	0:13413ea9a877	985	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
ganlikun	0:13413ea9a877	986	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
ganlikun	0:13413ea9a877	987
ganlikun	0:13413ea9a877	988	/* SysTick Calibration Register Definitions */
ganlikun	0:13413ea9a877	989	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
ganlikun	0:13413ea9a877	990	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
ganlikun	0:13413ea9a877	991
ganlikun	0:13413ea9a877	992	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
ganlikun	0:13413ea9a877	993	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
ganlikun	0:13413ea9a877	994
ganlikun	0:13413ea9a877	995	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
ganlikun	0:13413ea9a877	996	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
ganlikun	0:13413ea9a877	997
ganlikun	0:13413ea9a877	998	/@} end of group CMSIS_SysTick /
ganlikun	0:13413ea9a877	999
ganlikun	0:13413ea9a877	1000
ganlikun	0:13413ea9a877	1001	/**
ganlikun	0:13413ea9a877	1002	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1003	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
ganlikun	0:13413ea9a877	1004	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
ganlikun	0:13413ea9a877	1005	@{
ganlikun	0:13413ea9a877	1006	*/
ganlikun	0:13413ea9a877	1007
ganlikun	0:13413ea9a877	1008	/**
ganlikun	0:13413ea9a877	1009	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
ganlikun	0:13413ea9a877	1010	*/
ganlikun	0:13413ea9a877	1011	typedef struct
ganlikun	0:13413ea9a877	1012	{
ganlikun	0:13413ea9a877	1013	__OM union
ganlikun	0:13413ea9a877	1014	{
ganlikun	0:13413ea9a877	1015	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
ganlikun	0:13413ea9a877	1016	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
ganlikun	0:13413ea9a877	1017	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
ganlikun	0:13413ea9a877	1018	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
ganlikun	0:13413ea9a877	1019	uint32_t RESERVED0[864U];
ganlikun	0:13413ea9a877	1020	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
ganlikun	0:13413ea9a877	1021	uint32_t RESERVED1[15U];
ganlikun	0:13413ea9a877	1022	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
ganlikun	0:13413ea9a877	1023	uint32_t RESERVED2[15U];
ganlikun	0:13413ea9a877	1024	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
ganlikun	0:13413ea9a877	1025	uint32_t RESERVED3[29U];
ganlikun	0:13413ea9a877	1026	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
ganlikun	0:13413ea9a877	1027	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
ganlikun	0:13413ea9a877	1028	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
ganlikun	0:13413ea9a877	1029	uint32_t RESERVED4[43U];
ganlikun	0:13413ea9a877	1030	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
ganlikun	0:13413ea9a877	1031	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
ganlikun	0:13413ea9a877	1032	uint32_t RESERVED5[6U];
ganlikun	0:13413ea9a877	1033	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
ganlikun	0:13413ea9a877	1034	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
ganlikun	0:13413ea9a877	1035	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
ganlikun	0:13413ea9a877	1036	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
ganlikun	0:13413ea9a877	1037	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
ganlikun	0:13413ea9a877	1038	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
ganlikun	0:13413ea9a877	1039	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
ganlikun	0:13413ea9a877	1040	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
ganlikun	0:13413ea9a877	1041	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
ganlikun	0:13413ea9a877	1042	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
ganlikun	0:13413ea9a877	1043	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
ganlikun	0:13413ea9a877	1044	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
ganlikun	0:13413ea9a877	1045	} ITM_Type;
ganlikun	0:13413ea9a877	1046
ganlikun	0:13413ea9a877	1047	/* ITM Trace Privilege Register Definitions */
ganlikun	0:13413ea9a877	1048	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
ganlikun	0:13413ea9a877	1049	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
ganlikun	0:13413ea9a877	1050
ganlikun	0:13413ea9a877	1051	/* ITM Trace Control Register Definitions */
ganlikun	0:13413ea9a877	1052	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
ganlikun	0:13413ea9a877	1053	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
ganlikun	0:13413ea9a877	1054
ganlikun	0:13413ea9a877	1055	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
ganlikun	0:13413ea9a877	1056	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
ganlikun	0:13413ea9a877	1057
ganlikun	0:13413ea9a877	1058	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
ganlikun	0:13413ea9a877	1059	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
ganlikun	0:13413ea9a877	1060
ganlikun	0:13413ea9a877	1061	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
ganlikun	0:13413ea9a877	1062	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
ganlikun	0:13413ea9a877	1063
ganlikun	0:13413ea9a877	1064	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
ganlikun	0:13413ea9a877	1065	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
ganlikun	0:13413ea9a877	1066
ganlikun	0:13413ea9a877	1067	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
ganlikun	0:13413ea9a877	1068	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
ganlikun	0:13413ea9a877	1069
ganlikun	0:13413ea9a877	1070	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
ganlikun	0:13413ea9a877	1071	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
ganlikun	0:13413ea9a877	1072
ganlikun	0:13413ea9a877	1073	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
ganlikun	0:13413ea9a877	1074	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
ganlikun	0:13413ea9a877	1075
ganlikun	0:13413ea9a877	1076	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
ganlikun	0:13413ea9a877	1077	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
ganlikun	0:13413ea9a877	1078
ganlikun	0:13413ea9a877	1079	/* ITM Integration Write Register Definitions */
ganlikun	0:13413ea9a877	1080	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
ganlikun	0:13413ea9a877	1081	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
ganlikun	0:13413ea9a877	1082
ganlikun	0:13413ea9a877	1083	/* ITM Integration Read Register Definitions */
ganlikun	0:13413ea9a877	1084	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
ganlikun	0:13413ea9a877	1085	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
ganlikun	0:13413ea9a877	1086
ganlikun	0:13413ea9a877	1087	/* ITM Integration Mode Control Register Definitions */
ganlikun	0:13413ea9a877	1088	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
ganlikun	0:13413ea9a877	1089	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
ganlikun	0:13413ea9a877	1090
ganlikun	0:13413ea9a877	1091	/* ITM Lock Status Register Definitions */
ganlikun	0:13413ea9a877	1092	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
ganlikun	0:13413ea9a877	1093	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
ganlikun	0:13413ea9a877	1094
ganlikun	0:13413ea9a877	1095	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
ganlikun	0:13413ea9a877	1096	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
ganlikun	0:13413ea9a877	1097
ganlikun	0:13413ea9a877	1098	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
ganlikun	0:13413ea9a877	1099	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
ganlikun	0:13413ea9a877	1100
ganlikun	0:13413ea9a877	1101	/@}/ /* end of group CMSIS_ITM */
ganlikun	0:13413ea9a877	1102
ganlikun	0:13413ea9a877	1103
ganlikun	0:13413ea9a877	1104	/**
ganlikun	0:13413ea9a877	1105	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1106	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
ganlikun	0:13413ea9a877	1107	\brief Type definitions for the Data Watchpoint and Trace (DWT)
ganlikun	0:13413ea9a877	1108	@{
ganlikun	0:13413ea9a877	1109	*/
ganlikun	0:13413ea9a877	1110
ganlikun	0:13413ea9a877	1111	/**
ganlikun	0:13413ea9a877	1112	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
ganlikun	0:13413ea9a877	1113	*/
ganlikun	0:13413ea9a877	1114	typedef struct
ganlikun	0:13413ea9a877	1115	{
ganlikun	0:13413ea9a877	1116	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
ganlikun	0:13413ea9a877	1117	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
ganlikun	0:13413ea9a877	1118	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
ganlikun	0:13413ea9a877	1119	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
ganlikun	0:13413ea9a877	1120	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
ganlikun	0:13413ea9a877	1121	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
ganlikun	0:13413ea9a877	1122	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
ganlikun	0:13413ea9a877	1123	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
ganlikun	0:13413ea9a877	1124	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
ganlikun	0:13413ea9a877	1125	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
ganlikun	0:13413ea9a877	1126	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
ganlikun	0:13413ea9a877	1127	uint32_t RESERVED0[1U];
ganlikun	0:13413ea9a877	1128	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
ganlikun	0:13413ea9a877	1129	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
ganlikun	0:13413ea9a877	1130	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
ganlikun	0:13413ea9a877	1131	uint32_t RESERVED1[1U];
ganlikun	0:13413ea9a877	1132	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
ganlikun	0:13413ea9a877	1133	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
ganlikun	0:13413ea9a877	1134	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
ganlikun	0:13413ea9a877	1135	uint32_t RESERVED2[1U];
ganlikun	0:13413ea9a877	1136	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
ganlikun	0:13413ea9a877	1137	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
ganlikun	0:13413ea9a877	1138	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
ganlikun	0:13413ea9a877	1139	uint32_t RESERVED3[981U];
ganlikun	0:13413ea9a877	1140	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
ganlikun	0:13413ea9a877	1141	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
ganlikun	0:13413ea9a877	1142	} DWT_Type;
ganlikun	0:13413ea9a877	1143
ganlikun	0:13413ea9a877	1144	/* DWT Control Register Definitions */
ganlikun	0:13413ea9a877	1145	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
ganlikun	0:13413ea9a877	1146	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
ganlikun	0:13413ea9a877	1147
ganlikun	0:13413ea9a877	1148	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
ganlikun	0:13413ea9a877	1149	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
ganlikun	0:13413ea9a877	1150
ganlikun	0:13413ea9a877	1151	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
ganlikun	0:13413ea9a877	1152	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
ganlikun	0:13413ea9a877	1153
ganlikun	0:13413ea9a877	1154	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
ganlikun	0:13413ea9a877	1155	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
ganlikun	0:13413ea9a877	1156
ganlikun	0:13413ea9a877	1157	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
ganlikun	0:13413ea9a877	1158	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
ganlikun	0:13413ea9a877	1159
ganlikun	0:13413ea9a877	1160	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
ganlikun	0:13413ea9a877	1161	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
ganlikun	0:13413ea9a877	1162
ganlikun	0:13413ea9a877	1163	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
ganlikun	0:13413ea9a877	1164	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
ganlikun	0:13413ea9a877	1165
ganlikun	0:13413ea9a877	1166	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
ganlikun	0:13413ea9a877	1167	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
ganlikun	0:13413ea9a877	1168
ganlikun	0:13413ea9a877	1169	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
ganlikun	0:13413ea9a877	1170	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
ganlikun	0:13413ea9a877	1171
ganlikun	0:13413ea9a877	1172	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
ganlikun	0:13413ea9a877	1173	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
ganlikun	0:13413ea9a877	1174
ganlikun	0:13413ea9a877	1175	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
ganlikun	0:13413ea9a877	1176	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
ganlikun	0:13413ea9a877	1177
ganlikun	0:13413ea9a877	1178	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
ganlikun	0:13413ea9a877	1179	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
ganlikun	0:13413ea9a877	1180
ganlikun	0:13413ea9a877	1181	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
ganlikun	0:13413ea9a877	1182	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
ganlikun	0:13413ea9a877	1183
ganlikun	0:13413ea9a877	1184	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
ganlikun	0:13413ea9a877	1185	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
ganlikun	0:13413ea9a877	1186
ganlikun	0:13413ea9a877	1187	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
ganlikun	0:13413ea9a877	1188	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
ganlikun	0:13413ea9a877	1189
ganlikun	0:13413ea9a877	1190	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
ganlikun	0:13413ea9a877	1191	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
ganlikun	0:13413ea9a877	1192
ganlikun	0:13413ea9a877	1193	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
ganlikun	0:13413ea9a877	1194	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
ganlikun	0:13413ea9a877	1195
ganlikun	0:13413ea9a877	1196	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
ganlikun	0:13413ea9a877	1197	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
ganlikun	0:13413ea9a877	1198
ganlikun	0:13413ea9a877	1199	/* DWT CPI Count Register Definitions */
ganlikun	0:13413ea9a877	1200	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
ganlikun	0:13413ea9a877	1201	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
ganlikun	0:13413ea9a877	1202
ganlikun	0:13413ea9a877	1203	/* DWT Exception Overhead Count Register Definitions */
ganlikun	0:13413ea9a877	1204	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
ganlikun	0:13413ea9a877	1205	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
ganlikun	0:13413ea9a877	1206
ganlikun	0:13413ea9a877	1207	/* DWT Sleep Count Register Definitions */
ganlikun	0:13413ea9a877	1208	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
ganlikun	0:13413ea9a877	1209	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
ganlikun	0:13413ea9a877	1210
ganlikun	0:13413ea9a877	1211	/* DWT LSU Count Register Definitions */
ganlikun	0:13413ea9a877	1212	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
ganlikun	0:13413ea9a877	1213	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
ganlikun	0:13413ea9a877	1214
ganlikun	0:13413ea9a877	1215	/* DWT Folded-instruction Count Register Definitions */
ganlikun	0:13413ea9a877	1216	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
ganlikun	0:13413ea9a877	1217	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
ganlikun	0:13413ea9a877	1218
ganlikun	0:13413ea9a877	1219	/* DWT Comparator Mask Register Definitions */
ganlikun	0:13413ea9a877	1220	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
ganlikun	0:13413ea9a877	1221	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
ganlikun	0:13413ea9a877	1222
ganlikun	0:13413ea9a877	1223	/* DWT Comparator Function Register Definitions */
ganlikun	0:13413ea9a877	1224	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
ganlikun	0:13413ea9a877	1225	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
ganlikun	0:13413ea9a877	1226
ganlikun	0:13413ea9a877	1227	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
ganlikun	0:13413ea9a877	1228	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
ganlikun	0:13413ea9a877	1229
ganlikun	0:13413ea9a877	1230	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
ganlikun	0:13413ea9a877	1231	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
ganlikun	0:13413ea9a877	1232
ganlikun	0:13413ea9a877	1233	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
ganlikun	0:13413ea9a877	1234	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
ganlikun	0:13413ea9a877	1235
ganlikun	0:13413ea9a877	1236	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
ganlikun	0:13413ea9a877	1237	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
ganlikun	0:13413ea9a877	1238
ganlikun	0:13413ea9a877	1239	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
ganlikun	0:13413ea9a877	1240	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
ganlikun	0:13413ea9a877	1241
ganlikun	0:13413ea9a877	1242	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
ganlikun	0:13413ea9a877	1243	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
ganlikun	0:13413ea9a877	1244
ganlikun	0:13413ea9a877	1245	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
ganlikun	0:13413ea9a877	1246	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
ganlikun	0:13413ea9a877	1247
ganlikun	0:13413ea9a877	1248	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
ganlikun	0:13413ea9a877	1249	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
ganlikun	0:13413ea9a877	1250
ganlikun	0:13413ea9a877	1251	/@}/ /* end of group CMSIS_DWT */
ganlikun	0:13413ea9a877	1252
ganlikun	0:13413ea9a877	1253
ganlikun	0:13413ea9a877	1254	/**
ganlikun	0:13413ea9a877	1255	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1256	\defgroup CMSIS_TPI Trace Port Interface (TPI)
ganlikun	0:13413ea9a877	1257	\brief Type definitions for the Trace Port Interface (TPI)
ganlikun	0:13413ea9a877	1258	@{
ganlikun	0:13413ea9a877	1259	*/
ganlikun	0:13413ea9a877	1260
ganlikun	0:13413ea9a877	1261	/**
ganlikun	0:13413ea9a877	1262	\brief Structure type to access the Trace Port Interface Register (TPI).
ganlikun	0:13413ea9a877	1263	*/
ganlikun	0:13413ea9a877	1264	typedef struct
ganlikun	0:13413ea9a877	1265	{
ganlikun	0:13413ea9a877	1266	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
ganlikun	0:13413ea9a877	1267	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
ganlikun	0:13413ea9a877	1268	uint32_t RESERVED0[2U];
ganlikun	0:13413ea9a877	1269	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
ganlikun	0:13413ea9a877	1270	uint32_t RESERVED1[55U];
ganlikun	0:13413ea9a877	1271	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
ganlikun	0:13413ea9a877	1272	uint32_t RESERVED2[131U];
ganlikun	0:13413ea9a877	1273	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
ganlikun	0:13413ea9a877	1274	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
ganlikun	0:13413ea9a877	1275	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
ganlikun	0:13413ea9a877	1276	uint32_t RESERVED3[759U];
ganlikun	0:13413ea9a877	1277	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
ganlikun	0:13413ea9a877	1278	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
ganlikun	0:13413ea9a877	1279	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
ganlikun	0:13413ea9a877	1280	uint32_t RESERVED4[1U];
ganlikun	0:13413ea9a877	1281	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
ganlikun	0:13413ea9a877	1282	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
ganlikun	0:13413ea9a877	1283	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
ganlikun	0:13413ea9a877	1284	uint32_t RESERVED5[39U];
ganlikun	0:13413ea9a877	1285	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
ganlikun	0:13413ea9a877	1286	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
ganlikun	0:13413ea9a877	1287	uint32_t RESERVED7[8U];
ganlikun	0:13413ea9a877	1288	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
ganlikun	0:13413ea9a877	1289	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
ganlikun	0:13413ea9a877	1290	} TPI_Type;
ganlikun	0:13413ea9a877	1291
ganlikun	0:13413ea9a877	1292	/* TPI Asynchronous Clock Prescaler Register Definitions */
ganlikun	0:13413ea9a877	1293	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
ganlikun	0:13413ea9a877	1294	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
ganlikun	0:13413ea9a877	1295
ganlikun	0:13413ea9a877	1296	/* TPI Selected Pin Protocol Register Definitions */
ganlikun	0:13413ea9a877	1297	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
ganlikun	0:13413ea9a877	1298	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
ganlikun	0:13413ea9a877	1299
ganlikun	0:13413ea9a877	1300	/* TPI Formatter and Flush Status Register Definitions */
ganlikun	0:13413ea9a877	1301	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
ganlikun	0:13413ea9a877	1302	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
ganlikun	0:13413ea9a877	1303
ganlikun	0:13413ea9a877	1304	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
ganlikun	0:13413ea9a877	1305	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
ganlikun	0:13413ea9a877	1306
ganlikun	0:13413ea9a877	1307	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
ganlikun	0:13413ea9a877	1308	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
ganlikun	0:13413ea9a877	1309
ganlikun	0:13413ea9a877	1310	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
ganlikun	0:13413ea9a877	1311	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
ganlikun	0:13413ea9a877	1312
ganlikun	0:13413ea9a877	1313	/* TPI Formatter and Flush Control Register Definitions */
ganlikun	0:13413ea9a877	1314	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
ganlikun	0:13413ea9a877	1315	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
ganlikun	0:13413ea9a877	1316
ganlikun	0:13413ea9a877	1317	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
ganlikun	0:13413ea9a877	1318	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
ganlikun	0:13413ea9a877	1319
ganlikun	0:13413ea9a877	1320	/* TPI TRIGGER Register Definitions */
ganlikun	0:13413ea9a877	1321	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
ganlikun	0:13413ea9a877	1322	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
ganlikun	0:13413ea9a877	1323
ganlikun	0:13413ea9a877	1324	/* TPI Integration ETM Data Register Definitions (FIFO0) */
ganlikun	0:13413ea9a877	1325	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
ganlikun	0:13413ea9a877	1326	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
ganlikun	0:13413ea9a877	1327
ganlikun	0:13413ea9a877	1328	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
ganlikun	0:13413ea9a877	1329	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
ganlikun	0:13413ea9a877	1330
ganlikun	0:13413ea9a877	1331	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
ganlikun	0:13413ea9a877	1332	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
ganlikun	0:13413ea9a877	1333
ganlikun	0:13413ea9a877	1334	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
ganlikun	0:13413ea9a877	1335	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
ganlikun	0:13413ea9a877	1336
ganlikun	0:13413ea9a877	1337	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
ganlikun	0:13413ea9a877	1338	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
ganlikun	0:13413ea9a877	1339
ganlikun	0:13413ea9a877	1340	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
ganlikun	0:13413ea9a877	1341	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
ganlikun	0:13413ea9a877	1342
ganlikun	0:13413ea9a877	1343	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
ganlikun	0:13413ea9a877	1344	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
ganlikun	0:13413ea9a877	1345
ganlikun	0:13413ea9a877	1346	/* TPI ITATBCTR2 Register Definitions */
ganlikun	0:13413ea9a877	1347	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
ganlikun	0:13413ea9a877	1348	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
ganlikun	0:13413ea9a877	1349
ganlikun	0:13413ea9a877	1350	/* TPI Integration ITM Data Register Definitions (FIFO1) */
ganlikun	0:13413ea9a877	1351	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
ganlikun	0:13413ea9a877	1352	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
ganlikun	0:13413ea9a877	1353
ganlikun	0:13413ea9a877	1354	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
ganlikun	0:13413ea9a877	1355	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
ganlikun	0:13413ea9a877	1356
ganlikun	0:13413ea9a877	1357	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
ganlikun	0:13413ea9a877	1358	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
ganlikun	0:13413ea9a877	1359
ganlikun	0:13413ea9a877	1360	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
ganlikun	0:13413ea9a877	1361	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
ganlikun	0:13413ea9a877	1362
ganlikun	0:13413ea9a877	1363	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
ganlikun	0:13413ea9a877	1364	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
ganlikun	0:13413ea9a877	1365
ganlikun	0:13413ea9a877	1366	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
ganlikun	0:13413ea9a877	1367	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
ganlikun	0:13413ea9a877	1368
ganlikun	0:13413ea9a877	1369	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
ganlikun	0:13413ea9a877	1370	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
ganlikun	0:13413ea9a877	1371
ganlikun	0:13413ea9a877	1372	/* TPI ITATBCTR0 Register Definitions */
ganlikun	0:13413ea9a877	1373	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
ganlikun	0:13413ea9a877	1374	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
ganlikun	0:13413ea9a877	1375
ganlikun	0:13413ea9a877	1376	/* TPI Integration Mode Control Register Definitions */
ganlikun	0:13413ea9a877	1377	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
ganlikun	0:13413ea9a877	1378	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
ganlikun	0:13413ea9a877	1379
ganlikun	0:13413ea9a877	1380	/* TPI DEVID Register Definitions */
ganlikun	0:13413ea9a877	1381	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
ganlikun	0:13413ea9a877	1382	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
ganlikun	0:13413ea9a877	1383
ganlikun	0:13413ea9a877	1384	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
ganlikun	0:13413ea9a877	1385	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
ganlikun	0:13413ea9a877	1386
ganlikun	0:13413ea9a877	1387	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
ganlikun	0:13413ea9a877	1388	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
ganlikun	0:13413ea9a877	1389
ganlikun	0:13413ea9a877	1390	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
ganlikun	0:13413ea9a877	1391	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
ganlikun	0:13413ea9a877	1392
ganlikun	0:13413ea9a877	1393	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
ganlikun	0:13413ea9a877	1394	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
ganlikun	0:13413ea9a877	1395
ganlikun	0:13413ea9a877	1396	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
ganlikun	0:13413ea9a877	1397	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
ganlikun	0:13413ea9a877	1398
ganlikun	0:13413ea9a877	1399	/* TPI DEVTYPE Register Definitions */
ganlikun	0:13413ea9a877	1400	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
ganlikun	0:13413ea9a877	1401	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
ganlikun	0:13413ea9a877	1402
ganlikun	0:13413ea9a877	1403	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
ganlikun	0:13413ea9a877	1404	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
ganlikun	0:13413ea9a877	1405
ganlikun	0:13413ea9a877	1406	/@}/ /* end of group CMSIS_TPI */
ganlikun	0:13413ea9a877	1407
ganlikun	0:13413ea9a877	1408
ganlikun	0:13413ea9a877	1409	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	1410	/**
ganlikun	0:13413ea9a877	1411	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1412	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
ganlikun	0:13413ea9a877	1413	\brief Type definitions for the Memory Protection Unit (MPU)
ganlikun	0:13413ea9a877	1414	@{
ganlikun	0:13413ea9a877	1415	*/
ganlikun	0:13413ea9a877	1416
ganlikun	0:13413ea9a877	1417	/**
ganlikun	0:13413ea9a877	1418	\brief Structure type to access the Memory Protection Unit (MPU).
ganlikun	0:13413ea9a877	1419	*/
ganlikun	0:13413ea9a877	1420	typedef struct
ganlikun	0:13413ea9a877	1421	{
ganlikun	0:13413ea9a877	1422	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
ganlikun	0:13413ea9a877	1423	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
ganlikun	0:13413ea9a877	1424	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
ganlikun	0:13413ea9a877	1425	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
ganlikun	0:13413ea9a877	1426	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
ganlikun	0:13413ea9a877	1427	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
ganlikun	0:13413ea9a877	1428	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
ganlikun	0:13413ea9a877	1429	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
ganlikun	0:13413ea9a877	1430	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
ganlikun	0:13413ea9a877	1431	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
ganlikun	0:13413ea9a877	1432	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
ganlikun	0:13413ea9a877	1433	} MPU_Type;
ganlikun	0:13413ea9a877	1434
ganlikun	0:13413ea9a877	1435	/* MPU Type Register Definitions */
ganlikun	0:13413ea9a877	1436	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
ganlikun	0:13413ea9a877	1437	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
ganlikun	0:13413ea9a877	1438
ganlikun	0:13413ea9a877	1439	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
ganlikun	0:13413ea9a877	1440	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
ganlikun	0:13413ea9a877	1441
ganlikun	0:13413ea9a877	1442	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
ganlikun	0:13413ea9a877	1443	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
ganlikun	0:13413ea9a877	1444
ganlikun	0:13413ea9a877	1445	/* MPU Control Register Definitions */
ganlikun	0:13413ea9a877	1446	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
ganlikun	0:13413ea9a877	1447	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
ganlikun	0:13413ea9a877	1448
ganlikun	0:13413ea9a877	1449	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
ganlikun	0:13413ea9a877	1450	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
ganlikun	0:13413ea9a877	1451
ganlikun	0:13413ea9a877	1452	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
ganlikun	0:13413ea9a877	1453	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
ganlikun	0:13413ea9a877	1454
ganlikun	0:13413ea9a877	1455	/* MPU Region Number Register Definitions */
ganlikun	0:13413ea9a877	1456	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
ganlikun	0:13413ea9a877	1457	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
ganlikun	0:13413ea9a877	1458
ganlikun	0:13413ea9a877	1459	/* MPU Region Base Address Register Definitions */
ganlikun	0:13413ea9a877	1460	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
ganlikun	0:13413ea9a877	1461	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
ganlikun	0:13413ea9a877	1462
ganlikun	0:13413ea9a877	1463	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
ganlikun	0:13413ea9a877	1464	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
ganlikun	0:13413ea9a877	1465
ganlikun	0:13413ea9a877	1466	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
ganlikun	0:13413ea9a877	1467	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
ganlikun	0:13413ea9a877	1468
ganlikun	0:13413ea9a877	1469	/* MPU Region Attribute and Size Register Definitions */
ganlikun	0:13413ea9a877	1470	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
ganlikun	0:13413ea9a877	1471	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
ganlikun	0:13413ea9a877	1472
ganlikun	0:13413ea9a877	1473	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
ganlikun	0:13413ea9a877	1474	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
ganlikun	0:13413ea9a877	1475
ganlikun	0:13413ea9a877	1476	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
ganlikun	0:13413ea9a877	1477	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
ganlikun	0:13413ea9a877	1478
ganlikun	0:13413ea9a877	1479	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
ganlikun	0:13413ea9a877	1480	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
ganlikun	0:13413ea9a877	1481
ganlikun	0:13413ea9a877	1482	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
ganlikun	0:13413ea9a877	1483	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
ganlikun	0:13413ea9a877	1484
ganlikun	0:13413ea9a877	1485	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
ganlikun	0:13413ea9a877	1486	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
ganlikun	0:13413ea9a877	1487
ganlikun	0:13413ea9a877	1488	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
ganlikun	0:13413ea9a877	1489	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
ganlikun	0:13413ea9a877	1490
ganlikun	0:13413ea9a877	1491	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
ganlikun	0:13413ea9a877	1492	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
ganlikun	0:13413ea9a877	1493
ganlikun	0:13413ea9a877	1494	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
ganlikun	0:13413ea9a877	1495	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
ganlikun	0:13413ea9a877	1496
ganlikun	0:13413ea9a877	1497	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
ganlikun	0:13413ea9a877	1498	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
ganlikun	0:13413ea9a877	1499
ganlikun	0:13413ea9a877	1500	/@} end of group CMSIS_MPU /
ganlikun	0:13413ea9a877	1501	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
ganlikun	0:13413ea9a877	1502
ganlikun	0:13413ea9a877	1503
ganlikun	0:13413ea9a877	1504	/**
ganlikun	0:13413ea9a877	1505	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1506	\defgroup CMSIS_FPU Floating Point Unit (FPU)
ganlikun	0:13413ea9a877	1507	\brief Type definitions for the Floating Point Unit (FPU)
ganlikun	0:13413ea9a877	1508	@{
ganlikun	0:13413ea9a877	1509	*/
ganlikun	0:13413ea9a877	1510
ganlikun	0:13413ea9a877	1511	/**
ganlikun	0:13413ea9a877	1512	\brief Structure type to access the Floating Point Unit (FPU).
ganlikun	0:13413ea9a877	1513	*/
ganlikun	0:13413ea9a877	1514	typedef struct
ganlikun	0:13413ea9a877	1515	{
ganlikun	0:13413ea9a877	1516	uint32_t RESERVED0[1U];
ganlikun	0:13413ea9a877	1517	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
ganlikun	0:13413ea9a877	1518	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
ganlikun	0:13413ea9a877	1519	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
ganlikun	0:13413ea9a877	1520	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
ganlikun	0:13413ea9a877	1521	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
ganlikun	0:13413ea9a877	1522	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
ganlikun	0:13413ea9a877	1523	} FPU_Type;
ganlikun	0:13413ea9a877	1524
ganlikun	0:13413ea9a877	1525	/* Floating-Point Context Control Register Definitions */
ganlikun	0:13413ea9a877	1526	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
ganlikun	0:13413ea9a877	1527	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
ganlikun	0:13413ea9a877	1528
ganlikun	0:13413ea9a877	1529	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
ganlikun	0:13413ea9a877	1530	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
ganlikun	0:13413ea9a877	1531
ganlikun	0:13413ea9a877	1532	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
ganlikun	0:13413ea9a877	1533	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
ganlikun	0:13413ea9a877	1534
ganlikun	0:13413ea9a877	1535	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
ganlikun	0:13413ea9a877	1536	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
ganlikun	0:13413ea9a877	1537
ganlikun	0:13413ea9a877	1538	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
ganlikun	0:13413ea9a877	1539	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
ganlikun	0:13413ea9a877	1540
ganlikun	0:13413ea9a877	1541	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
ganlikun	0:13413ea9a877	1542	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
ganlikun	0:13413ea9a877	1543
ganlikun	0:13413ea9a877	1544	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
ganlikun	0:13413ea9a877	1545	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
ganlikun	0:13413ea9a877	1546
ganlikun	0:13413ea9a877	1547	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
ganlikun	0:13413ea9a877	1548	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
ganlikun	0:13413ea9a877	1549
ganlikun	0:13413ea9a877	1550	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
ganlikun	0:13413ea9a877	1551	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
ganlikun	0:13413ea9a877	1552
ganlikun	0:13413ea9a877	1553	/* Floating-Point Context Address Register Definitions */
ganlikun	0:13413ea9a877	1554	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
ganlikun	0:13413ea9a877	1555	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
ganlikun	0:13413ea9a877	1556
ganlikun	0:13413ea9a877	1557	/* Floating-Point Default Status Control Register Definitions */
ganlikun	0:13413ea9a877	1558	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
ganlikun	0:13413ea9a877	1559	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
ganlikun	0:13413ea9a877	1560
ganlikun	0:13413ea9a877	1561	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
ganlikun	0:13413ea9a877	1562	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
ganlikun	0:13413ea9a877	1563
ganlikun	0:13413ea9a877	1564	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
ganlikun	0:13413ea9a877	1565	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
ganlikun	0:13413ea9a877	1566
ganlikun	0:13413ea9a877	1567	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
ganlikun	0:13413ea9a877	1568	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
ganlikun	0:13413ea9a877	1569
ganlikun	0:13413ea9a877	1570	/* Media and FP Feature Register 0 Definitions */
ganlikun	0:13413ea9a877	1571	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
ganlikun	0:13413ea9a877	1572	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
ganlikun	0:13413ea9a877	1573
ganlikun	0:13413ea9a877	1574	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
ganlikun	0:13413ea9a877	1575	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
ganlikun	0:13413ea9a877	1576
ganlikun	0:13413ea9a877	1577	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
ganlikun	0:13413ea9a877	1578	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
ganlikun	0:13413ea9a877	1579
ganlikun	0:13413ea9a877	1580	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
ganlikun	0:13413ea9a877	1581	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
ganlikun	0:13413ea9a877	1582
ganlikun	0:13413ea9a877	1583	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
ganlikun	0:13413ea9a877	1584	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
ganlikun	0:13413ea9a877	1585
ganlikun	0:13413ea9a877	1586	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
ganlikun	0:13413ea9a877	1587	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
ganlikun	0:13413ea9a877	1588
ganlikun	0:13413ea9a877	1589	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
ganlikun	0:13413ea9a877	1590	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
ganlikun	0:13413ea9a877	1591
ganlikun	0:13413ea9a877	1592	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
ganlikun	0:13413ea9a877	1593	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
ganlikun	0:13413ea9a877	1594
ganlikun	0:13413ea9a877	1595	/* Media and FP Feature Register 1 Definitions */
ganlikun	0:13413ea9a877	1596	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
ganlikun	0:13413ea9a877	1597	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
ganlikun	0:13413ea9a877	1598
ganlikun	0:13413ea9a877	1599	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
ganlikun	0:13413ea9a877	1600	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
ganlikun	0:13413ea9a877	1601
ganlikun	0:13413ea9a877	1602	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
ganlikun	0:13413ea9a877	1603	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
ganlikun	0:13413ea9a877	1604
ganlikun	0:13413ea9a877	1605	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
ganlikun	0:13413ea9a877	1606	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
ganlikun	0:13413ea9a877	1607
ganlikun	0:13413ea9a877	1608	/* Media and FP Feature Register 2 Definitions */
ganlikun	0:13413ea9a877	1609
ganlikun	0:13413ea9a877	1610	/@} end of group CMSIS_FPU /
ganlikun	0:13413ea9a877	1611
ganlikun	0:13413ea9a877	1612
ganlikun	0:13413ea9a877	1613	/**
ganlikun	0:13413ea9a877	1614	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1615	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
ganlikun	0:13413ea9a877	1616	\brief Type definitions for the Core Debug Registers
ganlikun	0:13413ea9a877	1617	@{
ganlikun	0:13413ea9a877	1618	*/
ganlikun	0:13413ea9a877	1619
ganlikun	0:13413ea9a877	1620	/**
ganlikun	0:13413ea9a877	1621	\brief Structure type to access the Core Debug Register (CoreDebug).
ganlikun	0:13413ea9a877	1622	*/
ganlikun	0:13413ea9a877	1623	typedef struct
ganlikun	0:13413ea9a877	1624	{
ganlikun	0:13413ea9a877	1625	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
ganlikun	0:13413ea9a877	1626	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
ganlikun	0:13413ea9a877	1627	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
ganlikun	0:13413ea9a877	1628	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
ganlikun	0:13413ea9a877	1629	} CoreDebug_Type;
ganlikun	0:13413ea9a877	1630
ganlikun	0:13413ea9a877	1631	/* Debug Halting Control and Status Register Definitions */
ganlikun	0:13413ea9a877	1632	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
ganlikun	0:13413ea9a877	1633	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
ganlikun	0:13413ea9a877	1634
ganlikun	0:13413ea9a877	1635	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
ganlikun	0:13413ea9a877	1636	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
ganlikun	0:13413ea9a877	1637
ganlikun	0:13413ea9a877	1638	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
ganlikun	0:13413ea9a877	1639	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
ganlikun	0:13413ea9a877	1640
ganlikun	0:13413ea9a877	1641	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
ganlikun	0:13413ea9a877	1642	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
ganlikun	0:13413ea9a877	1643
ganlikun	0:13413ea9a877	1644	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
ganlikun	0:13413ea9a877	1645	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
ganlikun	0:13413ea9a877	1646
ganlikun	0:13413ea9a877	1647	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
ganlikun	0:13413ea9a877	1648	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
ganlikun	0:13413ea9a877	1649
ganlikun	0:13413ea9a877	1650	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
ganlikun	0:13413ea9a877	1651	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
ganlikun	0:13413ea9a877	1652
ganlikun	0:13413ea9a877	1653	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
ganlikun	0:13413ea9a877	1654	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
ganlikun	0:13413ea9a877	1655
ganlikun	0:13413ea9a877	1656	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
ganlikun	0:13413ea9a877	1657	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
ganlikun	0:13413ea9a877	1658
ganlikun	0:13413ea9a877	1659	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
ganlikun	0:13413ea9a877	1660	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
ganlikun	0:13413ea9a877	1661
ganlikun	0:13413ea9a877	1662	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
ganlikun	0:13413ea9a877	1663	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
ganlikun	0:13413ea9a877	1664
ganlikun	0:13413ea9a877	1665	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
ganlikun	0:13413ea9a877	1666	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
ganlikun	0:13413ea9a877	1667
ganlikun	0:13413ea9a877	1668	/* Debug Core Register Selector Register Definitions */
ganlikun	0:13413ea9a877	1669	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
ganlikun	0:13413ea9a877	1670	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
ganlikun	0:13413ea9a877	1671
ganlikun	0:13413ea9a877	1672	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
ganlikun	0:13413ea9a877	1673	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
ganlikun	0:13413ea9a877	1674
ganlikun	0:13413ea9a877	1675	/* Debug Exception and Monitor Control Register Definitions */
ganlikun	0:13413ea9a877	1676	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
ganlikun	0:13413ea9a877	1677	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
ganlikun	0:13413ea9a877	1678
ganlikun	0:13413ea9a877	1679	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
ganlikun	0:13413ea9a877	1680	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
ganlikun	0:13413ea9a877	1681
ganlikun	0:13413ea9a877	1682	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
ganlikun	0:13413ea9a877	1683	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
ganlikun	0:13413ea9a877	1684
ganlikun	0:13413ea9a877	1685	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
ganlikun	0:13413ea9a877	1686	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
ganlikun	0:13413ea9a877	1687
ganlikun	0:13413ea9a877	1688	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
ganlikun	0:13413ea9a877	1689	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
ganlikun	0:13413ea9a877	1690
ganlikun	0:13413ea9a877	1691	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
ganlikun	0:13413ea9a877	1692	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
ganlikun	0:13413ea9a877	1693
ganlikun	0:13413ea9a877	1694	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
ganlikun	0:13413ea9a877	1695	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
ganlikun	0:13413ea9a877	1696
ganlikun	0:13413ea9a877	1697	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
ganlikun	0:13413ea9a877	1698	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
ganlikun	0:13413ea9a877	1699
ganlikun	0:13413ea9a877	1700	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
ganlikun	0:13413ea9a877	1701	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
ganlikun	0:13413ea9a877	1702
ganlikun	0:13413ea9a877	1703	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
ganlikun	0:13413ea9a877	1704	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
ganlikun	0:13413ea9a877	1705
ganlikun	0:13413ea9a877	1706	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
ganlikun	0:13413ea9a877	1707	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
ganlikun	0:13413ea9a877	1708
ganlikun	0:13413ea9a877	1709	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
ganlikun	0:13413ea9a877	1710	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
ganlikun	0:13413ea9a877	1711
ganlikun	0:13413ea9a877	1712	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
ganlikun	0:13413ea9a877	1713	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
ganlikun	0:13413ea9a877	1714
ganlikun	0:13413ea9a877	1715	/@} end of group CMSIS_CoreDebug /
ganlikun	0:13413ea9a877	1716
ganlikun	0:13413ea9a877	1717
ganlikun	0:13413ea9a877	1718	/**
ganlikun	0:13413ea9a877	1719	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1720	\defgroup CMSIS_core_bitfield Core register bit field macros
ganlikun	0:13413ea9a877	1721	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
ganlikun	0:13413ea9a877	1722	@{
ganlikun	0:13413ea9a877	1723	*/
ganlikun	0:13413ea9a877	1724
ganlikun	0:13413ea9a877	1725	/**
ganlikun	0:13413ea9a877	1726	\brief Mask and shift a bit field value for use in a register bit range.
ganlikun	0:13413ea9a877	1727	\param[in] field Name of the register bit field.
ganlikun	0:13413ea9a877	1728	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
ganlikun	0:13413ea9a877	1729	\return Masked and shifted value.
ganlikun	0:13413ea9a877	1730	*/
ganlikun	0:13413ea9a877	1731	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
ganlikun	0:13413ea9a877	1732
ganlikun	0:13413ea9a877	1733	/**
ganlikun	0:13413ea9a877	1734	\brief Mask and shift a register value to extract a bit filed value.
ganlikun	0:13413ea9a877	1735	\param[in] field Name of the register bit field.
ganlikun	0:13413ea9a877	1736	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
ganlikun	0:13413ea9a877	1737	\return Masked and shifted bit field value.
ganlikun	0:13413ea9a877	1738	*/
ganlikun	0:13413ea9a877	1739	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ganlikun	0:13413ea9a877	1740
ganlikun	0:13413ea9a877	1741	/@} end of group CMSIS_core_bitfield /
ganlikun	0:13413ea9a877	1742
ganlikun	0:13413ea9a877	1743
ganlikun	0:13413ea9a877	1744	/**
ganlikun	0:13413ea9a877	1745	\ingroup CMSIS_core_register
ganlikun	0:13413ea9a877	1746	\defgroup CMSIS_core_base Core Definitions
ganlikun	0:13413ea9a877	1747	\brief Definitions for base addresses, unions, and structures.
ganlikun	0:13413ea9a877	1748	@{
ganlikun	0:13413ea9a877	1749	*/
ganlikun	0:13413ea9a877	1750
ganlikun	0:13413ea9a877	1751	/* Memory mapping of Core Hardware */
ganlikun	0:13413ea9a877	1752	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
ganlikun	0:13413ea9a877	1753	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
ganlikun	0:13413ea9a877	1754	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
ganlikun	0:13413ea9a877	1755	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
ganlikun	0:13413ea9a877	1756	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
ganlikun	0:13413ea9a877	1757	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
ganlikun	0:13413ea9a877	1758	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
ganlikun	0:13413ea9a877	1759	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
ganlikun	0:13413ea9a877	1760
ganlikun	0:13413ea9a877	1761	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
ganlikun	0:13413ea9a877	1762	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
ganlikun	0:13413ea9a877	1763	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
ganlikun	0:13413ea9a877	1764	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
ganlikun	0:13413ea9a877	1765	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
ganlikun	0:13413ea9a877	1766	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
ganlikun	0:13413ea9a877	1767	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
ganlikun	0:13413ea9a877	1768	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
ganlikun	0:13413ea9a877	1769
ganlikun	0:13413ea9a877	1770	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun	0:13413ea9a877	1771	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
ganlikun	0:13413ea9a877	1772	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
ganlikun	0:13413ea9a877	1773	#endif
ganlikun	0:13413ea9a877	1774
ganlikun	0:13413ea9a877	1775	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
ganlikun	0:13413ea9a877	1776	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
ganlikun	0:13413ea9a877	1777
ganlikun	0:13413ea9a877	1778	/@} /
ganlikun	0:13413ea9a877	1779
ganlikun	0:13413ea9a877	1780
ganlikun	0:13413ea9a877	1781
ganlikun	0:13413ea9a877	1782	/*******************************************************************************
ganlikun	0:13413ea9a877	1783	* Hardware Abstraction Layer
ganlikun	0:13413ea9a877	1784	Core Function Interface contains:
ganlikun	0:13413ea9a877	1785	- Core NVIC Functions
ganlikun	0:13413ea9a877	1786	- Core SysTick Functions
ganlikun	0:13413ea9a877	1787	- Core Debug Functions
ganlikun	0:13413ea9a877	1788	- Core Register Access Functions
ganlikun	0:13413ea9a877	1789	******************************************************************************/
ganlikun	0:13413ea9a877	1790	/**
ganlikun	0:13413ea9a877	1791	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
ganlikun	0:13413ea9a877	1792	*/
ganlikun	0:13413ea9a877	1793
ganlikun	0:13413ea9a877	1794
ganlikun	0:13413ea9a877	1795
ganlikun	0:13413ea9a877	1796	/* ########################## NVIC functions #################################### */
ganlikun	0:13413ea9a877	1797	/**
ganlikun	0:13413ea9a877	1798	\ingroup CMSIS_Core_FunctionInterface
ganlikun	0:13413ea9a877	1799	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
ganlikun	0:13413ea9a877	1800	\brief Functions that manage interrupts and exceptions via the NVIC.
ganlikun	0:13413ea9a877	1801	@{
ganlikun	0:13413ea9a877	1802	*/
ganlikun	0:13413ea9a877	1803
ganlikun	0:13413ea9a877	1804	#ifdef CMSIS_NVIC_VIRTUAL
ganlikun	0:13413ea9a877	1805	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun	0:13413ea9a877	1806	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
ganlikun	0:13413ea9a877	1807	#endif
ganlikun	0:13413ea9a877	1808	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun	0:13413ea9a877	1809	#else
ganlikun	0:13413ea9a877	1810	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
ganlikun	0:13413ea9a877	1811	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
ganlikun	0:13413ea9a877	1812	#define NVIC_EnableIRQ __NVIC_EnableIRQ
ganlikun	0:13413ea9a877	1813	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
ganlikun	0:13413ea9a877	1814	#define NVIC_DisableIRQ __NVIC_DisableIRQ
ganlikun	0:13413ea9a877	1815	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
ganlikun	0:13413ea9a877	1816	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
ganlikun	0:13413ea9a877	1817	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
ganlikun	0:13413ea9a877	1818	#define NVIC_GetActive __NVIC_GetActive
ganlikun	0:13413ea9a877	1819	#define NVIC_SetPriority __NVIC_SetPriority
ganlikun	0:13413ea9a877	1820	#define NVIC_GetPriority __NVIC_GetPriority
ganlikun	0:13413ea9a877	1821	#define NVIC_SystemReset __NVIC_SystemReset
ganlikun	0:13413ea9a877	1822	#endif /* CMSIS_NVIC_VIRTUAL */
ganlikun	0:13413ea9a877	1823
ganlikun	0:13413ea9a877	1824	#ifdef CMSIS_VECTAB_VIRTUAL
ganlikun	0:13413ea9a877	1825	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun	0:13413ea9a877	1826	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
ganlikun	0:13413ea9a877	1827	#endif
ganlikun	0:13413ea9a877	1828	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun	0:13413ea9a877	1829	#else
ganlikun	0:13413ea9a877	1830	#define NVIC_SetVector __NVIC_SetVector
ganlikun	0:13413ea9a877	1831	#define NVIC_GetVector __NVIC_GetVector
ganlikun	0:13413ea9a877	1832	#endif /* (CMSIS_VECTAB_VIRTUAL) */
ganlikun	0:13413ea9a877	1833
ganlikun	0:13413ea9a877	1834	#define NVIC_USER_IRQ_OFFSET 16
ganlikun	0:13413ea9a877	1835
ganlikun	0:13413ea9a877	1836
ganlikun	0:13413ea9a877	1837
ganlikun	0:13413ea9a877	1838	/**
ganlikun	0:13413ea9a877	1839	\brief Set Priority Grouping
ganlikun	0:13413ea9a877	1840	\details Sets the priority grouping field using the required unlock sequence.
ganlikun	0:13413ea9a877	1841	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
ganlikun	0:13413ea9a877	1842	Only values from 0..7 are used.
ganlikun	0:13413ea9a877	1843	In case of a conflict between priority grouping and available
ganlikun	0:13413ea9a877	1844	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
ganlikun	0:13413ea9a877	1845	\param [in] PriorityGroup Priority grouping field.
ganlikun	0:13413ea9a877	1846	*/
ganlikun	0:13413ea9a877	1847	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
ganlikun	0:13413ea9a877	1848	{
ganlikun	0:13413ea9a877	1849	uint32_t reg_value;
ganlikun	0:13413ea9a877	1850	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
ganlikun	0:13413ea9a877	1851
ganlikun	0:13413ea9a877	1852	reg_value = SCB->AIRCR; /* read old register configuration */
ganlikun	0:13413ea9a877	1853	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
ganlikun	0:13413ea9a877	1854	reg_value = (reg_value \|
ganlikun	0:13413ea9a877	1855	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
ganlikun	0:13413ea9a877	1856	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
ganlikun	0:13413ea9a877	1857	SCB->AIRCR = reg_value;
ganlikun	0:13413ea9a877	1858	}
ganlikun	0:13413ea9a877	1859
ganlikun	0:13413ea9a877	1860
ganlikun	0:13413ea9a877	1861	/**
ganlikun	0:13413ea9a877	1862	\brief Get Priority Grouping
ganlikun	0:13413ea9a877	1863	\details Reads the priority grouping field from the NVIC Interrupt Controller.
ganlikun	0:13413ea9a877	1864	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
ganlikun	0:13413ea9a877	1865	*/
ganlikun	0:13413ea9a877	1866	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
ganlikun	0:13413ea9a877	1867	{
ganlikun	0:13413ea9a877	1868	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
ganlikun	0:13413ea9a877	1869	}
ganlikun	0:13413ea9a877	1870
ganlikun	0:13413ea9a877	1871
ganlikun	0:13413ea9a877	1872	/**
ganlikun	0:13413ea9a877	1873	\brief Enable Interrupt
ganlikun	0:13413ea9a877	1874	\details Enables a device specific interrupt in the NVIC interrupt controller.
ganlikun	0:13413ea9a877	1875	\param [in] IRQn Device specific interrupt number.
ganlikun	0:13413ea9a877	1876	\note IRQn must not be negative.
ganlikun	0:13413ea9a877	1877	*/
ganlikun	0:13413ea9a877	1878	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	1879	{
ganlikun	0:13413ea9a877	1880	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	1881	{
ganlikun	0:13413ea9a877	1882	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun	0:13413ea9a877	1883	}
ganlikun	0:13413ea9a877	1884	}
ganlikun	0:13413ea9a877	1885
ganlikun	0:13413ea9a877	1886
ganlikun	0:13413ea9a877	1887	/**
ganlikun	0:13413ea9a877	1888	\brief Get Interrupt Enable status
ganlikun	0:13413ea9a877	1889	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
ganlikun	0:13413ea9a877	1890	\param [in] IRQn Device specific interrupt number.
ganlikun	0:13413ea9a877	1891	\return 0 Interrupt is not enabled.
ganlikun	0:13413ea9a877	1892	\return 1 Interrupt is enabled.
ganlikun	0:13413ea9a877	1893	\note IRQn must not be negative.
ganlikun	0:13413ea9a877	1894	*/
ganlikun	0:13413ea9a877	1895	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	1896	{
ganlikun	0:13413ea9a877	1897	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	1898	{
ganlikun	0:13413ea9a877	1899	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun	0:13413ea9a877	1900	}
ganlikun	0:13413ea9a877	1901	else
ganlikun	0:13413ea9a877	1902	{
ganlikun	0:13413ea9a877	1903	return(0U);
ganlikun	0:13413ea9a877	1904	}
ganlikun	0:13413ea9a877	1905	}
ganlikun	0:13413ea9a877	1906
ganlikun	0:13413ea9a877	1907
ganlikun	0:13413ea9a877	1908	/**
ganlikun	0:13413ea9a877	1909	\brief Disable Interrupt
ganlikun	0:13413ea9a877	1910	\details Disables a device specific interrupt in the NVIC interrupt controller.
ganlikun	0:13413ea9a877	1911	\param [in] IRQn Device specific interrupt number.
ganlikun	0:13413ea9a877	1912	\note IRQn must not be negative.
ganlikun	0:13413ea9a877	1913	*/
ganlikun	0:13413ea9a877	1914	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	1915	{
ganlikun	0:13413ea9a877	1916	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	1917	{
ganlikun	0:13413ea9a877	1918	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun	0:13413ea9a877	1919	__DSB();
ganlikun	0:13413ea9a877	1920	__ISB();
ganlikun	0:13413ea9a877	1921	}
ganlikun	0:13413ea9a877	1922	}
ganlikun	0:13413ea9a877	1923
ganlikun	0:13413ea9a877	1924
ganlikun	0:13413ea9a877	1925	/**
ganlikun	0:13413ea9a877	1926	\brief Get Pending Interrupt
ganlikun	0:13413ea9a877	1927	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
ganlikun	0:13413ea9a877	1928	\param [in] IRQn Device specific interrupt number.
ganlikun	0:13413ea9a877	1929	\return 0 Interrupt status is not pending.
ganlikun	0:13413ea9a877	1930	\return 1 Interrupt status is pending.
ganlikun	0:13413ea9a877	1931	\note IRQn must not be negative.
ganlikun	0:13413ea9a877	1932	*/
ganlikun	0:13413ea9a877	1933	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	1934	{
ganlikun	0:13413ea9a877	1935	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	1936	{
ganlikun	0:13413ea9a877	1937	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun	0:13413ea9a877	1938	}
ganlikun	0:13413ea9a877	1939	else
ganlikun	0:13413ea9a877	1940	{
ganlikun	0:13413ea9a877	1941	return(0U);
ganlikun	0:13413ea9a877	1942	}
ganlikun	0:13413ea9a877	1943	}
ganlikun	0:13413ea9a877	1944
ganlikun	0:13413ea9a877	1945
ganlikun	0:13413ea9a877	1946	/**
ganlikun	0:13413ea9a877	1947	\brief Set Pending Interrupt
ganlikun	0:13413ea9a877	1948	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun	0:13413ea9a877	1949	\param [in] IRQn Device specific interrupt number.
ganlikun	0:13413ea9a877	1950	\note IRQn must not be negative.
ganlikun	0:13413ea9a877	1951	*/
ganlikun	0:13413ea9a877	1952	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	1953	{
ganlikun	0:13413ea9a877	1954	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	1955	{
ganlikun	0:13413ea9a877	1956	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun	0:13413ea9a877	1957	}
ganlikun	0:13413ea9a877	1958	}
ganlikun	0:13413ea9a877	1959
ganlikun	0:13413ea9a877	1960
ganlikun	0:13413ea9a877	1961	/**
ganlikun	0:13413ea9a877	1962	\brief Clear Pending Interrupt
ganlikun	0:13413ea9a877	1963	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun	0:13413ea9a877	1964	\param [in] IRQn Device specific interrupt number.
ganlikun	0:13413ea9a877	1965	\note IRQn must not be negative.
ganlikun	0:13413ea9a877	1966	*/
ganlikun	0:13413ea9a877	1967	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	1968	{
ganlikun	0:13413ea9a877	1969	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	1970	{
ganlikun	0:13413ea9a877	1971	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun	0:13413ea9a877	1972	}
ganlikun	0:13413ea9a877	1973	}
ganlikun	0:13413ea9a877	1974
ganlikun	0:13413ea9a877	1975
ganlikun	0:13413ea9a877	1976	/**
ganlikun	0:13413ea9a877	1977	\brief Get Active Interrupt
ganlikun	0:13413ea9a877	1978	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
ganlikun	0:13413ea9a877	1979	\param [in] IRQn Device specific interrupt number.
ganlikun	0:13413ea9a877	1980	\return 0 Interrupt status is not active.
ganlikun	0:13413ea9a877	1981	\return 1 Interrupt status is active.
ganlikun	0:13413ea9a877	1982	\note IRQn must not be negative.
ganlikun	0:13413ea9a877	1983	*/
ganlikun	0:13413ea9a877	1984	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	1985	{
ganlikun	0:13413ea9a877	1986	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	1987	{
ganlikun	0:13413ea9a877	1988	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun	0:13413ea9a877	1989	}
ganlikun	0:13413ea9a877	1990	else
ganlikun	0:13413ea9a877	1991	{
ganlikun	0:13413ea9a877	1992	return(0U);
ganlikun	0:13413ea9a877	1993	}
ganlikun	0:13413ea9a877	1994	}
ganlikun	0:13413ea9a877	1995
ganlikun	0:13413ea9a877	1996
ganlikun	0:13413ea9a877	1997	/**
ganlikun	0:13413ea9a877	1998	\brief Set Interrupt Priority
ganlikun	0:13413ea9a877	1999	\details Sets the priority of a device specific interrupt or a processor exception.
ganlikun	0:13413ea9a877	2000	The interrupt number can be positive to specify a device specific interrupt,
ganlikun	0:13413ea9a877	2001	or negative to specify a processor exception.
ganlikun	0:13413ea9a877	2002	\param [in] IRQn Interrupt number.
ganlikun	0:13413ea9a877	2003	\param [in] priority Priority to set.
ganlikun	0:13413ea9a877	2004	\note The priority cannot be set for every processor exception.
ganlikun	0:13413ea9a877	2005	*/
ganlikun	0:13413ea9a877	2006	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ganlikun	0:13413ea9a877	2007	{
ganlikun	0:13413ea9a877	2008	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	2009	{
ganlikun	0:13413ea9a877	2010	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
ganlikun	0:13413ea9a877	2011	}
ganlikun	0:13413ea9a877	2012	else
ganlikun	0:13413ea9a877	2013	{
ganlikun	0:13413ea9a877	2014	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
ganlikun	0:13413ea9a877	2015	}
ganlikun	0:13413ea9a877	2016	}
ganlikun	0:13413ea9a877	2017
ganlikun	0:13413ea9a877	2018
ganlikun	0:13413ea9a877	2019	/**
ganlikun	0:13413ea9a877	2020	\brief Get Interrupt Priority
ganlikun	0:13413ea9a877	2021	\details Reads the priority of a device specific interrupt or a processor exception.
ganlikun	0:13413ea9a877	2022	The interrupt number can be positive to specify a device specific interrupt,
ganlikun	0:13413ea9a877	2023	or negative to specify a processor exception.
ganlikun	0:13413ea9a877	2024	\param [in] IRQn Interrupt number.
ganlikun	0:13413ea9a877	2025	\return Interrupt Priority.
ganlikun	0:13413ea9a877	2026	Value is aligned automatically to the implemented priority bits of the microcontroller.
ganlikun	0:13413ea9a877	2027	*/
ganlikun	0:13413ea9a877	2028	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	2029	{
ganlikun	0:13413ea9a877	2030
ganlikun	0:13413ea9a877	2031	if ((int32_t)(IRQn) >= 0)
ganlikun	0:13413ea9a877	2032	{
ganlikun	0:13413ea9a877	2033	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
ganlikun	0:13413ea9a877	2034	}
ganlikun	0:13413ea9a877	2035	else
ganlikun	0:13413ea9a877	2036	{
ganlikun	0:13413ea9a877	2037	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
ganlikun	0:13413ea9a877	2038	}
ganlikun	0:13413ea9a877	2039	}
ganlikun	0:13413ea9a877	2040
ganlikun	0:13413ea9a877	2041
ganlikun	0:13413ea9a877	2042	/**
ganlikun	0:13413ea9a877	2043	\brief Encode Priority
ganlikun	0:13413ea9a877	2044	\details Encodes the priority for an interrupt with the given priority group,
ganlikun	0:13413ea9a877	2045	preemptive priority value, and subpriority value.
ganlikun	0:13413ea9a877	2046	In case of a conflict between priority grouping and available
ganlikun	0:13413ea9a877	2047	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
ganlikun	0:13413ea9a877	2048	\param [in] PriorityGroup Used priority group.
ganlikun	0:13413ea9a877	2049	\param [in] PreemptPriority Preemptive priority value (starting from 0).
ganlikun	0:13413ea9a877	2050	\param [in] SubPriority Subpriority value (starting from 0).
ganlikun	0:13413ea9a877	2051	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
ganlikun	0:13413ea9a877	2052	*/
ganlikun	0:13413ea9a877	2053	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
ganlikun	0:13413ea9a877	2054	{
ganlikun	0:13413ea9a877	2055	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
ganlikun	0:13413ea9a877	2056	uint32_t PreemptPriorityBits;
ganlikun	0:13413ea9a877	2057	uint32_t SubPriorityBits;
ganlikun	0:13413ea9a877	2058
ganlikun	0:13413ea9a877	2059	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
ganlikun	0:13413ea9a877	2060	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
ganlikun	0:13413ea9a877	2061
ganlikun	0:13413ea9a877	2062	return (
ganlikun	0:13413ea9a877	2063	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
ganlikun	0:13413ea9a877	2064	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
ganlikun	0:13413ea9a877	2065	);
ganlikun	0:13413ea9a877	2066	}
ganlikun	0:13413ea9a877	2067
ganlikun	0:13413ea9a877	2068
ganlikun	0:13413ea9a877	2069	/**
ganlikun	0:13413ea9a877	2070	\brief Decode Priority
ganlikun	0:13413ea9a877	2071	\details Decodes an interrupt priority value with a given priority group to
ganlikun	0:13413ea9a877	2072	preemptive priority value and subpriority value.
ganlikun	0:13413ea9a877	2073	In case of a conflict between priority grouping and available
ganlikun	0:13413ea9a877	2074	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
ganlikun	0:13413ea9a877	2075	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
ganlikun	0:13413ea9a877	2076	\param [in] PriorityGroup Used priority group.
ganlikun	0:13413ea9a877	2077	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
ganlikun	0:13413ea9a877	2078	\param [out] pSubPriority Subpriority value (starting from 0).
ganlikun	0:13413ea9a877	2079	*/
ganlikun	0:13413ea9a877	2080	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
ganlikun	0:13413ea9a877	2081	{
ganlikun	0:13413ea9a877	2082	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
ganlikun	0:13413ea9a877	2083	uint32_t PreemptPriorityBits;
ganlikun	0:13413ea9a877	2084	uint32_t SubPriorityBits;
ganlikun	0:13413ea9a877	2085
ganlikun	0:13413ea9a877	2086	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
ganlikun	0:13413ea9a877	2087	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
ganlikun	0:13413ea9a877	2088
ganlikun	0:13413ea9a877	2089	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
ganlikun	0:13413ea9a877	2090	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
ganlikun	0:13413ea9a877	2091	}
ganlikun	0:13413ea9a877	2092
ganlikun	0:13413ea9a877	2093
ganlikun	0:13413ea9a877	2094	/**
ganlikun	0:13413ea9a877	2095	\brief Set Interrupt Vector
ganlikun	0:13413ea9a877	2096	\details Sets an interrupt vector in SRAM based interrupt vector table.
ganlikun	0:13413ea9a877	2097	The interrupt number can be positive to specify a device specific interrupt,
ganlikun	0:13413ea9a877	2098	or negative to specify a processor exception.
ganlikun	0:13413ea9a877	2099	VTOR must been relocated to SRAM before.
ganlikun	0:13413ea9a877	2100	\param [in] IRQn Interrupt number
ganlikun	0:13413ea9a877	2101	\param [in] vector Address of interrupt handler function
ganlikun	0:13413ea9a877	2102	*/
ganlikun	0:13413ea9a877	2103	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
ganlikun	0:13413ea9a877	2104	{
ganlikun	0:13413ea9a877	2105	uint32_t vectors = (uint32_t )SCB->VTOR;
ganlikun	0:13413ea9a877	2106	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
ganlikun	0:13413ea9a877	2107	}
ganlikun	0:13413ea9a877	2108
ganlikun	0:13413ea9a877	2109
ganlikun	0:13413ea9a877	2110	/**
ganlikun	0:13413ea9a877	2111	\brief Get Interrupt Vector
ganlikun	0:13413ea9a877	2112	\details Reads an interrupt vector from interrupt vector table.
ganlikun	0:13413ea9a877	2113	The interrupt number can be positive to specify a device specific interrupt,
ganlikun	0:13413ea9a877	2114	or negative to specify a processor exception.
ganlikun	0:13413ea9a877	2115	\param [in] IRQn Interrupt number.
ganlikun	0:13413ea9a877	2116	\return Address of interrupt handler function
ganlikun	0:13413ea9a877	2117	*/
ganlikun	0:13413ea9a877	2118	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
ganlikun	0:13413ea9a877	2119	{
ganlikun	0:13413ea9a877	2120	uint32_t vectors = (uint32_t )SCB->VTOR;
ganlikun	0:13413ea9a877	2121	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
ganlikun	0:13413ea9a877	2122	}
ganlikun	0:13413ea9a877	2123
ganlikun	0:13413ea9a877	2124
ganlikun	0:13413ea9a877	2125	/**
ganlikun	0:13413ea9a877	2126	\brief System Reset
ganlikun	0:13413ea9a877	2127	\details Initiates a system reset request to reset the MCU.
ganlikun	0:13413ea9a877	2128	*/
ganlikun	0:13413ea9a877	2129	__STATIC_INLINE void __NVIC_SystemReset(void)
ganlikun	0:13413ea9a877	2130	{
ganlikun	0:13413ea9a877	2131	__DSB(); /* Ensure all outstanding memory accesses included
ganlikun	0:13413ea9a877	2132	buffered write are completed before reset */
ganlikun	0:13413ea9a877	2133	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
ganlikun	0:13413ea9a877	2134	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
ganlikun	0:13413ea9a877	2135	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
ganlikun	0:13413ea9a877	2136	__DSB(); /* Ensure completion of memory access */
ganlikun	0:13413ea9a877	2137
ganlikun	0:13413ea9a877	2138	for(;;) /* wait until reset */
ganlikun	0:13413ea9a877	2139	{
ganlikun	0:13413ea9a877	2140	__NOP();
ganlikun	0:13413ea9a877	2141	}
ganlikun	0:13413ea9a877	2142	}
ganlikun	0:13413ea9a877	2143
ganlikun	0:13413ea9a877	2144	/@} end of CMSIS_Core_NVICFunctions /
ganlikun	0:13413ea9a877	2145
ganlikun	0:13413ea9a877	2146
ganlikun	0:13413ea9a877	2147	/* ########################## FPU functions #################################### */
ganlikun	0:13413ea9a877	2148	/**
ganlikun	0:13413ea9a877	2149	\ingroup CMSIS_Core_FunctionInterface
ganlikun	0:13413ea9a877	2150	\defgroup CMSIS_Core_FpuFunctions FPU Functions
ganlikun	0:13413ea9a877	2151	\brief Function that provides FPU type.
ganlikun	0:13413ea9a877	2152	@{
ganlikun	0:13413ea9a877	2153	*/
ganlikun	0:13413ea9a877	2154
ganlikun	0:13413ea9a877	2155	/**
ganlikun	0:13413ea9a877	2156	\brief get FPU type
ganlikun	0:13413ea9a877	2157	\details returns the FPU type
ganlikun	0:13413ea9a877	2158	\returns
ganlikun	0:13413ea9a877	2159	- \b 0: No FPU
ganlikun	0:13413ea9a877	2160	- \b 1: Single precision FPU
ganlikun	0:13413ea9a877	2161	- \b 2: Double + Single precision FPU
ganlikun	0:13413ea9a877	2162	*/
ganlikun	0:13413ea9a877	2163	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
ganlikun	0:13413ea9a877	2164	{
ganlikun	0:13413ea9a877	2165	uint32_t mvfr0;
ganlikun	0:13413ea9a877	2166
ganlikun	0:13413ea9a877	2167	mvfr0 = SCB->MVFR0;
ganlikun	0:13413ea9a877	2168	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
ganlikun	0:13413ea9a877	2169	{
ganlikun	0:13413ea9a877	2170	return 2U; /* Double + Single precision FPU */
ganlikun	0:13413ea9a877	2171	}
ganlikun	0:13413ea9a877	2172	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
ganlikun	0:13413ea9a877	2173	{
ganlikun	0:13413ea9a877	2174	return 1U; /* Single precision FPU */
ganlikun	0:13413ea9a877	2175	}
ganlikun	0:13413ea9a877	2176	else
ganlikun	0:13413ea9a877	2177	{
ganlikun	0:13413ea9a877	2178	return 0U; /* No FPU */
ganlikun	0:13413ea9a877	2179	}
ganlikun	0:13413ea9a877	2180	}
ganlikun	0:13413ea9a877	2181
ganlikun	0:13413ea9a877	2182
ganlikun	0:13413ea9a877	2183	/@} end of CMSIS_Core_FpuFunctions /
ganlikun	0:13413ea9a877	2184
ganlikun	0:13413ea9a877	2185
ganlikun	0:13413ea9a877	2186
ganlikun	0:13413ea9a877	2187	/* ########################## Cache functions #################################### */
ganlikun	0:13413ea9a877	2188	/**
ganlikun	0:13413ea9a877	2189	\ingroup CMSIS_Core_FunctionInterface
ganlikun	0:13413ea9a877	2190	\defgroup CMSIS_Core_CacheFunctions Cache Functions
ganlikun	0:13413ea9a877	2191	\brief Functions that configure Instruction and Data cache.
ganlikun	0:13413ea9a877	2192	@{
ganlikun	0:13413ea9a877	2193	*/
ganlikun	0:13413ea9a877	2194
ganlikun	0:13413ea9a877	2195	/* Cache Size ID Register Macros */
ganlikun	0:13413ea9a877	2196	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
ganlikun	0:13413ea9a877	2197	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
ganlikun	0:13413ea9a877	2198
ganlikun	0:13413ea9a877	2199
ganlikun	0:13413ea9a877	2200	/**
ganlikun	0:13413ea9a877	2201	\brief Enable I-Cache
ganlikun	0:13413ea9a877	2202	\details Turns on I-Cache
ganlikun	0:13413ea9a877	2203	*/
ganlikun	0:13413ea9a877	2204	__STATIC_INLINE void SCB_EnableICache (void)
ganlikun	0:13413ea9a877	2205	{
ganlikun	0:13413ea9a877	2206	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2207	__DSB();
ganlikun	0:13413ea9a877	2208	__ISB();
ganlikun	0:13413ea9a877	2209	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
ganlikun	0:13413ea9a877	2210	__DSB();
ganlikun	0:13413ea9a877	2211	__ISB();
ganlikun	0:13413ea9a877	2212	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
ganlikun	0:13413ea9a877	2213	__DSB();
ganlikun	0:13413ea9a877	2214	__ISB();
ganlikun	0:13413ea9a877	2215	#endif
ganlikun	0:13413ea9a877	2216	}
ganlikun	0:13413ea9a877	2217
ganlikun	0:13413ea9a877	2218
ganlikun	0:13413ea9a877	2219	/**
ganlikun	0:13413ea9a877	2220	\brief Disable I-Cache
ganlikun	0:13413ea9a877	2221	\details Turns off I-Cache
ganlikun	0:13413ea9a877	2222	*/
ganlikun	0:13413ea9a877	2223	__STATIC_INLINE void SCB_DisableICache (void)
ganlikun	0:13413ea9a877	2224	{
ganlikun	0:13413ea9a877	2225	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2226	__DSB();
ganlikun	0:13413ea9a877	2227	__ISB();
ganlikun	0:13413ea9a877	2228	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
ganlikun	0:13413ea9a877	2229	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
ganlikun	0:13413ea9a877	2230	__DSB();
ganlikun	0:13413ea9a877	2231	__ISB();
ganlikun	0:13413ea9a877	2232	#endif
ganlikun	0:13413ea9a877	2233	}
ganlikun	0:13413ea9a877	2234
ganlikun	0:13413ea9a877	2235
ganlikun	0:13413ea9a877	2236	/**
ganlikun	0:13413ea9a877	2237	\brief Invalidate I-Cache
ganlikun	0:13413ea9a877	2238	\details Invalidates I-Cache
ganlikun	0:13413ea9a877	2239	*/
ganlikun	0:13413ea9a877	2240	__STATIC_INLINE void SCB_InvalidateICache (void)
ganlikun	0:13413ea9a877	2241	{
ganlikun	0:13413ea9a877	2242	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2243	__DSB();
ganlikun	0:13413ea9a877	2244	__ISB();
ganlikun	0:13413ea9a877	2245	SCB->ICIALLU = 0UL;
ganlikun	0:13413ea9a877	2246	__DSB();
ganlikun	0:13413ea9a877	2247	__ISB();
ganlikun	0:13413ea9a877	2248	#endif
ganlikun	0:13413ea9a877	2249	}
ganlikun	0:13413ea9a877	2250
ganlikun	0:13413ea9a877	2251
ganlikun	0:13413ea9a877	2252	/**
ganlikun	0:13413ea9a877	2253	\brief Enable D-Cache
ganlikun	0:13413ea9a877	2254	\details Turns on D-Cache
ganlikun	0:13413ea9a877	2255	*/
ganlikun	0:13413ea9a877	2256	__STATIC_INLINE void SCB_EnableDCache (void)
ganlikun	0:13413ea9a877	2257	{
ganlikun	0:13413ea9a877	2258	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2259	uint32_t ccsidr;
ganlikun	0:13413ea9a877	2260	uint32_t sets;
ganlikun	0:13413ea9a877	2261	uint32_t ways;
ganlikun	0:13413ea9a877	2262
ganlikun	0:13413ea9a877	2263	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
ganlikun	0:13413ea9a877	2264	__DSB();
ganlikun	0:13413ea9a877	2265
ganlikun	0:13413ea9a877	2266	ccsidr = SCB->CCSIDR;
ganlikun	0:13413ea9a877	2267
ganlikun	0:13413ea9a877	2268	/* invalidate D-Cache */
ganlikun	0:13413ea9a877	2269	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
ganlikun	0:13413ea9a877	2270	do {
ganlikun	0:13413ea9a877	2271	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
ganlikun	0:13413ea9a877	2272	do {
ganlikun	0:13413ea9a877	2273	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
ganlikun	0:13413ea9a877	2274	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
ganlikun	0:13413ea9a877	2275	#if defined ( __CC_ARM )
ganlikun	0:13413ea9a877	2276	__schedule_barrier();
ganlikun	0:13413ea9a877	2277	#endif
ganlikun	0:13413ea9a877	2278	} while (ways-- != 0U);
ganlikun	0:13413ea9a877	2279	} while(sets-- != 0U);
ganlikun	0:13413ea9a877	2280	__DSB();
ganlikun	0:13413ea9a877	2281
ganlikun	0:13413ea9a877	2282	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
ganlikun	0:13413ea9a877	2283
ganlikun	0:13413ea9a877	2284	__DSB();
ganlikun	0:13413ea9a877	2285	__ISB();
ganlikun	0:13413ea9a877	2286	#endif
ganlikun	0:13413ea9a877	2287	}
ganlikun	0:13413ea9a877	2288
ganlikun	0:13413ea9a877	2289
ganlikun	0:13413ea9a877	2290	/**
ganlikun	0:13413ea9a877	2291	\brief Disable D-Cache
ganlikun	0:13413ea9a877	2292	\details Turns off D-Cache
ganlikun	0:13413ea9a877	2293	*/
ganlikun	0:13413ea9a877	2294	__STATIC_INLINE void SCB_DisableDCache (void)
ganlikun	0:13413ea9a877	2295	{
ganlikun	0:13413ea9a877	2296	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2297	register uint32_t ccsidr;
ganlikun	0:13413ea9a877	2298	register uint32_t sets;
ganlikun	0:13413ea9a877	2299	register uint32_t ways;
ganlikun	0:13413ea9a877	2300
ganlikun	0:13413ea9a877	2301	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
ganlikun	0:13413ea9a877	2302	__DSB();
ganlikun	0:13413ea9a877	2303
ganlikun	0:13413ea9a877	2304	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
ganlikun	0:13413ea9a877	2305	__DSB();
ganlikun	0:13413ea9a877	2306
ganlikun	0:13413ea9a877	2307	ccsidr = SCB->CCSIDR;
ganlikun	0:13413ea9a877	2308
ganlikun	0:13413ea9a877	2309	/* clean & invalidate D-Cache */
ganlikun	0:13413ea9a877	2310	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
ganlikun	0:13413ea9a877	2311	do {
ganlikun	0:13413ea9a877	2312	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
ganlikun	0:13413ea9a877	2313	do {
ganlikun	0:13413ea9a877	2314	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
ganlikun	0:13413ea9a877	2315	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
ganlikun	0:13413ea9a877	2316	#if defined ( __CC_ARM )
ganlikun	0:13413ea9a877	2317	__schedule_barrier();
ganlikun	0:13413ea9a877	2318	#endif
ganlikun	0:13413ea9a877	2319	} while (ways-- != 0U);
ganlikun	0:13413ea9a877	2320	} while(sets-- != 0U);
ganlikun	0:13413ea9a877	2321
ganlikun	0:13413ea9a877	2322	__DSB();
ganlikun	0:13413ea9a877	2323	__ISB();
ganlikun	0:13413ea9a877	2324	#endif
ganlikun	0:13413ea9a877	2325	}
ganlikun	0:13413ea9a877	2326
ganlikun	0:13413ea9a877	2327
ganlikun	0:13413ea9a877	2328	/**
ganlikun	0:13413ea9a877	2329	\brief Invalidate D-Cache
ganlikun	0:13413ea9a877	2330	\details Invalidates D-Cache
ganlikun	0:13413ea9a877	2331	*/
ganlikun	0:13413ea9a877	2332	__STATIC_INLINE void SCB_InvalidateDCache (void)
ganlikun	0:13413ea9a877	2333	{
ganlikun	0:13413ea9a877	2334	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2335	uint32_t ccsidr;
ganlikun	0:13413ea9a877	2336	uint32_t sets;
ganlikun	0:13413ea9a877	2337	uint32_t ways;
ganlikun	0:13413ea9a877	2338
ganlikun	0:13413ea9a877	2339	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
ganlikun	0:13413ea9a877	2340	__DSB();
ganlikun	0:13413ea9a877	2341
ganlikun	0:13413ea9a877	2342	ccsidr = SCB->CCSIDR;
ganlikun	0:13413ea9a877	2343
ganlikun	0:13413ea9a877	2344	/* invalidate D-Cache */
ganlikun	0:13413ea9a877	2345	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
ganlikun	0:13413ea9a877	2346	do {
ganlikun	0:13413ea9a877	2347	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
ganlikun	0:13413ea9a877	2348	do {
ganlikun	0:13413ea9a877	2349	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
ganlikun	0:13413ea9a877	2350	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
ganlikun	0:13413ea9a877	2351	#if defined ( __CC_ARM )
ganlikun	0:13413ea9a877	2352	__schedule_barrier();
ganlikun	0:13413ea9a877	2353	#endif
ganlikun	0:13413ea9a877	2354	} while (ways-- != 0U);
ganlikun	0:13413ea9a877	2355	} while(sets-- != 0U);
ganlikun	0:13413ea9a877	2356
ganlikun	0:13413ea9a877	2357	__DSB();
ganlikun	0:13413ea9a877	2358	__ISB();
ganlikun	0:13413ea9a877	2359	#endif
ganlikun	0:13413ea9a877	2360	}
ganlikun	0:13413ea9a877	2361
ganlikun	0:13413ea9a877	2362
ganlikun	0:13413ea9a877	2363	/**
ganlikun	0:13413ea9a877	2364	\brief Clean D-Cache
ganlikun	0:13413ea9a877	2365	\details Cleans D-Cache
ganlikun	0:13413ea9a877	2366	*/
ganlikun	0:13413ea9a877	2367	__STATIC_INLINE void SCB_CleanDCache (void)
ganlikun	0:13413ea9a877	2368	{
ganlikun	0:13413ea9a877	2369	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2370	uint32_t ccsidr;
ganlikun	0:13413ea9a877	2371	uint32_t sets;
ganlikun	0:13413ea9a877	2372	uint32_t ways;
ganlikun	0:13413ea9a877	2373
ganlikun	0:13413ea9a877	2374	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
ganlikun	0:13413ea9a877	2375	__DSB();
ganlikun	0:13413ea9a877	2376
ganlikun	0:13413ea9a877	2377	ccsidr = SCB->CCSIDR;
ganlikun	0:13413ea9a877	2378
ganlikun	0:13413ea9a877	2379	/* clean D-Cache */
ganlikun	0:13413ea9a877	2380	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
ganlikun	0:13413ea9a877	2381	do {
ganlikun	0:13413ea9a877	2382	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
ganlikun	0:13413ea9a877	2383	do {
ganlikun	0:13413ea9a877	2384	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
ganlikun	0:13413ea9a877	2385	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
ganlikun	0:13413ea9a877	2386	#if defined ( __CC_ARM )
ganlikun	0:13413ea9a877	2387	__schedule_barrier();
ganlikun	0:13413ea9a877	2388	#endif
ganlikun	0:13413ea9a877	2389	} while (ways-- != 0U);
ganlikun	0:13413ea9a877	2390	} while(sets-- != 0U);
ganlikun	0:13413ea9a877	2391
ganlikun	0:13413ea9a877	2392	__DSB();
ganlikun	0:13413ea9a877	2393	__ISB();
ganlikun	0:13413ea9a877	2394	#endif
ganlikun	0:13413ea9a877	2395	}
ganlikun	0:13413ea9a877	2396
ganlikun	0:13413ea9a877	2397
ganlikun	0:13413ea9a877	2398	/**
ganlikun	0:13413ea9a877	2399	\brief Clean & Invalidate D-Cache
ganlikun	0:13413ea9a877	2400	\details Cleans and Invalidates D-Cache
ganlikun	0:13413ea9a877	2401	*/
ganlikun	0:13413ea9a877	2402	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
ganlikun	0:13413ea9a877	2403	{
ganlikun	0:13413ea9a877	2404	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2405	uint32_t ccsidr;
ganlikun	0:13413ea9a877	2406	uint32_t sets;
ganlikun	0:13413ea9a877	2407	uint32_t ways;
ganlikun	0:13413ea9a877	2408
ganlikun	0:13413ea9a877	2409	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
ganlikun	0:13413ea9a877	2410	__DSB();
ganlikun	0:13413ea9a877	2411
ganlikun	0:13413ea9a877	2412	ccsidr = SCB->CCSIDR;
ganlikun	0:13413ea9a877	2413
ganlikun	0:13413ea9a877	2414	/* clean & invalidate D-Cache */
ganlikun	0:13413ea9a877	2415	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
ganlikun	0:13413ea9a877	2416	do {
ganlikun	0:13413ea9a877	2417	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
ganlikun	0:13413ea9a877	2418	do {
ganlikun	0:13413ea9a877	2419	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
ganlikun	0:13413ea9a877	2420	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
ganlikun	0:13413ea9a877	2421	#if defined ( __CC_ARM )
ganlikun	0:13413ea9a877	2422	__schedule_barrier();
ganlikun	0:13413ea9a877	2423	#endif
ganlikun	0:13413ea9a877	2424	} while (ways-- != 0U);
ganlikun	0:13413ea9a877	2425	} while(sets-- != 0U);
ganlikun	0:13413ea9a877	2426
ganlikun	0:13413ea9a877	2427	__DSB();
ganlikun	0:13413ea9a877	2428	__ISB();
ganlikun	0:13413ea9a877	2429	#endif
ganlikun	0:13413ea9a877	2430	}
ganlikun	0:13413ea9a877	2431
ganlikun	0:13413ea9a877	2432
ganlikun	0:13413ea9a877	2433	/**
ganlikun	0:13413ea9a877	2434	\brief D-Cache Invalidate by address
ganlikun	0:13413ea9a877	2435	\details Invalidates D-Cache for the given address
ganlikun	0:13413ea9a877	2436	\param[in] addr address (aligned to 32-byte boundary)
ganlikun	0:13413ea9a877	2437	\param[in] dsize size of memory block (in number of bytes)
ganlikun	0:13413ea9a877	2438	*/
ganlikun	0:13413ea9a877	2439	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
ganlikun	0:13413ea9a877	2440	{
ganlikun	0:13413ea9a877	2441	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2442	int32_t op_size = dsize;
ganlikun	0:13413ea9a877	2443	uint32_t op_addr = (uint32_t)addr;
ganlikun	0:13413ea9a877	2444	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
ganlikun	0:13413ea9a877	2445
ganlikun	0:13413ea9a877	2446	__DSB();
ganlikun	0:13413ea9a877	2447
ganlikun	0:13413ea9a877	2448	while (op_size > 0) {
ganlikun	0:13413ea9a877	2449	SCB->DCIMVAC = op_addr;
ganlikun	0:13413ea9a877	2450	op_addr += (uint32_t)linesize;
ganlikun	0:13413ea9a877	2451	op_size -= linesize;
ganlikun	0:13413ea9a877	2452	}
ganlikun	0:13413ea9a877	2453
ganlikun	0:13413ea9a877	2454	__DSB();
ganlikun	0:13413ea9a877	2455	__ISB();
ganlikun	0:13413ea9a877	2456	#endif
ganlikun	0:13413ea9a877	2457	}
ganlikun	0:13413ea9a877	2458
ganlikun	0:13413ea9a877	2459
ganlikun	0:13413ea9a877	2460	/**
ganlikun	0:13413ea9a877	2461	\brief D-Cache Clean by address
ganlikun	0:13413ea9a877	2462	\details Cleans D-Cache for the given address
ganlikun	0:13413ea9a877	2463	\param[in] addr address (aligned to 32-byte boundary)
ganlikun	0:13413ea9a877	2464	\param[in] dsize size of memory block (in number of bytes)
ganlikun	0:13413ea9a877	2465	*/
ganlikun	0:13413ea9a877	2466	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
ganlikun	0:13413ea9a877	2467	{
ganlikun	0:13413ea9a877	2468	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2469	int32_t op_size = dsize;
ganlikun	0:13413ea9a877	2470	uint32_t op_addr = (uint32_t) addr;
ganlikun	0:13413ea9a877	2471	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
ganlikun	0:13413ea9a877	2472
ganlikun	0:13413ea9a877	2473	__DSB();
ganlikun	0:13413ea9a877	2474
ganlikun	0:13413ea9a877	2475	while (op_size > 0) {
ganlikun	0:13413ea9a877	2476	SCB->DCCMVAC = op_addr;
ganlikun	0:13413ea9a877	2477	op_addr += (uint32_t)linesize;
ganlikun	0:13413ea9a877	2478	op_size -= linesize;
ganlikun	0:13413ea9a877	2479	}
ganlikun	0:13413ea9a877	2480
ganlikun	0:13413ea9a877	2481	__DSB();
ganlikun	0:13413ea9a877	2482	__ISB();
ganlikun	0:13413ea9a877	2483	#endif
ganlikun	0:13413ea9a877	2484	}
ganlikun	0:13413ea9a877	2485
ganlikun	0:13413ea9a877	2486
ganlikun	0:13413ea9a877	2487	/**
ganlikun	0:13413ea9a877	2488	\brief D-Cache Clean and Invalidate by address
ganlikun	0:13413ea9a877	2489	\details Cleans and invalidates D_Cache for the given address
ganlikun	0:13413ea9a877	2490	\param[in] addr address (aligned to 32-byte boundary)
ganlikun	0:13413ea9a877	2491	\param[in] dsize size of memory block (in number of bytes)
ganlikun	0:13413ea9a877	2492	*/
ganlikun	0:13413ea9a877	2493	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
ganlikun	0:13413ea9a877	2494	{
ganlikun	0:13413ea9a877	2495	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
ganlikun	0:13413ea9a877	2496	int32_t op_size = dsize;
ganlikun	0:13413ea9a877	2497	uint32_t op_addr = (uint32_t) addr;
ganlikun	0:13413ea9a877	2498	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
ganlikun	0:13413ea9a877	2499
ganlikun	0:13413ea9a877	2500	__DSB();
ganlikun	0:13413ea9a877	2501
ganlikun	0:13413ea9a877	2502	while (op_size > 0) {
ganlikun	0:13413ea9a877	2503	SCB->DCCIMVAC = op_addr;
ganlikun	0:13413ea9a877	2504	op_addr += (uint32_t)linesize;
ganlikun	0:13413ea9a877	2505	op_size -= linesize;
ganlikun	0:13413ea9a877	2506	}
ganlikun	0:13413ea9a877	2507
ganlikun	0:13413ea9a877	2508	__DSB();
ganlikun	0:13413ea9a877	2509	__ISB();
ganlikun	0:13413ea9a877	2510	#endif
ganlikun	0:13413ea9a877	2511	}
ganlikun	0:13413ea9a877	2512
ganlikun	0:13413ea9a877	2513
ganlikun	0:13413ea9a877	2514	/@} end of CMSIS_Core_CacheFunctions /
ganlikun	0:13413ea9a877	2515
ganlikun	0:13413ea9a877	2516
ganlikun	0:13413ea9a877	2517
ganlikun	0:13413ea9a877	2518	/* ################################## SysTick function ############################################ */
ganlikun	0:13413ea9a877	2519	/**
ganlikun	0:13413ea9a877	2520	\ingroup CMSIS_Core_FunctionInterface
ganlikun	0:13413ea9a877	2521	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
ganlikun	0:13413ea9a877	2522	\brief Functions that configure the System.
ganlikun	0:13413ea9a877	2523	@{
ganlikun	0:13413ea9a877	2524	*/
ganlikun	0:13413ea9a877	2525
ganlikun	0:13413ea9a877	2526	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
ganlikun	0:13413ea9a877	2527
ganlikun	0:13413ea9a877	2528	/**
ganlikun	0:13413ea9a877	2529	\brief System Tick Configuration
ganlikun	0:13413ea9a877	2530	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
ganlikun	0:13413ea9a877	2531	Counter is in free running mode to generate periodic interrupts.
ganlikun	0:13413ea9a877	2532	\param [in] ticks Number of ticks between two interrupts.
ganlikun	0:13413ea9a877	2533	\return 0 Function succeeded.
ganlikun	0:13413ea9a877	2534	\return 1 Function failed.
ganlikun	0:13413ea9a877	2535	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ganlikun	0:13413ea9a877	2536	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
ganlikun	0:13413ea9a877	2537	must contain a vendor-specific implementation of this function.
ganlikun	0:13413ea9a877	2538	*/
ganlikun	0:13413ea9a877	2539	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ganlikun	0:13413ea9a877	2540	{
ganlikun	0:13413ea9a877	2541	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
ganlikun	0:13413ea9a877	2542	{
ganlikun	0:13413ea9a877	2543	return (1UL); /* Reload value impossible */
ganlikun	0:13413ea9a877	2544	}
ganlikun	0:13413ea9a877	2545
ganlikun	0:13413ea9a877	2546	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
ganlikun	0:13413ea9a877	2547	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
ganlikun	0:13413ea9a877	2548	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
ganlikun	0:13413ea9a877	2549	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
ganlikun	0:13413ea9a877	2550	SysTick_CTRL_TICKINT_Msk \|
ganlikun	0:13413ea9a877	2551	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ganlikun	0:13413ea9a877	2552	return (0UL); /* Function successful */
ganlikun	0:13413ea9a877	2553	}
ganlikun	0:13413ea9a877	2554
ganlikun	0:13413ea9a877	2555	#endif
ganlikun	0:13413ea9a877	2556
ganlikun	0:13413ea9a877	2557	/@} end of CMSIS_Core_SysTickFunctions /
ganlikun	0:13413ea9a877	2558
ganlikun	0:13413ea9a877	2559
ganlikun	0:13413ea9a877	2560
ganlikun	0:13413ea9a877	2561	/* ##################################### Debug In/Output function ########################################### */
ganlikun	0:13413ea9a877	2562	/**
ganlikun	0:13413ea9a877	2563	\ingroup CMSIS_Core_FunctionInterface
ganlikun	0:13413ea9a877	2564	\defgroup CMSIS_core_DebugFunctions ITM Functions
ganlikun	0:13413ea9a877	2565	\brief Functions that access the ITM debug interface.
ganlikun	0:13413ea9a877	2566	@{
ganlikun	0:13413ea9a877	2567	*/
ganlikun	0:13413ea9a877	2568
ganlikun	0:13413ea9a877	2569	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
ganlikun	0:13413ea9a877	2570	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
ganlikun	0:13413ea9a877	2571
ganlikun	0:13413ea9a877	2572
ganlikun	0:13413ea9a877	2573	/**
ganlikun	0:13413ea9a877	2574	\brief ITM Send Character
ganlikun	0:13413ea9a877	2575	\details Transmits a character via the ITM channel 0, and
ganlikun	0:13413ea9a877	2576	\li Just returns when no debugger is connected that has booked the output.
ganlikun	0:13413ea9a877	2577	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
ganlikun	0:13413ea9a877	2578	\param [in] ch Character to transmit.
ganlikun	0:13413ea9a877	2579	\returns Character to transmit.
ganlikun	0:13413ea9a877	2580	*/
ganlikun	0:13413ea9a877	2581	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
ganlikun	0:13413ea9a877	2582	{
ganlikun	0:13413ea9a877	2583	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
ganlikun	0:13413ea9a877	2584	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
ganlikun	0:13413ea9a877	2585	{
ganlikun	0:13413ea9a877	2586	while (ITM->PORT[0U].u32 == 0UL)
ganlikun	0:13413ea9a877	2587	{
ganlikun	0:13413ea9a877	2588	__NOP();
ganlikun	0:13413ea9a877	2589	}
ganlikun	0:13413ea9a877	2590	ITM->PORT[0U].u8 = (uint8_t)ch;
ganlikun	0:13413ea9a877	2591	}
ganlikun	0:13413ea9a877	2592	return (ch);
ganlikun	0:13413ea9a877	2593	}
ganlikun	0:13413ea9a877	2594
ganlikun	0:13413ea9a877	2595
ganlikun	0:13413ea9a877	2596	/**
ganlikun	0:13413ea9a877	2597	\brief ITM Receive Character
ganlikun	0:13413ea9a877	2598	\details Inputs a character via the external variable \ref ITM_RxBuffer.
ganlikun	0:13413ea9a877	2599	\return Received character.
ganlikun	0:13413ea9a877	2600	\return -1 No character pending.
ganlikun	0:13413ea9a877	2601	*/
ganlikun	0:13413ea9a877	2602	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
ganlikun	0:13413ea9a877	2603	{
ganlikun	0:13413ea9a877	2604	int32_t ch = -1; /* no character available */
ganlikun	0:13413ea9a877	2605
ganlikun	0:13413ea9a877	2606	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
ganlikun	0:13413ea9a877	2607	{
ganlikun	0:13413ea9a877	2608	ch = ITM_RxBuffer;
ganlikun	0:13413ea9a877	2609	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
ganlikun	0:13413ea9a877	2610	}
ganlikun	0:13413ea9a877	2611
ganlikun	0:13413ea9a877	2612	return (ch);
ganlikun	0:13413ea9a877	2613	}
ganlikun	0:13413ea9a877	2614
ganlikun	0:13413ea9a877	2615
ganlikun	0:13413ea9a877	2616	/**
ganlikun	0:13413ea9a877	2617	\brief ITM Check Character
ganlikun	0:13413ea9a877	2618	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
ganlikun	0:13413ea9a877	2619	\return 0 No character available.
ganlikun	0:13413ea9a877	2620	\return 1 Character available.
ganlikun	0:13413ea9a877	2621	*/
ganlikun	0:13413ea9a877	2622	__STATIC_INLINE int32_t ITM_CheckChar (void)
ganlikun	0:13413ea9a877	2623	{
ganlikun	0:13413ea9a877	2624
ganlikun	0:13413ea9a877	2625	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
ganlikun	0:13413ea9a877	2626	{
ganlikun	0:13413ea9a877	2627	return (0); /* no character available */
ganlikun	0:13413ea9a877	2628	}
ganlikun	0:13413ea9a877	2629	else
ganlikun	0:13413ea9a877	2630	{
ganlikun	0:13413ea9a877	2631	return (1); /* character available */
ganlikun	0:13413ea9a877	2632	}
ganlikun	0:13413ea9a877	2633	}
ganlikun	0:13413ea9a877	2634
ganlikun	0:13413ea9a877	2635	/@} end of CMSIS_core_DebugFunctions /
ganlikun	0:13413ea9a877	2636
ganlikun	0:13413ea9a877	2637
ganlikun	0:13413ea9a877	2638
ganlikun	0:13413ea9a877	2639
ganlikun	0:13413ea9a877	2640	#ifdef __cplusplus
ganlikun	0:13413ea9a877	2641	}
ganlikun	0:13413ea9a877	2642	#endif
ganlikun	0:13413ea9a877	2643
ganlikun	0:13413ea9a877	2644	#endif /* __CORE_CM7_H_DEPENDANT */
ganlikun	0:13413ea9a877	2645
ganlikun	0:13413ea9a877	2646	#endif /* __CMSIS_GENERIC */
ganlikun	0:13413ea9a877	2647
ganlikun	0:13413ea9a877	2648

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Type:	Library
Created:	12 Jun 2022
Imports:	2
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

cmsis/core_cm7.h@0:13413ea9a877, 2022-06-12 (annotated)

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