Gan likun / mbed-dev

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cmsis/core_cm3.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

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ganlikun 0:13413ea9a877 1 /**************************************************************************//**
ganlikun 0:13413ea9a877 2 * @file core_cm3.h
ganlikun 0:13413ea9a877 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
ganlikun 0:13413ea9a877 4 * @version V5.0.2
ganlikun 0:13413ea9a877 5 * @date 13. February 2017
ganlikun 0:13413ea9a877 6 ******************************************************************************/
ganlikun 0:13413ea9a877 7 /*
ganlikun 0:13413ea9a877 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
ganlikun 0:13413ea9a877 9 *
ganlikun 0:13413ea9a877 10 * SPDX-License-Identifier: Apache-2.0
ganlikun 0:13413ea9a877 11 *
ganlikun 0:13413ea9a877 12 * Licensed under the Apache License, Version 2.0 (the License); you may
ganlikun 0:13413ea9a877 13 * not use this file except in compliance with the License.
ganlikun 0:13413ea9a877 14 * You may obtain a copy of the License at
ganlikun 0:13413ea9a877 15 *
ganlikun 0:13413ea9a877 16 * www.apache.org/licenses/LICENSE-2.0
ganlikun 0:13413ea9a877 17 *
ganlikun 0:13413ea9a877 18 * Unless required by applicable law or agreed to in writing, software
ganlikun 0:13413ea9a877 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ganlikun 0:13413ea9a877 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ganlikun 0:13413ea9a877 21 * See the License for the specific language governing permissions and
ganlikun 0:13413ea9a877 22 * limitations under the License.
ganlikun 0:13413ea9a877 23 */
ganlikun 0:13413ea9a877 24
ganlikun 0:13413ea9a877 25 #if defined ( __ICCARM__ )
ganlikun 0:13413ea9a877 26 #pragma system_include /* treat file as system include file for MISRA check */
ganlikun 0:13413ea9a877 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:13413ea9a877 28 #pragma clang system_header /* treat file as system include file */
ganlikun 0:13413ea9a877 29 #endif
ganlikun 0:13413ea9a877 30
ganlikun 0:13413ea9a877 31 #ifndef __CORE_CM3_H_GENERIC
ganlikun 0:13413ea9a877 32 #define __CORE_CM3_H_GENERIC
ganlikun 0:13413ea9a877 33
ganlikun 0:13413ea9a877 34 #include <stdint.h>
ganlikun 0:13413ea9a877 35
ganlikun 0:13413ea9a877 36 #ifdef __cplusplus
ganlikun 0:13413ea9a877 37 extern "C" {
ganlikun 0:13413ea9a877 38 #endif
ganlikun 0:13413ea9a877 39
ganlikun 0:13413ea9a877 40 /**
ganlikun 0:13413ea9a877 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
ganlikun 0:13413ea9a877 42 CMSIS violates the following MISRA-C:2004 rules:
ganlikun 0:13413ea9a877 43
ganlikun 0:13413ea9a877 44 \li Required Rule 8.5, object/function definition in header file.<br>
ganlikun 0:13413ea9a877 45 Function definitions in header files are used to allow 'inlining'.
ganlikun 0:13413ea9a877 46
ganlikun 0:13413ea9a877 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
ganlikun 0:13413ea9a877 48 Unions are used for effective representation of core registers.
ganlikun 0:13413ea9a877 49
ganlikun 0:13413ea9a877 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
ganlikun 0:13413ea9a877 51 Function-like macros are used to allow more efficient code.
ganlikun 0:13413ea9a877 52 */
ganlikun 0:13413ea9a877 53
ganlikun 0:13413ea9a877 54
ganlikun 0:13413ea9a877 55 /*******************************************************************************
ganlikun 0:13413ea9a877 56 * CMSIS definitions
ganlikun 0:13413ea9a877 57 ******************************************************************************/
ganlikun 0:13413ea9a877 58 /**
ganlikun 0:13413ea9a877 59 \ingroup Cortex_M3
ganlikun 0:13413ea9a877 60 @{
ganlikun 0:13413ea9a877 61 */
ganlikun 0:13413ea9a877 62
ganlikun 0:13413ea9a877 63 /* CMSIS CM3 definitions */
ganlikun 0:13413ea9a877 64 #define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
ganlikun 0:13413ea9a877 65 #define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
ganlikun 0:13413ea9a877 66 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
ganlikun 0:13413ea9a877 67 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
ganlikun 0:13413ea9a877 68
ganlikun 0:13413ea9a877 69 #define __CORTEX_M (3U) /*!< Cortex-M Core */
ganlikun 0:13413ea9a877 70
ganlikun 0:13413ea9a877 71 /** __FPU_USED indicates whether an FPU is used or not.
ganlikun 0:13413ea9a877 72 This core does not support an FPU at all
ganlikun 0:13413ea9a877 73 */
ganlikun 0:13413ea9a877 74 #define __FPU_USED 0U
ganlikun 0:13413ea9a877 75
ganlikun 0:13413ea9a877 76 #if defined ( __CC_ARM )
ganlikun 0:13413ea9a877 77 #if defined __TARGET_FPU_VFP
ganlikun 0:13413ea9a877 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 79 #endif
ganlikun 0:13413ea9a877 80
ganlikun 0:13413ea9a877 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:13413ea9a877 82 #if defined __ARM_PCS_VFP
ganlikun 0:13413ea9a877 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 84 #endif
ganlikun 0:13413ea9a877 85
ganlikun 0:13413ea9a877 86 #elif defined ( __GNUC__ )
ganlikun 0:13413ea9a877 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
ganlikun 0:13413ea9a877 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 89 #endif
ganlikun 0:13413ea9a877 90
ganlikun 0:13413ea9a877 91 #elif defined ( __ICCARM__ )
ganlikun 0:13413ea9a877 92 #if defined __ARMVFP__
ganlikun 0:13413ea9a877 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 94 #endif
ganlikun 0:13413ea9a877 95
ganlikun 0:13413ea9a877 96 #elif defined ( __TI_ARM__ )
ganlikun 0:13413ea9a877 97 #if defined __TI_VFP_SUPPORT__
ganlikun 0:13413ea9a877 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 99 #endif
ganlikun 0:13413ea9a877 100
ganlikun 0:13413ea9a877 101 #elif defined ( __TASKING__ )
ganlikun 0:13413ea9a877 102 #if defined __FPU_VFP__
ganlikun 0:13413ea9a877 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 104 #endif
ganlikun 0:13413ea9a877 105
ganlikun 0:13413ea9a877 106 #elif defined ( __CSMC__ )
ganlikun 0:13413ea9a877 107 #if ( __CSMC__ & 0x400U)
ganlikun 0:13413ea9a877 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 109 #endif
ganlikun 0:13413ea9a877 110
ganlikun 0:13413ea9a877 111 #endif
ganlikun 0:13413ea9a877 112
ganlikun 0:13413ea9a877 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
ganlikun 0:13413ea9a877 114
ganlikun 0:13413ea9a877 115
ganlikun 0:13413ea9a877 116 #ifdef __cplusplus
ganlikun 0:13413ea9a877 117 }
ganlikun 0:13413ea9a877 118 #endif
ganlikun 0:13413ea9a877 119
ganlikun 0:13413ea9a877 120 #endif /* __CORE_CM3_H_GENERIC */
ganlikun 0:13413ea9a877 121
ganlikun 0:13413ea9a877 122 #ifndef __CMSIS_GENERIC
ganlikun 0:13413ea9a877 123
ganlikun 0:13413ea9a877 124 #ifndef __CORE_CM3_H_DEPENDANT
ganlikun 0:13413ea9a877 125 #define __CORE_CM3_H_DEPENDANT
ganlikun 0:13413ea9a877 126
ganlikun 0:13413ea9a877 127 #ifdef __cplusplus
ganlikun 0:13413ea9a877 128 extern "C" {
ganlikun 0:13413ea9a877 129 #endif
ganlikun 0:13413ea9a877 130
ganlikun 0:13413ea9a877 131 /* check device defines and use defaults */
ganlikun 0:13413ea9a877 132 #if defined __CHECK_DEVICE_DEFINES
ganlikun 0:13413ea9a877 133 #ifndef __CM3_REV
ganlikun 0:13413ea9a877 134 #define __CM3_REV 0x0200U
ganlikun 0:13413ea9a877 135 #warning "__CM3_REV not defined in device header file; using default!"
ganlikun 0:13413ea9a877 136 #endif
ganlikun 0:13413ea9a877 137
ganlikun 0:13413ea9a877 138 #ifndef __MPU_PRESENT
ganlikun 0:13413ea9a877 139 #define __MPU_PRESENT 0U
ganlikun 0:13413ea9a877 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
ganlikun 0:13413ea9a877 141 #endif
ganlikun 0:13413ea9a877 142
ganlikun 0:13413ea9a877 143 #ifndef __NVIC_PRIO_BITS
ganlikun 0:13413ea9a877 144 #define __NVIC_PRIO_BITS 3U
ganlikun 0:13413ea9a877 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
ganlikun 0:13413ea9a877 146 #endif
ganlikun 0:13413ea9a877 147
ganlikun 0:13413ea9a877 148 #ifndef __Vendor_SysTickConfig
ganlikun 0:13413ea9a877 149 #define __Vendor_SysTickConfig 0U
ganlikun 0:13413ea9a877 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
ganlikun 0:13413ea9a877 151 #endif
ganlikun 0:13413ea9a877 152 #endif
ganlikun 0:13413ea9a877 153
ganlikun 0:13413ea9a877 154 /* IO definitions (access restrictions to peripheral registers) */
ganlikun 0:13413ea9a877 155 /**
ganlikun 0:13413ea9a877 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
ganlikun 0:13413ea9a877 157
ganlikun 0:13413ea9a877 158 <strong>IO Type Qualifiers</strong> are used
ganlikun 0:13413ea9a877 159 \li to specify the access to peripheral variables.
ganlikun 0:13413ea9a877 160 \li for automatic generation of peripheral register debug information.
ganlikun 0:13413ea9a877 161 */
ganlikun 0:13413ea9a877 162 #ifdef __cplusplus
ganlikun 0:13413ea9a877 163 #define __I volatile /*!< Defines 'read only' permissions */
ganlikun 0:13413ea9a877 164 #else
ganlikun 0:13413ea9a877 165 #define __I volatile const /*!< Defines 'read only' permissions */
ganlikun 0:13413ea9a877 166 #endif
ganlikun 0:13413ea9a877 167 #define __O volatile /*!< Defines 'write only' permissions */
ganlikun 0:13413ea9a877 168 #define __IO volatile /*!< Defines 'read / write' permissions */
ganlikun 0:13413ea9a877 169
ganlikun 0:13413ea9a877 170 /* following defines should be used for structure members */
ganlikun 0:13413ea9a877 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
ganlikun 0:13413ea9a877 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
ganlikun 0:13413ea9a877 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
ganlikun 0:13413ea9a877 174
ganlikun 0:13413ea9a877 175 /*@} end of group Cortex_M3 */
ganlikun 0:13413ea9a877 176
ganlikun 0:13413ea9a877 177
ganlikun 0:13413ea9a877 178
ganlikun 0:13413ea9a877 179 /*******************************************************************************
ganlikun 0:13413ea9a877 180 * Register Abstraction
ganlikun 0:13413ea9a877 181 Core Register contain:
ganlikun 0:13413ea9a877 182 - Core Register
ganlikun 0:13413ea9a877 183 - Core NVIC Register
ganlikun 0:13413ea9a877 184 - Core SCB Register
ganlikun 0:13413ea9a877 185 - Core SysTick Register
ganlikun 0:13413ea9a877 186 - Core Debug Register
ganlikun 0:13413ea9a877 187 - Core MPU Register
ganlikun 0:13413ea9a877 188 ******************************************************************************/
ganlikun 0:13413ea9a877 189 /**
ganlikun 0:13413ea9a877 190 \defgroup CMSIS_core_register Defines and Type Definitions
ganlikun 0:13413ea9a877 191 \brief Type definitions and defines for Cortex-M processor based devices.
ganlikun 0:13413ea9a877 192 */
ganlikun 0:13413ea9a877 193
ganlikun 0:13413ea9a877 194 /**
ganlikun 0:13413ea9a877 195 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 196 \defgroup CMSIS_CORE Status and Control Registers
ganlikun 0:13413ea9a877 197 \brief Core Register type definitions.
ganlikun 0:13413ea9a877 198 @{
ganlikun 0:13413ea9a877 199 */
ganlikun 0:13413ea9a877 200
ganlikun 0:13413ea9a877 201 /**
ganlikun 0:13413ea9a877 202 \brief Union type to access the Application Program Status Register (APSR).
ganlikun 0:13413ea9a877 203 */
ganlikun 0:13413ea9a877 204 typedef union
ganlikun 0:13413ea9a877 205 {
ganlikun 0:13413ea9a877 206 struct
ganlikun 0:13413ea9a877 207 {
ganlikun 0:13413ea9a877 208 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
ganlikun 0:13413ea9a877 209 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
ganlikun 0:13413ea9a877 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:13413ea9a877 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:13413ea9a877 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:13413ea9a877 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:13413ea9a877 214 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 215 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 216 } APSR_Type;
ganlikun 0:13413ea9a877 217
ganlikun 0:13413ea9a877 218 /* APSR Register Definitions */
ganlikun 0:13413ea9a877 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
ganlikun 0:13413ea9a877 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
ganlikun 0:13413ea9a877 221
ganlikun 0:13413ea9a877 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
ganlikun 0:13413ea9a877 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
ganlikun 0:13413ea9a877 224
ganlikun 0:13413ea9a877 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
ganlikun 0:13413ea9a877 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
ganlikun 0:13413ea9a877 227
ganlikun 0:13413ea9a877 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
ganlikun 0:13413ea9a877 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
ganlikun 0:13413ea9a877 230
ganlikun 0:13413ea9a877 231 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
ganlikun 0:13413ea9a877 232 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
ganlikun 0:13413ea9a877 233
ganlikun 0:13413ea9a877 234
ganlikun 0:13413ea9a877 235 /**
ganlikun 0:13413ea9a877 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
ganlikun 0:13413ea9a877 237 */
ganlikun 0:13413ea9a877 238 typedef union
ganlikun 0:13413ea9a877 239 {
ganlikun 0:13413ea9a877 240 struct
ganlikun 0:13413ea9a877 241 {
ganlikun 0:13413ea9a877 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:13413ea9a877 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
ganlikun 0:13413ea9a877 244 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 245 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 246 } IPSR_Type;
ganlikun 0:13413ea9a877 247
ganlikun 0:13413ea9a877 248 /* IPSR Register Definitions */
ganlikun 0:13413ea9a877 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
ganlikun 0:13413ea9a877 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
ganlikun 0:13413ea9a877 251
ganlikun 0:13413ea9a877 252
ganlikun 0:13413ea9a877 253 /**
ganlikun 0:13413ea9a877 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ganlikun 0:13413ea9a877 255 */
ganlikun 0:13413ea9a877 256 typedef union
ganlikun 0:13413ea9a877 257 {
ganlikun 0:13413ea9a877 258 struct
ganlikun 0:13413ea9a877 259 {
ganlikun 0:13413ea9a877 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:13413ea9a877 261 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
ganlikun 0:13413ea9a877 262 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
ganlikun 0:13413ea9a877 263 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
ganlikun 0:13413ea9a877 264 uint32_t T:1; /*!< bit: 24 Thumb bit */
ganlikun 0:13413ea9a877 265 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
ganlikun 0:13413ea9a877 266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
ganlikun 0:13413ea9a877 267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:13413ea9a877 268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:13413ea9a877 269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:13413ea9a877 270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:13413ea9a877 271 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 272 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 273 } xPSR_Type;
ganlikun 0:13413ea9a877 274
ganlikun 0:13413ea9a877 275 /* xPSR Register Definitions */
ganlikun 0:13413ea9a877 276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
ganlikun 0:13413ea9a877 277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
ganlikun 0:13413ea9a877 278
ganlikun 0:13413ea9a877 279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
ganlikun 0:13413ea9a877 280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
ganlikun 0:13413ea9a877 281
ganlikun 0:13413ea9a877 282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
ganlikun 0:13413ea9a877 283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
ganlikun 0:13413ea9a877 284
ganlikun 0:13413ea9a877 285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
ganlikun 0:13413ea9a877 286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
ganlikun 0:13413ea9a877 287
ganlikun 0:13413ea9a877 288 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
ganlikun 0:13413ea9a877 289 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
ganlikun 0:13413ea9a877 290
ganlikun 0:13413ea9a877 291 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
ganlikun 0:13413ea9a877 292 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
ganlikun 0:13413ea9a877 293
ganlikun 0:13413ea9a877 294 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
ganlikun 0:13413ea9a877 295 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
ganlikun 0:13413ea9a877 296
ganlikun 0:13413ea9a877 297 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
ganlikun 0:13413ea9a877 298 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
ganlikun 0:13413ea9a877 299
ganlikun 0:13413ea9a877 300 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
ganlikun 0:13413ea9a877 301 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
ganlikun 0:13413ea9a877 302
ganlikun 0:13413ea9a877 303
ganlikun 0:13413ea9a877 304 /**
ganlikun 0:13413ea9a877 305 \brief Union type to access the Control Registers (CONTROL).
ganlikun 0:13413ea9a877 306 */
ganlikun 0:13413ea9a877 307 typedef union
ganlikun 0:13413ea9a877 308 {
ganlikun 0:13413ea9a877 309 struct
ganlikun 0:13413ea9a877 310 {
ganlikun 0:13413ea9a877 311 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
ganlikun 0:13413ea9a877 312 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
ganlikun 0:13413ea9a877 313 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
ganlikun 0:13413ea9a877 314 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 315 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 316 } CONTROL_Type;
ganlikun 0:13413ea9a877 317
ganlikun 0:13413ea9a877 318 /* CONTROL Register Definitions */
ganlikun 0:13413ea9a877 319 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
ganlikun 0:13413ea9a877 320 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
ganlikun 0:13413ea9a877 321
ganlikun 0:13413ea9a877 322 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
ganlikun 0:13413ea9a877 323 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
ganlikun 0:13413ea9a877 324
ganlikun 0:13413ea9a877 325 /*@} end of group CMSIS_CORE */
ganlikun 0:13413ea9a877 326
ganlikun 0:13413ea9a877 327
ganlikun 0:13413ea9a877 328 /**
ganlikun 0:13413ea9a877 329 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 330 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
ganlikun 0:13413ea9a877 331 \brief Type definitions for the NVIC Registers
ganlikun 0:13413ea9a877 332 @{
ganlikun 0:13413ea9a877 333 */
ganlikun 0:13413ea9a877 334
ganlikun 0:13413ea9a877 335 /**
ganlikun 0:13413ea9a877 336 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
ganlikun 0:13413ea9a877 337 */
ganlikun 0:13413ea9a877 338 typedef struct
ganlikun 0:13413ea9a877 339 {
ganlikun 0:13413ea9a877 340 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
ganlikun 0:13413ea9a877 341 uint32_t RESERVED0[24U];
ganlikun 0:13413ea9a877 342 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
ganlikun 0:13413ea9a877 343 uint32_t RSERVED1[24U];
ganlikun 0:13413ea9a877 344 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
ganlikun 0:13413ea9a877 345 uint32_t RESERVED2[24U];
ganlikun 0:13413ea9a877 346 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
ganlikun 0:13413ea9a877 347 uint32_t RESERVED3[24U];
ganlikun 0:13413ea9a877 348 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
ganlikun 0:13413ea9a877 349 uint32_t RESERVED4[56U];
ganlikun 0:13413ea9a877 350 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
ganlikun 0:13413ea9a877 351 uint32_t RESERVED5[644U];
ganlikun 0:13413ea9a877 352 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
ganlikun 0:13413ea9a877 353 } NVIC_Type;
ganlikun 0:13413ea9a877 354
ganlikun 0:13413ea9a877 355 /* Software Triggered Interrupt Register Definitions */
ganlikun 0:13413ea9a877 356 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
ganlikun 0:13413ea9a877 357 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
ganlikun 0:13413ea9a877 358
ganlikun 0:13413ea9a877 359 /*@} end of group CMSIS_NVIC */
ganlikun 0:13413ea9a877 360
ganlikun 0:13413ea9a877 361
ganlikun 0:13413ea9a877 362 /**
ganlikun 0:13413ea9a877 363 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 364 \defgroup CMSIS_SCB System Control Block (SCB)
ganlikun 0:13413ea9a877 365 \brief Type definitions for the System Control Block Registers
ganlikun 0:13413ea9a877 366 @{
ganlikun 0:13413ea9a877 367 */
ganlikun 0:13413ea9a877 368
ganlikun 0:13413ea9a877 369 /**
ganlikun 0:13413ea9a877 370 \brief Structure type to access the System Control Block (SCB).
ganlikun 0:13413ea9a877 371 */
ganlikun 0:13413ea9a877 372 typedef struct
ganlikun 0:13413ea9a877 373 {
ganlikun 0:13413ea9a877 374 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
ganlikun 0:13413ea9a877 375 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
ganlikun 0:13413ea9a877 376 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
ganlikun 0:13413ea9a877 377 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
ganlikun 0:13413ea9a877 378 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
ganlikun 0:13413ea9a877 379 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
ganlikun 0:13413ea9a877 380 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
ganlikun 0:13413ea9a877 381 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
ganlikun 0:13413ea9a877 382 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
ganlikun 0:13413ea9a877 383 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
ganlikun 0:13413ea9a877 384 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
ganlikun 0:13413ea9a877 385 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
ganlikun 0:13413ea9a877 386 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
ganlikun 0:13413ea9a877 387 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
ganlikun 0:13413ea9a877 388 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
ganlikun 0:13413ea9a877 389 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
ganlikun 0:13413ea9a877 390 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
ganlikun 0:13413ea9a877 391 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
ganlikun 0:13413ea9a877 392 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
ganlikun 0:13413ea9a877 393 uint32_t RESERVED0[5U];
ganlikun 0:13413ea9a877 394 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
ganlikun 0:13413ea9a877 395 } SCB_Type;
ganlikun 0:13413ea9a877 396
ganlikun 0:13413ea9a877 397 /* SCB CPUID Register Definitions */
ganlikun 0:13413ea9a877 398 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
ganlikun 0:13413ea9a877 399 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
ganlikun 0:13413ea9a877 400
ganlikun 0:13413ea9a877 401 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
ganlikun 0:13413ea9a877 402 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
ganlikun 0:13413ea9a877 403
ganlikun 0:13413ea9a877 404 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
ganlikun 0:13413ea9a877 405 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
ganlikun 0:13413ea9a877 406
ganlikun 0:13413ea9a877 407 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
ganlikun 0:13413ea9a877 408 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
ganlikun 0:13413ea9a877 409
ganlikun 0:13413ea9a877 410 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
ganlikun 0:13413ea9a877 411 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
ganlikun 0:13413ea9a877 412
ganlikun 0:13413ea9a877 413 /* SCB Interrupt Control State Register Definitions */
ganlikun 0:13413ea9a877 414 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
ganlikun 0:13413ea9a877 415 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
ganlikun 0:13413ea9a877 416
ganlikun 0:13413ea9a877 417 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
ganlikun 0:13413ea9a877 418 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
ganlikun 0:13413ea9a877 419
ganlikun 0:13413ea9a877 420 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
ganlikun 0:13413ea9a877 421 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
ganlikun 0:13413ea9a877 422
ganlikun 0:13413ea9a877 423 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
ganlikun 0:13413ea9a877 424 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
ganlikun 0:13413ea9a877 425
ganlikun 0:13413ea9a877 426 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
ganlikun 0:13413ea9a877 427 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
ganlikun 0:13413ea9a877 428
ganlikun 0:13413ea9a877 429 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
ganlikun 0:13413ea9a877 430 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
ganlikun 0:13413ea9a877 431
ganlikun 0:13413ea9a877 432 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
ganlikun 0:13413ea9a877 433 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
ganlikun 0:13413ea9a877 434
ganlikun 0:13413ea9a877 435 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
ganlikun 0:13413ea9a877 436 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
ganlikun 0:13413ea9a877 437
ganlikun 0:13413ea9a877 438 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
ganlikun 0:13413ea9a877 439 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
ganlikun 0:13413ea9a877 440
ganlikun 0:13413ea9a877 441 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
ganlikun 0:13413ea9a877 442 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
ganlikun 0:13413ea9a877 443
ganlikun 0:13413ea9a877 444 /* SCB Vector Table Offset Register Definitions */
ganlikun 0:13413ea9a877 445 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
ganlikun 0:13413ea9a877 446 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
ganlikun 0:13413ea9a877 447 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
ganlikun 0:13413ea9a877 448
ganlikun 0:13413ea9a877 449 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
ganlikun 0:13413ea9a877 450 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
ganlikun 0:13413ea9a877 451 #else
ganlikun 0:13413ea9a877 452 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
ganlikun 0:13413ea9a877 453 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
ganlikun 0:13413ea9a877 454 #endif
ganlikun 0:13413ea9a877 455
ganlikun 0:13413ea9a877 456 /* SCB Application Interrupt and Reset Control Register Definitions */
ganlikun 0:13413ea9a877 457 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
ganlikun 0:13413ea9a877 458 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
ganlikun 0:13413ea9a877 459
ganlikun 0:13413ea9a877 460 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
ganlikun 0:13413ea9a877 461 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
ganlikun 0:13413ea9a877 462
ganlikun 0:13413ea9a877 463 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
ganlikun 0:13413ea9a877 464 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
ganlikun 0:13413ea9a877 465
ganlikun 0:13413ea9a877 466 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
ganlikun 0:13413ea9a877 467 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
ganlikun 0:13413ea9a877 468
ganlikun 0:13413ea9a877 469 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
ganlikun 0:13413ea9a877 470 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
ganlikun 0:13413ea9a877 471
ganlikun 0:13413ea9a877 472 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
ganlikun 0:13413ea9a877 473 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
ganlikun 0:13413ea9a877 474
ganlikun 0:13413ea9a877 475 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
ganlikun 0:13413ea9a877 476 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
ganlikun 0:13413ea9a877 477
ganlikun 0:13413ea9a877 478 /* SCB System Control Register Definitions */
ganlikun 0:13413ea9a877 479 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
ganlikun 0:13413ea9a877 480 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
ganlikun 0:13413ea9a877 481
ganlikun 0:13413ea9a877 482 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
ganlikun 0:13413ea9a877 483 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
ganlikun 0:13413ea9a877 484
ganlikun 0:13413ea9a877 485 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
ganlikun 0:13413ea9a877 486 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
ganlikun 0:13413ea9a877 487
ganlikun 0:13413ea9a877 488 /* SCB Configuration Control Register Definitions */
ganlikun 0:13413ea9a877 489 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
ganlikun 0:13413ea9a877 490 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
ganlikun 0:13413ea9a877 491
ganlikun 0:13413ea9a877 492 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
ganlikun 0:13413ea9a877 493 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
ganlikun 0:13413ea9a877 494
ganlikun 0:13413ea9a877 495 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
ganlikun 0:13413ea9a877 496 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
ganlikun 0:13413ea9a877 497
ganlikun 0:13413ea9a877 498 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
ganlikun 0:13413ea9a877 499 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
ganlikun 0:13413ea9a877 500
ganlikun 0:13413ea9a877 501 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
ganlikun 0:13413ea9a877 502 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
ganlikun 0:13413ea9a877 503
ganlikun 0:13413ea9a877 504 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
ganlikun 0:13413ea9a877 505 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
ganlikun 0:13413ea9a877 506
ganlikun 0:13413ea9a877 507 /* SCB System Handler Control and State Register Definitions */
ganlikun 0:13413ea9a877 508 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
ganlikun 0:13413ea9a877 509 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
ganlikun 0:13413ea9a877 510
ganlikun 0:13413ea9a877 511 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
ganlikun 0:13413ea9a877 512 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
ganlikun 0:13413ea9a877 513
ganlikun 0:13413ea9a877 514 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
ganlikun 0:13413ea9a877 515 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
ganlikun 0:13413ea9a877 516
ganlikun 0:13413ea9a877 517 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
ganlikun 0:13413ea9a877 518 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
ganlikun 0:13413ea9a877 519
ganlikun 0:13413ea9a877 520 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
ganlikun 0:13413ea9a877 521 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
ganlikun 0:13413ea9a877 522
ganlikun 0:13413ea9a877 523 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
ganlikun 0:13413ea9a877 524 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
ganlikun 0:13413ea9a877 525
ganlikun 0:13413ea9a877 526 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
ganlikun 0:13413ea9a877 527 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
ganlikun 0:13413ea9a877 528
ganlikun 0:13413ea9a877 529 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
ganlikun 0:13413ea9a877 530 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
ganlikun 0:13413ea9a877 531
ganlikun 0:13413ea9a877 532 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
ganlikun 0:13413ea9a877 533 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
ganlikun 0:13413ea9a877 534
ganlikun 0:13413ea9a877 535 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
ganlikun 0:13413ea9a877 536 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
ganlikun 0:13413ea9a877 537
ganlikun 0:13413ea9a877 538 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
ganlikun 0:13413ea9a877 539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
ganlikun 0:13413ea9a877 540
ganlikun 0:13413ea9a877 541 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
ganlikun 0:13413ea9a877 542 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
ganlikun 0:13413ea9a877 543
ganlikun 0:13413ea9a877 544 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
ganlikun 0:13413ea9a877 545 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
ganlikun 0:13413ea9a877 546
ganlikun 0:13413ea9a877 547 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
ganlikun 0:13413ea9a877 548 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
ganlikun 0:13413ea9a877 549
ganlikun 0:13413ea9a877 550 /* SCB Configurable Fault Status Register Definitions */
ganlikun 0:13413ea9a877 551 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
ganlikun 0:13413ea9a877 552 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
ganlikun 0:13413ea9a877 553
ganlikun 0:13413ea9a877 554 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
ganlikun 0:13413ea9a877 555 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
ganlikun 0:13413ea9a877 556
ganlikun 0:13413ea9a877 557 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
ganlikun 0:13413ea9a877 558 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
ganlikun 0:13413ea9a877 559
ganlikun 0:13413ea9a877 560 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
ganlikun 0:13413ea9a877 561 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
ganlikun 0:13413ea9a877 562 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
ganlikun 0:13413ea9a877 563
ganlikun 0:13413ea9a877 564 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
ganlikun 0:13413ea9a877 565 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
ganlikun 0:13413ea9a877 566
ganlikun 0:13413ea9a877 567 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
ganlikun 0:13413ea9a877 568 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
ganlikun 0:13413ea9a877 569
ganlikun 0:13413ea9a877 570 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
ganlikun 0:13413ea9a877 571 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
ganlikun 0:13413ea9a877 572
ganlikun 0:13413ea9a877 573 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
ganlikun 0:13413ea9a877 574 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
ganlikun 0:13413ea9a877 575
ganlikun 0:13413ea9a877 576 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
ganlikun 0:13413ea9a877 577 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
ganlikun 0:13413ea9a877 578 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
ganlikun 0:13413ea9a877 579
ganlikun 0:13413ea9a877 580 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
ganlikun 0:13413ea9a877 581 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
ganlikun 0:13413ea9a877 582
ganlikun 0:13413ea9a877 583 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
ganlikun 0:13413ea9a877 584 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
ganlikun 0:13413ea9a877 585
ganlikun 0:13413ea9a877 586 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
ganlikun 0:13413ea9a877 587 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
ganlikun 0:13413ea9a877 588
ganlikun 0:13413ea9a877 589 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
ganlikun 0:13413ea9a877 590 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
ganlikun 0:13413ea9a877 591
ganlikun 0:13413ea9a877 592 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
ganlikun 0:13413ea9a877 593 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
ganlikun 0:13413ea9a877 594
ganlikun 0:13413ea9a877 595 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
ganlikun 0:13413ea9a877 596 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
ganlikun 0:13413ea9a877 597 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
ganlikun 0:13413ea9a877 598
ganlikun 0:13413ea9a877 599 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
ganlikun 0:13413ea9a877 600 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
ganlikun 0:13413ea9a877 601
ganlikun 0:13413ea9a877 602 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
ganlikun 0:13413ea9a877 603 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
ganlikun 0:13413ea9a877 604
ganlikun 0:13413ea9a877 605 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
ganlikun 0:13413ea9a877 606 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
ganlikun 0:13413ea9a877 607
ganlikun 0:13413ea9a877 608 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
ganlikun 0:13413ea9a877 609 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
ganlikun 0:13413ea9a877 610
ganlikun 0:13413ea9a877 611 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
ganlikun 0:13413ea9a877 612 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
ganlikun 0:13413ea9a877 613
ganlikun 0:13413ea9a877 614 /* SCB Hard Fault Status Register Definitions */
ganlikun 0:13413ea9a877 615 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
ganlikun 0:13413ea9a877 616 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
ganlikun 0:13413ea9a877 617
ganlikun 0:13413ea9a877 618 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
ganlikun 0:13413ea9a877 619 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
ganlikun 0:13413ea9a877 620
ganlikun 0:13413ea9a877 621 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
ganlikun 0:13413ea9a877 622 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
ganlikun 0:13413ea9a877 623
ganlikun 0:13413ea9a877 624 /* SCB Debug Fault Status Register Definitions */
ganlikun 0:13413ea9a877 625 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
ganlikun 0:13413ea9a877 626 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
ganlikun 0:13413ea9a877 627
ganlikun 0:13413ea9a877 628 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
ganlikun 0:13413ea9a877 629 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
ganlikun 0:13413ea9a877 630
ganlikun 0:13413ea9a877 631 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
ganlikun 0:13413ea9a877 632 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
ganlikun 0:13413ea9a877 633
ganlikun 0:13413ea9a877 634 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
ganlikun 0:13413ea9a877 635 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
ganlikun 0:13413ea9a877 636
ganlikun 0:13413ea9a877 637 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
ganlikun 0:13413ea9a877 638 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
ganlikun 0:13413ea9a877 639
ganlikun 0:13413ea9a877 640 /*@} end of group CMSIS_SCB */
ganlikun 0:13413ea9a877 641
ganlikun 0:13413ea9a877 642
ganlikun 0:13413ea9a877 643 /**
ganlikun 0:13413ea9a877 644 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 645 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
ganlikun 0:13413ea9a877 646 \brief Type definitions for the System Control and ID Register not in the SCB
ganlikun 0:13413ea9a877 647 @{
ganlikun 0:13413ea9a877 648 */
ganlikun 0:13413ea9a877 649
ganlikun 0:13413ea9a877 650 /**
ganlikun 0:13413ea9a877 651 \brief Structure type to access the System Control and ID Register not in the SCB.
ganlikun 0:13413ea9a877 652 */
ganlikun 0:13413ea9a877 653 typedef struct
ganlikun 0:13413ea9a877 654 {
ganlikun 0:13413ea9a877 655 uint32_t RESERVED0[1U];
ganlikun 0:13413ea9a877 656 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
ganlikun 0:13413ea9a877 657 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
ganlikun 0:13413ea9a877 658 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
ganlikun 0:13413ea9a877 659 #else
ganlikun 0:13413ea9a877 660 uint32_t RESERVED1[1U];
ganlikun 0:13413ea9a877 661 #endif
ganlikun 0:13413ea9a877 662 } SCnSCB_Type;
ganlikun 0:13413ea9a877 663
ganlikun 0:13413ea9a877 664 /* Interrupt Controller Type Register Definitions */
ganlikun 0:13413ea9a877 665 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
ganlikun 0:13413ea9a877 666 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
ganlikun 0:13413ea9a877 667
ganlikun 0:13413ea9a877 668 /* Auxiliary Control Register Definitions */
ganlikun 0:13413ea9a877 669
ganlikun 0:13413ea9a877 670 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
ganlikun 0:13413ea9a877 671 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
ganlikun 0:13413ea9a877 672
ganlikun 0:13413ea9a877 673 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
ganlikun 0:13413ea9a877 674 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
ganlikun 0:13413ea9a877 675
ganlikun 0:13413ea9a877 676 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
ganlikun 0:13413ea9a877 677 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
ganlikun 0:13413ea9a877 678
ganlikun 0:13413ea9a877 679 /*@} end of group CMSIS_SCnotSCB */
ganlikun 0:13413ea9a877 680
ganlikun 0:13413ea9a877 681
ganlikun 0:13413ea9a877 682 /**
ganlikun 0:13413ea9a877 683 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 684 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
ganlikun 0:13413ea9a877 685 \brief Type definitions for the System Timer Registers.
ganlikun 0:13413ea9a877 686 @{
ganlikun 0:13413ea9a877 687 */
ganlikun 0:13413ea9a877 688
ganlikun 0:13413ea9a877 689 /**
ganlikun 0:13413ea9a877 690 \brief Structure type to access the System Timer (SysTick).
ganlikun 0:13413ea9a877 691 */
ganlikun 0:13413ea9a877 692 typedef struct
ganlikun 0:13413ea9a877 693 {
ganlikun 0:13413ea9a877 694 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
ganlikun 0:13413ea9a877 695 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
ganlikun 0:13413ea9a877 696 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
ganlikun 0:13413ea9a877 697 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
ganlikun 0:13413ea9a877 698 } SysTick_Type;
ganlikun 0:13413ea9a877 699
ganlikun 0:13413ea9a877 700 /* SysTick Control / Status Register Definitions */
ganlikun 0:13413ea9a877 701 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
ganlikun 0:13413ea9a877 702 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
ganlikun 0:13413ea9a877 703
ganlikun 0:13413ea9a877 704 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
ganlikun 0:13413ea9a877 705 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
ganlikun 0:13413ea9a877 706
ganlikun 0:13413ea9a877 707 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
ganlikun 0:13413ea9a877 708 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
ganlikun 0:13413ea9a877 709
ganlikun 0:13413ea9a877 710 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
ganlikun 0:13413ea9a877 711 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
ganlikun 0:13413ea9a877 712
ganlikun 0:13413ea9a877 713 /* SysTick Reload Register Definitions */
ganlikun 0:13413ea9a877 714 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
ganlikun 0:13413ea9a877 715 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
ganlikun 0:13413ea9a877 716
ganlikun 0:13413ea9a877 717 /* SysTick Current Register Definitions */
ganlikun 0:13413ea9a877 718 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
ganlikun 0:13413ea9a877 719 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
ganlikun 0:13413ea9a877 720
ganlikun 0:13413ea9a877 721 /* SysTick Calibration Register Definitions */
ganlikun 0:13413ea9a877 722 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
ganlikun 0:13413ea9a877 723 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
ganlikun 0:13413ea9a877 724
ganlikun 0:13413ea9a877 725 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
ganlikun 0:13413ea9a877 726 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
ganlikun 0:13413ea9a877 727
ganlikun 0:13413ea9a877 728 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
ganlikun 0:13413ea9a877 729 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
ganlikun 0:13413ea9a877 730
ganlikun 0:13413ea9a877 731 /*@} end of group CMSIS_SysTick */
ganlikun 0:13413ea9a877 732
ganlikun 0:13413ea9a877 733
ganlikun 0:13413ea9a877 734 /**
ganlikun 0:13413ea9a877 735 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 736 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
ganlikun 0:13413ea9a877 737 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
ganlikun 0:13413ea9a877 738 @{
ganlikun 0:13413ea9a877 739 */
ganlikun 0:13413ea9a877 740
ganlikun 0:13413ea9a877 741 /**
ganlikun 0:13413ea9a877 742 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
ganlikun 0:13413ea9a877 743 */
ganlikun 0:13413ea9a877 744 typedef struct
ganlikun 0:13413ea9a877 745 {
ganlikun 0:13413ea9a877 746 __OM union
ganlikun 0:13413ea9a877 747 {
ganlikun 0:13413ea9a877 748 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
ganlikun 0:13413ea9a877 749 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
ganlikun 0:13413ea9a877 750 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
ganlikun 0:13413ea9a877 751 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
ganlikun 0:13413ea9a877 752 uint32_t RESERVED0[864U];
ganlikun 0:13413ea9a877 753 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
ganlikun 0:13413ea9a877 754 uint32_t RESERVED1[15U];
ganlikun 0:13413ea9a877 755 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
ganlikun 0:13413ea9a877 756 uint32_t RESERVED2[15U];
ganlikun 0:13413ea9a877 757 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
ganlikun 0:13413ea9a877 758 uint32_t RESERVED3[29U];
ganlikun 0:13413ea9a877 759 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
ganlikun 0:13413ea9a877 760 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
ganlikun 0:13413ea9a877 761 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
ganlikun 0:13413ea9a877 762 uint32_t RESERVED4[43U];
ganlikun 0:13413ea9a877 763 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
ganlikun 0:13413ea9a877 764 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
ganlikun 0:13413ea9a877 765 uint32_t RESERVED5[6U];
ganlikun 0:13413ea9a877 766 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
ganlikun 0:13413ea9a877 767 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
ganlikun 0:13413ea9a877 768 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
ganlikun 0:13413ea9a877 769 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
ganlikun 0:13413ea9a877 770 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
ganlikun 0:13413ea9a877 771 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
ganlikun 0:13413ea9a877 772 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
ganlikun 0:13413ea9a877 773 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
ganlikun 0:13413ea9a877 774 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
ganlikun 0:13413ea9a877 775 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
ganlikun 0:13413ea9a877 776 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
ganlikun 0:13413ea9a877 777 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
ganlikun 0:13413ea9a877 778 } ITM_Type;
ganlikun 0:13413ea9a877 779
ganlikun 0:13413ea9a877 780 /* ITM Trace Privilege Register Definitions */
ganlikun 0:13413ea9a877 781 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
ganlikun 0:13413ea9a877 782 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
ganlikun 0:13413ea9a877 783
ganlikun 0:13413ea9a877 784 /* ITM Trace Control Register Definitions */
ganlikun 0:13413ea9a877 785 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
ganlikun 0:13413ea9a877 786 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
ganlikun 0:13413ea9a877 787
ganlikun 0:13413ea9a877 788 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
ganlikun 0:13413ea9a877 789 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
ganlikun 0:13413ea9a877 790
ganlikun 0:13413ea9a877 791 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
ganlikun 0:13413ea9a877 792 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
ganlikun 0:13413ea9a877 793
ganlikun 0:13413ea9a877 794 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
ganlikun 0:13413ea9a877 795 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
ganlikun 0:13413ea9a877 796
ganlikun 0:13413ea9a877 797 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
ganlikun 0:13413ea9a877 798 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
ganlikun 0:13413ea9a877 799
ganlikun 0:13413ea9a877 800 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
ganlikun 0:13413ea9a877 801 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
ganlikun 0:13413ea9a877 802
ganlikun 0:13413ea9a877 803 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
ganlikun 0:13413ea9a877 804 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
ganlikun 0:13413ea9a877 805
ganlikun 0:13413ea9a877 806 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
ganlikun 0:13413ea9a877 807 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
ganlikun 0:13413ea9a877 808
ganlikun 0:13413ea9a877 809 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
ganlikun 0:13413ea9a877 810 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
ganlikun 0:13413ea9a877 811
ganlikun 0:13413ea9a877 812 /* ITM Integration Write Register Definitions */
ganlikun 0:13413ea9a877 813 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
ganlikun 0:13413ea9a877 814 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
ganlikun 0:13413ea9a877 815
ganlikun 0:13413ea9a877 816 /* ITM Integration Read Register Definitions */
ganlikun 0:13413ea9a877 817 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
ganlikun 0:13413ea9a877 818 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
ganlikun 0:13413ea9a877 819
ganlikun 0:13413ea9a877 820 /* ITM Integration Mode Control Register Definitions */
ganlikun 0:13413ea9a877 821 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
ganlikun 0:13413ea9a877 822 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
ganlikun 0:13413ea9a877 823
ganlikun 0:13413ea9a877 824 /* ITM Lock Status Register Definitions */
ganlikun 0:13413ea9a877 825 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
ganlikun 0:13413ea9a877 826 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
ganlikun 0:13413ea9a877 827
ganlikun 0:13413ea9a877 828 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
ganlikun 0:13413ea9a877 829 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
ganlikun 0:13413ea9a877 830
ganlikun 0:13413ea9a877 831 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
ganlikun 0:13413ea9a877 832 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
ganlikun 0:13413ea9a877 833
ganlikun 0:13413ea9a877 834 /*@}*/ /* end of group CMSIS_ITM */
ganlikun 0:13413ea9a877 835
ganlikun 0:13413ea9a877 836
ganlikun 0:13413ea9a877 837 /**
ganlikun 0:13413ea9a877 838 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 839 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
ganlikun 0:13413ea9a877 840 \brief Type definitions for the Data Watchpoint and Trace (DWT)
ganlikun 0:13413ea9a877 841 @{
ganlikun 0:13413ea9a877 842 */
ganlikun 0:13413ea9a877 843
ganlikun 0:13413ea9a877 844 /**
ganlikun 0:13413ea9a877 845 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
ganlikun 0:13413ea9a877 846 */
ganlikun 0:13413ea9a877 847 typedef struct
ganlikun 0:13413ea9a877 848 {
ganlikun 0:13413ea9a877 849 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
ganlikun 0:13413ea9a877 850 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
ganlikun 0:13413ea9a877 851 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
ganlikun 0:13413ea9a877 852 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
ganlikun 0:13413ea9a877 853 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
ganlikun 0:13413ea9a877 854 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
ganlikun 0:13413ea9a877 855 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
ganlikun 0:13413ea9a877 856 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
ganlikun 0:13413ea9a877 857 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
ganlikun 0:13413ea9a877 858 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
ganlikun 0:13413ea9a877 859 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
ganlikun 0:13413ea9a877 860 uint32_t RESERVED0[1U];
ganlikun 0:13413ea9a877 861 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
ganlikun 0:13413ea9a877 862 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
ganlikun 0:13413ea9a877 863 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
ganlikun 0:13413ea9a877 864 uint32_t RESERVED1[1U];
ganlikun 0:13413ea9a877 865 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
ganlikun 0:13413ea9a877 866 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
ganlikun 0:13413ea9a877 867 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
ganlikun 0:13413ea9a877 868 uint32_t RESERVED2[1U];
ganlikun 0:13413ea9a877 869 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
ganlikun 0:13413ea9a877 870 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
ganlikun 0:13413ea9a877 871 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
ganlikun 0:13413ea9a877 872 } DWT_Type;
ganlikun 0:13413ea9a877 873
ganlikun 0:13413ea9a877 874 /* DWT Control Register Definitions */
ganlikun 0:13413ea9a877 875 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
ganlikun 0:13413ea9a877 876 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
ganlikun 0:13413ea9a877 877
ganlikun 0:13413ea9a877 878 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
ganlikun 0:13413ea9a877 879 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
ganlikun 0:13413ea9a877 880
ganlikun 0:13413ea9a877 881 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
ganlikun 0:13413ea9a877 882 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
ganlikun 0:13413ea9a877 883
ganlikun 0:13413ea9a877 884 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
ganlikun 0:13413ea9a877 885 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
ganlikun 0:13413ea9a877 886
ganlikun 0:13413ea9a877 887 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
ganlikun 0:13413ea9a877 888 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
ganlikun 0:13413ea9a877 889
ganlikun 0:13413ea9a877 890 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
ganlikun 0:13413ea9a877 891 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
ganlikun 0:13413ea9a877 892
ganlikun 0:13413ea9a877 893 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
ganlikun 0:13413ea9a877 894 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
ganlikun 0:13413ea9a877 895
ganlikun 0:13413ea9a877 896 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
ganlikun 0:13413ea9a877 897 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
ganlikun 0:13413ea9a877 898
ganlikun 0:13413ea9a877 899 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
ganlikun 0:13413ea9a877 900 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
ganlikun 0:13413ea9a877 901
ganlikun 0:13413ea9a877 902 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
ganlikun 0:13413ea9a877 903 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
ganlikun 0:13413ea9a877 904
ganlikun 0:13413ea9a877 905 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
ganlikun 0:13413ea9a877 906 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
ganlikun 0:13413ea9a877 907
ganlikun 0:13413ea9a877 908 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
ganlikun 0:13413ea9a877 909 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
ganlikun 0:13413ea9a877 910
ganlikun 0:13413ea9a877 911 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
ganlikun 0:13413ea9a877 912 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
ganlikun 0:13413ea9a877 913
ganlikun 0:13413ea9a877 914 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
ganlikun 0:13413ea9a877 915 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
ganlikun 0:13413ea9a877 916
ganlikun 0:13413ea9a877 917 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
ganlikun 0:13413ea9a877 918 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
ganlikun 0:13413ea9a877 919
ganlikun 0:13413ea9a877 920 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
ganlikun 0:13413ea9a877 921 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
ganlikun 0:13413ea9a877 922
ganlikun 0:13413ea9a877 923 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
ganlikun 0:13413ea9a877 924 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
ganlikun 0:13413ea9a877 925
ganlikun 0:13413ea9a877 926 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
ganlikun 0:13413ea9a877 927 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
ganlikun 0:13413ea9a877 928
ganlikun 0:13413ea9a877 929 /* DWT CPI Count Register Definitions */
ganlikun 0:13413ea9a877 930 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
ganlikun 0:13413ea9a877 931 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
ganlikun 0:13413ea9a877 932
ganlikun 0:13413ea9a877 933 /* DWT Exception Overhead Count Register Definitions */
ganlikun 0:13413ea9a877 934 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
ganlikun 0:13413ea9a877 935 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
ganlikun 0:13413ea9a877 936
ganlikun 0:13413ea9a877 937 /* DWT Sleep Count Register Definitions */
ganlikun 0:13413ea9a877 938 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
ganlikun 0:13413ea9a877 939 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
ganlikun 0:13413ea9a877 940
ganlikun 0:13413ea9a877 941 /* DWT LSU Count Register Definitions */
ganlikun 0:13413ea9a877 942 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
ganlikun 0:13413ea9a877 943 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
ganlikun 0:13413ea9a877 944
ganlikun 0:13413ea9a877 945 /* DWT Folded-instruction Count Register Definitions */
ganlikun 0:13413ea9a877 946 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
ganlikun 0:13413ea9a877 947 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
ganlikun 0:13413ea9a877 948
ganlikun 0:13413ea9a877 949 /* DWT Comparator Mask Register Definitions */
ganlikun 0:13413ea9a877 950 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
ganlikun 0:13413ea9a877 951 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
ganlikun 0:13413ea9a877 952
ganlikun 0:13413ea9a877 953 /* DWT Comparator Function Register Definitions */
ganlikun 0:13413ea9a877 954 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
ganlikun 0:13413ea9a877 955 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
ganlikun 0:13413ea9a877 956
ganlikun 0:13413ea9a877 957 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
ganlikun 0:13413ea9a877 958 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
ganlikun 0:13413ea9a877 959
ganlikun 0:13413ea9a877 960 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
ganlikun 0:13413ea9a877 961 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
ganlikun 0:13413ea9a877 962
ganlikun 0:13413ea9a877 963 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
ganlikun 0:13413ea9a877 964 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
ganlikun 0:13413ea9a877 965
ganlikun 0:13413ea9a877 966 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
ganlikun 0:13413ea9a877 967 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
ganlikun 0:13413ea9a877 968
ganlikun 0:13413ea9a877 969 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
ganlikun 0:13413ea9a877 970 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
ganlikun 0:13413ea9a877 971
ganlikun 0:13413ea9a877 972 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
ganlikun 0:13413ea9a877 973 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
ganlikun 0:13413ea9a877 974
ganlikun 0:13413ea9a877 975 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
ganlikun 0:13413ea9a877 976 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
ganlikun 0:13413ea9a877 977
ganlikun 0:13413ea9a877 978 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
ganlikun 0:13413ea9a877 979 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
ganlikun 0:13413ea9a877 980
ganlikun 0:13413ea9a877 981 /*@}*/ /* end of group CMSIS_DWT */
ganlikun 0:13413ea9a877 982
ganlikun 0:13413ea9a877 983
ganlikun 0:13413ea9a877 984 /**
ganlikun 0:13413ea9a877 985 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 986 \defgroup CMSIS_TPI Trace Port Interface (TPI)
ganlikun 0:13413ea9a877 987 \brief Type definitions for the Trace Port Interface (TPI)
ganlikun 0:13413ea9a877 988 @{
ganlikun 0:13413ea9a877 989 */
ganlikun 0:13413ea9a877 990
ganlikun 0:13413ea9a877 991 /**
ganlikun 0:13413ea9a877 992 \brief Structure type to access the Trace Port Interface Register (TPI).
ganlikun 0:13413ea9a877 993 */
ganlikun 0:13413ea9a877 994 typedef struct
ganlikun 0:13413ea9a877 995 {
ganlikun 0:13413ea9a877 996 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
ganlikun 0:13413ea9a877 997 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
ganlikun 0:13413ea9a877 998 uint32_t RESERVED0[2U];
ganlikun 0:13413ea9a877 999 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
ganlikun 0:13413ea9a877 1000 uint32_t RESERVED1[55U];
ganlikun 0:13413ea9a877 1001 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
ganlikun 0:13413ea9a877 1002 uint32_t RESERVED2[131U];
ganlikun 0:13413ea9a877 1003 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
ganlikun 0:13413ea9a877 1004 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
ganlikun 0:13413ea9a877 1005 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
ganlikun 0:13413ea9a877 1006 uint32_t RESERVED3[759U];
ganlikun 0:13413ea9a877 1007 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
ganlikun 0:13413ea9a877 1008 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
ganlikun 0:13413ea9a877 1009 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
ganlikun 0:13413ea9a877 1010 uint32_t RESERVED4[1U];
ganlikun 0:13413ea9a877 1011 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
ganlikun 0:13413ea9a877 1012 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
ganlikun 0:13413ea9a877 1013 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
ganlikun 0:13413ea9a877 1014 uint32_t RESERVED5[39U];
ganlikun 0:13413ea9a877 1015 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
ganlikun 0:13413ea9a877 1016 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
ganlikun 0:13413ea9a877 1017 uint32_t RESERVED7[8U];
ganlikun 0:13413ea9a877 1018 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
ganlikun 0:13413ea9a877 1019 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
ganlikun 0:13413ea9a877 1020 } TPI_Type;
ganlikun 0:13413ea9a877 1021
ganlikun 0:13413ea9a877 1022 /* TPI Asynchronous Clock Prescaler Register Definitions */
ganlikun 0:13413ea9a877 1023 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
ganlikun 0:13413ea9a877 1024 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
ganlikun 0:13413ea9a877 1025
ganlikun 0:13413ea9a877 1026 /* TPI Selected Pin Protocol Register Definitions */
ganlikun 0:13413ea9a877 1027 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
ganlikun 0:13413ea9a877 1028 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
ganlikun 0:13413ea9a877 1029
ganlikun 0:13413ea9a877 1030 /* TPI Formatter and Flush Status Register Definitions */
ganlikun 0:13413ea9a877 1031 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
ganlikun 0:13413ea9a877 1032 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
ganlikun 0:13413ea9a877 1033
ganlikun 0:13413ea9a877 1034 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
ganlikun 0:13413ea9a877 1035 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
ganlikun 0:13413ea9a877 1036
ganlikun 0:13413ea9a877 1037 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
ganlikun 0:13413ea9a877 1038 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
ganlikun 0:13413ea9a877 1039
ganlikun 0:13413ea9a877 1040 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
ganlikun 0:13413ea9a877 1041 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
ganlikun 0:13413ea9a877 1042
ganlikun 0:13413ea9a877 1043 /* TPI Formatter and Flush Control Register Definitions */
ganlikun 0:13413ea9a877 1044 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
ganlikun 0:13413ea9a877 1045 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
ganlikun 0:13413ea9a877 1046
ganlikun 0:13413ea9a877 1047 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
ganlikun 0:13413ea9a877 1048 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
ganlikun 0:13413ea9a877 1049
ganlikun 0:13413ea9a877 1050 /* TPI TRIGGER Register Definitions */
ganlikun 0:13413ea9a877 1051 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
ganlikun 0:13413ea9a877 1052 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
ganlikun 0:13413ea9a877 1053
ganlikun 0:13413ea9a877 1054 /* TPI Integration ETM Data Register Definitions (FIFO0) */
ganlikun 0:13413ea9a877 1055 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
ganlikun 0:13413ea9a877 1056 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
ganlikun 0:13413ea9a877 1057
ganlikun 0:13413ea9a877 1058 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
ganlikun 0:13413ea9a877 1059 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
ganlikun 0:13413ea9a877 1060
ganlikun 0:13413ea9a877 1061 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
ganlikun 0:13413ea9a877 1062 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
ganlikun 0:13413ea9a877 1063
ganlikun 0:13413ea9a877 1064 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
ganlikun 0:13413ea9a877 1065 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
ganlikun 0:13413ea9a877 1066
ganlikun 0:13413ea9a877 1067 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
ganlikun 0:13413ea9a877 1068 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
ganlikun 0:13413ea9a877 1069
ganlikun 0:13413ea9a877 1070 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
ganlikun 0:13413ea9a877 1071 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
ganlikun 0:13413ea9a877 1072
ganlikun 0:13413ea9a877 1073 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
ganlikun 0:13413ea9a877 1074 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
ganlikun 0:13413ea9a877 1075
ganlikun 0:13413ea9a877 1076 /* TPI ITATBCTR2 Register Definitions */
ganlikun 0:13413ea9a877 1077 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
ganlikun 0:13413ea9a877 1078 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
ganlikun 0:13413ea9a877 1079
ganlikun 0:13413ea9a877 1080 /* TPI Integration ITM Data Register Definitions (FIFO1) */
ganlikun 0:13413ea9a877 1081 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
ganlikun 0:13413ea9a877 1082 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
ganlikun 0:13413ea9a877 1083
ganlikun 0:13413ea9a877 1084 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
ganlikun 0:13413ea9a877 1085 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
ganlikun 0:13413ea9a877 1086
ganlikun 0:13413ea9a877 1087 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
ganlikun 0:13413ea9a877 1088 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
ganlikun 0:13413ea9a877 1089
ganlikun 0:13413ea9a877 1090 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
ganlikun 0:13413ea9a877 1091 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
ganlikun 0:13413ea9a877 1092
ganlikun 0:13413ea9a877 1093 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
ganlikun 0:13413ea9a877 1094 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
ganlikun 0:13413ea9a877 1095
ganlikun 0:13413ea9a877 1096 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
ganlikun 0:13413ea9a877 1097 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
ganlikun 0:13413ea9a877 1098
ganlikun 0:13413ea9a877 1099 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
ganlikun 0:13413ea9a877 1100 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
ganlikun 0:13413ea9a877 1101
ganlikun 0:13413ea9a877 1102 /* TPI ITATBCTR0 Register Definitions */
ganlikun 0:13413ea9a877 1103 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
ganlikun 0:13413ea9a877 1104 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
ganlikun 0:13413ea9a877 1105
ganlikun 0:13413ea9a877 1106 /* TPI Integration Mode Control Register Definitions */
ganlikun 0:13413ea9a877 1107 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
ganlikun 0:13413ea9a877 1108 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
ganlikun 0:13413ea9a877 1109
ganlikun 0:13413ea9a877 1110 /* TPI DEVID Register Definitions */
ganlikun 0:13413ea9a877 1111 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
ganlikun 0:13413ea9a877 1112 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
ganlikun 0:13413ea9a877 1113
ganlikun 0:13413ea9a877 1114 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
ganlikun 0:13413ea9a877 1115 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
ganlikun 0:13413ea9a877 1116
ganlikun 0:13413ea9a877 1117 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
ganlikun 0:13413ea9a877 1118 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
ganlikun 0:13413ea9a877 1119
ganlikun 0:13413ea9a877 1120 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
ganlikun 0:13413ea9a877 1121 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
ganlikun 0:13413ea9a877 1122
ganlikun 0:13413ea9a877 1123 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
ganlikun 0:13413ea9a877 1124 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
ganlikun 0:13413ea9a877 1125
ganlikun 0:13413ea9a877 1126 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
ganlikun 0:13413ea9a877 1127 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
ganlikun 0:13413ea9a877 1128
ganlikun 0:13413ea9a877 1129 /* TPI DEVTYPE Register Definitions */
ganlikun 0:13413ea9a877 1130 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
ganlikun 0:13413ea9a877 1131 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
ganlikun 0:13413ea9a877 1132
ganlikun 0:13413ea9a877 1133 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
ganlikun 0:13413ea9a877 1134 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
ganlikun 0:13413ea9a877 1135
ganlikun 0:13413ea9a877 1136 /*@}*/ /* end of group CMSIS_TPI */
ganlikun 0:13413ea9a877 1137
ganlikun 0:13413ea9a877 1138
ganlikun 0:13413ea9a877 1139 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:13413ea9a877 1140 /**
ganlikun 0:13413ea9a877 1141 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 1142 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
ganlikun 0:13413ea9a877 1143 \brief Type definitions for the Memory Protection Unit (MPU)
ganlikun 0:13413ea9a877 1144 @{
ganlikun 0:13413ea9a877 1145 */
ganlikun 0:13413ea9a877 1146
ganlikun 0:13413ea9a877 1147 /**
ganlikun 0:13413ea9a877 1148 \brief Structure type to access the Memory Protection Unit (MPU).
ganlikun 0:13413ea9a877 1149 */
ganlikun 0:13413ea9a877 1150 typedef struct
ganlikun 0:13413ea9a877 1151 {
ganlikun 0:13413ea9a877 1152 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
ganlikun 0:13413ea9a877 1153 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
ganlikun 0:13413ea9a877 1154 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
ganlikun 0:13413ea9a877 1155 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
ganlikun 0:13413ea9a877 1156 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
ganlikun 0:13413ea9a877 1157 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
ganlikun 0:13413ea9a877 1158 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
ganlikun 0:13413ea9a877 1159 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
ganlikun 0:13413ea9a877 1160 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
ganlikun 0:13413ea9a877 1161 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
ganlikun 0:13413ea9a877 1162 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
ganlikun 0:13413ea9a877 1163 } MPU_Type;
ganlikun 0:13413ea9a877 1164
ganlikun 0:13413ea9a877 1165 /* MPU Type Register Definitions */
ganlikun 0:13413ea9a877 1166 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
ganlikun 0:13413ea9a877 1167 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
ganlikun 0:13413ea9a877 1168
ganlikun 0:13413ea9a877 1169 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
ganlikun 0:13413ea9a877 1170 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
ganlikun 0:13413ea9a877 1171
ganlikun 0:13413ea9a877 1172 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
ganlikun 0:13413ea9a877 1173 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
ganlikun 0:13413ea9a877 1174
ganlikun 0:13413ea9a877 1175 /* MPU Control Register Definitions */
ganlikun 0:13413ea9a877 1176 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
ganlikun 0:13413ea9a877 1177 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
ganlikun 0:13413ea9a877 1178
ganlikun 0:13413ea9a877 1179 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
ganlikun 0:13413ea9a877 1180 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
ganlikun 0:13413ea9a877 1181
ganlikun 0:13413ea9a877 1182 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
ganlikun 0:13413ea9a877 1183 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
ganlikun 0:13413ea9a877 1184
ganlikun 0:13413ea9a877 1185 /* MPU Region Number Register Definitions */
ganlikun 0:13413ea9a877 1186 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
ganlikun 0:13413ea9a877 1187 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
ganlikun 0:13413ea9a877 1188
ganlikun 0:13413ea9a877 1189 /* MPU Region Base Address Register Definitions */
ganlikun 0:13413ea9a877 1190 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
ganlikun 0:13413ea9a877 1191 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
ganlikun 0:13413ea9a877 1192
ganlikun 0:13413ea9a877 1193 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
ganlikun 0:13413ea9a877 1194 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
ganlikun 0:13413ea9a877 1195
ganlikun 0:13413ea9a877 1196 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
ganlikun 0:13413ea9a877 1197 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
ganlikun 0:13413ea9a877 1198
ganlikun 0:13413ea9a877 1199 /* MPU Region Attribute and Size Register Definitions */
ganlikun 0:13413ea9a877 1200 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
ganlikun 0:13413ea9a877 1201 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
ganlikun 0:13413ea9a877 1202
ganlikun 0:13413ea9a877 1203 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
ganlikun 0:13413ea9a877 1204 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
ganlikun 0:13413ea9a877 1205
ganlikun 0:13413ea9a877 1206 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
ganlikun 0:13413ea9a877 1207 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
ganlikun 0:13413ea9a877 1208
ganlikun 0:13413ea9a877 1209 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
ganlikun 0:13413ea9a877 1210 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
ganlikun 0:13413ea9a877 1211
ganlikun 0:13413ea9a877 1212 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
ganlikun 0:13413ea9a877 1213 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
ganlikun 0:13413ea9a877 1214
ganlikun 0:13413ea9a877 1215 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
ganlikun 0:13413ea9a877 1216 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
ganlikun 0:13413ea9a877 1217
ganlikun 0:13413ea9a877 1218 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
ganlikun 0:13413ea9a877 1219 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
ganlikun 0:13413ea9a877 1220
ganlikun 0:13413ea9a877 1221 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
ganlikun 0:13413ea9a877 1222 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
ganlikun 0:13413ea9a877 1223
ganlikun 0:13413ea9a877 1224 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
ganlikun 0:13413ea9a877 1225 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
ganlikun 0:13413ea9a877 1226
ganlikun 0:13413ea9a877 1227 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
ganlikun 0:13413ea9a877 1228 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
ganlikun 0:13413ea9a877 1229
ganlikun 0:13413ea9a877 1230 /*@} end of group CMSIS_MPU */
ganlikun 0:13413ea9a877 1231 #endif
ganlikun 0:13413ea9a877 1232
ganlikun 0:13413ea9a877 1233
ganlikun 0:13413ea9a877 1234 /**
ganlikun 0:13413ea9a877 1235 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 1236 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
ganlikun 0:13413ea9a877 1237 \brief Type definitions for the Core Debug Registers
ganlikun 0:13413ea9a877 1238 @{
ganlikun 0:13413ea9a877 1239 */
ganlikun 0:13413ea9a877 1240
ganlikun 0:13413ea9a877 1241 /**
ganlikun 0:13413ea9a877 1242 \brief Structure type to access the Core Debug Register (CoreDebug).
ganlikun 0:13413ea9a877 1243 */
ganlikun 0:13413ea9a877 1244 typedef struct
ganlikun 0:13413ea9a877 1245 {
ganlikun 0:13413ea9a877 1246 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
ganlikun 0:13413ea9a877 1247 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
ganlikun 0:13413ea9a877 1248 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
ganlikun 0:13413ea9a877 1249 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
ganlikun 0:13413ea9a877 1250 } CoreDebug_Type;
ganlikun 0:13413ea9a877 1251
ganlikun 0:13413ea9a877 1252 /* Debug Halting Control and Status Register Definitions */
ganlikun 0:13413ea9a877 1253 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
ganlikun 0:13413ea9a877 1254 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
ganlikun 0:13413ea9a877 1255
ganlikun 0:13413ea9a877 1256 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
ganlikun 0:13413ea9a877 1257 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
ganlikun 0:13413ea9a877 1258
ganlikun 0:13413ea9a877 1259 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
ganlikun 0:13413ea9a877 1260 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
ganlikun 0:13413ea9a877 1261
ganlikun 0:13413ea9a877 1262 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
ganlikun 0:13413ea9a877 1263 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
ganlikun 0:13413ea9a877 1264
ganlikun 0:13413ea9a877 1265 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
ganlikun 0:13413ea9a877 1266 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
ganlikun 0:13413ea9a877 1267
ganlikun 0:13413ea9a877 1268 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
ganlikun 0:13413ea9a877 1269 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
ganlikun 0:13413ea9a877 1270
ganlikun 0:13413ea9a877 1271 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
ganlikun 0:13413ea9a877 1272 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
ganlikun 0:13413ea9a877 1273
ganlikun 0:13413ea9a877 1274 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
ganlikun 0:13413ea9a877 1275 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
ganlikun 0:13413ea9a877 1276
ganlikun 0:13413ea9a877 1277 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
ganlikun 0:13413ea9a877 1278 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
ganlikun 0:13413ea9a877 1279
ganlikun 0:13413ea9a877 1280 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
ganlikun 0:13413ea9a877 1281 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
ganlikun 0:13413ea9a877 1282
ganlikun 0:13413ea9a877 1283 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
ganlikun 0:13413ea9a877 1284 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
ganlikun 0:13413ea9a877 1285
ganlikun 0:13413ea9a877 1286 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
ganlikun 0:13413ea9a877 1287 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
ganlikun 0:13413ea9a877 1288
ganlikun 0:13413ea9a877 1289 /* Debug Core Register Selector Register Definitions */
ganlikun 0:13413ea9a877 1290 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
ganlikun 0:13413ea9a877 1291 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
ganlikun 0:13413ea9a877 1292
ganlikun 0:13413ea9a877 1293 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
ganlikun 0:13413ea9a877 1294 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
ganlikun 0:13413ea9a877 1295
ganlikun 0:13413ea9a877 1296 /* Debug Exception and Monitor Control Register Definitions */
ganlikun 0:13413ea9a877 1297 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
ganlikun 0:13413ea9a877 1298 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
ganlikun 0:13413ea9a877 1299
ganlikun 0:13413ea9a877 1300 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
ganlikun 0:13413ea9a877 1301 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
ganlikun 0:13413ea9a877 1302
ganlikun 0:13413ea9a877 1303 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
ganlikun 0:13413ea9a877 1304 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
ganlikun 0:13413ea9a877 1305
ganlikun 0:13413ea9a877 1306 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
ganlikun 0:13413ea9a877 1307 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
ganlikun 0:13413ea9a877 1308
ganlikun 0:13413ea9a877 1309 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
ganlikun 0:13413ea9a877 1310 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
ganlikun 0:13413ea9a877 1311
ganlikun 0:13413ea9a877 1312 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
ganlikun 0:13413ea9a877 1313 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
ganlikun 0:13413ea9a877 1314
ganlikun 0:13413ea9a877 1315 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
ganlikun 0:13413ea9a877 1316 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
ganlikun 0:13413ea9a877 1317
ganlikun 0:13413ea9a877 1318 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
ganlikun 0:13413ea9a877 1319 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
ganlikun 0:13413ea9a877 1320
ganlikun 0:13413ea9a877 1321 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
ganlikun 0:13413ea9a877 1322 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
ganlikun 0:13413ea9a877 1323
ganlikun 0:13413ea9a877 1324 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
ganlikun 0:13413ea9a877 1325 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
ganlikun 0:13413ea9a877 1326
ganlikun 0:13413ea9a877 1327 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
ganlikun 0:13413ea9a877 1328 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
ganlikun 0:13413ea9a877 1329
ganlikun 0:13413ea9a877 1330 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
ganlikun 0:13413ea9a877 1331 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
ganlikun 0:13413ea9a877 1332
ganlikun 0:13413ea9a877 1333 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
ganlikun 0:13413ea9a877 1334 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
ganlikun 0:13413ea9a877 1335
ganlikun 0:13413ea9a877 1336 /*@} end of group CMSIS_CoreDebug */
ganlikun 0:13413ea9a877 1337
ganlikun 0:13413ea9a877 1338
ganlikun 0:13413ea9a877 1339 /**
ganlikun 0:13413ea9a877 1340 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 1341 \defgroup CMSIS_core_bitfield Core register bit field macros
ganlikun 0:13413ea9a877 1342 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
ganlikun 0:13413ea9a877 1343 @{
ganlikun 0:13413ea9a877 1344 */
ganlikun 0:13413ea9a877 1345
ganlikun 0:13413ea9a877 1346 /**
ganlikun 0:13413ea9a877 1347 \brief Mask and shift a bit field value for use in a register bit range.
ganlikun 0:13413ea9a877 1348 \param[in] field Name of the register bit field.
ganlikun 0:13413ea9a877 1349 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
ganlikun 0:13413ea9a877 1350 \return Masked and shifted value.
ganlikun 0:13413ea9a877 1351 */
ganlikun 0:13413ea9a877 1352 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
ganlikun 0:13413ea9a877 1353
ganlikun 0:13413ea9a877 1354 /**
ganlikun 0:13413ea9a877 1355 \brief Mask and shift a register value to extract a bit filed value.
ganlikun 0:13413ea9a877 1356 \param[in] field Name of the register bit field.
ganlikun 0:13413ea9a877 1357 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
ganlikun 0:13413ea9a877 1358 \return Masked and shifted bit field value.
ganlikun 0:13413ea9a877 1359 */
ganlikun 0:13413ea9a877 1360 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ganlikun 0:13413ea9a877 1361
ganlikun 0:13413ea9a877 1362 /*@} end of group CMSIS_core_bitfield */
ganlikun 0:13413ea9a877 1363
ganlikun 0:13413ea9a877 1364
ganlikun 0:13413ea9a877 1365 /**
ganlikun 0:13413ea9a877 1366 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 1367 \defgroup CMSIS_core_base Core Definitions
ganlikun 0:13413ea9a877 1368 \brief Definitions for base addresses, unions, and structures.
ganlikun 0:13413ea9a877 1369 @{
ganlikun 0:13413ea9a877 1370 */
ganlikun 0:13413ea9a877 1371
ganlikun 0:13413ea9a877 1372 /* Memory mapping of Core Hardware */
ganlikun 0:13413ea9a877 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
ganlikun 0:13413ea9a877 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
ganlikun 0:13413ea9a877 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
ganlikun 0:13413ea9a877 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
ganlikun 0:13413ea9a877 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
ganlikun 0:13413ea9a877 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
ganlikun 0:13413ea9a877 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
ganlikun 0:13413ea9a877 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
ganlikun 0:13413ea9a877 1381
ganlikun 0:13413ea9a877 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
ganlikun 0:13413ea9a877 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
ganlikun 0:13413ea9a877 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
ganlikun 0:13413ea9a877 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
ganlikun 0:13413ea9a877 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
ganlikun 0:13413ea9a877 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
ganlikun 0:13413ea9a877 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
ganlikun 0:13413ea9a877 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
ganlikun 0:13413ea9a877 1390
ganlikun 0:13413ea9a877 1391 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:13413ea9a877 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
ganlikun 0:13413ea9a877 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
ganlikun 0:13413ea9a877 1394 #endif
ganlikun 0:13413ea9a877 1395
ganlikun 0:13413ea9a877 1396 /*@} */
ganlikun 0:13413ea9a877 1397
ganlikun 0:13413ea9a877 1398
ganlikun 0:13413ea9a877 1399
ganlikun 0:13413ea9a877 1400 /*******************************************************************************
ganlikun 0:13413ea9a877 1401 * Hardware Abstraction Layer
ganlikun 0:13413ea9a877 1402 Core Function Interface contains:
ganlikun 0:13413ea9a877 1403 - Core NVIC Functions
ganlikun 0:13413ea9a877 1404 - Core SysTick Functions
ganlikun 0:13413ea9a877 1405 - Core Debug Functions
ganlikun 0:13413ea9a877 1406 - Core Register Access Functions
ganlikun 0:13413ea9a877 1407 ******************************************************************************/
ganlikun 0:13413ea9a877 1408 /**
ganlikun 0:13413ea9a877 1409 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
ganlikun 0:13413ea9a877 1410 */
ganlikun 0:13413ea9a877 1411
ganlikun 0:13413ea9a877 1412
ganlikun 0:13413ea9a877 1413
ganlikun 0:13413ea9a877 1414 /* ########################## NVIC functions #################################### */
ganlikun 0:13413ea9a877 1415 /**
ganlikun 0:13413ea9a877 1416 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1417 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
ganlikun 0:13413ea9a877 1418 \brief Functions that manage interrupts and exceptions via the NVIC.
ganlikun 0:13413ea9a877 1419 @{
ganlikun 0:13413ea9a877 1420 */
ganlikun 0:13413ea9a877 1421
ganlikun 0:13413ea9a877 1422 #ifdef CMSIS_NVIC_VIRTUAL
ganlikun 0:13413ea9a877 1423 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1424 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
ganlikun 0:13413ea9a877 1425 #endif
ganlikun 0:13413ea9a877 1426 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1427 #else
ganlikun 0:13413ea9a877 1428 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
ganlikun 0:13413ea9a877 1429 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
ganlikun 0:13413ea9a877 1430 #define NVIC_EnableIRQ __NVIC_EnableIRQ
ganlikun 0:13413ea9a877 1431 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
ganlikun 0:13413ea9a877 1432 #define NVIC_DisableIRQ __NVIC_DisableIRQ
ganlikun 0:13413ea9a877 1433 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
ganlikun 0:13413ea9a877 1434 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
ganlikun 0:13413ea9a877 1435 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
ganlikun 0:13413ea9a877 1436 #define NVIC_GetActive __NVIC_GetActive
ganlikun 0:13413ea9a877 1437 #define NVIC_SetPriority __NVIC_SetPriority
ganlikun 0:13413ea9a877 1438 #define NVIC_GetPriority __NVIC_GetPriority
ganlikun 0:13413ea9a877 1439 #define NVIC_SystemReset __NVIC_SystemReset
ganlikun 0:13413ea9a877 1440 #endif /* CMSIS_NVIC_VIRTUAL */
ganlikun 0:13413ea9a877 1441
ganlikun 0:13413ea9a877 1442 #ifdef CMSIS_VECTAB_VIRTUAL
ganlikun 0:13413ea9a877 1443 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1444 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
ganlikun 0:13413ea9a877 1445 #endif
ganlikun 0:13413ea9a877 1446 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1447 #else
ganlikun 0:13413ea9a877 1448 #define NVIC_SetVector __NVIC_SetVector
ganlikun 0:13413ea9a877 1449 #define NVIC_GetVector __NVIC_GetVector
ganlikun 0:13413ea9a877 1450 #endif /* (CMSIS_VECTAB_VIRTUAL) */
ganlikun 0:13413ea9a877 1451
ganlikun 0:13413ea9a877 1452 #define NVIC_USER_IRQ_OFFSET 16
ganlikun 0:13413ea9a877 1453
ganlikun 0:13413ea9a877 1454
ganlikun 0:13413ea9a877 1455
ganlikun 0:13413ea9a877 1456 /**
ganlikun 0:13413ea9a877 1457 \brief Set Priority Grouping
ganlikun 0:13413ea9a877 1458 \details Sets the priority grouping field using the required unlock sequence.
ganlikun 0:13413ea9a877 1459 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
ganlikun 0:13413ea9a877 1460 Only values from 0..7 are used.
ganlikun 0:13413ea9a877 1461 In case of a conflict between priority grouping and available
ganlikun 0:13413ea9a877 1462 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
ganlikun 0:13413ea9a877 1463 \param [in] PriorityGroup Priority grouping field.
ganlikun 0:13413ea9a877 1464 */
ganlikun 0:13413ea9a877 1465 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
ganlikun 0:13413ea9a877 1466 {
ganlikun 0:13413ea9a877 1467 uint32_t reg_value;
ganlikun 0:13413ea9a877 1468 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
ganlikun 0:13413ea9a877 1469
ganlikun 0:13413ea9a877 1470 reg_value = SCB->AIRCR; /* read old register configuration */
ganlikun 0:13413ea9a877 1471 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
ganlikun 0:13413ea9a877 1472 reg_value = (reg_value |
ganlikun 0:13413ea9a877 1473 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
ganlikun 0:13413ea9a877 1474 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
ganlikun 0:13413ea9a877 1475 SCB->AIRCR = reg_value;
ganlikun 0:13413ea9a877 1476 }
ganlikun 0:13413ea9a877 1477
ganlikun 0:13413ea9a877 1478
ganlikun 0:13413ea9a877 1479 /**
ganlikun 0:13413ea9a877 1480 \brief Get Priority Grouping
ganlikun 0:13413ea9a877 1481 \details Reads the priority grouping field from the NVIC Interrupt Controller.
ganlikun 0:13413ea9a877 1482 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
ganlikun 0:13413ea9a877 1483 */
ganlikun 0:13413ea9a877 1484 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
ganlikun 0:13413ea9a877 1485 {
ganlikun 0:13413ea9a877 1486 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
ganlikun 0:13413ea9a877 1487 }
ganlikun 0:13413ea9a877 1488
ganlikun 0:13413ea9a877 1489
ganlikun 0:13413ea9a877 1490 /**
ganlikun 0:13413ea9a877 1491 \brief Enable Interrupt
ganlikun 0:13413ea9a877 1492 \details Enables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:13413ea9a877 1493 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1494 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1495 */
ganlikun 0:13413ea9a877 1496 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1497 {
ganlikun 0:13413ea9a877 1498 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1499 {
ganlikun 0:13413ea9a877 1500 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1501 }
ganlikun 0:13413ea9a877 1502 }
ganlikun 0:13413ea9a877 1503
ganlikun 0:13413ea9a877 1504
ganlikun 0:13413ea9a877 1505 /**
ganlikun 0:13413ea9a877 1506 \brief Get Interrupt Enable status
ganlikun 0:13413ea9a877 1507 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
ganlikun 0:13413ea9a877 1508 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1509 \return 0 Interrupt is not enabled.
ganlikun 0:13413ea9a877 1510 \return 1 Interrupt is enabled.
ganlikun 0:13413ea9a877 1511 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1512 */
ganlikun 0:13413ea9a877 1513 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1514 {
ganlikun 0:13413ea9a877 1515 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1516 {
ganlikun 0:13413ea9a877 1517 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1518 }
ganlikun 0:13413ea9a877 1519 else
ganlikun 0:13413ea9a877 1520 {
ganlikun 0:13413ea9a877 1521 return(0U);
ganlikun 0:13413ea9a877 1522 }
ganlikun 0:13413ea9a877 1523 }
ganlikun 0:13413ea9a877 1524
ganlikun 0:13413ea9a877 1525
ganlikun 0:13413ea9a877 1526 /**
ganlikun 0:13413ea9a877 1527 \brief Disable Interrupt
ganlikun 0:13413ea9a877 1528 \details Disables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:13413ea9a877 1529 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1530 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1531 */
ganlikun 0:13413ea9a877 1532 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1533 {
ganlikun 0:13413ea9a877 1534 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1535 {
ganlikun 0:13413ea9a877 1536 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1537 __DSB();
ganlikun 0:13413ea9a877 1538 __ISB();
ganlikun 0:13413ea9a877 1539 }
ganlikun 0:13413ea9a877 1540 }
ganlikun 0:13413ea9a877 1541
ganlikun 0:13413ea9a877 1542
ganlikun 0:13413ea9a877 1543 /**
ganlikun 0:13413ea9a877 1544 \brief Get Pending Interrupt
ganlikun 0:13413ea9a877 1545 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
ganlikun 0:13413ea9a877 1546 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1547 \return 0 Interrupt status is not pending.
ganlikun 0:13413ea9a877 1548 \return 1 Interrupt status is pending.
ganlikun 0:13413ea9a877 1549 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1550 */
ganlikun 0:13413ea9a877 1551 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1552 {
ganlikun 0:13413ea9a877 1553 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1554 {
ganlikun 0:13413ea9a877 1555 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1556 }
ganlikun 0:13413ea9a877 1557 else
ganlikun 0:13413ea9a877 1558 {
ganlikun 0:13413ea9a877 1559 return(0U);
ganlikun 0:13413ea9a877 1560 }
ganlikun 0:13413ea9a877 1561 }
ganlikun 0:13413ea9a877 1562
ganlikun 0:13413ea9a877 1563
ganlikun 0:13413ea9a877 1564 /**
ganlikun 0:13413ea9a877 1565 \brief Set Pending Interrupt
ganlikun 0:13413ea9a877 1566 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:13413ea9a877 1567 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1568 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1569 */
ganlikun 0:13413ea9a877 1570 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1571 {
ganlikun 0:13413ea9a877 1572 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1573 {
ganlikun 0:13413ea9a877 1574 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1575 }
ganlikun 0:13413ea9a877 1576 }
ganlikun 0:13413ea9a877 1577
ganlikun 0:13413ea9a877 1578
ganlikun 0:13413ea9a877 1579 /**
ganlikun 0:13413ea9a877 1580 \brief Clear Pending Interrupt
ganlikun 0:13413ea9a877 1581 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:13413ea9a877 1582 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1583 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1584 */
ganlikun 0:13413ea9a877 1585 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1586 {
ganlikun 0:13413ea9a877 1587 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1588 {
ganlikun 0:13413ea9a877 1589 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1590 }
ganlikun 0:13413ea9a877 1591 }
ganlikun 0:13413ea9a877 1592
ganlikun 0:13413ea9a877 1593
ganlikun 0:13413ea9a877 1594 /**
ganlikun 0:13413ea9a877 1595 \brief Get Active Interrupt
ganlikun 0:13413ea9a877 1596 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
ganlikun 0:13413ea9a877 1597 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1598 \return 0 Interrupt status is not active.
ganlikun 0:13413ea9a877 1599 \return 1 Interrupt status is active.
ganlikun 0:13413ea9a877 1600 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1601 */
ganlikun 0:13413ea9a877 1602 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1603 {
ganlikun 0:13413ea9a877 1604 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1605 {
ganlikun 0:13413ea9a877 1606 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1607 }
ganlikun 0:13413ea9a877 1608 else
ganlikun 0:13413ea9a877 1609 {
ganlikun 0:13413ea9a877 1610 return(0U);
ganlikun 0:13413ea9a877 1611 }
ganlikun 0:13413ea9a877 1612 }
ganlikun 0:13413ea9a877 1613
ganlikun 0:13413ea9a877 1614
ganlikun 0:13413ea9a877 1615 /**
ganlikun 0:13413ea9a877 1616 \brief Set Interrupt Priority
ganlikun 0:13413ea9a877 1617 \details Sets the priority of a device specific interrupt or a processor exception.
ganlikun 0:13413ea9a877 1618 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1619 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1620 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1621 \param [in] priority Priority to set.
ganlikun 0:13413ea9a877 1622 \note The priority cannot be set for every processor exception.
ganlikun 0:13413ea9a877 1623 */
ganlikun 0:13413ea9a877 1624 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ganlikun 0:13413ea9a877 1625 {
ganlikun 0:13413ea9a877 1626 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1627 {
ganlikun 0:13413ea9a877 1628 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
ganlikun 0:13413ea9a877 1629 }
ganlikun 0:13413ea9a877 1630 else
ganlikun 0:13413ea9a877 1631 {
ganlikun 0:13413ea9a877 1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
ganlikun 0:13413ea9a877 1633 }
ganlikun 0:13413ea9a877 1634 }
ganlikun 0:13413ea9a877 1635
ganlikun 0:13413ea9a877 1636
ganlikun 0:13413ea9a877 1637 /**
ganlikun 0:13413ea9a877 1638 \brief Get Interrupt Priority
ganlikun 0:13413ea9a877 1639 \details Reads the priority of a device specific interrupt or a processor exception.
ganlikun 0:13413ea9a877 1640 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1641 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1642 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1643 \return Interrupt Priority.
ganlikun 0:13413ea9a877 1644 Value is aligned automatically to the implemented priority bits of the microcontroller.
ganlikun 0:13413ea9a877 1645 */
ganlikun 0:13413ea9a877 1646 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1647 {
ganlikun 0:13413ea9a877 1648
ganlikun 0:13413ea9a877 1649 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1650 {
ganlikun 0:13413ea9a877 1651 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:13413ea9a877 1652 }
ganlikun 0:13413ea9a877 1653 else
ganlikun 0:13413ea9a877 1654 {
ganlikun 0:13413ea9a877 1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:13413ea9a877 1656 }
ganlikun 0:13413ea9a877 1657 }
ganlikun 0:13413ea9a877 1658
ganlikun 0:13413ea9a877 1659
ganlikun 0:13413ea9a877 1660 /**
ganlikun 0:13413ea9a877 1661 \brief Encode Priority
ganlikun 0:13413ea9a877 1662 \details Encodes the priority for an interrupt with the given priority group,
ganlikun 0:13413ea9a877 1663 preemptive priority value, and subpriority value.
ganlikun 0:13413ea9a877 1664 In case of a conflict between priority grouping and available
ganlikun 0:13413ea9a877 1665 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
ganlikun 0:13413ea9a877 1666 \param [in] PriorityGroup Used priority group.
ganlikun 0:13413ea9a877 1667 \param [in] PreemptPriority Preemptive priority value (starting from 0).
ganlikun 0:13413ea9a877 1668 \param [in] SubPriority Subpriority value (starting from 0).
ganlikun 0:13413ea9a877 1669 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
ganlikun 0:13413ea9a877 1670 */
ganlikun 0:13413ea9a877 1671 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
ganlikun 0:13413ea9a877 1672 {
ganlikun 0:13413ea9a877 1673 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
ganlikun 0:13413ea9a877 1674 uint32_t PreemptPriorityBits;
ganlikun 0:13413ea9a877 1675 uint32_t SubPriorityBits;
ganlikun 0:13413ea9a877 1676
ganlikun 0:13413ea9a877 1677 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
ganlikun 0:13413ea9a877 1678 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
ganlikun 0:13413ea9a877 1679
ganlikun 0:13413ea9a877 1680 return (
ganlikun 0:13413ea9a877 1681 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
ganlikun 0:13413ea9a877 1682 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
ganlikun 0:13413ea9a877 1683 );
ganlikun 0:13413ea9a877 1684 }
ganlikun 0:13413ea9a877 1685
ganlikun 0:13413ea9a877 1686
ganlikun 0:13413ea9a877 1687 /**
ganlikun 0:13413ea9a877 1688 \brief Decode Priority
ganlikun 0:13413ea9a877 1689 \details Decodes an interrupt priority value with a given priority group to
ganlikun 0:13413ea9a877 1690 preemptive priority value and subpriority value.
ganlikun 0:13413ea9a877 1691 In case of a conflict between priority grouping and available
ganlikun 0:13413ea9a877 1692 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
ganlikun 0:13413ea9a877 1693 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
ganlikun 0:13413ea9a877 1694 \param [in] PriorityGroup Used priority group.
ganlikun 0:13413ea9a877 1695 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
ganlikun 0:13413ea9a877 1696 \param [out] pSubPriority Subpriority value (starting from 0).
ganlikun 0:13413ea9a877 1697 */
ganlikun 0:13413ea9a877 1698 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
ganlikun 0:13413ea9a877 1699 {
ganlikun 0:13413ea9a877 1700 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
ganlikun 0:13413ea9a877 1701 uint32_t PreemptPriorityBits;
ganlikun 0:13413ea9a877 1702 uint32_t SubPriorityBits;
ganlikun 0:13413ea9a877 1703
ganlikun 0:13413ea9a877 1704 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
ganlikun 0:13413ea9a877 1705 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
ganlikun 0:13413ea9a877 1706
ganlikun 0:13413ea9a877 1707 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
ganlikun 0:13413ea9a877 1708 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
ganlikun 0:13413ea9a877 1709 }
ganlikun 0:13413ea9a877 1710
ganlikun 0:13413ea9a877 1711
ganlikun 0:13413ea9a877 1712 /**
ganlikun 0:13413ea9a877 1713 \brief Set Interrupt Vector
ganlikun 0:13413ea9a877 1714 \details Sets an interrupt vector in SRAM based interrupt vector table.
ganlikun 0:13413ea9a877 1715 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1716 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1717 VTOR must been relocated to SRAM before.
ganlikun 0:13413ea9a877 1718 \param [in] IRQn Interrupt number
ganlikun 0:13413ea9a877 1719 \param [in] vector Address of interrupt handler function
ganlikun 0:13413ea9a877 1720 */
ganlikun 0:13413ea9a877 1721 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
ganlikun 0:13413ea9a877 1722 {
ganlikun 0:13413ea9a877 1723 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:13413ea9a877 1724 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
ganlikun 0:13413ea9a877 1725 }
ganlikun 0:13413ea9a877 1726
ganlikun 0:13413ea9a877 1727
ganlikun 0:13413ea9a877 1728 /**
ganlikun 0:13413ea9a877 1729 \brief Get Interrupt Vector
ganlikun 0:13413ea9a877 1730 \details Reads an interrupt vector from interrupt vector table.
ganlikun 0:13413ea9a877 1731 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1732 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1733 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1734 \return Address of interrupt handler function
ganlikun 0:13413ea9a877 1735 */
ganlikun 0:13413ea9a877 1736 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1737 {
ganlikun 0:13413ea9a877 1738 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:13413ea9a877 1739 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
ganlikun 0:13413ea9a877 1740 }
ganlikun 0:13413ea9a877 1741
ganlikun 0:13413ea9a877 1742
ganlikun 0:13413ea9a877 1743 /**
ganlikun 0:13413ea9a877 1744 \brief System Reset
ganlikun 0:13413ea9a877 1745 \details Initiates a system reset request to reset the MCU.
ganlikun 0:13413ea9a877 1746 */
ganlikun 0:13413ea9a877 1747 __STATIC_INLINE void __NVIC_SystemReset(void)
ganlikun 0:13413ea9a877 1748 {
ganlikun 0:13413ea9a877 1749 __DSB(); /* Ensure all outstanding memory accesses included
ganlikun 0:13413ea9a877 1750 buffered write are completed before reset */
ganlikun 0:13413ea9a877 1751 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
ganlikun 0:13413ea9a877 1752 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
ganlikun 0:13413ea9a877 1753 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
ganlikun 0:13413ea9a877 1754 __DSB(); /* Ensure completion of memory access */
ganlikun 0:13413ea9a877 1755
ganlikun 0:13413ea9a877 1756 for(;;) /* wait until reset */
ganlikun 0:13413ea9a877 1757 {
ganlikun 0:13413ea9a877 1758 __NOP();
ganlikun 0:13413ea9a877 1759 }
ganlikun 0:13413ea9a877 1760 }
ganlikun 0:13413ea9a877 1761
ganlikun 0:13413ea9a877 1762 /*@} end of CMSIS_Core_NVICFunctions */
ganlikun 0:13413ea9a877 1763
ganlikun 0:13413ea9a877 1764
ganlikun 0:13413ea9a877 1765 /* ########################## FPU functions #################################### */
ganlikun 0:13413ea9a877 1766 /**
ganlikun 0:13413ea9a877 1767 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1768 \defgroup CMSIS_Core_FpuFunctions FPU Functions
ganlikun 0:13413ea9a877 1769 \brief Function that provides FPU type.
ganlikun 0:13413ea9a877 1770 @{
ganlikun 0:13413ea9a877 1771 */
ganlikun 0:13413ea9a877 1772
ganlikun 0:13413ea9a877 1773 /**
ganlikun 0:13413ea9a877 1774 \brief get FPU type
ganlikun 0:13413ea9a877 1775 \details returns the FPU type
ganlikun 0:13413ea9a877 1776 \returns
ganlikun 0:13413ea9a877 1777 - \b 0: No FPU
ganlikun 0:13413ea9a877 1778 - \b 1: Single precision FPU
ganlikun 0:13413ea9a877 1779 - \b 2: Double + Single precision FPU
ganlikun 0:13413ea9a877 1780 */
ganlikun 0:13413ea9a877 1781 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
ganlikun 0:13413ea9a877 1782 {
ganlikun 0:13413ea9a877 1783 return 0U; /* No FPU */
ganlikun 0:13413ea9a877 1784 }
ganlikun 0:13413ea9a877 1785
ganlikun 0:13413ea9a877 1786
ganlikun 0:13413ea9a877 1787 /*@} end of CMSIS_Core_FpuFunctions */
ganlikun 0:13413ea9a877 1788
ganlikun 0:13413ea9a877 1789
ganlikun 0:13413ea9a877 1790
ganlikun 0:13413ea9a877 1791 /* ################################## SysTick function ############################################ */
ganlikun 0:13413ea9a877 1792 /**
ganlikun 0:13413ea9a877 1793 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
ganlikun 0:13413ea9a877 1795 \brief Functions that configure the System.
ganlikun 0:13413ea9a877 1796 @{
ganlikun 0:13413ea9a877 1797 */
ganlikun 0:13413ea9a877 1798
ganlikun 0:13413ea9a877 1799 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
ganlikun 0:13413ea9a877 1800
ganlikun 0:13413ea9a877 1801 /**
ganlikun 0:13413ea9a877 1802 \brief System Tick Configuration
ganlikun 0:13413ea9a877 1803 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
ganlikun 0:13413ea9a877 1804 Counter is in free running mode to generate periodic interrupts.
ganlikun 0:13413ea9a877 1805 \param [in] ticks Number of ticks between two interrupts.
ganlikun 0:13413ea9a877 1806 \return 0 Function succeeded.
ganlikun 0:13413ea9a877 1807 \return 1 Function failed.
ganlikun 0:13413ea9a877 1808 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ganlikun 0:13413ea9a877 1809 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
ganlikun 0:13413ea9a877 1810 must contain a vendor-specific implementation of this function.
ganlikun 0:13413ea9a877 1811 */
ganlikun 0:13413ea9a877 1812 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ganlikun 0:13413ea9a877 1813 {
ganlikun 0:13413ea9a877 1814 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
ganlikun 0:13413ea9a877 1815 {
ganlikun 0:13413ea9a877 1816 return (1UL); /* Reload value impossible */
ganlikun 0:13413ea9a877 1817 }
ganlikun 0:13413ea9a877 1818
ganlikun 0:13413ea9a877 1819 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
ganlikun 0:13413ea9a877 1820 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
ganlikun 0:13413ea9a877 1821 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
ganlikun 0:13413ea9a877 1822 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
ganlikun 0:13413ea9a877 1823 SysTick_CTRL_TICKINT_Msk |
ganlikun 0:13413ea9a877 1824 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ganlikun 0:13413ea9a877 1825 return (0UL); /* Function successful */
ganlikun 0:13413ea9a877 1826 }
ganlikun 0:13413ea9a877 1827
ganlikun 0:13413ea9a877 1828 #endif
ganlikun 0:13413ea9a877 1829
ganlikun 0:13413ea9a877 1830 /*@} end of CMSIS_Core_SysTickFunctions */
ganlikun 0:13413ea9a877 1831
ganlikun 0:13413ea9a877 1832
ganlikun 0:13413ea9a877 1833
ganlikun 0:13413ea9a877 1834 /* ##################################### Debug In/Output function ########################################### */
ganlikun 0:13413ea9a877 1835 /**
ganlikun 0:13413ea9a877 1836 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1837 \defgroup CMSIS_core_DebugFunctions ITM Functions
ganlikun 0:13413ea9a877 1838 \brief Functions that access the ITM debug interface.
ganlikun 0:13413ea9a877 1839 @{
ganlikun 0:13413ea9a877 1840 */
ganlikun 0:13413ea9a877 1841
ganlikun 0:13413ea9a877 1842 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
ganlikun 0:13413ea9a877 1843 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
ganlikun 0:13413ea9a877 1844
ganlikun 0:13413ea9a877 1845
ganlikun 0:13413ea9a877 1846 /**
ganlikun 0:13413ea9a877 1847 \brief ITM Send Character
ganlikun 0:13413ea9a877 1848 \details Transmits a character via the ITM channel 0, and
ganlikun 0:13413ea9a877 1849 \li Just returns when no debugger is connected that has booked the output.
ganlikun 0:13413ea9a877 1850 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
ganlikun 0:13413ea9a877 1851 \param [in] ch Character to transmit.
ganlikun 0:13413ea9a877 1852 \returns Character to transmit.
ganlikun 0:13413ea9a877 1853 */
ganlikun 0:13413ea9a877 1854 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
ganlikun 0:13413ea9a877 1855 {
ganlikun 0:13413ea9a877 1856 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
ganlikun 0:13413ea9a877 1857 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
ganlikun 0:13413ea9a877 1858 {
ganlikun 0:13413ea9a877 1859 while (ITM->PORT[0U].u32 == 0UL)
ganlikun 0:13413ea9a877 1860 {
ganlikun 0:13413ea9a877 1861 __NOP();
ganlikun 0:13413ea9a877 1862 }
ganlikun 0:13413ea9a877 1863 ITM->PORT[0U].u8 = (uint8_t)ch;
ganlikun 0:13413ea9a877 1864 }
ganlikun 0:13413ea9a877 1865 return (ch);
ganlikun 0:13413ea9a877 1866 }
ganlikun 0:13413ea9a877 1867
ganlikun 0:13413ea9a877 1868
ganlikun 0:13413ea9a877 1869 /**
ganlikun 0:13413ea9a877 1870 \brief ITM Receive Character
ganlikun 0:13413ea9a877 1871 \details Inputs a character via the external variable \ref ITM_RxBuffer.
ganlikun 0:13413ea9a877 1872 \return Received character.
ganlikun 0:13413ea9a877 1873 \return -1 No character pending.
ganlikun 0:13413ea9a877 1874 */
ganlikun 0:13413ea9a877 1875 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
ganlikun 0:13413ea9a877 1876 {
ganlikun 0:13413ea9a877 1877 int32_t ch = -1; /* no character available */
ganlikun 0:13413ea9a877 1878
ganlikun 0:13413ea9a877 1879 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
ganlikun 0:13413ea9a877 1880 {
ganlikun 0:13413ea9a877 1881 ch = ITM_RxBuffer;
ganlikun 0:13413ea9a877 1882 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
ganlikun 0:13413ea9a877 1883 }
ganlikun 0:13413ea9a877 1884
ganlikun 0:13413ea9a877 1885 return (ch);
ganlikun 0:13413ea9a877 1886 }
ganlikun 0:13413ea9a877 1887
ganlikun 0:13413ea9a877 1888
ganlikun 0:13413ea9a877 1889 /**
ganlikun 0:13413ea9a877 1890 \brief ITM Check Character
ganlikun 0:13413ea9a877 1891 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
ganlikun 0:13413ea9a877 1892 \return 0 No character available.
ganlikun 0:13413ea9a877 1893 \return 1 Character available.
ganlikun 0:13413ea9a877 1894 */
ganlikun 0:13413ea9a877 1895 __STATIC_INLINE int32_t ITM_CheckChar (void)
ganlikun 0:13413ea9a877 1896 {
ganlikun 0:13413ea9a877 1897
ganlikun 0:13413ea9a877 1898 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
ganlikun 0:13413ea9a877 1899 {
ganlikun 0:13413ea9a877 1900 return (0); /* no character available */
ganlikun 0:13413ea9a877 1901 }
ganlikun 0:13413ea9a877 1902 else
ganlikun 0:13413ea9a877 1903 {
ganlikun 0:13413ea9a877 1904 return (1); /* character available */
ganlikun 0:13413ea9a877 1905 }
ganlikun 0:13413ea9a877 1906 }
ganlikun 0:13413ea9a877 1907
ganlikun 0:13413ea9a877 1908 /*@} end of CMSIS_core_DebugFunctions */
ganlikun 0:13413ea9a877 1909
ganlikun 0:13413ea9a877 1910
ganlikun 0:13413ea9a877 1911
ganlikun 0:13413ea9a877 1912
ganlikun 0:13413ea9a877 1913 #ifdef __cplusplus
ganlikun 0:13413ea9a877 1914 }
ganlikun 0:13413ea9a877 1915 #endif
ganlikun 0:13413ea9a877 1916
ganlikun 0:13413ea9a877 1917 #endif /* __CORE_CM3_H_DEPENDANT */
ganlikun 0:13413ea9a877 1918
ganlikun 0:13413ea9a877 1919 #endif /* __CMSIS_GENERIC */
ganlikun 0:13413ea9a877 1920