Gan likun / mbed-dev

00

cmsis/core_cm23.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:13413ea9a877 1 /**************************************************************************//**
ganlikun 0:13413ea9a877 2 * @file core_cm23.h
ganlikun 0:13413ea9a877 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
ganlikun 0:13413ea9a877 4 * @version V5.0.2
ganlikun 0:13413ea9a877 5 * @date 13. February 2017
ganlikun 0:13413ea9a877 6 ******************************************************************************/
ganlikun 0:13413ea9a877 7 /*
ganlikun 0:13413ea9a877 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
ganlikun 0:13413ea9a877 9 *
ganlikun 0:13413ea9a877 10 * SPDX-License-Identifier: Apache-2.0
ganlikun 0:13413ea9a877 11 *
ganlikun 0:13413ea9a877 12 * Licensed under the Apache License, Version 2.0 (the License); you may
ganlikun 0:13413ea9a877 13 * not use this file except in compliance with the License.
ganlikun 0:13413ea9a877 14 * You may obtain a copy of the License at
ganlikun 0:13413ea9a877 15 *
ganlikun 0:13413ea9a877 16 * www.apache.org/licenses/LICENSE-2.0
ganlikun 0:13413ea9a877 17 *
ganlikun 0:13413ea9a877 18 * Unless required by applicable law or agreed to in writing, software
ganlikun 0:13413ea9a877 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ganlikun 0:13413ea9a877 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ganlikun 0:13413ea9a877 21 * See the License for the specific language governing permissions and
ganlikun 0:13413ea9a877 22 * limitations under the License.
ganlikun 0:13413ea9a877 23 */
ganlikun 0:13413ea9a877 24
ganlikun 0:13413ea9a877 25 #if defined ( __ICCARM__ )
ganlikun 0:13413ea9a877 26 #pragma system_include /* treat file as system include file for MISRA check */
ganlikun 0:13413ea9a877 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:13413ea9a877 28 #pragma clang system_header /* treat file as system include file */
ganlikun 0:13413ea9a877 29 #endif
ganlikun 0:13413ea9a877 30
ganlikun 0:13413ea9a877 31 #ifndef __CORE_CM23_H_GENERIC
ganlikun 0:13413ea9a877 32 #define __CORE_CM23_H_GENERIC
ganlikun 0:13413ea9a877 33
ganlikun 0:13413ea9a877 34 #include <stdint.h>
ganlikun 0:13413ea9a877 35
ganlikun 0:13413ea9a877 36 #ifdef __cplusplus
ganlikun 0:13413ea9a877 37 extern "C" {
ganlikun 0:13413ea9a877 38 #endif
ganlikun 0:13413ea9a877 39
ganlikun 0:13413ea9a877 40 /**
ganlikun 0:13413ea9a877 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
ganlikun 0:13413ea9a877 42 CMSIS violates the following MISRA-C:2004 rules:
ganlikun 0:13413ea9a877 43
ganlikun 0:13413ea9a877 44 \li Required Rule 8.5, object/function definition in header file.<br>
ganlikun 0:13413ea9a877 45 Function definitions in header files are used to allow 'inlining'.
ganlikun 0:13413ea9a877 46
ganlikun 0:13413ea9a877 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
ganlikun 0:13413ea9a877 48 Unions are used for effective representation of core registers.
ganlikun 0:13413ea9a877 49
ganlikun 0:13413ea9a877 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
ganlikun 0:13413ea9a877 51 Function-like macros are used to allow more efficient code.
ganlikun 0:13413ea9a877 52 */
ganlikun 0:13413ea9a877 53
ganlikun 0:13413ea9a877 54
ganlikun 0:13413ea9a877 55 /*******************************************************************************
ganlikun 0:13413ea9a877 56 * CMSIS definitions
ganlikun 0:13413ea9a877 57 ******************************************************************************/
ganlikun 0:13413ea9a877 58 /**
ganlikun 0:13413ea9a877 59 \ingroup Cortex_M23
ganlikun 0:13413ea9a877 60 @{
ganlikun 0:13413ea9a877 61 */
ganlikun 0:13413ea9a877 62
ganlikun 0:13413ea9a877 63 /* CMSIS cmGrebe definitions */
ganlikun 0:13413ea9a877 64 #define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
ganlikun 0:13413ea9a877 65 #define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
ganlikun 0:13413ea9a877 66 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
ganlikun 0:13413ea9a877 67 __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
ganlikun 0:13413ea9a877 68
ganlikun 0:13413ea9a877 69 #define __CORTEX_M (23U) /*!< Cortex-M Core */
ganlikun 0:13413ea9a877 70
ganlikun 0:13413ea9a877 71 /** __FPU_USED indicates whether an FPU is used or not.
ganlikun 0:13413ea9a877 72 This core does not support an FPU at all
ganlikun 0:13413ea9a877 73 */
ganlikun 0:13413ea9a877 74 #define __FPU_USED 0U
ganlikun 0:13413ea9a877 75
ganlikun 0:13413ea9a877 76 #if defined ( __CC_ARM )
ganlikun 0:13413ea9a877 77 #if defined __TARGET_FPU_VFP
ganlikun 0:13413ea9a877 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 79 #endif
ganlikun 0:13413ea9a877 80
ganlikun 0:13413ea9a877 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:13413ea9a877 82 #if defined __ARM_PCS_VFP
ganlikun 0:13413ea9a877 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 84 #endif
ganlikun 0:13413ea9a877 85
ganlikun 0:13413ea9a877 86 #elif defined ( __GNUC__ )
ganlikun 0:13413ea9a877 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
ganlikun 0:13413ea9a877 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 89 #endif
ganlikun 0:13413ea9a877 90
ganlikun 0:13413ea9a877 91 #elif defined ( __ICCARM__ )
ganlikun 0:13413ea9a877 92 #if defined __ARMVFP__
ganlikun 0:13413ea9a877 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 94 #endif
ganlikun 0:13413ea9a877 95
ganlikun 0:13413ea9a877 96 #elif defined ( __TI_ARM__ )
ganlikun 0:13413ea9a877 97 #if defined __TI_VFP_SUPPORT__
ganlikun 0:13413ea9a877 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 99 #endif
ganlikun 0:13413ea9a877 100
ganlikun 0:13413ea9a877 101 #elif defined ( __TASKING__ )
ganlikun 0:13413ea9a877 102 #if defined __FPU_VFP__
ganlikun 0:13413ea9a877 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 104 #endif
ganlikun 0:13413ea9a877 105
ganlikun 0:13413ea9a877 106 #elif defined ( __CSMC__ )
ganlikun 0:13413ea9a877 107 #if ( __CSMC__ & 0x400U)
ganlikun 0:13413ea9a877 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:13413ea9a877 109 #endif
ganlikun 0:13413ea9a877 110
ganlikun 0:13413ea9a877 111 #endif
ganlikun 0:13413ea9a877 112
ganlikun 0:13413ea9a877 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
ganlikun 0:13413ea9a877 114
ganlikun 0:13413ea9a877 115
ganlikun 0:13413ea9a877 116 #ifdef __cplusplus
ganlikun 0:13413ea9a877 117 }
ganlikun 0:13413ea9a877 118 #endif
ganlikun 0:13413ea9a877 119
ganlikun 0:13413ea9a877 120 #endif /* __CORE_CM23_H_GENERIC */
ganlikun 0:13413ea9a877 121
ganlikun 0:13413ea9a877 122 #ifndef __CMSIS_GENERIC
ganlikun 0:13413ea9a877 123
ganlikun 0:13413ea9a877 124 #ifndef __CORE_CM23_H_DEPENDANT
ganlikun 0:13413ea9a877 125 #define __CORE_CM23_H_DEPENDANT
ganlikun 0:13413ea9a877 126
ganlikun 0:13413ea9a877 127 #ifdef __cplusplus
ganlikun 0:13413ea9a877 128 extern "C" {
ganlikun 0:13413ea9a877 129 #endif
ganlikun 0:13413ea9a877 130
ganlikun 0:13413ea9a877 131 /* check device defines and use defaults */
ganlikun 0:13413ea9a877 132 #if defined __CHECK_DEVICE_DEFINES
ganlikun 0:13413ea9a877 133 #ifndef __CM23_REV
ganlikun 0:13413ea9a877 134 #define __CM23_REV 0x0000U
ganlikun 0:13413ea9a877 135 #warning "__CM23_REV not defined in device header file; using default!"
ganlikun 0:13413ea9a877 136 #endif
ganlikun 0:13413ea9a877 137
ganlikun 0:13413ea9a877 138 #ifndef __FPU_PRESENT
ganlikun 0:13413ea9a877 139 #define __FPU_PRESENT 0U
ganlikun 0:13413ea9a877 140 #warning "__FPU_PRESENT not defined in device header file; using default!"
ganlikun 0:13413ea9a877 141 #endif
ganlikun 0:13413ea9a877 142
ganlikun 0:13413ea9a877 143 #ifndef __MPU_PRESENT
ganlikun 0:13413ea9a877 144 #define __MPU_PRESENT 0U
ganlikun 0:13413ea9a877 145 #warning "__MPU_PRESENT not defined in device header file; using default!"
ganlikun 0:13413ea9a877 146 #endif
ganlikun 0:13413ea9a877 147
ganlikun 0:13413ea9a877 148 #ifndef __SAUREGION_PRESENT
ganlikun 0:13413ea9a877 149 #define __SAUREGION_PRESENT 0U
ganlikun 0:13413ea9a877 150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
ganlikun 0:13413ea9a877 151 #endif
ganlikun 0:13413ea9a877 152
ganlikun 0:13413ea9a877 153 #ifndef __VTOR_PRESENT
ganlikun 0:13413ea9a877 154 #define __VTOR_PRESENT 0U
ganlikun 0:13413ea9a877 155 #warning "__VTOR_PRESENT not defined in device header file; using default!"
ganlikun 0:13413ea9a877 156 #endif
ganlikun 0:13413ea9a877 157
ganlikun 0:13413ea9a877 158 #ifndef __NVIC_PRIO_BITS
ganlikun 0:13413ea9a877 159 #define __NVIC_PRIO_BITS 2U
ganlikun 0:13413ea9a877 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
ganlikun 0:13413ea9a877 161 #endif
ganlikun 0:13413ea9a877 162
ganlikun 0:13413ea9a877 163 #ifndef __Vendor_SysTickConfig
ganlikun 0:13413ea9a877 164 #define __Vendor_SysTickConfig 0U
ganlikun 0:13413ea9a877 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
ganlikun 0:13413ea9a877 166 #endif
ganlikun 0:13413ea9a877 167
ganlikun 0:13413ea9a877 168 #ifndef __ETM_PRESENT
ganlikun 0:13413ea9a877 169 #define __ETM_PRESENT 0U
ganlikun 0:13413ea9a877 170 #warning "__ETM_PRESENT not defined in device header file; using default!"
ganlikun 0:13413ea9a877 171 #endif
ganlikun 0:13413ea9a877 172
ganlikun 0:13413ea9a877 173 #ifndef __MTB_PRESENT
ganlikun 0:13413ea9a877 174 #define __MTB_PRESENT 0U
ganlikun 0:13413ea9a877 175 #warning "__MTB_PRESENT not defined in device header file; using default!"
ganlikun 0:13413ea9a877 176 #endif
ganlikun 0:13413ea9a877 177
ganlikun 0:13413ea9a877 178 #endif
ganlikun 0:13413ea9a877 179
ganlikun 0:13413ea9a877 180 /* IO definitions (access restrictions to peripheral registers) */
ganlikun 0:13413ea9a877 181 /**
ganlikun 0:13413ea9a877 182 \defgroup CMSIS_glob_defs CMSIS Global Defines
ganlikun 0:13413ea9a877 183
ganlikun 0:13413ea9a877 184 <strong>IO Type Qualifiers</strong> are used
ganlikun 0:13413ea9a877 185 \li to specify the access to peripheral variables.
ganlikun 0:13413ea9a877 186 \li for automatic generation of peripheral register debug information.
ganlikun 0:13413ea9a877 187 */
ganlikun 0:13413ea9a877 188 #ifdef __cplusplus
ganlikun 0:13413ea9a877 189 #define __I volatile /*!< Defines 'read only' permissions */
ganlikun 0:13413ea9a877 190 #else
ganlikun 0:13413ea9a877 191 #define __I volatile const /*!< Defines 'read only' permissions */
ganlikun 0:13413ea9a877 192 #endif
ganlikun 0:13413ea9a877 193 #define __O volatile /*!< Defines 'write only' permissions */
ganlikun 0:13413ea9a877 194 #define __IO volatile /*!< Defines 'read / write' permissions */
ganlikun 0:13413ea9a877 195
ganlikun 0:13413ea9a877 196 /* following defines should be used for structure members */
ganlikun 0:13413ea9a877 197 #define __IM volatile const /*! Defines 'read only' structure member permissions */
ganlikun 0:13413ea9a877 198 #define __OM volatile /*! Defines 'write only' structure member permissions */
ganlikun 0:13413ea9a877 199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
ganlikun 0:13413ea9a877 200
ganlikun 0:13413ea9a877 201 /*@} end of group Cortex_M23 */
ganlikun 0:13413ea9a877 202
ganlikun 0:13413ea9a877 203
ganlikun 0:13413ea9a877 204
ganlikun 0:13413ea9a877 205 /*******************************************************************************
ganlikun 0:13413ea9a877 206 * Register Abstraction
ganlikun 0:13413ea9a877 207 Core Register contain:
ganlikun 0:13413ea9a877 208 - Core Register
ganlikun 0:13413ea9a877 209 - Core NVIC Register
ganlikun 0:13413ea9a877 210 - Core SCB Register
ganlikun 0:13413ea9a877 211 - Core SysTick Register
ganlikun 0:13413ea9a877 212 - Core Debug Register
ganlikun 0:13413ea9a877 213 - Core MPU Register
ganlikun 0:13413ea9a877 214 - Core SAU Register
ganlikun 0:13413ea9a877 215 ******************************************************************************/
ganlikun 0:13413ea9a877 216 /**
ganlikun 0:13413ea9a877 217 \defgroup CMSIS_core_register Defines and Type Definitions
ganlikun 0:13413ea9a877 218 \brief Type definitions and defines for Cortex-M processor based devices.
ganlikun 0:13413ea9a877 219 */
ganlikun 0:13413ea9a877 220
ganlikun 0:13413ea9a877 221 /**
ganlikun 0:13413ea9a877 222 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 223 \defgroup CMSIS_CORE Status and Control Registers
ganlikun 0:13413ea9a877 224 \brief Core Register type definitions.
ganlikun 0:13413ea9a877 225 @{
ganlikun 0:13413ea9a877 226 */
ganlikun 0:13413ea9a877 227
ganlikun 0:13413ea9a877 228 /**
ganlikun 0:13413ea9a877 229 \brief Union type to access the Application Program Status Register (APSR).
ganlikun 0:13413ea9a877 230 */
ganlikun 0:13413ea9a877 231 typedef union
ganlikun 0:13413ea9a877 232 {
ganlikun 0:13413ea9a877 233 struct
ganlikun 0:13413ea9a877 234 {
ganlikun 0:13413ea9a877 235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
ganlikun 0:13413ea9a877 236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:13413ea9a877 237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:13413ea9a877 238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:13413ea9a877 239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:13413ea9a877 240 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 241 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 242 } APSR_Type;
ganlikun 0:13413ea9a877 243
ganlikun 0:13413ea9a877 244 /* APSR Register Definitions */
ganlikun 0:13413ea9a877 245 #define APSR_N_Pos 31U /*!< APSR: N Position */
ganlikun 0:13413ea9a877 246 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
ganlikun 0:13413ea9a877 247
ganlikun 0:13413ea9a877 248 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
ganlikun 0:13413ea9a877 249 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
ganlikun 0:13413ea9a877 250
ganlikun 0:13413ea9a877 251 #define APSR_C_Pos 29U /*!< APSR: C Position */
ganlikun 0:13413ea9a877 252 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
ganlikun 0:13413ea9a877 253
ganlikun 0:13413ea9a877 254 #define APSR_V_Pos 28U /*!< APSR: V Position */
ganlikun 0:13413ea9a877 255 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
ganlikun 0:13413ea9a877 256
ganlikun 0:13413ea9a877 257
ganlikun 0:13413ea9a877 258 /**
ganlikun 0:13413ea9a877 259 \brief Union type to access the Interrupt Program Status Register (IPSR).
ganlikun 0:13413ea9a877 260 */
ganlikun 0:13413ea9a877 261 typedef union
ganlikun 0:13413ea9a877 262 {
ganlikun 0:13413ea9a877 263 struct
ganlikun 0:13413ea9a877 264 {
ganlikun 0:13413ea9a877 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:13413ea9a877 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
ganlikun 0:13413ea9a877 267 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 268 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 269 } IPSR_Type;
ganlikun 0:13413ea9a877 270
ganlikun 0:13413ea9a877 271 /* IPSR Register Definitions */
ganlikun 0:13413ea9a877 272 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
ganlikun 0:13413ea9a877 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
ganlikun 0:13413ea9a877 274
ganlikun 0:13413ea9a877 275
ganlikun 0:13413ea9a877 276 /**
ganlikun 0:13413ea9a877 277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ganlikun 0:13413ea9a877 278 */
ganlikun 0:13413ea9a877 279 typedef union
ganlikun 0:13413ea9a877 280 {
ganlikun 0:13413ea9a877 281 struct
ganlikun 0:13413ea9a877 282 {
ganlikun 0:13413ea9a877 283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:13413ea9a877 284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
ganlikun 0:13413ea9a877 285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
ganlikun 0:13413ea9a877 286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
ganlikun 0:13413ea9a877 287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:13413ea9a877 288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:13413ea9a877 289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:13413ea9a877 290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:13413ea9a877 291 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 292 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 293 } xPSR_Type;
ganlikun 0:13413ea9a877 294
ganlikun 0:13413ea9a877 295 /* xPSR Register Definitions */
ganlikun 0:13413ea9a877 296 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
ganlikun 0:13413ea9a877 297 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
ganlikun 0:13413ea9a877 298
ganlikun 0:13413ea9a877 299 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
ganlikun 0:13413ea9a877 300 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
ganlikun 0:13413ea9a877 301
ganlikun 0:13413ea9a877 302 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
ganlikun 0:13413ea9a877 303 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
ganlikun 0:13413ea9a877 304
ganlikun 0:13413ea9a877 305 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
ganlikun 0:13413ea9a877 306 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
ganlikun 0:13413ea9a877 307
ganlikun 0:13413ea9a877 308 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
ganlikun 0:13413ea9a877 309 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
ganlikun 0:13413ea9a877 310
ganlikun 0:13413ea9a877 311 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
ganlikun 0:13413ea9a877 312 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
ganlikun 0:13413ea9a877 313
ganlikun 0:13413ea9a877 314
ganlikun 0:13413ea9a877 315 /**
ganlikun 0:13413ea9a877 316 \brief Union type to access the Control Registers (CONTROL).
ganlikun 0:13413ea9a877 317 */
ganlikun 0:13413ea9a877 318 typedef union
ganlikun 0:13413ea9a877 319 {
ganlikun 0:13413ea9a877 320 struct
ganlikun 0:13413ea9a877 321 {
ganlikun 0:13413ea9a877 322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
ganlikun 0:13413ea9a877 323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
ganlikun 0:13413ea9a877 324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
ganlikun 0:13413ea9a877 325 } b; /*!< Structure used for bit access */
ganlikun 0:13413ea9a877 326 uint32_t w; /*!< Type used for word access */
ganlikun 0:13413ea9a877 327 } CONTROL_Type;
ganlikun 0:13413ea9a877 328
ganlikun 0:13413ea9a877 329 /* CONTROL Register Definitions */
ganlikun 0:13413ea9a877 330 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
ganlikun 0:13413ea9a877 331 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
ganlikun 0:13413ea9a877 332
ganlikun 0:13413ea9a877 333 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
ganlikun 0:13413ea9a877 334 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
ganlikun 0:13413ea9a877 335
ganlikun 0:13413ea9a877 336 /*@} end of group CMSIS_CORE */
ganlikun 0:13413ea9a877 337
ganlikun 0:13413ea9a877 338
ganlikun 0:13413ea9a877 339 /**
ganlikun 0:13413ea9a877 340 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
ganlikun 0:13413ea9a877 342 \brief Type definitions for the NVIC Registers
ganlikun 0:13413ea9a877 343 @{
ganlikun 0:13413ea9a877 344 */
ganlikun 0:13413ea9a877 345
ganlikun 0:13413ea9a877 346 /**
ganlikun 0:13413ea9a877 347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
ganlikun 0:13413ea9a877 348 */
ganlikun 0:13413ea9a877 349 typedef struct
ganlikun 0:13413ea9a877 350 {
ganlikun 0:13413ea9a877 351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
ganlikun 0:13413ea9a877 352 uint32_t RESERVED0[16U];
ganlikun 0:13413ea9a877 353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
ganlikun 0:13413ea9a877 354 uint32_t RSERVED1[16U];
ganlikun 0:13413ea9a877 355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
ganlikun 0:13413ea9a877 356 uint32_t RESERVED2[16U];
ganlikun 0:13413ea9a877 357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
ganlikun 0:13413ea9a877 358 uint32_t RESERVED3[16U];
ganlikun 0:13413ea9a877 359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
ganlikun 0:13413ea9a877 360 uint32_t RESERVED4[16U];
ganlikun 0:13413ea9a877 361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
ganlikun 0:13413ea9a877 362 uint32_t RESERVED5[16U];
ganlikun 0:13413ea9a877 363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
ganlikun 0:13413ea9a877 364 } NVIC_Type;
ganlikun 0:13413ea9a877 365
ganlikun 0:13413ea9a877 366 /*@} end of group CMSIS_NVIC */
ganlikun 0:13413ea9a877 367
ganlikun 0:13413ea9a877 368
ganlikun 0:13413ea9a877 369 /**
ganlikun 0:13413ea9a877 370 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 371 \defgroup CMSIS_SCB System Control Block (SCB)
ganlikun 0:13413ea9a877 372 \brief Type definitions for the System Control Block Registers
ganlikun 0:13413ea9a877 373 @{
ganlikun 0:13413ea9a877 374 */
ganlikun 0:13413ea9a877 375
ganlikun 0:13413ea9a877 376 /**
ganlikun 0:13413ea9a877 377 \brief Structure type to access the System Control Block (SCB).
ganlikun 0:13413ea9a877 378 */
ganlikun 0:13413ea9a877 379 typedef struct
ganlikun 0:13413ea9a877 380 {
ganlikun 0:13413ea9a877 381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
ganlikun 0:13413ea9a877 382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
ganlikun 0:13413ea9a877 383 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:13413ea9a877 384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
ganlikun 0:13413ea9a877 385 #else
ganlikun 0:13413ea9a877 386 uint32_t RESERVED0;
ganlikun 0:13413ea9a877 387 #endif
ganlikun 0:13413ea9a877 388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
ganlikun 0:13413ea9a877 389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
ganlikun 0:13413ea9a877 390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
ganlikun 0:13413ea9a877 391 uint32_t RESERVED1;
ganlikun 0:13413ea9a877 392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
ganlikun 0:13413ea9a877 393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
ganlikun 0:13413ea9a877 394 } SCB_Type;
ganlikun 0:13413ea9a877 395
ganlikun 0:13413ea9a877 396 /* SCB CPUID Register Definitions */
ganlikun 0:13413ea9a877 397 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
ganlikun 0:13413ea9a877 398 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
ganlikun 0:13413ea9a877 399
ganlikun 0:13413ea9a877 400 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
ganlikun 0:13413ea9a877 401 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
ganlikun 0:13413ea9a877 402
ganlikun 0:13413ea9a877 403 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
ganlikun 0:13413ea9a877 404 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
ganlikun 0:13413ea9a877 405
ganlikun 0:13413ea9a877 406 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
ganlikun 0:13413ea9a877 407 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
ganlikun 0:13413ea9a877 408
ganlikun 0:13413ea9a877 409 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
ganlikun 0:13413ea9a877 410 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
ganlikun 0:13413ea9a877 411
ganlikun 0:13413ea9a877 412 /* SCB Interrupt Control State Register Definitions */
ganlikun 0:13413ea9a877 413 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
ganlikun 0:13413ea9a877 414 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
ganlikun 0:13413ea9a877 415
ganlikun 0:13413ea9a877 416 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
ganlikun 0:13413ea9a877 417 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
ganlikun 0:13413ea9a877 418
ganlikun 0:13413ea9a877 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
ganlikun 0:13413ea9a877 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
ganlikun 0:13413ea9a877 421
ganlikun 0:13413ea9a877 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
ganlikun 0:13413ea9a877 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
ganlikun 0:13413ea9a877 424
ganlikun 0:13413ea9a877 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
ganlikun 0:13413ea9a877 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
ganlikun 0:13413ea9a877 427
ganlikun 0:13413ea9a877 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
ganlikun 0:13413ea9a877 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
ganlikun 0:13413ea9a877 430
ganlikun 0:13413ea9a877 431 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
ganlikun 0:13413ea9a877 432 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
ganlikun 0:13413ea9a877 433
ganlikun 0:13413ea9a877 434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
ganlikun 0:13413ea9a877 435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
ganlikun 0:13413ea9a877 436
ganlikun 0:13413ea9a877 437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
ganlikun 0:13413ea9a877 438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
ganlikun 0:13413ea9a877 439
ganlikun 0:13413ea9a877 440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
ganlikun 0:13413ea9a877 441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
ganlikun 0:13413ea9a877 442
ganlikun 0:13413ea9a877 443 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
ganlikun 0:13413ea9a877 444 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
ganlikun 0:13413ea9a877 445
ganlikun 0:13413ea9a877 446 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
ganlikun 0:13413ea9a877 447 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
ganlikun 0:13413ea9a877 448
ganlikun 0:13413ea9a877 449 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:13413ea9a877 450 /* SCB Vector Table Offset Register Definitions */
ganlikun 0:13413ea9a877 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
ganlikun 0:13413ea9a877 452 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
ganlikun 0:13413ea9a877 453 #endif
ganlikun 0:13413ea9a877 454
ganlikun 0:13413ea9a877 455 /* SCB Application Interrupt and Reset Control Register Definitions */
ganlikun 0:13413ea9a877 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
ganlikun 0:13413ea9a877 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
ganlikun 0:13413ea9a877 458
ganlikun 0:13413ea9a877 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
ganlikun 0:13413ea9a877 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
ganlikun 0:13413ea9a877 461
ganlikun 0:13413ea9a877 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
ganlikun 0:13413ea9a877 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
ganlikun 0:13413ea9a877 464
ganlikun 0:13413ea9a877 465 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
ganlikun 0:13413ea9a877 466 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
ganlikun 0:13413ea9a877 467
ganlikun 0:13413ea9a877 468 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
ganlikun 0:13413ea9a877 469 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
ganlikun 0:13413ea9a877 470
ganlikun 0:13413ea9a877 471 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
ganlikun 0:13413ea9a877 472 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
ganlikun 0:13413ea9a877 473
ganlikun 0:13413ea9a877 474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
ganlikun 0:13413ea9a877 475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
ganlikun 0:13413ea9a877 476
ganlikun 0:13413ea9a877 477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
ganlikun 0:13413ea9a877 478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
ganlikun 0:13413ea9a877 479
ganlikun 0:13413ea9a877 480 /* SCB System Control Register Definitions */
ganlikun 0:13413ea9a877 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
ganlikun 0:13413ea9a877 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
ganlikun 0:13413ea9a877 483
ganlikun 0:13413ea9a877 484 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
ganlikun 0:13413ea9a877 485 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
ganlikun 0:13413ea9a877 486
ganlikun 0:13413ea9a877 487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
ganlikun 0:13413ea9a877 488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
ganlikun 0:13413ea9a877 489
ganlikun 0:13413ea9a877 490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
ganlikun 0:13413ea9a877 491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
ganlikun 0:13413ea9a877 492
ganlikun 0:13413ea9a877 493 /* SCB Configuration Control Register Definitions */
ganlikun 0:13413ea9a877 494 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
ganlikun 0:13413ea9a877 495 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
ganlikun 0:13413ea9a877 496
ganlikun 0:13413ea9a877 497 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
ganlikun 0:13413ea9a877 498 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
ganlikun 0:13413ea9a877 499
ganlikun 0:13413ea9a877 500 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
ganlikun 0:13413ea9a877 501 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
ganlikun 0:13413ea9a877 502
ganlikun 0:13413ea9a877 503 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
ganlikun 0:13413ea9a877 504 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
ganlikun 0:13413ea9a877 505
ganlikun 0:13413ea9a877 506 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
ganlikun 0:13413ea9a877 507 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
ganlikun 0:13413ea9a877 508
ganlikun 0:13413ea9a877 509 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
ganlikun 0:13413ea9a877 510 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
ganlikun 0:13413ea9a877 511
ganlikun 0:13413ea9a877 512 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
ganlikun 0:13413ea9a877 513 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
ganlikun 0:13413ea9a877 514
ganlikun 0:13413ea9a877 515 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
ganlikun 0:13413ea9a877 516 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
ganlikun 0:13413ea9a877 517
ganlikun 0:13413ea9a877 518 /* SCB System Handler Control and State Register Definitions */
ganlikun 0:13413ea9a877 519 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
ganlikun 0:13413ea9a877 520 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
ganlikun 0:13413ea9a877 521
ganlikun 0:13413ea9a877 522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
ganlikun 0:13413ea9a877 523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
ganlikun 0:13413ea9a877 524
ganlikun 0:13413ea9a877 525 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
ganlikun 0:13413ea9a877 526 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
ganlikun 0:13413ea9a877 527
ganlikun 0:13413ea9a877 528 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
ganlikun 0:13413ea9a877 529 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
ganlikun 0:13413ea9a877 530
ganlikun 0:13413ea9a877 531 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
ganlikun 0:13413ea9a877 532 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
ganlikun 0:13413ea9a877 533
ganlikun 0:13413ea9a877 534 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
ganlikun 0:13413ea9a877 535 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
ganlikun 0:13413ea9a877 536
ganlikun 0:13413ea9a877 537 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
ganlikun 0:13413ea9a877 538 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
ganlikun 0:13413ea9a877 539
ganlikun 0:13413ea9a877 540 /*@} end of group CMSIS_SCB */
ganlikun 0:13413ea9a877 541
ganlikun 0:13413ea9a877 542
ganlikun 0:13413ea9a877 543 /**
ganlikun 0:13413ea9a877 544 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 545 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
ganlikun 0:13413ea9a877 546 \brief Type definitions for the System Timer Registers.
ganlikun 0:13413ea9a877 547 @{
ganlikun 0:13413ea9a877 548 */
ganlikun 0:13413ea9a877 549
ganlikun 0:13413ea9a877 550 /**
ganlikun 0:13413ea9a877 551 \brief Structure type to access the System Timer (SysTick).
ganlikun 0:13413ea9a877 552 */
ganlikun 0:13413ea9a877 553 typedef struct
ganlikun 0:13413ea9a877 554 {
ganlikun 0:13413ea9a877 555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
ganlikun 0:13413ea9a877 556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
ganlikun 0:13413ea9a877 557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
ganlikun 0:13413ea9a877 558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
ganlikun 0:13413ea9a877 559 } SysTick_Type;
ganlikun 0:13413ea9a877 560
ganlikun 0:13413ea9a877 561 /* SysTick Control / Status Register Definitions */
ganlikun 0:13413ea9a877 562 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
ganlikun 0:13413ea9a877 563 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
ganlikun 0:13413ea9a877 564
ganlikun 0:13413ea9a877 565 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
ganlikun 0:13413ea9a877 566 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
ganlikun 0:13413ea9a877 567
ganlikun 0:13413ea9a877 568 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
ganlikun 0:13413ea9a877 569 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
ganlikun 0:13413ea9a877 570
ganlikun 0:13413ea9a877 571 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
ganlikun 0:13413ea9a877 572 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
ganlikun 0:13413ea9a877 573
ganlikun 0:13413ea9a877 574 /* SysTick Reload Register Definitions */
ganlikun 0:13413ea9a877 575 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
ganlikun 0:13413ea9a877 576 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
ganlikun 0:13413ea9a877 577
ganlikun 0:13413ea9a877 578 /* SysTick Current Register Definitions */
ganlikun 0:13413ea9a877 579 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
ganlikun 0:13413ea9a877 580 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
ganlikun 0:13413ea9a877 581
ganlikun 0:13413ea9a877 582 /* SysTick Calibration Register Definitions */
ganlikun 0:13413ea9a877 583 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
ganlikun 0:13413ea9a877 584 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
ganlikun 0:13413ea9a877 585
ganlikun 0:13413ea9a877 586 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
ganlikun 0:13413ea9a877 587 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
ganlikun 0:13413ea9a877 588
ganlikun 0:13413ea9a877 589 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
ganlikun 0:13413ea9a877 590 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
ganlikun 0:13413ea9a877 591
ganlikun 0:13413ea9a877 592 /*@} end of group CMSIS_SysTick */
ganlikun 0:13413ea9a877 593
ganlikun 0:13413ea9a877 594
ganlikun 0:13413ea9a877 595 /**
ganlikun 0:13413ea9a877 596 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
ganlikun 0:13413ea9a877 598 \brief Type definitions for the Data Watchpoint and Trace (DWT)
ganlikun 0:13413ea9a877 599 @{
ganlikun 0:13413ea9a877 600 */
ganlikun 0:13413ea9a877 601
ganlikun 0:13413ea9a877 602 /**
ganlikun 0:13413ea9a877 603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
ganlikun 0:13413ea9a877 604 */
ganlikun 0:13413ea9a877 605 typedef struct
ganlikun 0:13413ea9a877 606 {
ganlikun 0:13413ea9a877 607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
ganlikun 0:13413ea9a877 608 uint32_t RESERVED0[6U];
ganlikun 0:13413ea9a877 609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
ganlikun 0:13413ea9a877 610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
ganlikun 0:13413ea9a877 611 uint32_t RESERVED1[1U];
ganlikun 0:13413ea9a877 612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
ganlikun 0:13413ea9a877 613 uint32_t RESERVED2[1U];
ganlikun 0:13413ea9a877 614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
ganlikun 0:13413ea9a877 615 uint32_t RESERVED3[1U];
ganlikun 0:13413ea9a877 616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
ganlikun 0:13413ea9a877 617 uint32_t RESERVED4[1U];
ganlikun 0:13413ea9a877 618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
ganlikun 0:13413ea9a877 619 uint32_t RESERVED5[1U];
ganlikun 0:13413ea9a877 620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
ganlikun 0:13413ea9a877 621 uint32_t RESERVED6[1U];
ganlikun 0:13413ea9a877 622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
ganlikun 0:13413ea9a877 623 uint32_t RESERVED7[1U];
ganlikun 0:13413ea9a877 624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
ganlikun 0:13413ea9a877 625 uint32_t RESERVED8[1U];
ganlikun 0:13413ea9a877 626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
ganlikun 0:13413ea9a877 627 uint32_t RESERVED9[1U];
ganlikun 0:13413ea9a877 628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
ganlikun 0:13413ea9a877 629 uint32_t RESERVED10[1U];
ganlikun 0:13413ea9a877 630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
ganlikun 0:13413ea9a877 631 uint32_t RESERVED11[1U];
ganlikun 0:13413ea9a877 632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
ganlikun 0:13413ea9a877 633 uint32_t RESERVED12[1U];
ganlikun 0:13413ea9a877 634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
ganlikun 0:13413ea9a877 635 uint32_t RESERVED13[1U];
ganlikun 0:13413ea9a877 636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
ganlikun 0:13413ea9a877 637 uint32_t RESERVED14[1U];
ganlikun 0:13413ea9a877 638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
ganlikun 0:13413ea9a877 639 uint32_t RESERVED15[1U];
ganlikun 0:13413ea9a877 640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
ganlikun 0:13413ea9a877 641 uint32_t RESERVED16[1U];
ganlikun 0:13413ea9a877 642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
ganlikun 0:13413ea9a877 643 uint32_t RESERVED17[1U];
ganlikun 0:13413ea9a877 644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
ganlikun 0:13413ea9a877 645 uint32_t RESERVED18[1U];
ganlikun 0:13413ea9a877 646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
ganlikun 0:13413ea9a877 647 uint32_t RESERVED19[1U];
ganlikun 0:13413ea9a877 648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
ganlikun 0:13413ea9a877 649 uint32_t RESERVED20[1U];
ganlikun 0:13413ea9a877 650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
ganlikun 0:13413ea9a877 651 uint32_t RESERVED21[1U];
ganlikun 0:13413ea9a877 652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
ganlikun 0:13413ea9a877 653 uint32_t RESERVED22[1U];
ganlikun 0:13413ea9a877 654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
ganlikun 0:13413ea9a877 655 uint32_t RESERVED23[1U];
ganlikun 0:13413ea9a877 656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
ganlikun 0:13413ea9a877 657 uint32_t RESERVED24[1U];
ganlikun 0:13413ea9a877 658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
ganlikun 0:13413ea9a877 659 uint32_t RESERVED25[1U];
ganlikun 0:13413ea9a877 660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
ganlikun 0:13413ea9a877 661 uint32_t RESERVED26[1U];
ganlikun 0:13413ea9a877 662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
ganlikun 0:13413ea9a877 663 uint32_t RESERVED27[1U];
ganlikun 0:13413ea9a877 664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
ganlikun 0:13413ea9a877 665 uint32_t RESERVED28[1U];
ganlikun 0:13413ea9a877 666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
ganlikun 0:13413ea9a877 667 uint32_t RESERVED29[1U];
ganlikun 0:13413ea9a877 668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
ganlikun 0:13413ea9a877 669 uint32_t RESERVED30[1U];
ganlikun 0:13413ea9a877 670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
ganlikun 0:13413ea9a877 671 uint32_t RESERVED31[1U];
ganlikun 0:13413ea9a877 672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
ganlikun 0:13413ea9a877 673 } DWT_Type;
ganlikun 0:13413ea9a877 674
ganlikun 0:13413ea9a877 675 /* DWT Control Register Definitions */
ganlikun 0:13413ea9a877 676 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
ganlikun 0:13413ea9a877 677 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
ganlikun 0:13413ea9a877 678
ganlikun 0:13413ea9a877 679 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
ganlikun 0:13413ea9a877 680 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
ganlikun 0:13413ea9a877 681
ganlikun 0:13413ea9a877 682 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
ganlikun 0:13413ea9a877 683 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
ganlikun 0:13413ea9a877 684
ganlikun 0:13413ea9a877 685 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
ganlikun 0:13413ea9a877 686 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
ganlikun 0:13413ea9a877 687
ganlikun 0:13413ea9a877 688 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
ganlikun 0:13413ea9a877 689 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
ganlikun 0:13413ea9a877 690
ganlikun 0:13413ea9a877 691 /* DWT Comparator Function Register Definitions */
ganlikun 0:13413ea9a877 692 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
ganlikun 0:13413ea9a877 693 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
ganlikun 0:13413ea9a877 694
ganlikun 0:13413ea9a877 695 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
ganlikun 0:13413ea9a877 696 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
ganlikun 0:13413ea9a877 697
ganlikun 0:13413ea9a877 698 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
ganlikun 0:13413ea9a877 699 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
ganlikun 0:13413ea9a877 700
ganlikun 0:13413ea9a877 701 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
ganlikun 0:13413ea9a877 702 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
ganlikun 0:13413ea9a877 703
ganlikun 0:13413ea9a877 704 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
ganlikun 0:13413ea9a877 705 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
ganlikun 0:13413ea9a877 706
ganlikun 0:13413ea9a877 707 /*@}*/ /* end of group CMSIS_DWT */
ganlikun 0:13413ea9a877 708
ganlikun 0:13413ea9a877 709
ganlikun 0:13413ea9a877 710 /**
ganlikun 0:13413ea9a877 711 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 712 \defgroup CMSIS_TPI Trace Port Interface (TPI)
ganlikun 0:13413ea9a877 713 \brief Type definitions for the Trace Port Interface (TPI)
ganlikun 0:13413ea9a877 714 @{
ganlikun 0:13413ea9a877 715 */
ganlikun 0:13413ea9a877 716
ganlikun 0:13413ea9a877 717 /**
ganlikun 0:13413ea9a877 718 \brief Structure type to access the Trace Port Interface Register (TPI).
ganlikun 0:13413ea9a877 719 */
ganlikun 0:13413ea9a877 720 typedef struct
ganlikun 0:13413ea9a877 721 {
ganlikun 0:13413ea9a877 722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
ganlikun 0:13413ea9a877 723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
ganlikun 0:13413ea9a877 724 uint32_t RESERVED0[2U];
ganlikun 0:13413ea9a877 725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
ganlikun 0:13413ea9a877 726 uint32_t RESERVED1[55U];
ganlikun 0:13413ea9a877 727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
ganlikun 0:13413ea9a877 728 uint32_t RESERVED2[131U];
ganlikun 0:13413ea9a877 729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
ganlikun 0:13413ea9a877 730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
ganlikun 0:13413ea9a877 731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
ganlikun 0:13413ea9a877 732 uint32_t RESERVED3[759U];
ganlikun 0:13413ea9a877 733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
ganlikun 0:13413ea9a877 734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
ganlikun 0:13413ea9a877 735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
ganlikun 0:13413ea9a877 736 uint32_t RESERVED4[1U];
ganlikun 0:13413ea9a877 737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
ganlikun 0:13413ea9a877 738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
ganlikun 0:13413ea9a877 739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
ganlikun 0:13413ea9a877 740 uint32_t RESERVED5[39U];
ganlikun 0:13413ea9a877 741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
ganlikun 0:13413ea9a877 742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
ganlikun 0:13413ea9a877 743 uint32_t RESERVED7[8U];
ganlikun 0:13413ea9a877 744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
ganlikun 0:13413ea9a877 745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
ganlikun 0:13413ea9a877 746 } TPI_Type;
ganlikun 0:13413ea9a877 747
ganlikun 0:13413ea9a877 748 /* TPI Asynchronous Clock Prescaler Register Definitions */
ganlikun 0:13413ea9a877 749 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
ganlikun 0:13413ea9a877 750 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
ganlikun 0:13413ea9a877 751
ganlikun 0:13413ea9a877 752 /* TPI Selected Pin Protocol Register Definitions */
ganlikun 0:13413ea9a877 753 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
ganlikun 0:13413ea9a877 754 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
ganlikun 0:13413ea9a877 755
ganlikun 0:13413ea9a877 756 /* TPI Formatter and Flush Status Register Definitions */
ganlikun 0:13413ea9a877 757 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
ganlikun 0:13413ea9a877 758 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
ganlikun 0:13413ea9a877 759
ganlikun 0:13413ea9a877 760 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
ganlikun 0:13413ea9a877 761 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
ganlikun 0:13413ea9a877 762
ganlikun 0:13413ea9a877 763 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
ganlikun 0:13413ea9a877 764 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
ganlikun 0:13413ea9a877 765
ganlikun 0:13413ea9a877 766 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
ganlikun 0:13413ea9a877 767 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
ganlikun 0:13413ea9a877 768
ganlikun 0:13413ea9a877 769 /* TPI Formatter and Flush Control Register Definitions */
ganlikun 0:13413ea9a877 770 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
ganlikun 0:13413ea9a877 771 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
ganlikun 0:13413ea9a877 772
ganlikun 0:13413ea9a877 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
ganlikun 0:13413ea9a877 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
ganlikun 0:13413ea9a877 775
ganlikun 0:13413ea9a877 776 /* TPI TRIGGER Register Definitions */
ganlikun 0:13413ea9a877 777 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
ganlikun 0:13413ea9a877 778 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
ganlikun 0:13413ea9a877 779
ganlikun 0:13413ea9a877 780 /* TPI Integration ETM Data Register Definitions (FIFO0) */
ganlikun 0:13413ea9a877 781 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
ganlikun 0:13413ea9a877 782 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
ganlikun 0:13413ea9a877 783
ganlikun 0:13413ea9a877 784 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
ganlikun 0:13413ea9a877 785 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
ganlikun 0:13413ea9a877 786
ganlikun 0:13413ea9a877 787 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
ganlikun 0:13413ea9a877 788 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
ganlikun 0:13413ea9a877 789
ganlikun 0:13413ea9a877 790 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
ganlikun 0:13413ea9a877 791 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
ganlikun 0:13413ea9a877 792
ganlikun 0:13413ea9a877 793 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
ganlikun 0:13413ea9a877 794 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
ganlikun 0:13413ea9a877 795
ganlikun 0:13413ea9a877 796 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
ganlikun 0:13413ea9a877 797 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
ganlikun 0:13413ea9a877 798
ganlikun 0:13413ea9a877 799 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
ganlikun 0:13413ea9a877 800 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
ganlikun 0:13413ea9a877 801
ganlikun 0:13413ea9a877 802 /* TPI ITATBCTR2 Register Definitions */
ganlikun 0:13413ea9a877 803 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
ganlikun 0:13413ea9a877 804 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
ganlikun 0:13413ea9a877 805
ganlikun 0:13413ea9a877 806 /* TPI Integration ITM Data Register Definitions (FIFO1) */
ganlikun 0:13413ea9a877 807 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
ganlikun 0:13413ea9a877 808 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
ganlikun 0:13413ea9a877 809
ganlikun 0:13413ea9a877 810 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
ganlikun 0:13413ea9a877 811 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
ganlikun 0:13413ea9a877 812
ganlikun 0:13413ea9a877 813 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
ganlikun 0:13413ea9a877 814 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
ganlikun 0:13413ea9a877 815
ganlikun 0:13413ea9a877 816 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
ganlikun 0:13413ea9a877 817 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
ganlikun 0:13413ea9a877 818
ganlikun 0:13413ea9a877 819 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
ganlikun 0:13413ea9a877 820 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
ganlikun 0:13413ea9a877 821
ganlikun 0:13413ea9a877 822 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
ganlikun 0:13413ea9a877 823 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
ganlikun 0:13413ea9a877 824
ganlikun 0:13413ea9a877 825 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
ganlikun 0:13413ea9a877 826 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
ganlikun 0:13413ea9a877 827
ganlikun 0:13413ea9a877 828 /* TPI ITATBCTR0 Register Definitions */
ganlikun 0:13413ea9a877 829 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
ganlikun 0:13413ea9a877 830 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
ganlikun 0:13413ea9a877 831
ganlikun 0:13413ea9a877 832 /* TPI Integration Mode Control Register Definitions */
ganlikun 0:13413ea9a877 833 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
ganlikun 0:13413ea9a877 834 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
ganlikun 0:13413ea9a877 835
ganlikun 0:13413ea9a877 836 /* TPI DEVID Register Definitions */
ganlikun 0:13413ea9a877 837 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
ganlikun 0:13413ea9a877 838 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
ganlikun 0:13413ea9a877 839
ganlikun 0:13413ea9a877 840 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
ganlikun 0:13413ea9a877 841 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
ganlikun 0:13413ea9a877 842
ganlikun 0:13413ea9a877 843 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
ganlikun 0:13413ea9a877 844 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
ganlikun 0:13413ea9a877 845
ganlikun 0:13413ea9a877 846 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
ganlikun 0:13413ea9a877 847 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
ganlikun 0:13413ea9a877 848
ganlikun 0:13413ea9a877 849 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
ganlikun 0:13413ea9a877 850 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
ganlikun 0:13413ea9a877 851
ganlikun 0:13413ea9a877 852 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
ganlikun 0:13413ea9a877 853 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
ganlikun 0:13413ea9a877 854
ganlikun 0:13413ea9a877 855 /* TPI DEVTYPE Register Definitions */
ganlikun 0:13413ea9a877 856 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
ganlikun 0:13413ea9a877 857 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
ganlikun 0:13413ea9a877 858
ganlikun 0:13413ea9a877 859 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
ganlikun 0:13413ea9a877 860 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
ganlikun 0:13413ea9a877 861
ganlikun 0:13413ea9a877 862 /*@}*/ /* end of group CMSIS_TPI */
ganlikun 0:13413ea9a877 863
ganlikun 0:13413ea9a877 864
ganlikun 0:13413ea9a877 865 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:13413ea9a877 866 /**
ganlikun 0:13413ea9a877 867 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 868 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
ganlikun 0:13413ea9a877 869 \brief Type definitions for the Memory Protection Unit (MPU)
ganlikun 0:13413ea9a877 870 @{
ganlikun 0:13413ea9a877 871 */
ganlikun 0:13413ea9a877 872
ganlikun 0:13413ea9a877 873 /**
ganlikun 0:13413ea9a877 874 \brief Structure type to access the Memory Protection Unit (MPU).
ganlikun 0:13413ea9a877 875 */
ganlikun 0:13413ea9a877 876 typedef struct
ganlikun 0:13413ea9a877 877 {
ganlikun 0:13413ea9a877 878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
ganlikun 0:13413ea9a877 879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
ganlikun 0:13413ea9a877 880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
ganlikun 0:13413ea9a877 881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
ganlikun 0:13413ea9a877 882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
ganlikun 0:13413ea9a877 883 uint32_t RESERVED0[7U];
ganlikun 0:13413ea9a877 884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
ganlikun 0:13413ea9a877 885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
ganlikun 0:13413ea9a877 886 } MPU_Type;
ganlikun 0:13413ea9a877 887
ganlikun 0:13413ea9a877 888 /* MPU Type Register Definitions */
ganlikun 0:13413ea9a877 889 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
ganlikun 0:13413ea9a877 890 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
ganlikun 0:13413ea9a877 891
ganlikun 0:13413ea9a877 892 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
ganlikun 0:13413ea9a877 893 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
ganlikun 0:13413ea9a877 894
ganlikun 0:13413ea9a877 895 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
ganlikun 0:13413ea9a877 896 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
ganlikun 0:13413ea9a877 897
ganlikun 0:13413ea9a877 898 /* MPU Control Register Definitions */
ganlikun 0:13413ea9a877 899 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
ganlikun 0:13413ea9a877 900 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
ganlikun 0:13413ea9a877 901
ganlikun 0:13413ea9a877 902 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
ganlikun 0:13413ea9a877 903 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
ganlikun 0:13413ea9a877 904
ganlikun 0:13413ea9a877 905 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
ganlikun 0:13413ea9a877 906 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
ganlikun 0:13413ea9a877 907
ganlikun 0:13413ea9a877 908 /* MPU Region Number Register Definitions */
ganlikun 0:13413ea9a877 909 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
ganlikun 0:13413ea9a877 910 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
ganlikun 0:13413ea9a877 911
ganlikun 0:13413ea9a877 912 /* MPU Region Base Address Register Definitions */
ganlikun 0:13413ea9a877 913 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
ganlikun 0:13413ea9a877 914 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
ganlikun 0:13413ea9a877 915
ganlikun 0:13413ea9a877 916 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
ganlikun 0:13413ea9a877 917 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
ganlikun 0:13413ea9a877 918
ganlikun 0:13413ea9a877 919 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
ganlikun 0:13413ea9a877 920 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
ganlikun 0:13413ea9a877 921
ganlikun 0:13413ea9a877 922 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
ganlikun 0:13413ea9a877 923 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
ganlikun 0:13413ea9a877 924
ganlikun 0:13413ea9a877 925 /* MPU Region Limit Address Register Definitions */
ganlikun 0:13413ea9a877 926 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
ganlikun 0:13413ea9a877 927 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
ganlikun 0:13413ea9a877 928
ganlikun 0:13413ea9a877 929 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
ganlikun 0:13413ea9a877 930 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
ganlikun 0:13413ea9a877 931
ganlikun 0:13413ea9a877 932 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
ganlikun 0:13413ea9a877 933 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
ganlikun 0:13413ea9a877 934
ganlikun 0:13413ea9a877 935 /* MPU Memory Attribute Indirection Register 0 Definitions */
ganlikun 0:13413ea9a877 936 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
ganlikun 0:13413ea9a877 937 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
ganlikun 0:13413ea9a877 938
ganlikun 0:13413ea9a877 939 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
ganlikun 0:13413ea9a877 940 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
ganlikun 0:13413ea9a877 941
ganlikun 0:13413ea9a877 942 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
ganlikun 0:13413ea9a877 943 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
ganlikun 0:13413ea9a877 944
ganlikun 0:13413ea9a877 945 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
ganlikun 0:13413ea9a877 946 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
ganlikun 0:13413ea9a877 947
ganlikun 0:13413ea9a877 948 /* MPU Memory Attribute Indirection Register 1 Definitions */
ganlikun 0:13413ea9a877 949 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
ganlikun 0:13413ea9a877 950 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
ganlikun 0:13413ea9a877 951
ganlikun 0:13413ea9a877 952 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
ganlikun 0:13413ea9a877 953 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
ganlikun 0:13413ea9a877 954
ganlikun 0:13413ea9a877 955 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
ganlikun 0:13413ea9a877 956 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
ganlikun 0:13413ea9a877 957
ganlikun 0:13413ea9a877 958 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
ganlikun 0:13413ea9a877 959 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
ganlikun 0:13413ea9a877 960
ganlikun 0:13413ea9a877 961 /*@} end of group CMSIS_MPU */
ganlikun 0:13413ea9a877 962 #endif
ganlikun 0:13413ea9a877 963
ganlikun 0:13413ea9a877 964
ganlikun 0:13413ea9a877 965 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:13413ea9a877 966 /**
ganlikun 0:13413ea9a877 967 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 968 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
ganlikun 0:13413ea9a877 969 \brief Type definitions for the Security Attribution Unit (SAU)
ganlikun 0:13413ea9a877 970 @{
ganlikun 0:13413ea9a877 971 */
ganlikun 0:13413ea9a877 972
ganlikun 0:13413ea9a877 973 /**
ganlikun 0:13413ea9a877 974 \brief Structure type to access the Security Attribution Unit (SAU).
ganlikun 0:13413ea9a877 975 */
ganlikun 0:13413ea9a877 976 typedef struct
ganlikun 0:13413ea9a877 977 {
ganlikun 0:13413ea9a877 978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
ganlikun 0:13413ea9a877 979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
ganlikun 0:13413ea9a877 980 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
ganlikun 0:13413ea9a877 981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
ganlikun 0:13413ea9a877 982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
ganlikun 0:13413ea9a877 983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
ganlikun 0:13413ea9a877 984 #endif
ganlikun 0:13413ea9a877 985 } SAU_Type;
ganlikun 0:13413ea9a877 986
ganlikun 0:13413ea9a877 987 /* SAU Control Register Definitions */
ganlikun 0:13413ea9a877 988 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
ganlikun 0:13413ea9a877 989 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
ganlikun 0:13413ea9a877 990
ganlikun 0:13413ea9a877 991 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
ganlikun 0:13413ea9a877 992 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
ganlikun 0:13413ea9a877 993
ganlikun 0:13413ea9a877 994 /* SAU Type Register Definitions */
ganlikun 0:13413ea9a877 995 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
ganlikun 0:13413ea9a877 996 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
ganlikun 0:13413ea9a877 997
ganlikun 0:13413ea9a877 998 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
ganlikun 0:13413ea9a877 999 /* SAU Region Number Register Definitions */
ganlikun 0:13413ea9a877 1000 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
ganlikun 0:13413ea9a877 1001 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
ganlikun 0:13413ea9a877 1002
ganlikun 0:13413ea9a877 1003 /* SAU Region Base Address Register Definitions */
ganlikun 0:13413ea9a877 1004 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
ganlikun 0:13413ea9a877 1005 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
ganlikun 0:13413ea9a877 1006
ganlikun 0:13413ea9a877 1007 /* SAU Region Limit Address Register Definitions */
ganlikun 0:13413ea9a877 1008 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
ganlikun 0:13413ea9a877 1009 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
ganlikun 0:13413ea9a877 1010
ganlikun 0:13413ea9a877 1011 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
ganlikun 0:13413ea9a877 1012 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
ganlikun 0:13413ea9a877 1013
ganlikun 0:13413ea9a877 1014 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
ganlikun 0:13413ea9a877 1015 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
ganlikun 0:13413ea9a877 1016
ganlikun 0:13413ea9a877 1017 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
ganlikun 0:13413ea9a877 1018
ganlikun 0:13413ea9a877 1019 /*@} end of group CMSIS_SAU */
ganlikun 0:13413ea9a877 1020 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:13413ea9a877 1021
ganlikun 0:13413ea9a877 1022
ganlikun 0:13413ea9a877 1023 /**
ganlikun 0:13413ea9a877 1024 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 1025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
ganlikun 0:13413ea9a877 1026 \brief Type definitions for the Core Debug Registers
ganlikun 0:13413ea9a877 1027 @{
ganlikun 0:13413ea9a877 1028 */
ganlikun 0:13413ea9a877 1029
ganlikun 0:13413ea9a877 1030 /**
ganlikun 0:13413ea9a877 1031 \brief Structure type to access the Core Debug Register (CoreDebug).
ganlikun 0:13413ea9a877 1032 */
ganlikun 0:13413ea9a877 1033 typedef struct
ganlikun 0:13413ea9a877 1034 {
ganlikun 0:13413ea9a877 1035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
ganlikun 0:13413ea9a877 1036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
ganlikun 0:13413ea9a877 1037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
ganlikun 0:13413ea9a877 1038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
ganlikun 0:13413ea9a877 1039 uint32_t RESERVED4[1U];
ganlikun 0:13413ea9a877 1040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
ganlikun 0:13413ea9a877 1041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
ganlikun 0:13413ea9a877 1042 } CoreDebug_Type;
ganlikun 0:13413ea9a877 1043
ganlikun 0:13413ea9a877 1044 /* Debug Halting Control and Status Register Definitions */
ganlikun 0:13413ea9a877 1045 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
ganlikun 0:13413ea9a877 1046 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
ganlikun 0:13413ea9a877 1047
ganlikun 0:13413ea9a877 1048 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
ganlikun 0:13413ea9a877 1049 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
ganlikun 0:13413ea9a877 1050
ganlikun 0:13413ea9a877 1051 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
ganlikun 0:13413ea9a877 1052 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
ganlikun 0:13413ea9a877 1053
ganlikun 0:13413ea9a877 1054 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
ganlikun 0:13413ea9a877 1055 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
ganlikun 0:13413ea9a877 1056
ganlikun 0:13413ea9a877 1057 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
ganlikun 0:13413ea9a877 1058 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
ganlikun 0:13413ea9a877 1059
ganlikun 0:13413ea9a877 1060 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
ganlikun 0:13413ea9a877 1061 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
ganlikun 0:13413ea9a877 1062
ganlikun 0:13413ea9a877 1063 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
ganlikun 0:13413ea9a877 1064 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
ganlikun 0:13413ea9a877 1065
ganlikun 0:13413ea9a877 1066 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
ganlikun 0:13413ea9a877 1067 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
ganlikun 0:13413ea9a877 1068
ganlikun 0:13413ea9a877 1069 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
ganlikun 0:13413ea9a877 1070 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
ganlikun 0:13413ea9a877 1071
ganlikun 0:13413ea9a877 1072 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
ganlikun 0:13413ea9a877 1073 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
ganlikun 0:13413ea9a877 1074
ganlikun 0:13413ea9a877 1075 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
ganlikun 0:13413ea9a877 1076 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
ganlikun 0:13413ea9a877 1077
ganlikun 0:13413ea9a877 1078 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
ganlikun 0:13413ea9a877 1079 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
ganlikun 0:13413ea9a877 1080
ganlikun 0:13413ea9a877 1081 /* Debug Core Register Selector Register Definitions */
ganlikun 0:13413ea9a877 1082 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
ganlikun 0:13413ea9a877 1083 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
ganlikun 0:13413ea9a877 1084
ganlikun 0:13413ea9a877 1085 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
ganlikun 0:13413ea9a877 1086 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
ganlikun 0:13413ea9a877 1087
ganlikun 0:13413ea9a877 1088 /* Debug Exception and Monitor Control Register */
ganlikun 0:13413ea9a877 1089 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
ganlikun 0:13413ea9a877 1090 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
ganlikun 0:13413ea9a877 1091
ganlikun 0:13413ea9a877 1092 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
ganlikun 0:13413ea9a877 1093 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
ganlikun 0:13413ea9a877 1094
ganlikun 0:13413ea9a877 1095 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
ganlikun 0:13413ea9a877 1096 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
ganlikun 0:13413ea9a877 1097
ganlikun 0:13413ea9a877 1098 /* Debug Authentication Control Register Definitions */
ganlikun 0:13413ea9a877 1099 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
ganlikun 0:13413ea9a877 1100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
ganlikun 0:13413ea9a877 1101
ganlikun 0:13413ea9a877 1102 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
ganlikun 0:13413ea9a877 1103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
ganlikun 0:13413ea9a877 1104
ganlikun 0:13413ea9a877 1105 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
ganlikun 0:13413ea9a877 1106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
ganlikun 0:13413ea9a877 1107
ganlikun 0:13413ea9a877 1108 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
ganlikun 0:13413ea9a877 1109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
ganlikun 0:13413ea9a877 1110
ganlikun 0:13413ea9a877 1111 /* Debug Security Control and Status Register Definitions */
ganlikun 0:13413ea9a877 1112 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
ganlikun 0:13413ea9a877 1113 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
ganlikun 0:13413ea9a877 1114
ganlikun 0:13413ea9a877 1115 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
ganlikun 0:13413ea9a877 1116 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
ganlikun 0:13413ea9a877 1117
ganlikun 0:13413ea9a877 1118 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
ganlikun 0:13413ea9a877 1119 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
ganlikun 0:13413ea9a877 1120
ganlikun 0:13413ea9a877 1121 /*@} end of group CMSIS_CoreDebug */
ganlikun 0:13413ea9a877 1122
ganlikun 0:13413ea9a877 1123
ganlikun 0:13413ea9a877 1124 /**
ganlikun 0:13413ea9a877 1125 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 1126 \defgroup CMSIS_core_bitfield Core register bit field macros
ganlikun 0:13413ea9a877 1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
ganlikun 0:13413ea9a877 1128 @{
ganlikun 0:13413ea9a877 1129 */
ganlikun 0:13413ea9a877 1130
ganlikun 0:13413ea9a877 1131 /**
ganlikun 0:13413ea9a877 1132 \brief Mask and shift a bit field value for use in a register bit range.
ganlikun 0:13413ea9a877 1133 \param[in] field Name of the register bit field.
ganlikun 0:13413ea9a877 1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
ganlikun 0:13413ea9a877 1135 \return Masked and shifted value.
ganlikun 0:13413ea9a877 1136 */
ganlikun 0:13413ea9a877 1137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
ganlikun 0:13413ea9a877 1138
ganlikun 0:13413ea9a877 1139 /**
ganlikun 0:13413ea9a877 1140 \brief Mask and shift a register value to extract a bit filed value.
ganlikun 0:13413ea9a877 1141 \param[in] field Name of the register bit field.
ganlikun 0:13413ea9a877 1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
ganlikun 0:13413ea9a877 1143 \return Masked and shifted bit field value.
ganlikun 0:13413ea9a877 1144 */
ganlikun 0:13413ea9a877 1145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ganlikun 0:13413ea9a877 1146
ganlikun 0:13413ea9a877 1147 /*@} end of group CMSIS_core_bitfield */
ganlikun 0:13413ea9a877 1148
ganlikun 0:13413ea9a877 1149
ganlikun 0:13413ea9a877 1150 /**
ganlikun 0:13413ea9a877 1151 \ingroup CMSIS_core_register
ganlikun 0:13413ea9a877 1152 \defgroup CMSIS_core_base Core Definitions
ganlikun 0:13413ea9a877 1153 \brief Definitions for base addresses, unions, and structures.
ganlikun 0:13413ea9a877 1154 @{
ganlikun 0:13413ea9a877 1155 */
ganlikun 0:13413ea9a877 1156
ganlikun 0:13413ea9a877 1157 /* Memory mapping of Core Hardware */
ganlikun 0:13413ea9a877 1158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
ganlikun 0:13413ea9a877 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
ganlikun 0:13413ea9a877 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
ganlikun 0:13413ea9a877 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
ganlikun 0:13413ea9a877 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
ganlikun 0:13413ea9a877 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
ganlikun 0:13413ea9a877 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
ganlikun 0:13413ea9a877 1165
ganlikun 0:13413ea9a877 1166
ganlikun 0:13413ea9a877 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
ganlikun 0:13413ea9a877 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
ganlikun 0:13413ea9a877 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
ganlikun 0:13413ea9a877 1170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
ganlikun 0:13413ea9a877 1171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
ganlikun 0:13413ea9a877 1172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
ganlikun 0:13413ea9a877 1173
ganlikun 0:13413ea9a877 1174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:13413ea9a877 1175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
ganlikun 0:13413ea9a877 1176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
ganlikun 0:13413ea9a877 1177 #endif
ganlikun 0:13413ea9a877 1178
ganlikun 0:13413ea9a877 1179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:13413ea9a877 1180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
ganlikun 0:13413ea9a877 1181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
ganlikun 0:13413ea9a877 1182 #endif
ganlikun 0:13413ea9a877 1183
ganlikun 0:13413ea9a877 1184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:13413ea9a877 1185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
ganlikun 0:13413ea9a877 1186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
ganlikun 0:13413ea9a877 1187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
ganlikun 0:13413ea9a877 1188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
ganlikun 0:13413ea9a877 1189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
ganlikun 0:13413ea9a877 1190
ganlikun 0:13413ea9a877 1191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
ganlikun 0:13413ea9a877 1192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
ganlikun 0:13413ea9a877 1193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
ganlikun 0:13413ea9a877 1194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
ganlikun 0:13413ea9a877 1195
ganlikun 0:13413ea9a877 1196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:13413ea9a877 1197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
ganlikun 0:13413ea9a877 1198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
ganlikun 0:13413ea9a877 1199 #endif
ganlikun 0:13413ea9a877 1200
ganlikun 0:13413ea9a877 1201 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:13413ea9a877 1202 /*@} */
ganlikun 0:13413ea9a877 1203
ganlikun 0:13413ea9a877 1204
ganlikun 0:13413ea9a877 1205
ganlikun 0:13413ea9a877 1206 /*******************************************************************************
ganlikun 0:13413ea9a877 1207 * Hardware Abstraction Layer
ganlikun 0:13413ea9a877 1208 Core Function Interface contains:
ganlikun 0:13413ea9a877 1209 - Core NVIC Functions
ganlikun 0:13413ea9a877 1210 - Core SysTick Functions
ganlikun 0:13413ea9a877 1211 - Core Register Access Functions
ganlikun 0:13413ea9a877 1212 ******************************************************************************/
ganlikun 0:13413ea9a877 1213 /**
ganlikun 0:13413ea9a877 1214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
ganlikun 0:13413ea9a877 1215 */
ganlikun 0:13413ea9a877 1216
ganlikun 0:13413ea9a877 1217
ganlikun 0:13413ea9a877 1218
ganlikun 0:13413ea9a877 1219 /* ########################## NVIC functions #################################### */
ganlikun 0:13413ea9a877 1220 /**
ganlikun 0:13413ea9a877 1221 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
ganlikun 0:13413ea9a877 1223 \brief Functions that manage interrupts and exceptions via the NVIC.
ganlikun 0:13413ea9a877 1224 @{
ganlikun 0:13413ea9a877 1225 */
ganlikun 0:13413ea9a877 1226
ganlikun 0:13413ea9a877 1227 #ifdef CMSIS_NVIC_VIRTUAL
ganlikun 0:13413ea9a877 1228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
ganlikun 0:13413ea9a877 1230 #endif
ganlikun 0:13413ea9a877 1231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1232 #else
ganlikun 0:13413ea9a877 1233 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
ganlikun 0:13413ea9a877 1234 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
ganlikun 0:13413ea9a877 1235 #define NVIC_EnableIRQ __NVIC_EnableIRQ
ganlikun 0:13413ea9a877 1236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
ganlikun 0:13413ea9a877 1237 #define NVIC_DisableIRQ __NVIC_DisableIRQ
ganlikun 0:13413ea9a877 1238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
ganlikun 0:13413ea9a877 1239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
ganlikun 0:13413ea9a877 1240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
ganlikun 0:13413ea9a877 1241 #define NVIC_GetActive __NVIC_GetActive
ganlikun 0:13413ea9a877 1242 #define NVIC_SetPriority __NVIC_SetPriority
ganlikun 0:13413ea9a877 1243 #define NVIC_GetPriority __NVIC_GetPriority
ganlikun 0:13413ea9a877 1244 #define NVIC_SystemReset __NVIC_SystemReset
ganlikun 0:13413ea9a877 1245 #endif /* CMSIS_NVIC_VIRTUAL */
ganlikun 0:13413ea9a877 1246
ganlikun 0:13413ea9a877 1247 #ifdef CMSIS_VECTAB_VIRTUAL
ganlikun 0:13413ea9a877 1248 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1249 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
ganlikun 0:13413ea9a877 1250 #endif
ganlikun 0:13413ea9a877 1251 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:13413ea9a877 1252 #else
ganlikun 0:13413ea9a877 1253 #define NVIC_SetVector __NVIC_SetVector
ganlikun 0:13413ea9a877 1254 #define NVIC_GetVector __NVIC_GetVector
ganlikun 0:13413ea9a877 1255 #endif /* (CMSIS_VECTAB_VIRTUAL) */
ganlikun 0:13413ea9a877 1256
ganlikun 0:13413ea9a877 1257 #define NVIC_USER_IRQ_OFFSET 16
ganlikun 0:13413ea9a877 1258
ganlikun 0:13413ea9a877 1259
ganlikun 0:13413ea9a877 1260 /* Interrupt Priorities are WORD accessible only under ARMv6M */
ganlikun 0:13413ea9a877 1261 /* The following MACROS handle generation of the register offset and byte masks */
ganlikun 0:13413ea9a877 1262 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ganlikun 0:13413ea9a877 1263 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
ganlikun 0:13413ea9a877 1264 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
ganlikun 0:13413ea9a877 1265
ganlikun 0:13413ea9a877 1266
ganlikun 0:13413ea9a877 1267 /**
ganlikun 0:13413ea9a877 1268 \brief Enable Interrupt
ganlikun 0:13413ea9a877 1269 \details Enables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:13413ea9a877 1270 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1271 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1272 */
ganlikun 0:13413ea9a877 1273 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1274 {
ganlikun 0:13413ea9a877 1275 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1276 {
ganlikun 0:13413ea9a877 1277 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1278 }
ganlikun 0:13413ea9a877 1279 }
ganlikun 0:13413ea9a877 1280
ganlikun 0:13413ea9a877 1281
ganlikun 0:13413ea9a877 1282 /**
ganlikun 0:13413ea9a877 1283 \brief Get Interrupt Enable status
ganlikun 0:13413ea9a877 1284 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
ganlikun 0:13413ea9a877 1285 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1286 \return 0 Interrupt is not enabled.
ganlikun 0:13413ea9a877 1287 \return 1 Interrupt is enabled.
ganlikun 0:13413ea9a877 1288 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1289 */
ganlikun 0:13413ea9a877 1290 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1291 {
ganlikun 0:13413ea9a877 1292 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1293 {
ganlikun 0:13413ea9a877 1294 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1295 }
ganlikun 0:13413ea9a877 1296 else
ganlikun 0:13413ea9a877 1297 {
ganlikun 0:13413ea9a877 1298 return(0U);
ganlikun 0:13413ea9a877 1299 }
ganlikun 0:13413ea9a877 1300 }
ganlikun 0:13413ea9a877 1301
ganlikun 0:13413ea9a877 1302
ganlikun 0:13413ea9a877 1303 /**
ganlikun 0:13413ea9a877 1304 \brief Disable Interrupt
ganlikun 0:13413ea9a877 1305 \details Disables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:13413ea9a877 1306 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1307 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1308 */
ganlikun 0:13413ea9a877 1309 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1310 {
ganlikun 0:13413ea9a877 1311 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1312 {
ganlikun 0:13413ea9a877 1313 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1314 __DSB();
ganlikun 0:13413ea9a877 1315 __ISB();
ganlikun 0:13413ea9a877 1316 }
ganlikun 0:13413ea9a877 1317 }
ganlikun 0:13413ea9a877 1318
ganlikun 0:13413ea9a877 1319
ganlikun 0:13413ea9a877 1320 /**
ganlikun 0:13413ea9a877 1321 \brief Get Pending Interrupt
ganlikun 0:13413ea9a877 1322 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
ganlikun 0:13413ea9a877 1323 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1324 \return 0 Interrupt status is not pending.
ganlikun 0:13413ea9a877 1325 \return 1 Interrupt status is pending.
ganlikun 0:13413ea9a877 1326 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1327 */
ganlikun 0:13413ea9a877 1328 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1329 {
ganlikun 0:13413ea9a877 1330 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1331 {
ganlikun 0:13413ea9a877 1332 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1333 }
ganlikun 0:13413ea9a877 1334 else
ganlikun 0:13413ea9a877 1335 {
ganlikun 0:13413ea9a877 1336 return(0U);
ganlikun 0:13413ea9a877 1337 }
ganlikun 0:13413ea9a877 1338 }
ganlikun 0:13413ea9a877 1339
ganlikun 0:13413ea9a877 1340
ganlikun 0:13413ea9a877 1341 /**
ganlikun 0:13413ea9a877 1342 \brief Set Pending Interrupt
ganlikun 0:13413ea9a877 1343 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:13413ea9a877 1344 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1345 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1346 */
ganlikun 0:13413ea9a877 1347 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1348 {
ganlikun 0:13413ea9a877 1349 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1350 {
ganlikun 0:13413ea9a877 1351 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1352 }
ganlikun 0:13413ea9a877 1353 }
ganlikun 0:13413ea9a877 1354
ganlikun 0:13413ea9a877 1355
ganlikun 0:13413ea9a877 1356 /**
ganlikun 0:13413ea9a877 1357 \brief Clear Pending Interrupt
ganlikun 0:13413ea9a877 1358 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:13413ea9a877 1359 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1360 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1361 */
ganlikun 0:13413ea9a877 1362 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1363 {
ganlikun 0:13413ea9a877 1364 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1365 {
ganlikun 0:13413ea9a877 1366 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1367 }
ganlikun 0:13413ea9a877 1368 }
ganlikun 0:13413ea9a877 1369
ganlikun 0:13413ea9a877 1370
ganlikun 0:13413ea9a877 1371 /**
ganlikun 0:13413ea9a877 1372 \brief Get Active Interrupt
ganlikun 0:13413ea9a877 1373 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
ganlikun 0:13413ea9a877 1374 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1375 \return 0 Interrupt status is not active.
ganlikun 0:13413ea9a877 1376 \return 1 Interrupt status is active.
ganlikun 0:13413ea9a877 1377 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1378 */
ganlikun 0:13413ea9a877 1379 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1380 {
ganlikun 0:13413ea9a877 1381 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1382 {
ganlikun 0:13413ea9a877 1383 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1384 }
ganlikun 0:13413ea9a877 1385 else
ganlikun 0:13413ea9a877 1386 {
ganlikun 0:13413ea9a877 1387 return(0U);
ganlikun 0:13413ea9a877 1388 }
ganlikun 0:13413ea9a877 1389 }
ganlikun 0:13413ea9a877 1390
ganlikun 0:13413ea9a877 1391
ganlikun 0:13413ea9a877 1392 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:13413ea9a877 1393 /**
ganlikun 0:13413ea9a877 1394 \brief Get Interrupt Target State
ganlikun 0:13413ea9a877 1395 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
ganlikun 0:13413ea9a877 1396 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1397 \return 0 if interrupt is assigned to Secure
ganlikun 0:13413ea9a877 1398 \return 1 if interrupt is assigned to Non Secure
ganlikun 0:13413ea9a877 1399 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1400 */
ganlikun 0:13413ea9a877 1401 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1402 {
ganlikun 0:13413ea9a877 1403 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1404 {
ganlikun 0:13413ea9a877 1405 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1406 }
ganlikun 0:13413ea9a877 1407 else
ganlikun 0:13413ea9a877 1408 {
ganlikun 0:13413ea9a877 1409 return(0U);
ganlikun 0:13413ea9a877 1410 }
ganlikun 0:13413ea9a877 1411 }
ganlikun 0:13413ea9a877 1412
ganlikun 0:13413ea9a877 1413
ganlikun 0:13413ea9a877 1414 /**
ganlikun 0:13413ea9a877 1415 \brief Set Interrupt Target State
ganlikun 0:13413ea9a877 1416 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
ganlikun 0:13413ea9a877 1417 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1418 \return 0 if interrupt is assigned to Secure
ganlikun 0:13413ea9a877 1419 1 if interrupt is assigned to Non Secure
ganlikun 0:13413ea9a877 1420 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1421 */
ganlikun 0:13413ea9a877 1422 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1423 {
ganlikun 0:13413ea9a877 1424 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1425 {
ganlikun 0:13413ea9a877 1426 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
ganlikun 0:13413ea9a877 1427 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1428 }
ganlikun 0:13413ea9a877 1429 else
ganlikun 0:13413ea9a877 1430 {
ganlikun 0:13413ea9a877 1431 return(0U);
ganlikun 0:13413ea9a877 1432 }
ganlikun 0:13413ea9a877 1433 }
ganlikun 0:13413ea9a877 1434
ganlikun 0:13413ea9a877 1435
ganlikun 0:13413ea9a877 1436 /**
ganlikun 0:13413ea9a877 1437 \brief Clear Interrupt Target State
ganlikun 0:13413ea9a877 1438 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
ganlikun 0:13413ea9a877 1439 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1440 \return 0 if interrupt is assigned to Secure
ganlikun 0:13413ea9a877 1441 1 if interrupt is assigned to Non Secure
ganlikun 0:13413ea9a877 1442 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1443 */
ganlikun 0:13413ea9a877 1444 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1445 {
ganlikun 0:13413ea9a877 1446 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1447 {
ganlikun 0:13413ea9a877 1448 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
ganlikun 0:13413ea9a877 1449 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1450 }
ganlikun 0:13413ea9a877 1451 else
ganlikun 0:13413ea9a877 1452 {
ganlikun 0:13413ea9a877 1453 return(0U);
ganlikun 0:13413ea9a877 1454 }
ganlikun 0:13413ea9a877 1455 }
ganlikun 0:13413ea9a877 1456 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:13413ea9a877 1457
ganlikun 0:13413ea9a877 1458
ganlikun 0:13413ea9a877 1459 /**
ganlikun 0:13413ea9a877 1460 \brief Set Interrupt Priority
ganlikun 0:13413ea9a877 1461 \details Sets the priority of a device specific interrupt or a processor exception.
ganlikun 0:13413ea9a877 1462 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1463 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1464 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1465 \param [in] priority Priority to set.
ganlikun 0:13413ea9a877 1466 \note The priority cannot be set for every processor exception.
ganlikun 0:13413ea9a877 1467 */
ganlikun 0:13413ea9a877 1468 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ganlikun 0:13413ea9a877 1469 {
ganlikun 0:13413ea9a877 1470 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1471 {
ganlikun 0:13413ea9a877 1472 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:13413ea9a877 1473 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:13413ea9a877 1474 }
ganlikun 0:13413ea9a877 1475 else
ganlikun 0:13413ea9a877 1476 {
ganlikun 0:13413ea9a877 1477 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:13413ea9a877 1478 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:13413ea9a877 1479 }
ganlikun 0:13413ea9a877 1480 }
ganlikun 0:13413ea9a877 1481
ganlikun 0:13413ea9a877 1482
ganlikun 0:13413ea9a877 1483 /**
ganlikun 0:13413ea9a877 1484 \brief Get Interrupt Priority
ganlikun 0:13413ea9a877 1485 \details Reads the priority of a device specific interrupt or a processor exception.
ganlikun 0:13413ea9a877 1486 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1487 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1488 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1489 \return Interrupt Priority.
ganlikun 0:13413ea9a877 1490 Value is aligned automatically to the implemented priority bits of the microcontroller.
ganlikun 0:13413ea9a877 1491 */
ganlikun 0:13413ea9a877 1492 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1493 {
ganlikun 0:13413ea9a877 1494
ganlikun 0:13413ea9a877 1495 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1496 {
ganlikun 0:13413ea9a877 1497 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:13413ea9a877 1498 }
ganlikun 0:13413ea9a877 1499 else
ganlikun 0:13413ea9a877 1500 {
ganlikun 0:13413ea9a877 1501 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:13413ea9a877 1502 }
ganlikun 0:13413ea9a877 1503 }
ganlikun 0:13413ea9a877 1504
ganlikun 0:13413ea9a877 1505
ganlikun 0:13413ea9a877 1506 /**
ganlikun 0:13413ea9a877 1507 \brief Set Interrupt Vector
ganlikun 0:13413ea9a877 1508 \details Sets an interrupt vector in SRAM based interrupt vector table.
ganlikun 0:13413ea9a877 1509 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1510 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1511 VTOR must been relocated to SRAM before.
ganlikun 0:13413ea9a877 1512 If VTOR is not present address 0 must be mapped to SRAM.
ganlikun 0:13413ea9a877 1513 \param [in] IRQn Interrupt number
ganlikun 0:13413ea9a877 1514 \param [in] vector Address of interrupt handler function
ganlikun 0:13413ea9a877 1515 */
ganlikun 0:13413ea9a877 1516 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
ganlikun 0:13413ea9a877 1517 {
ganlikun 0:13413ea9a877 1518 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:13413ea9a877 1519 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:13413ea9a877 1520 #else
ganlikun 0:13413ea9a877 1521 uint32_t *vectors = (uint32_t *)0x0U;
ganlikun 0:13413ea9a877 1522 #endif
ganlikun 0:13413ea9a877 1523 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
ganlikun 0:13413ea9a877 1524 }
ganlikun 0:13413ea9a877 1525
ganlikun 0:13413ea9a877 1526
ganlikun 0:13413ea9a877 1527 /**
ganlikun 0:13413ea9a877 1528 \brief Get Interrupt Vector
ganlikun 0:13413ea9a877 1529 \details Reads an interrupt vector from interrupt vector table.
ganlikun 0:13413ea9a877 1530 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1531 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1532 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1533 \return Address of interrupt handler function
ganlikun 0:13413ea9a877 1534 */
ganlikun 0:13413ea9a877 1535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1536 {
ganlikun 0:13413ea9a877 1537 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:13413ea9a877 1538 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:13413ea9a877 1539 #else
ganlikun 0:13413ea9a877 1540 uint32_t *vectors = (uint32_t *)0x0U;
ganlikun 0:13413ea9a877 1541 #endif
ganlikun 0:13413ea9a877 1542 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
ganlikun 0:13413ea9a877 1543 }
ganlikun 0:13413ea9a877 1544
ganlikun 0:13413ea9a877 1545
ganlikun 0:13413ea9a877 1546 /**
ganlikun 0:13413ea9a877 1547 \brief System Reset
ganlikun 0:13413ea9a877 1548 \details Initiates a system reset request to reset the MCU.
ganlikun 0:13413ea9a877 1549 */
ganlikun 0:13413ea9a877 1550 __STATIC_INLINE void __NVIC_SystemReset(void)
ganlikun 0:13413ea9a877 1551 {
ganlikun 0:13413ea9a877 1552 __DSB(); /* Ensure all outstanding memory accesses included
ganlikun 0:13413ea9a877 1553 buffered write are completed before reset */
ganlikun 0:13413ea9a877 1554 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
ganlikun 0:13413ea9a877 1555 SCB_AIRCR_SYSRESETREQ_Msk);
ganlikun 0:13413ea9a877 1556 __DSB(); /* Ensure completion of memory access */
ganlikun 0:13413ea9a877 1557
ganlikun 0:13413ea9a877 1558 for(;;) /* wait until reset */
ganlikun 0:13413ea9a877 1559 {
ganlikun 0:13413ea9a877 1560 __NOP();
ganlikun 0:13413ea9a877 1561 }
ganlikun 0:13413ea9a877 1562 }
ganlikun 0:13413ea9a877 1563
ganlikun 0:13413ea9a877 1564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:13413ea9a877 1565 /**
ganlikun 0:13413ea9a877 1566 \brief Enable Interrupt (non-secure)
ganlikun 0:13413ea9a877 1567 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
ganlikun 0:13413ea9a877 1568 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1569 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1570 */
ganlikun 0:13413ea9a877 1571 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1572 {
ganlikun 0:13413ea9a877 1573 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1574 {
ganlikun 0:13413ea9a877 1575 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1576 }
ganlikun 0:13413ea9a877 1577 }
ganlikun 0:13413ea9a877 1578
ganlikun 0:13413ea9a877 1579
ganlikun 0:13413ea9a877 1580 /**
ganlikun 0:13413ea9a877 1581 \brief Get Interrupt Enable status (non-secure)
ganlikun 0:13413ea9a877 1582 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
ganlikun 0:13413ea9a877 1583 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1584 \return 0 Interrupt is not enabled.
ganlikun 0:13413ea9a877 1585 \return 1 Interrupt is enabled.
ganlikun 0:13413ea9a877 1586 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1587 */
ganlikun 0:13413ea9a877 1588 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1589 {
ganlikun 0:13413ea9a877 1590 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1591 {
ganlikun 0:13413ea9a877 1592 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1593 }
ganlikun 0:13413ea9a877 1594 else
ganlikun 0:13413ea9a877 1595 {
ganlikun 0:13413ea9a877 1596 return(0U);
ganlikun 0:13413ea9a877 1597 }
ganlikun 0:13413ea9a877 1598 }
ganlikun 0:13413ea9a877 1599
ganlikun 0:13413ea9a877 1600
ganlikun 0:13413ea9a877 1601 /**
ganlikun 0:13413ea9a877 1602 \brief Disable Interrupt (non-secure)
ganlikun 0:13413ea9a877 1603 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
ganlikun 0:13413ea9a877 1604 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1605 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1606 */
ganlikun 0:13413ea9a877 1607 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1608 {
ganlikun 0:13413ea9a877 1609 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1610 {
ganlikun 0:13413ea9a877 1611 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1612 }
ganlikun 0:13413ea9a877 1613 }
ganlikun 0:13413ea9a877 1614
ganlikun 0:13413ea9a877 1615
ganlikun 0:13413ea9a877 1616 /**
ganlikun 0:13413ea9a877 1617 \brief Get Pending Interrupt (non-secure)
ganlikun 0:13413ea9a877 1618 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
ganlikun 0:13413ea9a877 1619 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1620 \return 0 Interrupt status is not pending.
ganlikun 0:13413ea9a877 1621 \return 1 Interrupt status is pending.
ganlikun 0:13413ea9a877 1622 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1623 */
ganlikun 0:13413ea9a877 1624 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1625 {
ganlikun 0:13413ea9a877 1626 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1627 {
ganlikun 0:13413ea9a877 1628 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1629 }
ganlikun 0:13413ea9a877 1630 }
ganlikun 0:13413ea9a877 1631
ganlikun 0:13413ea9a877 1632
ganlikun 0:13413ea9a877 1633 /**
ganlikun 0:13413ea9a877 1634 \brief Set Pending Interrupt (non-secure)
ganlikun 0:13413ea9a877 1635 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
ganlikun 0:13413ea9a877 1636 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1637 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1638 */
ganlikun 0:13413ea9a877 1639 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1640 {
ganlikun 0:13413ea9a877 1641 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1642 {
ganlikun 0:13413ea9a877 1643 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1644 }
ganlikun 0:13413ea9a877 1645 }
ganlikun 0:13413ea9a877 1646
ganlikun 0:13413ea9a877 1647
ganlikun 0:13413ea9a877 1648 /**
ganlikun 0:13413ea9a877 1649 \brief Clear Pending Interrupt (non-secure)
ganlikun 0:13413ea9a877 1650 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
ganlikun 0:13413ea9a877 1651 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1652 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1653 */
ganlikun 0:13413ea9a877 1654 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1655 {
ganlikun 0:13413ea9a877 1656 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1657 {
ganlikun 0:13413ea9a877 1658 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:13413ea9a877 1659 }
ganlikun 0:13413ea9a877 1660 }
ganlikun 0:13413ea9a877 1661
ganlikun 0:13413ea9a877 1662
ganlikun 0:13413ea9a877 1663 /**
ganlikun 0:13413ea9a877 1664 \brief Get Active Interrupt (non-secure)
ganlikun 0:13413ea9a877 1665 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
ganlikun 0:13413ea9a877 1666 \param [in] IRQn Device specific interrupt number.
ganlikun 0:13413ea9a877 1667 \return 0 Interrupt status is not active.
ganlikun 0:13413ea9a877 1668 \return 1 Interrupt status is active.
ganlikun 0:13413ea9a877 1669 \note IRQn must not be negative.
ganlikun 0:13413ea9a877 1670 */
ganlikun 0:13413ea9a877 1671 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1672 {
ganlikun 0:13413ea9a877 1673 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1674 {
ganlikun 0:13413ea9a877 1675 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:13413ea9a877 1676 }
ganlikun 0:13413ea9a877 1677 else
ganlikun 0:13413ea9a877 1678 {
ganlikun 0:13413ea9a877 1679 return(0U);
ganlikun 0:13413ea9a877 1680 }
ganlikun 0:13413ea9a877 1681 }
ganlikun 0:13413ea9a877 1682
ganlikun 0:13413ea9a877 1683
ganlikun 0:13413ea9a877 1684 /**
ganlikun 0:13413ea9a877 1685 \brief Set Interrupt Priority (non-secure)
ganlikun 0:13413ea9a877 1686 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
ganlikun 0:13413ea9a877 1687 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1688 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1689 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1690 \param [in] priority Priority to set.
ganlikun 0:13413ea9a877 1691 \note The priority cannot be set for every non-secure processor exception.
ganlikun 0:13413ea9a877 1692 */
ganlikun 0:13413ea9a877 1693 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
ganlikun 0:13413ea9a877 1694 {
ganlikun 0:13413ea9a877 1695 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1696 {
ganlikun 0:13413ea9a877 1697 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:13413ea9a877 1698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:13413ea9a877 1699 }
ganlikun 0:13413ea9a877 1700 else
ganlikun 0:13413ea9a877 1701 {
ganlikun 0:13413ea9a877 1702 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:13413ea9a877 1703 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:13413ea9a877 1704 }
ganlikun 0:13413ea9a877 1705 }
ganlikun 0:13413ea9a877 1706
ganlikun 0:13413ea9a877 1707
ganlikun 0:13413ea9a877 1708 /**
ganlikun 0:13413ea9a877 1709 \brief Get Interrupt Priority (non-secure)
ganlikun 0:13413ea9a877 1710 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
ganlikun 0:13413ea9a877 1711 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:13413ea9a877 1712 or negative to specify a processor exception.
ganlikun 0:13413ea9a877 1713 \param [in] IRQn Interrupt number.
ganlikun 0:13413ea9a877 1714 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
ganlikun 0:13413ea9a877 1715 */
ganlikun 0:13413ea9a877 1716 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
ganlikun 0:13413ea9a877 1717 {
ganlikun 0:13413ea9a877 1718
ganlikun 0:13413ea9a877 1719 if ((int32_t)(IRQn) >= 0)
ganlikun 0:13413ea9a877 1720 {
ganlikun 0:13413ea9a877 1721 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:13413ea9a877 1722 }
ganlikun 0:13413ea9a877 1723 else
ganlikun 0:13413ea9a877 1724 {
ganlikun 0:13413ea9a877 1725 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:13413ea9a877 1726 }
ganlikun 0:13413ea9a877 1727 }
ganlikun 0:13413ea9a877 1728 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:13413ea9a877 1729
ganlikun 0:13413ea9a877 1730 /*@} end of CMSIS_Core_NVICFunctions */
ganlikun 0:13413ea9a877 1731
ganlikun 0:13413ea9a877 1732
ganlikun 0:13413ea9a877 1733 /* ########################## FPU functions #################################### */
ganlikun 0:13413ea9a877 1734 /**
ganlikun 0:13413ea9a877 1735 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1736 \defgroup CMSIS_Core_FpuFunctions FPU Functions
ganlikun 0:13413ea9a877 1737 \brief Function that provides FPU type.
ganlikun 0:13413ea9a877 1738 @{
ganlikun 0:13413ea9a877 1739 */
ganlikun 0:13413ea9a877 1740
ganlikun 0:13413ea9a877 1741 /**
ganlikun 0:13413ea9a877 1742 \brief get FPU type
ganlikun 0:13413ea9a877 1743 \details returns the FPU type
ganlikun 0:13413ea9a877 1744 \returns
ganlikun 0:13413ea9a877 1745 - \b 0: No FPU
ganlikun 0:13413ea9a877 1746 - \b 1: Single precision FPU
ganlikun 0:13413ea9a877 1747 - \b 2: Double + Single precision FPU
ganlikun 0:13413ea9a877 1748 */
ganlikun 0:13413ea9a877 1749 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
ganlikun 0:13413ea9a877 1750 {
ganlikun 0:13413ea9a877 1751 return 0U; /* No FPU */
ganlikun 0:13413ea9a877 1752 }
ganlikun 0:13413ea9a877 1753
ganlikun 0:13413ea9a877 1754
ganlikun 0:13413ea9a877 1755 /*@} end of CMSIS_Core_FpuFunctions */
ganlikun 0:13413ea9a877 1756
ganlikun 0:13413ea9a877 1757
ganlikun 0:13413ea9a877 1758
ganlikun 0:13413ea9a877 1759 /* ########################## SAU functions #################################### */
ganlikun 0:13413ea9a877 1760 /**
ganlikun 0:13413ea9a877 1761 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1762 \defgroup CMSIS_Core_SAUFunctions SAU Functions
ganlikun 0:13413ea9a877 1763 \brief Functions that configure the SAU.
ganlikun 0:13413ea9a877 1764 @{
ganlikun 0:13413ea9a877 1765 */
ganlikun 0:13413ea9a877 1766
ganlikun 0:13413ea9a877 1767 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:13413ea9a877 1768
ganlikun 0:13413ea9a877 1769 /**
ganlikun 0:13413ea9a877 1770 \brief Enable SAU
ganlikun 0:13413ea9a877 1771 \details Enables the Security Attribution Unit (SAU).
ganlikun 0:13413ea9a877 1772 */
ganlikun 0:13413ea9a877 1773 __STATIC_INLINE void TZ_SAU_Enable(void)
ganlikun 0:13413ea9a877 1774 {
ganlikun 0:13413ea9a877 1775 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
ganlikun 0:13413ea9a877 1776 }
ganlikun 0:13413ea9a877 1777
ganlikun 0:13413ea9a877 1778
ganlikun 0:13413ea9a877 1779
ganlikun 0:13413ea9a877 1780 /**
ganlikun 0:13413ea9a877 1781 \brief Disable SAU
ganlikun 0:13413ea9a877 1782 \details Disables the Security Attribution Unit (SAU).
ganlikun 0:13413ea9a877 1783 */
ganlikun 0:13413ea9a877 1784 __STATIC_INLINE void TZ_SAU_Disable(void)
ganlikun 0:13413ea9a877 1785 {
ganlikun 0:13413ea9a877 1786 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
ganlikun 0:13413ea9a877 1787 }
ganlikun 0:13413ea9a877 1788
ganlikun 0:13413ea9a877 1789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:13413ea9a877 1790
ganlikun 0:13413ea9a877 1791 /*@} end of CMSIS_Core_SAUFunctions */
ganlikun 0:13413ea9a877 1792
ganlikun 0:13413ea9a877 1793
ganlikun 0:13413ea9a877 1794
ganlikun 0:13413ea9a877 1795
ganlikun 0:13413ea9a877 1796 /* ################################## SysTick function ############################################ */
ganlikun 0:13413ea9a877 1797 /**
ganlikun 0:13413ea9a877 1798 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:13413ea9a877 1799 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
ganlikun 0:13413ea9a877 1800 \brief Functions that configure the System.
ganlikun 0:13413ea9a877 1801 @{
ganlikun 0:13413ea9a877 1802 */
ganlikun 0:13413ea9a877 1803
ganlikun 0:13413ea9a877 1804 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
ganlikun 0:13413ea9a877 1805
ganlikun 0:13413ea9a877 1806 /**
ganlikun 0:13413ea9a877 1807 \brief System Tick Configuration
ganlikun 0:13413ea9a877 1808 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
ganlikun 0:13413ea9a877 1809 Counter is in free running mode to generate periodic interrupts.
ganlikun 0:13413ea9a877 1810 \param [in] ticks Number of ticks between two interrupts.
ganlikun 0:13413ea9a877 1811 \return 0 Function succeeded.
ganlikun 0:13413ea9a877 1812 \return 1 Function failed.
ganlikun 0:13413ea9a877 1813 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ganlikun 0:13413ea9a877 1814 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
ganlikun 0:13413ea9a877 1815 must contain a vendor-specific implementation of this function.
ganlikun 0:13413ea9a877 1816 */
ganlikun 0:13413ea9a877 1817 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ganlikun 0:13413ea9a877 1818 {
ganlikun 0:13413ea9a877 1819 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
ganlikun 0:13413ea9a877 1820 {
ganlikun 0:13413ea9a877 1821 return (1UL); /* Reload value impossible */
ganlikun 0:13413ea9a877 1822 }
ganlikun 0:13413ea9a877 1823
ganlikun 0:13413ea9a877 1824 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
ganlikun 0:13413ea9a877 1825 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
ganlikun 0:13413ea9a877 1826 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
ganlikun 0:13413ea9a877 1827 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
ganlikun 0:13413ea9a877 1828 SysTick_CTRL_TICKINT_Msk |
ganlikun 0:13413ea9a877 1829 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ganlikun 0:13413ea9a877 1830 return (0UL); /* Function successful */
ganlikun 0:13413ea9a877 1831 }
ganlikun 0:13413ea9a877 1832
ganlikun 0:13413ea9a877 1833 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:13413ea9a877 1834 /**
ganlikun 0:13413ea9a877 1835 \brief System Tick Configuration (non-secure)
ganlikun 0:13413ea9a877 1836 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
ganlikun 0:13413ea9a877 1837 Counter is in free running mode to generate periodic interrupts.
ganlikun 0:13413ea9a877 1838 \param [in] ticks Number of ticks between two interrupts.
ganlikun 0:13413ea9a877 1839 \return 0 Function succeeded.
ganlikun 0:13413ea9a877 1840 \return 1 Function failed.
ganlikun 0:13413ea9a877 1841 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ganlikun 0:13413ea9a877 1842 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
ganlikun 0:13413ea9a877 1843 must contain a vendor-specific implementation of this function.
ganlikun 0:13413ea9a877 1844
ganlikun 0:13413ea9a877 1845 */
ganlikun 0:13413ea9a877 1846 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
ganlikun 0:13413ea9a877 1847 {
ganlikun 0:13413ea9a877 1848 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
ganlikun 0:13413ea9a877 1849 {
ganlikun 0:13413ea9a877 1850 return (1UL); /* Reload value impossible */
ganlikun 0:13413ea9a877 1851 }
ganlikun 0:13413ea9a877 1852
ganlikun 0:13413ea9a877 1853 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
ganlikun 0:13413ea9a877 1854 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
ganlikun 0:13413ea9a877 1855 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
ganlikun 0:13413ea9a877 1856 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
ganlikun 0:13413ea9a877 1857 SysTick_CTRL_TICKINT_Msk |
ganlikun 0:13413ea9a877 1858 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ganlikun 0:13413ea9a877 1859 return (0UL); /* Function successful */
ganlikun 0:13413ea9a877 1860 }
ganlikun 0:13413ea9a877 1861 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:13413ea9a877 1862
ganlikun 0:13413ea9a877 1863 #endif
ganlikun 0:13413ea9a877 1864
ganlikun 0:13413ea9a877 1865 /*@} end of CMSIS_Core_SysTickFunctions */
ganlikun 0:13413ea9a877 1866
ganlikun 0:13413ea9a877 1867
ganlikun 0:13413ea9a877 1868
ganlikun 0:13413ea9a877 1869
ganlikun 0:13413ea9a877 1870 #ifdef __cplusplus
ganlikun 0:13413ea9a877 1871 }
ganlikun 0:13413ea9a877 1872 #endif
ganlikun 0:13413ea9a877 1873
ganlikun 0:13413ea9a877 1874 #endif /* __CORE_CM23_H_DEPENDANT */
ganlikun 0:13413ea9a877 1875
ganlikun 0:13413ea9a877 1876 #endif /* __CMSIS_GENERIC */
ganlikun 0:13413ea9a877 1877