Gan likun / The prosthetic control

The prosthetic control（MIT）

cmsis/core_sc000.h@0:20e0c61e0684, 2022-06-23 (annotated)

Committer:
ganlikun
Date:
Thu Jun 23 05:23:34 2022 +0000
Revision:
0:20e0c61e0684
01

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ganlikun 0:20e0c61e0684 1 /**************************************************************************//**
ganlikun 0:20e0c61e0684 2 * @file core_sc000.h
ganlikun 0:20e0c61e0684 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
ganlikun 0:20e0c61e0684 4 * @version V5.0.2
ganlikun 0:20e0c61e0684 5 * @date 13. February 2017
ganlikun 0:20e0c61e0684 6 ******************************************************************************/
ganlikun 0:20e0c61e0684 7 /*
ganlikun 0:20e0c61e0684 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
ganlikun 0:20e0c61e0684 9 *
ganlikun 0:20e0c61e0684 10 * SPDX-License-Identifier: Apache-2.0
ganlikun 0:20e0c61e0684 11 *
ganlikun 0:20e0c61e0684 12 * Licensed under the Apache License, Version 2.0 (the License); you may
ganlikun 0:20e0c61e0684 13 * not use this file except in compliance with the License.
ganlikun 0:20e0c61e0684 14 * You may obtain a copy of the License at
ganlikun 0:20e0c61e0684 15 *
ganlikun 0:20e0c61e0684 16 * www.apache.org/licenses/LICENSE-2.0
ganlikun 0:20e0c61e0684 17 *
ganlikun 0:20e0c61e0684 18 * Unless required by applicable law or agreed to in writing, software
ganlikun 0:20e0c61e0684 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ganlikun 0:20e0c61e0684 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ganlikun 0:20e0c61e0684 21 * See the License for the specific language governing permissions and
ganlikun 0:20e0c61e0684 22 * limitations under the License.
ganlikun 0:20e0c61e0684 23 */
ganlikun 0:20e0c61e0684 24
ganlikun 0:20e0c61e0684 25 #if defined ( __ICCARM__ )
ganlikun 0:20e0c61e0684 26 #pragma system_include /* treat file as system include file for MISRA check */
ganlikun 0:20e0c61e0684 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:20e0c61e0684 28 #pragma clang system_header /* treat file as system include file */
ganlikun 0:20e0c61e0684 29 #endif
ganlikun 0:20e0c61e0684 30
ganlikun 0:20e0c61e0684 31 #ifndef __CORE_SC000_H_GENERIC
ganlikun 0:20e0c61e0684 32 #define __CORE_SC000_H_GENERIC
ganlikun 0:20e0c61e0684 33
ganlikun 0:20e0c61e0684 34 #include <stdint.h>
ganlikun 0:20e0c61e0684 35
ganlikun 0:20e0c61e0684 36 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 37 extern "C" {
ganlikun 0:20e0c61e0684 38 #endif
ganlikun 0:20e0c61e0684 39
ganlikun 0:20e0c61e0684 40 /**
ganlikun 0:20e0c61e0684 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
ganlikun 0:20e0c61e0684 42 CMSIS violates the following MISRA-C:2004 rules:
ganlikun 0:20e0c61e0684 43
ganlikun 0:20e0c61e0684 44 \li Required Rule 8.5, object/function definition in header file.<br>
ganlikun 0:20e0c61e0684 45 Function definitions in header files are used to allow 'inlining'.
ganlikun 0:20e0c61e0684 46
ganlikun 0:20e0c61e0684 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
ganlikun 0:20e0c61e0684 48 Unions are used for effective representation of core registers.
ganlikun 0:20e0c61e0684 49
ganlikun 0:20e0c61e0684 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
ganlikun 0:20e0c61e0684 51 Function-like macros are used to allow more efficient code.
ganlikun 0:20e0c61e0684 52 */
ganlikun 0:20e0c61e0684 53
ganlikun 0:20e0c61e0684 54
ganlikun 0:20e0c61e0684 55 /*******************************************************************************
ganlikun 0:20e0c61e0684 56 * CMSIS definitions
ganlikun 0:20e0c61e0684 57 ******************************************************************************/
ganlikun 0:20e0c61e0684 58 /**
ganlikun 0:20e0c61e0684 59 \ingroup SC000
ganlikun 0:20e0c61e0684 60 @{
ganlikun 0:20e0c61e0684 61 */
ganlikun 0:20e0c61e0684 62
ganlikun 0:20e0c61e0684 63 /* CMSIS SC000 definitions */
ganlikun 0:20e0c61e0684 64 #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
ganlikun 0:20e0c61e0684 65 #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
ganlikun 0:20e0c61e0684 66 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
ganlikun 0:20e0c61e0684 67 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
ganlikun 0:20e0c61e0684 68
ganlikun 0:20e0c61e0684 69 #define __CORTEX_SC (000U) /*!< Cortex secure core */
ganlikun 0:20e0c61e0684 70
ganlikun 0:20e0c61e0684 71 /** __FPU_USED indicates whether an FPU is used or not.
ganlikun 0:20e0c61e0684 72 This core does not support an FPU at all
ganlikun 0:20e0c61e0684 73 */
ganlikun 0:20e0c61e0684 74 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 75
ganlikun 0:20e0c61e0684 76 #if defined ( __CC_ARM )
ganlikun 0:20e0c61e0684 77 #if defined __TARGET_FPU_VFP
ganlikun 0:20e0c61e0684 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 79 #endif
ganlikun 0:20e0c61e0684 80
ganlikun 0:20e0c61e0684 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:20e0c61e0684 82 #if defined __ARM_PCS_VFP
ganlikun 0:20e0c61e0684 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 84 #endif
ganlikun 0:20e0c61e0684 85
ganlikun 0:20e0c61e0684 86 #elif defined ( __GNUC__ )
ganlikun 0:20e0c61e0684 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
ganlikun 0:20e0c61e0684 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 89 #endif
ganlikun 0:20e0c61e0684 90
ganlikun 0:20e0c61e0684 91 #elif defined ( __ICCARM__ )
ganlikun 0:20e0c61e0684 92 #if defined __ARMVFP__
ganlikun 0:20e0c61e0684 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 94 #endif
ganlikun 0:20e0c61e0684 95
ganlikun 0:20e0c61e0684 96 #elif defined ( __TI_ARM__ )
ganlikun 0:20e0c61e0684 97 #if defined __TI_VFP_SUPPORT__
ganlikun 0:20e0c61e0684 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 99 #endif
ganlikun 0:20e0c61e0684 100
ganlikun 0:20e0c61e0684 101 #elif defined ( __TASKING__ )
ganlikun 0:20e0c61e0684 102 #if defined __FPU_VFP__
ganlikun 0:20e0c61e0684 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 104 #endif
ganlikun 0:20e0c61e0684 105
ganlikun 0:20e0c61e0684 106 #elif defined ( __CSMC__ )
ganlikun 0:20e0c61e0684 107 #if ( __CSMC__ & 0x400U)
ganlikun 0:20e0c61e0684 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 109 #endif
ganlikun 0:20e0c61e0684 110
ganlikun 0:20e0c61e0684 111 #endif
ganlikun 0:20e0c61e0684 112
ganlikun 0:20e0c61e0684 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
ganlikun 0:20e0c61e0684 114
ganlikun 0:20e0c61e0684 115
ganlikun 0:20e0c61e0684 116 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 117 }
ganlikun 0:20e0c61e0684 118 #endif
ganlikun 0:20e0c61e0684 119
ganlikun 0:20e0c61e0684 120 #endif /* __CORE_SC000_H_GENERIC */
ganlikun 0:20e0c61e0684 121
ganlikun 0:20e0c61e0684 122 #ifndef __CMSIS_GENERIC
ganlikun 0:20e0c61e0684 123
ganlikun 0:20e0c61e0684 124 #ifndef __CORE_SC000_H_DEPENDANT
ganlikun 0:20e0c61e0684 125 #define __CORE_SC000_H_DEPENDANT
ganlikun 0:20e0c61e0684 126
ganlikun 0:20e0c61e0684 127 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 128 extern "C" {
ganlikun 0:20e0c61e0684 129 #endif
ganlikun 0:20e0c61e0684 130
ganlikun 0:20e0c61e0684 131 /* check device defines and use defaults */
ganlikun 0:20e0c61e0684 132 #if defined __CHECK_DEVICE_DEFINES
ganlikun 0:20e0c61e0684 133 #ifndef __SC000_REV
ganlikun 0:20e0c61e0684 134 #define __SC000_REV 0x0000U
ganlikun 0:20e0c61e0684 135 #warning "__SC000_REV not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 136 #endif
ganlikun 0:20e0c61e0684 137
ganlikun 0:20e0c61e0684 138 #ifndef __MPU_PRESENT
ganlikun 0:20e0c61e0684 139 #define __MPU_PRESENT 0U
ganlikun 0:20e0c61e0684 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 141 #endif
ganlikun 0:20e0c61e0684 142
ganlikun 0:20e0c61e0684 143 #ifndef __NVIC_PRIO_BITS
ganlikun 0:20e0c61e0684 144 #define __NVIC_PRIO_BITS 2U
ganlikun 0:20e0c61e0684 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 146 #endif
ganlikun 0:20e0c61e0684 147
ganlikun 0:20e0c61e0684 148 #ifndef __Vendor_SysTickConfig
ganlikun 0:20e0c61e0684 149 #define __Vendor_SysTickConfig 0U
ganlikun 0:20e0c61e0684 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 151 #endif
ganlikun 0:20e0c61e0684 152 #endif
ganlikun 0:20e0c61e0684 153
ganlikun 0:20e0c61e0684 154 /* IO definitions (access restrictions to peripheral registers) */
ganlikun 0:20e0c61e0684 155 /**
ganlikun 0:20e0c61e0684 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
ganlikun 0:20e0c61e0684 157
ganlikun 0:20e0c61e0684 158 <strong>IO Type Qualifiers</strong> are used
ganlikun 0:20e0c61e0684 159 \li to specify the access to peripheral variables.
ganlikun 0:20e0c61e0684 160 \li for automatic generation of peripheral register debug information.
ganlikun 0:20e0c61e0684 161 */
ganlikun 0:20e0c61e0684 162 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 163 #define __I volatile /*!< Defines 'read only' permissions */
ganlikun 0:20e0c61e0684 164 #else
ganlikun 0:20e0c61e0684 165 #define __I volatile const /*!< Defines 'read only' permissions */
ganlikun 0:20e0c61e0684 166 #endif
ganlikun 0:20e0c61e0684 167 #define __O volatile /*!< Defines 'write only' permissions */
ganlikun 0:20e0c61e0684 168 #define __IO volatile /*!< Defines 'read / write' permissions */
ganlikun 0:20e0c61e0684 169
ganlikun 0:20e0c61e0684 170 /* following defines should be used for structure members */
ganlikun 0:20e0c61e0684 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
ganlikun 0:20e0c61e0684 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
ganlikun 0:20e0c61e0684 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
ganlikun 0:20e0c61e0684 174
ganlikun 0:20e0c61e0684 175 /*@} end of group SC000 */
ganlikun 0:20e0c61e0684 176
ganlikun 0:20e0c61e0684 177
ganlikun 0:20e0c61e0684 178
ganlikun 0:20e0c61e0684 179 /*******************************************************************************
ganlikun 0:20e0c61e0684 180 * Register Abstraction
ganlikun 0:20e0c61e0684 181 Core Register contain:
ganlikun 0:20e0c61e0684 182 - Core Register
ganlikun 0:20e0c61e0684 183 - Core NVIC Register
ganlikun 0:20e0c61e0684 184 - Core SCB Register
ganlikun 0:20e0c61e0684 185 - Core SysTick Register
ganlikun 0:20e0c61e0684 186 - Core MPU Register
ganlikun 0:20e0c61e0684 187 ******************************************************************************/
ganlikun 0:20e0c61e0684 188 /**
ganlikun 0:20e0c61e0684 189 \defgroup CMSIS_core_register Defines and Type Definitions
ganlikun 0:20e0c61e0684 190 \brief Type definitions and defines for Cortex-M processor based devices.
ganlikun 0:20e0c61e0684 191 */
ganlikun 0:20e0c61e0684 192
ganlikun 0:20e0c61e0684 193 /**
ganlikun 0:20e0c61e0684 194 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 195 \defgroup CMSIS_CORE Status and Control Registers
ganlikun 0:20e0c61e0684 196 \brief Core Register type definitions.
ganlikun 0:20e0c61e0684 197 @{
ganlikun 0:20e0c61e0684 198 */
ganlikun 0:20e0c61e0684 199
ganlikun 0:20e0c61e0684 200 /**
ganlikun 0:20e0c61e0684 201 \brief Union type to access the Application Program Status Register (APSR).
ganlikun 0:20e0c61e0684 202 */
ganlikun 0:20e0c61e0684 203 typedef union
ganlikun 0:20e0c61e0684 204 {
ganlikun 0:20e0c61e0684 205 struct
ganlikun 0:20e0c61e0684 206 {
ganlikun 0:20e0c61e0684 207 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
ganlikun 0:20e0c61e0684 208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:20e0c61e0684 209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:20e0c61e0684 210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:20e0c61e0684 211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:20e0c61e0684 212 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 213 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 214 } APSR_Type;
ganlikun 0:20e0c61e0684 215
ganlikun 0:20e0c61e0684 216 /* APSR Register Definitions */
ganlikun 0:20e0c61e0684 217 #define APSR_N_Pos 31U /*!< APSR: N Position */
ganlikun 0:20e0c61e0684 218 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
ganlikun 0:20e0c61e0684 219
ganlikun 0:20e0c61e0684 220 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
ganlikun 0:20e0c61e0684 221 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
ganlikun 0:20e0c61e0684 222
ganlikun 0:20e0c61e0684 223 #define APSR_C_Pos 29U /*!< APSR: C Position */
ganlikun 0:20e0c61e0684 224 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
ganlikun 0:20e0c61e0684 225
ganlikun 0:20e0c61e0684 226 #define APSR_V_Pos 28U /*!< APSR: V Position */
ganlikun 0:20e0c61e0684 227 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
ganlikun 0:20e0c61e0684 228
ganlikun 0:20e0c61e0684 229
ganlikun 0:20e0c61e0684 230 /**
ganlikun 0:20e0c61e0684 231 \brief Union type to access the Interrupt Program Status Register (IPSR).
ganlikun 0:20e0c61e0684 232 */
ganlikun 0:20e0c61e0684 233 typedef union
ganlikun 0:20e0c61e0684 234 {
ganlikun 0:20e0c61e0684 235 struct
ganlikun 0:20e0c61e0684 236 {
ganlikun 0:20e0c61e0684 237 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:20e0c61e0684 238 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
ganlikun 0:20e0c61e0684 239 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 240 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 241 } IPSR_Type;
ganlikun 0:20e0c61e0684 242
ganlikun 0:20e0c61e0684 243 /* IPSR Register Definitions */
ganlikun 0:20e0c61e0684 244 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
ganlikun 0:20e0c61e0684 245 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
ganlikun 0:20e0c61e0684 246
ganlikun 0:20e0c61e0684 247
ganlikun 0:20e0c61e0684 248 /**
ganlikun 0:20e0c61e0684 249 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ganlikun 0:20e0c61e0684 250 */
ganlikun 0:20e0c61e0684 251 typedef union
ganlikun 0:20e0c61e0684 252 {
ganlikun 0:20e0c61e0684 253 struct
ganlikun 0:20e0c61e0684 254 {
ganlikun 0:20e0c61e0684 255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:20e0c61e0684 256 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
ganlikun 0:20e0c61e0684 257 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
ganlikun 0:20e0c61e0684 258 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
ganlikun 0:20e0c61e0684 259 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:20e0c61e0684 260 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:20e0c61e0684 261 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:20e0c61e0684 262 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:20e0c61e0684 263 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 264 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 265 } xPSR_Type;
ganlikun 0:20e0c61e0684 266
ganlikun 0:20e0c61e0684 267 /* xPSR Register Definitions */
ganlikun 0:20e0c61e0684 268 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
ganlikun 0:20e0c61e0684 269 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
ganlikun 0:20e0c61e0684 270
ganlikun 0:20e0c61e0684 271 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
ganlikun 0:20e0c61e0684 272 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
ganlikun 0:20e0c61e0684 273
ganlikun 0:20e0c61e0684 274 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
ganlikun 0:20e0c61e0684 275 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
ganlikun 0:20e0c61e0684 276
ganlikun 0:20e0c61e0684 277 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
ganlikun 0:20e0c61e0684 278 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
ganlikun 0:20e0c61e0684 279
ganlikun 0:20e0c61e0684 280 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
ganlikun 0:20e0c61e0684 281 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
ganlikun 0:20e0c61e0684 282
ganlikun 0:20e0c61e0684 283 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
ganlikun 0:20e0c61e0684 284 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
ganlikun 0:20e0c61e0684 285
ganlikun 0:20e0c61e0684 286
ganlikun 0:20e0c61e0684 287 /**
ganlikun 0:20e0c61e0684 288 \brief Union type to access the Control Registers (CONTROL).
ganlikun 0:20e0c61e0684 289 */
ganlikun 0:20e0c61e0684 290 typedef union
ganlikun 0:20e0c61e0684 291 {
ganlikun 0:20e0c61e0684 292 struct
ganlikun 0:20e0c61e0684 293 {
ganlikun 0:20e0c61e0684 294 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
ganlikun 0:20e0c61e0684 295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
ganlikun 0:20e0c61e0684 296 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
ganlikun 0:20e0c61e0684 297 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 298 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 299 } CONTROL_Type;
ganlikun 0:20e0c61e0684 300
ganlikun 0:20e0c61e0684 301 /* CONTROL Register Definitions */
ganlikun 0:20e0c61e0684 302 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
ganlikun 0:20e0c61e0684 303 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
ganlikun 0:20e0c61e0684 304
ganlikun 0:20e0c61e0684 305 /*@} end of group CMSIS_CORE */
ganlikun 0:20e0c61e0684 306
ganlikun 0:20e0c61e0684 307
ganlikun 0:20e0c61e0684 308 /**
ganlikun 0:20e0c61e0684 309 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 310 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
ganlikun 0:20e0c61e0684 311 \brief Type definitions for the NVIC Registers
ganlikun 0:20e0c61e0684 312 @{
ganlikun 0:20e0c61e0684 313 */
ganlikun 0:20e0c61e0684 314
ganlikun 0:20e0c61e0684 315 /**
ganlikun 0:20e0c61e0684 316 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
ganlikun 0:20e0c61e0684 317 */
ganlikun 0:20e0c61e0684 318 typedef struct
ganlikun 0:20e0c61e0684 319 {
ganlikun 0:20e0c61e0684 320 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
ganlikun 0:20e0c61e0684 321 uint32_t RESERVED0[31U];
ganlikun 0:20e0c61e0684 322 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
ganlikun 0:20e0c61e0684 323 uint32_t RSERVED1[31U];
ganlikun 0:20e0c61e0684 324 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
ganlikun 0:20e0c61e0684 325 uint32_t RESERVED2[31U];
ganlikun 0:20e0c61e0684 326 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
ganlikun 0:20e0c61e0684 327 uint32_t RESERVED3[31U];
ganlikun 0:20e0c61e0684 328 uint32_t RESERVED4[64U];
ganlikun 0:20e0c61e0684 329 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
ganlikun 0:20e0c61e0684 330 } NVIC_Type;
ganlikun 0:20e0c61e0684 331
ganlikun 0:20e0c61e0684 332 /*@} end of group CMSIS_NVIC */
ganlikun 0:20e0c61e0684 333
ganlikun 0:20e0c61e0684 334
ganlikun 0:20e0c61e0684 335 /**
ganlikun 0:20e0c61e0684 336 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 337 \defgroup CMSIS_SCB System Control Block (SCB)
ganlikun 0:20e0c61e0684 338 \brief Type definitions for the System Control Block Registers
ganlikun 0:20e0c61e0684 339 @{
ganlikun 0:20e0c61e0684 340 */
ganlikun 0:20e0c61e0684 341
ganlikun 0:20e0c61e0684 342 /**
ganlikun 0:20e0c61e0684 343 \brief Structure type to access the System Control Block (SCB).
ganlikun 0:20e0c61e0684 344 */
ganlikun 0:20e0c61e0684 345 typedef struct
ganlikun 0:20e0c61e0684 346 {
ganlikun 0:20e0c61e0684 347 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
ganlikun 0:20e0c61e0684 348 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
ganlikun 0:20e0c61e0684 349 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
ganlikun 0:20e0c61e0684 350 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
ganlikun 0:20e0c61e0684 351 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
ganlikun 0:20e0c61e0684 352 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
ganlikun 0:20e0c61e0684 353 uint32_t RESERVED0[1U];
ganlikun 0:20e0c61e0684 354 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
ganlikun 0:20e0c61e0684 355 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
ganlikun 0:20e0c61e0684 356 uint32_t RESERVED1[154U];
ganlikun 0:20e0c61e0684 357 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
ganlikun 0:20e0c61e0684 358 } SCB_Type;
ganlikun 0:20e0c61e0684 359
ganlikun 0:20e0c61e0684 360 /* SCB CPUID Register Definitions */
ganlikun 0:20e0c61e0684 361 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
ganlikun 0:20e0c61e0684 362 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
ganlikun 0:20e0c61e0684 363
ganlikun 0:20e0c61e0684 364 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
ganlikun 0:20e0c61e0684 365 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
ganlikun 0:20e0c61e0684 366
ganlikun 0:20e0c61e0684 367 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
ganlikun 0:20e0c61e0684 368 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
ganlikun 0:20e0c61e0684 369
ganlikun 0:20e0c61e0684 370 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
ganlikun 0:20e0c61e0684 371 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
ganlikun 0:20e0c61e0684 372
ganlikun 0:20e0c61e0684 373 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
ganlikun 0:20e0c61e0684 374 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
ganlikun 0:20e0c61e0684 375
ganlikun 0:20e0c61e0684 376 /* SCB Interrupt Control State Register Definitions */
ganlikun 0:20e0c61e0684 377 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
ganlikun 0:20e0c61e0684 378 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
ganlikun 0:20e0c61e0684 379
ganlikun 0:20e0c61e0684 380 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
ganlikun 0:20e0c61e0684 381 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
ganlikun 0:20e0c61e0684 382
ganlikun 0:20e0c61e0684 383 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
ganlikun 0:20e0c61e0684 384 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
ganlikun 0:20e0c61e0684 385
ganlikun 0:20e0c61e0684 386 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
ganlikun 0:20e0c61e0684 387 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
ganlikun 0:20e0c61e0684 388
ganlikun 0:20e0c61e0684 389 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
ganlikun 0:20e0c61e0684 390 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
ganlikun 0:20e0c61e0684 391
ganlikun 0:20e0c61e0684 392 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
ganlikun 0:20e0c61e0684 393 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
ganlikun 0:20e0c61e0684 394
ganlikun 0:20e0c61e0684 395 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
ganlikun 0:20e0c61e0684 396 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
ganlikun 0:20e0c61e0684 397
ganlikun 0:20e0c61e0684 398 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
ganlikun 0:20e0c61e0684 399 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
ganlikun 0:20e0c61e0684 400
ganlikun 0:20e0c61e0684 401 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
ganlikun 0:20e0c61e0684 402 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
ganlikun 0:20e0c61e0684 403
ganlikun 0:20e0c61e0684 404 /* SCB Interrupt Control State Register Definitions */
ganlikun 0:20e0c61e0684 405 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
ganlikun 0:20e0c61e0684 406 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
ganlikun 0:20e0c61e0684 407
ganlikun 0:20e0c61e0684 408 /* SCB Application Interrupt and Reset Control Register Definitions */
ganlikun 0:20e0c61e0684 409 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
ganlikun 0:20e0c61e0684 410 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
ganlikun 0:20e0c61e0684 411
ganlikun 0:20e0c61e0684 412 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
ganlikun 0:20e0c61e0684 413 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
ganlikun 0:20e0c61e0684 414
ganlikun 0:20e0c61e0684 415 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
ganlikun 0:20e0c61e0684 416 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
ganlikun 0:20e0c61e0684 417
ganlikun 0:20e0c61e0684 418 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
ganlikun 0:20e0c61e0684 419 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
ganlikun 0:20e0c61e0684 420
ganlikun 0:20e0c61e0684 421 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
ganlikun 0:20e0c61e0684 422 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
ganlikun 0:20e0c61e0684 423
ganlikun 0:20e0c61e0684 424 /* SCB System Control Register Definitions */
ganlikun 0:20e0c61e0684 425 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
ganlikun 0:20e0c61e0684 426 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
ganlikun 0:20e0c61e0684 427
ganlikun 0:20e0c61e0684 428 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
ganlikun 0:20e0c61e0684 429 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
ganlikun 0:20e0c61e0684 430
ganlikun 0:20e0c61e0684 431 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
ganlikun 0:20e0c61e0684 432 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
ganlikun 0:20e0c61e0684 433
ganlikun 0:20e0c61e0684 434 /* SCB Configuration Control Register Definitions */
ganlikun 0:20e0c61e0684 435 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
ganlikun 0:20e0c61e0684 436 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
ganlikun 0:20e0c61e0684 437
ganlikun 0:20e0c61e0684 438 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
ganlikun 0:20e0c61e0684 439 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
ganlikun 0:20e0c61e0684 440
ganlikun 0:20e0c61e0684 441 /* SCB System Handler Control and State Register Definitions */
ganlikun 0:20e0c61e0684 442 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
ganlikun 0:20e0c61e0684 443 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
ganlikun 0:20e0c61e0684 444
ganlikun 0:20e0c61e0684 445 /*@} end of group CMSIS_SCB */
ganlikun 0:20e0c61e0684 446
ganlikun 0:20e0c61e0684 447
ganlikun 0:20e0c61e0684 448 /**
ganlikun 0:20e0c61e0684 449 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 450 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
ganlikun 0:20e0c61e0684 451 \brief Type definitions for the System Control and ID Register not in the SCB
ganlikun 0:20e0c61e0684 452 @{
ganlikun 0:20e0c61e0684 453 */
ganlikun 0:20e0c61e0684 454
ganlikun 0:20e0c61e0684 455 /**
ganlikun 0:20e0c61e0684 456 \brief Structure type to access the System Control and ID Register not in the SCB.
ganlikun 0:20e0c61e0684 457 */
ganlikun 0:20e0c61e0684 458 typedef struct
ganlikun 0:20e0c61e0684 459 {
ganlikun 0:20e0c61e0684 460 uint32_t RESERVED0[2U];
ganlikun 0:20e0c61e0684 461 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
ganlikun 0:20e0c61e0684 462 } SCnSCB_Type;
ganlikun 0:20e0c61e0684 463
ganlikun 0:20e0c61e0684 464 /* Auxiliary Control Register Definitions */
ganlikun 0:20e0c61e0684 465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
ganlikun 0:20e0c61e0684 466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
ganlikun 0:20e0c61e0684 467
ganlikun 0:20e0c61e0684 468 /*@} end of group CMSIS_SCnotSCB */
ganlikun 0:20e0c61e0684 469
ganlikun 0:20e0c61e0684 470
ganlikun 0:20e0c61e0684 471 /**
ganlikun 0:20e0c61e0684 472 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 473 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
ganlikun 0:20e0c61e0684 474 \brief Type definitions for the System Timer Registers.
ganlikun 0:20e0c61e0684 475 @{
ganlikun 0:20e0c61e0684 476 */
ganlikun 0:20e0c61e0684 477
ganlikun 0:20e0c61e0684 478 /**
ganlikun 0:20e0c61e0684 479 \brief Structure type to access the System Timer (SysTick).
ganlikun 0:20e0c61e0684 480 */
ganlikun 0:20e0c61e0684 481 typedef struct
ganlikun 0:20e0c61e0684 482 {
ganlikun 0:20e0c61e0684 483 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
ganlikun 0:20e0c61e0684 484 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
ganlikun 0:20e0c61e0684 485 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
ganlikun 0:20e0c61e0684 486 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
ganlikun 0:20e0c61e0684 487 } SysTick_Type;
ganlikun 0:20e0c61e0684 488
ganlikun 0:20e0c61e0684 489 /* SysTick Control / Status Register Definitions */
ganlikun 0:20e0c61e0684 490 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
ganlikun 0:20e0c61e0684 491 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
ganlikun 0:20e0c61e0684 492
ganlikun 0:20e0c61e0684 493 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
ganlikun 0:20e0c61e0684 494 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
ganlikun 0:20e0c61e0684 495
ganlikun 0:20e0c61e0684 496 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
ganlikun 0:20e0c61e0684 497 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
ganlikun 0:20e0c61e0684 498
ganlikun 0:20e0c61e0684 499 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
ganlikun 0:20e0c61e0684 500 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
ganlikun 0:20e0c61e0684 501
ganlikun 0:20e0c61e0684 502 /* SysTick Reload Register Definitions */
ganlikun 0:20e0c61e0684 503 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
ganlikun 0:20e0c61e0684 504 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
ganlikun 0:20e0c61e0684 505
ganlikun 0:20e0c61e0684 506 /* SysTick Current Register Definitions */
ganlikun 0:20e0c61e0684 507 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
ganlikun 0:20e0c61e0684 508 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
ganlikun 0:20e0c61e0684 509
ganlikun 0:20e0c61e0684 510 /* SysTick Calibration Register Definitions */
ganlikun 0:20e0c61e0684 511 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
ganlikun 0:20e0c61e0684 512 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
ganlikun 0:20e0c61e0684 513
ganlikun 0:20e0c61e0684 514 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
ganlikun 0:20e0c61e0684 515 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
ganlikun 0:20e0c61e0684 516
ganlikun 0:20e0c61e0684 517 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
ganlikun 0:20e0c61e0684 518 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
ganlikun 0:20e0c61e0684 519
ganlikun 0:20e0c61e0684 520 /*@} end of group CMSIS_SysTick */
ganlikun 0:20e0c61e0684 521
ganlikun 0:20e0c61e0684 522 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:20e0c61e0684 523 /**
ganlikun 0:20e0c61e0684 524 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 525 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
ganlikun 0:20e0c61e0684 526 \brief Type definitions for the Memory Protection Unit (MPU)
ganlikun 0:20e0c61e0684 527 @{
ganlikun 0:20e0c61e0684 528 */
ganlikun 0:20e0c61e0684 529
ganlikun 0:20e0c61e0684 530 /**
ganlikun 0:20e0c61e0684 531 \brief Structure type to access the Memory Protection Unit (MPU).
ganlikun 0:20e0c61e0684 532 */
ganlikun 0:20e0c61e0684 533 typedef struct
ganlikun 0:20e0c61e0684 534 {
ganlikun 0:20e0c61e0684 535 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
ganlikun 0:20e0c61e0684 536 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
ganlikun 0:20e0c61e0684 537 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
ganlikun 0:20e0c61e0684 538 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
ganlikun 0:20e0c61e0684 539 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
ganlikun 0:20e0c61e0684 540 } MPU_Type;
ganlikun 0:20e0c61e0684 541
ganlikun 0:20e0c61e0684 542 /* MPU Type Register Definitions */
ganlikun 0:20e0c61e0684 543 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
ganlikun 0:20e0c61e0684 544 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
ganlikun 0:20e0c61e0684 545
ganlikun 0:20e0c61e0684 546 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
ganlikun 0:20e0c61e0684 547 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
ganlikun 0:20e0c61e0684 548
ganlikun 0:20e0c61e0684 549 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
ganlikun 0:20e0c61e0684 550 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
ganlikun 0:20e0c61e0684 551
ganlikun 0:20e0c61e0684 552 /* MPU Control Register Definitions */
ganlikun 0:20e0c61e0684 553 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
ganlikun 0:20e0c61e0684 554 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
ganlikun 0:20e0c61e0684 555
ganlikun 0:20e0c61e0684 556 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
ganlikun 0:20e0c61e0684 557 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
ganlikun 0:20e0c61e0684 558
ganlikun 0:20e0c61e0684 559 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
ganlikun 0:20e0c61e0684 560 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
ganlikun 0:20e0c61e0684 561
ganlikun 0:20e0c61e0684 562 /* MPU Region Number Register Definitions */
ganlikun 0:20e0c61e0684 563 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
ganlikun 0:20e0c61e0684 564 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
ganlikun 0:20e0c61e0684 565
ganlikun 0:20e0c61e0684 566 /* MPU Region Base Address Register Definitions */
ganlikun 0:20e0c61e0684 567 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
ganlikun 0:20e0c61e0684 568 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
ganlikun 0:20e0c61e0684 569
ganlikun 0:20e0c61e0684 570 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
ganlikun 0:20e0c61e0684 571 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
ganlikun 0:20e0c61e0684 572
ganlikun 0:20e0c61e0684 573 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
ganlikun 0:20e0c61e0684 574 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
ganlikun 0:20e0c61e0684 575
ganlikun 0:20e0c61e0684 576 /* MPU Region Attribute and Size Register Definitions */
ganlikun 0:20e0c61e0684 577 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
ganlikun 0:20e0c61e0684 578 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
ganlikun 0:20e0c61e0684 579
ganlikun 0:20e0c61e0684 580 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
ganlikun 0:20e0c61e0684 581 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
ganlikun 0:20e0c61e0684 582
ganlikun 0:20e0c61e0684 583 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
ganlikun 0:20e0c61e0684 584 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
ganlikun 0:20e0c61e0684 585
ganlikun 0:20e0c61e0684 586 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
ganlikun 0:20e0c61e0684 587 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
ganlikun 0:20e0c61e0684 588
ganlikun 0:20e0c61e0684 589 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
ganlikun 0:20e0c61e0684 590 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
ganlikun 0:20e0c61e0684 591
ganlikun 0:20e0c61e0684 592 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
ganlikun 0:20e0c61e0684 593 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
ganlikun 0:20e0c61e0684 594
ganlikun 0:20e0c61e0684 595 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
ganlikun 0:20e0c61e0684 596 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
ganlikun 0:20e0c61e0684 597
ganlikun 0:20e0c61e0684 598 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
ganlikun 0:20e0c61e0684 599 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
ganlikun 0:20e0c61e0684 600
ganlikun 0:20e0c61e0684 601 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
ganlikun 0:20e0c61e0684 602 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
ganlikun 0:20e0c61e0684 603
ganlikun 0:20e0c61e0684 604 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
ganlikun 0:20e0c61e0684 605 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
ganlikun 0:20e0c61e0684 606
ganlikun 0:20e0c61e0684 607 /*@} end of group CMSIS_MPU */
ganlikun 0:20e0c61e0684 608 #endif
ganlikun 0:20e0c61e0684 609
ganlikun 0:20e0c61e0684 610
ganlikun 0:20e0c61e0684 611 /**
ganlikun 0:20e0c61e0684 612 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 613 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
ganlikun 0:20e0c61e0684 614 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
ganlikun 0:20e0c61e0684 615 Therefore they are not covered by the SC000 header file.
ganlikun 0:20e0c61e0684 616 @{
ganlikun 0:20e0c61e0684 617 */
ganlikun 0:20e0c61e0684 618 /*@} end of group CMSIS_CoreDebug */
ganlikun 0:20e0c61e0684 619
ganlikun 0:20e0c61e0684 620
ganlikun 0:20e0c61e0684 621 /**
ganlikun 0:20e0c61e0684 622 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 623 \defgroup CMSIS_core_bitfield Core register bit field macros
ganlikun 0:20e0c61e0684 624 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
ganlikun 0:20e0c61e0684 625 @{
ganlikun 0:20e0c61e0684 626 */
ganlikun 0:20e0c61e0684 627
ganlikun 0:20e0c61e0684 628 /**
ganlikun 0:20e0c61e0684 629 \brief Mask and shift a bit field value for use in a register bit range.
ganlikun 0:20e0c61e0684 630 \param[in] field Name of the register bit field.
ganlikun 0:20e0c61e0684 631 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
ganlikun 0:20e0c61e0684 632 \return Masked and shifted value.
ganlikun 0:20e0c61e0684 633 */
ganlikun 0:20e0c61e0684 634 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
ganlikun 0:20e0c61e0684 635
ganlikun 0:20e0c61e0684 636 /**
ganlikun 0:20e0c61e0684 637 \brief Mask and shift a register value to extract a bit filed value.
ganlikun 0:20e0c61e0684 638 \param[in] field Name of the register bit field.
ganlikun 0:20e0c61e0684 639 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
ganlikun 0:20e0c61e0684 640 \return Masked and shifted bit field value.
ganlikun 0:20e0c61e0684 641 */
ganlikun 0:20e0c61e0684 642 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ganlikun 0:20e0c61e0684 643
ganlikun 0:20e0c61e0684 644 /*@} end of group CMSIS_core_bitfield */
ganlikun 0:20e0c61e0684 645
ganlikun 0:20e0c61e0684 646
ganlikun 0:20e0c61e0684 647 /**
ganlikun 0:20e0c61e0684 648 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 649 \defgroup CMSIS_core_base Core Definitions
ganlikun 0:20e0c61e0684 650 \brief Definitions for base addresses, unions, and structures.
ganlikun 0:20e0c61e0684 651 @{
ganlikun 0:20e0c61e0684 652 */
ganlikun 0:20e0c61e0684 653
ganlikun 0:20e0c61e0684 654 /* Memory mapping of Core Hardware */
ganlikun 0:20e0c61e0684 655 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
ganlikun 0:20e0c61e0684 656 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
ganlikun 0:20e0c61e0684 657 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
ganlikun 0:20e0c61e0684 658 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
ganlikun 0:20e0c61e0684 659
ganlikun 0:20e0c61e0684 660 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
ganlikun 0:20e0c61e0684 661 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
ganlikun 0:20e0c61e0684 662 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
ganlikun 0:20e0c61e0684 663 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
ganlikun 0:20e0c61e0684 664
ganlikun 0:20e0c61e0684 665 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:20e0c61e0684 666 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
ganlikun 0:20e0c61e0684 667 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
ganlikun 0:20e0c61e0684 668 #endif
ganlikun 0:20e0c61e0684 669
ganlikun 0:20e0c61e0684 670 /*@} */
ganlikun 0:20e0c61e0684 671
ganlikun 0:20e0c61e0684 672
ganlikun 0:20e0c61e0684 673
ganlikun 0:20e0c61e0684 674 /*******************************************************************************
ganlikun 0:20e0c61e0684 675 * Hardware Abstraction Layer
ganlikun 0:20e0c61e0684 676 Core Function Interface contains:
ganlikun 0:20e0c61e0684 677 - Core NVIC Functions
ganlikun 0:20e0c61e0684 678 - Core SysTick Functions
ganlikun 0:20e0c61e0684 679 - Core Register Access Functions
ganlikun 0:20e0c61e0684 680 ******************************************************************************/
ganlikun 0:20e0c61e0684 681 /**
ganlikun 0:20e0c61e0684 682 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
ganlikun 0:20e0c61e0684 683 */
ganlikun 0:20e0c61e0684 684
ganlikun 0:20e0c61e0684 685
ganlikun 0:20e0c61e0684 686
ganlikun 0:20e0c61e0684 687 /* ########################## NVIC functions #################################### */
ganlikun 0:20e0c61e0684 688 /**
ganlikun 0:20e0c61e0684 689 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:20e0c61e0684 690 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
ganlikun 0:20e0c61e0684 691 \brief Functions that manage interrupts and exceptions via the NVIC.
ganlikun 0:20e0c61e0684 692 @{
ganlikun 0:20e0c61e0684 693 */
ganlikun 0:20e0c61e0684 694
ganlikun 0:20e0c61e0684 695 #ifdef CMSIS_NVIC_VIRTUAL
ganlikun 0:20e0c61e0684 696 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 697 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
ganlikun 0:20e0c61e0684 698 #endif
ganlikun 0:20e0c61e0684 699 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 700 #else
ganlikun 0:20e0c61e0684 701 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
ganlikun 0:20e0c61e0684 702 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
ganlikun 0:20e0c61e0684 703 #define NVIC_EnableIRQ __NVIC_EnableIRQ
ganlikun 0:20e0c61e0684 704 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
ganlikun 0:20e0c61e0684 705 #define NVIC_DisableIRQ __NVIC_DisableIRQ
ganlikun 0:20e0c61e0684 706 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
ganlikun 0:20e0c61e0684 707 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
ganlikun 0:20e0c61e0684 708 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
ganlikun 0:20e0c61e0684 709 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
ganlikun 0:20e0c61e0684 710 #define NVIC_SetPriority __NVIC_SetPriority
ganlikun 0:20e0c61e0684 711 #define NVIC_GetPriority __NVIC_GetPriority
ganlikun 0:20e0c61e0684 712 #define NVIC_SystemReset __NVIC_SystemReset
ganlikun 0:20e0c61e0684 713 #endif /* CMSIS_NVIC_VIRTUAL */
ganlikun 0:20e0c61e0684 714
ganlikun 0:20e0c61e0684 715 #ifdef CMSIS_VECTAB_VIRTUAL
ganlikun 0:20e0c61e0684 716 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 717 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
ganlikun 0:20e0c61e0684 718 #endif
ganlikun 0:20e0c61e0684 719 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 720 #else
ganlikun 0:20e0c61e0684 721 #define NVIC_SetVector __NVIC_SetVector
ganlikun 0:20e0c61e0684 722 #define NVIC_GetVector __NVIC_GetVector
ganlikun 0:20e0c61e0684 723 #endif /* (CMSIS_VECTAB_VIRTUAL) */
ganlikun 0:20e0c61e0684 724
ganlikun 0:20e0c61e0684 725 #define NVIC_USER_IRQ_OFFSET 16
ganlikun 0:20e0c61e0684 726
ganlikun 0:20e0c61e0684 727
ganlikun 0:20e0c61e0684 728 /* Interrupt Priorities are WORD accessible only under ARMv6M */
ganlikun 0:20e0c61e0684 729 /* The following MACROS handle generation of the register offset and byte masks */
ganlikun 0:20e0c61e0684 730 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ganlikun 0:20e0c61e0684 731 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
ganlikun 0:20e0c61e0684 732 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
ganlikun 0:20e0c61e0684 733
ganlikun 0:20e0c61e0684 734
ganlikun 0:20e0c61e0684 735 /**
ganlikun 0:20e0c61e0684 736 \brief Enable Interrupt
ganlikun 0:20e0c61e0684 737 \details Enables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:20e0c61e0684 738 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 739 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 740 */
ganlikun 0:20e0c61e0684 741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 742 {
ganlikun 0:20e0c61e0684 743 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 744 {
ganlikun 0:20e0c61e0684 745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 746 }
ganlikun 0:20e0c61e0684 747 }
ganlikun 0:20e0c61e0684 748
ganlikun 0:20e0c61e0684 749
ganlikun 0:20e0c61e0684 750 /**
ganlikun 0:20e0c61e0684 751 \brief Get Interrupt Enable status
ganlikun 0:20e0c61e0684 752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
ganlikun 0:20e0c61e0684 753 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 754 \return 0 Interrupt is not enabled.
ganlikun 0:20e0c61e0684 755 \return 1 Interrupt is enabled.
ganlikun 0:20e0c61e0684 756 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 757 */
ganlikun 0:20e0c61e0684 758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 759 {
ganlikun 0:20e0c61e0684 760 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 761 {
ganlikun 0:20e0c61e0684 762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 763 }
ganlikun 0:20e0c61e0684 764 else
ganlikun 0:20e0c61e0684 765 {
ganlikun 0:20e0c61e0684 766 return(0U);
ganlikun 0:20e0c61e0684 767 }
ganlikun 0:20e0c61e0684 768 }
ganlikun 0:20e0c61e0684 769
ganlikun 0:20e0c61e0684 770
ganlikun 0:20e0c61e0684 771 /**
ganlikun 0:20e0c61e0684 772 \brief Disable Interrupt
ganlikun 0:20e0c61e0684 773 \details Disables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:20e0c61e0684 774 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 775 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 776 */
ganlikun 0:20e0c61e0684 777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 778 {
ganlikun 0:20e0c61e0684 779 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 780 {
ganlikun 0:20e0c61e0684 781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 782 __DSB();
ganlikun 0:20e0c61e0684 783 __ISB();
ganlikun 0:20e0c61e0684 784 }
ganlikun 0:20e0c61e0684 785 }
ganlikun 0:20e0c61e0684 786
ganlikun 0:20e0c61e0684 787
ganlikun 0:20e0c61e0684 788 /**
ganlikun 0:20e0c61e0684 789 \brief Get Pending Interrupt
ganlikun 0:20e0c61e0684 790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
ganlikun 0:20e0c61e0684 791 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 792 \return 0 Interrupt status is not pending.
ganlikun 0:20e0c61e0684 793 \return 1 Interrupt status is pending.
ganlikun 0:20e0c61e0684 794 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 795 */
ganlikun 0:20e0c61e0684 796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 797 {
ganlikun 0:20e0c61e0684 798 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 799 {
ganlikun 0:20e0c61e0684 800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 801 }
ganlikun 0:20e0c61e0684 802 else
ganlikun 0:20e0c61e0684 803 {
ganlikun 0:20e0c61e0684 804 return(0U);
ganlikun 0:20e0c61e0684 805 }
ganlikun 0:20e0c61e0684 806 }
ganlikun 0:20e0c61e0684 807
ganlikun 0:20e0c61e0684 808
ganlikun 0:20e0c61e0684 809 /**
ganlikun 0:20e0c61e0684 810 \brief Set Pending Interrupt
ganlikun 0:20e0c61e0684 811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:20e0c61e0684 812 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 813 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 814 */
ganlikun 0:20e0c61e0684 815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 816 {
ganlikun 0:20e0c61e0684 817 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 818 {
ganlikun 0:20e0c61e0684 819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 820 }
ganlikun 0:20e0c61e0684 821 }
ganlikun 0:20e0c61e0684 822
ganlikun 0:20e0c61e0684 823
ganlikun 0:20e0c61e0684 824 /**
ganlikun 0:20e0c61e0684 825 \brief Clear Pending Interrupt
ganlikun 0:20e0c61e0684 826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:20e0c61e0684 827 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 828 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 829 */
ganlikun 0:20e0c61e0684 830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 831 {
ganlikun 0:20e0c61e0684 832 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 833 {
ganlikun 0:20e0c61e0684 834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 835 }
ganlikun 0:20e0c61e0684 836 }
ganlikun 0:20e0c61e0684 837
ganlikun 0:20e0c61e0684 838
ganlikun 0:20e0c61e0684 839 /**
ganlikun 0:20e0c61e0684 840 \brief Set Interrupt Priority
ganlikun 0:20e0c61e0684 841 \details Sets the priority of a device specific interrupt or a processor exception.
ganlikun 0:20e0c61e0684 842 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 843 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 844 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 845 \param [in] priority Priority to set.
ganlikun 0:20e0c61e0684 846 \note The priority cannot be set for every processor exception.
ganlikun 0:20e0c61e0684 847 */
ganlikun 0:20e0c61e0684 848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ganlikun 0:20e0c61e0684 849 {
ganlikun 0:20e0c61e0684 850 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 851 {
ganlikun 0:20e0c61e0684 852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:20e0c61e0684 853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:20e0c61e0684 854 }
ganlikun 0:20e0c61e0684 855 else
ganlikun 0:20e0c61e0684 856 {
ganlikun 0:20e0c61e0684 857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:20e0c61e0684 858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:20e0c61e0684 859 }
ganlikun 0:20e0c61e0684 860 }
ganlikun 0:20e0c61e0684 861
ganlikun 0:20e0c61e0684 862
ganlikun 0:20e0c61e0684 863 /**
ganlikun 0:20e0c61e0684 864 \brief Get Interrupt Priority
ganlikun 0:20e0c61e0684 865 \details Reads the priority of a device specific interrupt or a processor exception.
ganlikun 0:20e0c61e0684 866 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 867 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 868 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 869 \return Interrupt Priority.
ganlikun 0:20e0c61e0684 870 Value is aligned automatically to the implemented priority bits of the microcontroller.
ganlikun 0:20e0c61e0684 871 */
ganlikun 0:20e0c61e0684 872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 873 {
ganlikun 0:20e0c61e0684 874
ganlikun 0:20e0c61e0684 875 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 876 {
ganlikun 0:20e0c61e0684 877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:20e0c61e0684 878 }
ganlikun 0:20e0c61e0684 879 else
ganlikun 0:20e0c61e0684 880 {
ganlikun 0:20e0c61e0684 881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:20e0c61e0684 882 }
ganlikun 0:20e0c61e0684 883 }
ganlikun 0:20e0c61e0684 884
ganlikun 0:20e0c61e0684 885
ganlikun 0:20e0c61e0684 886 /**
ganlikun 0:20e0c61e0684 887 \brief Set Interrupt Vector
ganlikun 0:20e0c61e0684 888 \details Sets an interrupt vector in SRAM based interrupt vector table.
ganlikun 0:20e0c61e0684 889 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 890 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 891 VTOR must been relocated to SRAM before.
ganlikun 0:20e0c61e0684 892 \param [in] IRQn Interrupt number
ganlikun 0:20e0c61e0684 893 \param [in] vector Address of interrupt handler function
ganlikun 0:20e0c61e0684 894 */
ganlikun 0:20e0c61e0684 895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
ganlikun 0:20e0c61e0684 896 {
ganlikun 0:20e0c61e0684 897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:20e0c61e0684 898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
ganlikun 0:20e0c61e0684 899 }
ganlikun 0:20e0c61e0684 900
ganlikun 0:20e0c61e0684 901
ganlikun 0:20e0c61e0684 902 /**
ganlikun 0:20e0c61e0684 903 \brief Get Interrupt Vector
ganlikun 0:20e0c61e0684 904 \details Reads an interrupt vector from interrupt vector table.
ganlikun 0:20e0c61e0684 905 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 906 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 907 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 908 \return Address of interrupt handler function
ganlikun 0:20e0c61e0684 909 */
ganlikun 0:20e0c61e0684 910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 911 {
ganlikun 0:20e0c61e0684 912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:20e0c61e0684 913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
ganlikun 0:20e0c61e0684 914 }
ganlikun 0:20e0c61e0684 915
ganlikun 0:20e0c61e0684 916
ganlikun 0:20e0c61e0684 917 /**
ganlikun 0:20e0c61e0684 918 \brief System Reset
ganlikun 0:20e0c61e0684 919 \details Initiates a system reset request to reset the MCU.
ganlikun 0:20e0c61e0684 920 */
ganlikun 0:20e0c61e0684 921 __STATIC_INLINE void __NVIC_SystemReset(void)
ganlikun 0:20e0c61e0684 922 {
ganlikun 0:20e0c61e0684 923 __DSB(); /* Ensure all outstanding memory accesses included
ganlikun 0:20e0c61e0684 924 buffered write are completed before reset */
ganlikun 0:20e0c61e0684 925 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
ganlikun 0:20e0c61e0684 926 SCB_AIRCR_SYSRESETREQ_Msk);
ganlikun 0:20e0c61e0684 927 __DSB(); /* Ensure completion of memory access */
ganlikun 0:20e0c61e0684 928
ganlikun 0:20e0c61e0684 929 for(;;) /* wait until reset */
ganlikun 0:20e0c61e0684 930 {
ganlikun 0:20e0c61e0684 931 __NOP();
ganlikun 0:20e0c61e0684 932 }
ganlikun 0:20e0c61e0684 933 }
ganlikun 0:20e0c61e0684 934
ganlikun 0:20e0c61e0684 935 /*@} end of CMSIS_Core_NVICFunctions */
ganlikun 0:20e0c61e0684 936
ganlikun 0:20e0c61e0684 937
ganlikun 0:20e0c61e0684 938 /* ########################## FPU functions #################################### */
ganlikun 0:20e0c61e0684 939 /**
ganlikun 0:20e0c61e0684 940 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:20e0c61e0684 941 \defgroup CMSIS_Core_FpuFunctions FPU Functions
ganlikun 0:20e0c61e0684 942 \brief Function that provides FPU type.
ganlikun 0:20e0c61e0684 943 @{
ganlikun 0:20e0c61e0684 944 */
ganlikun 0:20e0c61e0684 945
ganlikun 0:20e0c61e0684 946 /**
ganlikun 0:20e0c61e0684 947 \brief get FPU type
ganlikun 0:20e0c61e0684 948 \details returns the FPU type
ganlikun 0:20e0c61e0684 949 \returns
ganlikun 0:20e0c61e0684 950 - \b 0: No FPU
ganlikun 0:20e0c61e0684 951 - \b 1: Single precision FPU
ganlikun 0:20e0c61e0684 952 - \b 2: Double + Single precision FPU
ganlikun 0:20e0c61e0684 953 */
ganlikun 0:20e0c61e0684 954 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
ganlikun 0:20e0c61e0684 955 {
ganlikun 0:20e0c61e0684 956 return 0U; /* No FPU */
ganlikun 0:20e0c61e0684 957 }
ganlikun 0:20e0c61e0684 958
ganlikun 0:20e0c61e0684 959
ganlikun 0:20e0c61e0684 960 /*@} end of CMSIS_Core_FpuFunctions */
ganlikun 0:20e0c61e0684 961
ganlikun 0:20e0c61e0684 962
ganlikun 0:20e0c61e0684 963
ganlikun 0:20e0c61e0684 964 /* ################################## SysTick function ############################################ */
ganlikun 0:20e0c61e0684 965 /**
ganlikun 0:20e0c61e0684 966 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:20e0c61e0684 967 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
ganlikun 0:20e0c61e0684 968 \brief Functions that configure the System.
ganlikun 0:20e0c61e0684 969 @{
ganlikun 0:20e0c61e0684 970 */
ganlikun 0:20e0c61e0684 971
ganlikun 0:20e0c61e0684 972 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
ganlikun 0:20e0c61e0684 973
ganlikun 0:20e0c61e0684 974 /**
ganlikun 0:20e0c61e0684 975 \brief System Tick Configuration
ganlikun 0:20e0c61e0684 976 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
ganlikun 0:20e0c61e0684 977 Counter is in free running mode to generate periodic interrupts.
ganlikun 0:20e0c61e0684 978 \param [in] ticks Number of ticks between two interrupts.
ganlikun 0:20e0c61e0684 979 \return 0 Function succeeded.
ganlikun 0:20e0c61e0684 980 \return 1 Function failed.
ganlikun 0:20e0c61e0684 981 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ganlikun 0:20e0c61e0684 982 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
ganlikun 0:20e0c61e0684 983 must contain a vendor-specific implementation of this function.
ganlikun 0:20e0c61e0684 984 */
ganlikun 0:20e0c61e0684 985 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ganlikun 0:20e0c61e0684 986 {
ganlikun 0:20e0c61e0684 987 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
ganlikun 0:20e0c61e0684 988 {
ganlikun 0:20e0c61e0684 989 return (1UL); /* Reload value impossible */
ganlikun 0:20e0c61e0684 990 }
ganlikun 0:20e0c61e0684 991
ganlikun 0:20e0c61e0684 992 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
ganlikun 0:20e0c61e0684 993 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
ganlikun 0:20e0c61e0684 994 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
ganlikun 0:20e0c61e0684 995 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
ganlikun 0:20e0c61e0684 996 SysTick_CTRL_TICKINT_Msk |
ganlikun 0:20e0c61e0684 997 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ganlikun 0:20e0c61e0684 998 return (0UL); /* Function successful */
ganlikun 0:20e0c61e0684 999 }
ganlikun 0:20e0c61e0684 1000
ganlikun 0:20e0c61e0684 1001 #endif
ganlikun 0:20e0c61e0684 1002
ganlikun 0:20e0c61e0684 1003 /*@} end of CMSIS_Core_SysTickFunctions */
ganlikun 0:20e0c61e0684 1004
ganlikun 0:20e0c61e0684 1005
ganlikun 0:20e0c61e0684 1006
ganlikun 0:20e0c61e0684 1007
ganlikun 0:20e0c61e0684 1008 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 1009 }
ganlikun 0:20e0c61e0684 1010 #endif
ganlikun 0:20e0c61e0684 1011
ganlikun 0:20e0c61e0684 1012 #endif /* __CORE_SC000_H_DEPENDANT */
ganlikun 0:20e0c61e0684 1013
ganlikun 0:20e0c61e0684 1014 #endif /* __CMSIS_GENERIC */
ganlikun 0:20e0c61e0684 1015