Gan likun / The prosthetic control

The prosthetic control（MIT）

cmsis/core_cm23.h@0:20e0c61e0684, 2022-06-23 (annotated)

Committer:
ganlikun
Date:
Thu Jun 23 05:23:34 2022 +0000
Revision:
0:20e0c61e0684
01

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:20e0c61e0684 1 /**************************************************************************//**
ganlikun 0:20e0c61e0684 2 * @file core_cm23.h
ganlikun 0:20e0c61e0684 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
ganlikun 0:20e0c61e0684 4 * @version V5.0.2
ganlikun 0:20e0c61e0684 5 * @date 13. February 2017
ganlikun 0:20e0c61e0684 6 ******************************************************************************/
ganlikun 0:20e0c61e0684 7 /*
ganlikun 0:20e0c61e0684 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
ganlikun 0:20e0c61e0684 9 *
ganlikun 0:20e0c61e0684 10 * SPDX-License-Identifier: Apache-2.0
ganlikun 0:20e0c61e0684 11 *
ganlikun 0:20e0c61e0684 12 * Licensed under the Apache License, Version 2.0 (the License); you may
ganlikun 0:20e0c61e0684 13 * not use this file except in compliance with the License.
ganlikun 0:20e0c61e0684 14 * You may obtain a copy of the License at
ganlikun 0:20e0c61e0684 15 *
ganlikun 0:20e0c61e0684 16 * www.apache.org/licenses/LICENSE-2.0
ganlikun 0:20e0c61e0684 17 *
ganlikun 0:20e0c61e0684 18 * Unless required by applicable law or agreed to in writing, software
ganlikun 0:20e0c61e0684 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ganlikun 0:20e0c61e0684 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ganlikun 0:20e0c61e0684 21 * See the License for the specific language governing permissions and
ganlikun 0:20e0c61e0684 22 * limitations under the License.
ganlikun 0:20e0c61e0684 23 */
ganlikun 0:20e0c61e0684 24
ganlikun 0:20e0c61e0684 25 #if defined ( __ICCARM__ )
ganlikun 0:20e0c61e0684 26 #pragma system_include /* treat file as system include file for MISRA check */
ganlikun 0:20e0c61e0684 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:20e0c61e0684 28 #pragma clang system_header /* treat file as system include file */
ganlikun 0:20e0c61e0684 29 #endif
ganlikun 0:20e0c61e0684 30
ganlikun 0:20e0c61e0684 31 #ifndef __CORE_CM23_H_GENERIC
ganlikun 0:20e0c61e0684 32 #define __CORE_CM23_H_GENERIC
ganlikun 0:20e0c61e0684 33
ganlikun 0:20e0c61e0684 34 #include <stdint.h>
ganlikun 0:20e0c61e0684 35
ganlikun 0:20e0c61e0684 36 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 37 extern "C" {
ganlikun 0:20e0c61e0684 38 #endif
ganlikun 0:20e0c61e0684 39
ganlikun 0:20e0c61e0684 40 /**
ganlikun 0:20e0c61e0684 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
ganlikun 0:20e0c61e0684 42 CMSIS violates the following MISRA-C:2004 rules:
ganlikun 0:20e0c61e0684 43
ganlikun 0:20e0c61e0684 44 \li Required Rule 8.5, object/function definition in header file.<br>
ganlikun 0:20e0c61e0684 45 Function definitions in header files are used to allow 'inlining'.
ganlikun 0:20e0c61e0684 46
ganlikun 0:20e0c61e0684 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
ganlikun 0:20e0c61e0684 48 Unions are used for effective representation of core registers.
ganlikun 0:20e0c61e0684 49
ganlikun 0:20e0c61e0684 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
ganlikun 0:20e0c61e0684 51 Function-like macros are used to allow more efficient code.
ganlikun 0:20e0c61e0684 52 */
ganlikun 0:20e0c61e0684 53
ganlikun 0:20e0c61e0684 54
ganlikun 0:20e0c61e0684 55 /*******************************************************************************
ganlikun 0:20e0c61e0684 56 * CMSIS definitions
ganlikun 0:20e0c61e0684 57 ******************************************************************************/
ganlikun 0:20e0c61e0684 58 /**
ganlikun 0:20e0c61e0684 59 \ingroup Cortex_M23
ganlikun 0:20e0c61e0684 60 @{
ganlikun 0:20e0c61e0684 61 */
ganlikun 0:20e0c61e0684 62
ganlikun 0:20e0c61e0684 63 /* CMSIS cmGrebe definitions */
ganlikun 0:20e0c61e0684 64 #define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
ganlikun 0:20e0c61e0684 65 #define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
ganlikun 0:20e0c61e0684 66 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
ganlikun 0:20e0c61e0684 67 __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
ganlikun 0:20e0c61e0684 68
ganlikun 0:20e0c61e0684 69 #define __CORTEX_M (23U) /*!< Cortex-M Core */
ganlikun 0:20e0c61e0684 70
ganlikun 0:20e0c61e0684 71 /** __FPU_USED indicates whether an FPU is used or not.
ganlikun 0:20e0c61e0684 72 This core does not support an FPU at all
ganlikun 0:20e0c61e0684 73 */
ganlikun 0:20e0c61e0684 74 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 75
ganlikun 0:20e0c61e0684 76 #if defined ( __CC_ARM )
ganlikun 0:20e0c61e0684 77 #if defined __TARGET_FPU_VFP
ganlikun 0:20e0c61e0684 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 79 #endif
ganlikun 0:20e0c61e0684 80
ganlikun 0:20e0c61e0684 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
ganlikun 0:20e0c61e0684 82 #if defined __ARM_PCS_VFP
ganlikun 0:20e0c61e0684 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 84 #endif
ganlikun 0:20e0c61e0684 85
ganlikun 0:20e0c61e0684 86 #elif defined ( __GNUC__ )
ganlikun 0:20e0c61e0684 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
ganlikun 0:20e0c61e0684 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 89 #endif
ganlikun 0:20e0c61e0684 90
ganlikun 0:20e0c61e0684 91 #elif defined ( __ICCARM__ )
ganlikun 0:20e0c61e0684 92 #if defined __ARMVFP__
ganlikun 0:20e0c61e0684 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 94 #endif
ganlikun 0:20e0c61e0684 95
ganlikun 0:20e0c61e0684 96 #elif defined ( __TI_ARM__ )
ganlikun 0:20e0c61e0684 97 #if defined __TI_VFP_SUPPORT__
ganlikun 0:20e0c61e0684 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 99 #endif
ganlikun 0:20e0c61e0684 100
ganlikun 0:20e0c61e0684 101 #elif defined ( __TASKING__ )
ganlikun 0:20e0c61e0684 102 #if defined __FPU_VFP__
ganlikun 0:20e0c61e0684 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 104 #endif
ganlikun 0:20e0c61e0684 105
ganlikun 0:20e0c61e0684 106 #elif defined ( __CSMC__ )
ganlikun 0:20e0c61e0684 107 #if ( __CSMC__ & 0x400U)
ganlikun 0:20e0c61e0684 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 109 #endif
ganlikun 0:20e0c61e0684 110
ganlikun 0:20e0c61e0684 111 #endif
ganlikun 0:20e0c61e0684 112
ganlikun 0:20e0c61e0684 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
ganlikun 0:20e0c61e0684 114
ganlikun 0:20e0c61e0684 115
ganlikun 0:20e0c61e0684 116 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 117 }
ganlikun 0:20e0c61e0684 118 #endif
ganlikun 0:20e0c61e0684 119
ganlikun 0:20e0c61e0684 120 #endif /* __CORE_CM23_H_GENERIC */
ganlikun 0:20e0c61e0684 121
ganlikun 0:20e0c61e0684 122 #ifndef __CMSIS_GENERIC
ganlikun 0:20e0c61e0684 123
ganlikun 0:20e0c61e0684 124 #ifndef __CORE_CM23_H_DEPENDANT
ganlikun 0:20e0c61e0684 125 #define __CORE_CM23_H_DEPENDANT
ganlikun 0:20e0c61e0684 126
ganlikun 0:20e0c61e0684 127 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 128 extern "C" {
ganlikun 0:20e0c61e0684 129 #endif
ganlikun 0:20e0c61e0684 130
ganlikun 0:20e0c61e0684 131 /* check device defines and use defaults */
ganlikun 0:20e0c61e0684 132 #if defined __CHECK_DEVICE_DEFINES
ganlikun 0:20e0c61e0684 133 #ifndef __CM23_REV
ganlikun 0:20e0c61e0684 134 #define __CM23_REV 0x0000U
ganlikun 0:20e0c61e0684 135 #warning "__CM23_REV not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 136 #endif
ganlikun 0:20e0c61e0684 137
ganlikun 0:20e0c61e0684 138 #ifndef __FPU_PRESENT
ganlikun 0:20e0c61e0684 139 #define __FPU_PRESENT 0U
ganlikun 0:20e0c61e0684 140 #warning "__FPU_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 141 #endif
ganlikun 0:20e0c61e0684 142
ganlikun 0:20e0c61e0684 143 #ifndef __MPU_PRESENT
ganlikun 0:20e0c61e0684 144 #define __MPU_PRESENT 0U
ganlikun 0:20e0c61e0684 145 #warning "__MPU_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 146 #endif
ganlikun 0:20e0c61e0684 147
ganlikun 0:20e0c61e0684 148 #ifndef __SAUREGION_PRESENT
ganlikun 0:20e0c61e0684 149 #define __SAUREGION_PRESENT 0U
ganlikun 0:20e0c61e0684 150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 151 #endif
ganlikun 0:20e0c61e0684 152
ganlikun 0:20e0c61e0684 153 #ifndef __VTOR_PRESENT
ganlikun 0:20e0c61e0684 154 #define __VTOR_PRESENT 0U
ganlikun 0:20e0c61e0684 155 #warning "__VTOR_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 156 #endif
ganlikun 0:20e0c61e0684 157
ganlikun 0:20e0c61e0684 158 #ifndef __NVIC_PRIO_BITS
ganlikun 0:20e0c61e0684 159 #define __NVIC_PRIO_BITS 2U
ganlikun 0:20e0c61e0684 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 161 #endif
ganlikun 0:20e0c61e0684 162
ganlikun 0:20e0c61e0684 163 #ifndef __Vendor_SysTickConfig
ganlikun 0:20e0c61e0684 164 #define __Vendor_SysTickConfig 0U
ganlikun 0:20e0c61e0684 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 166 #endif
ganlikun 0:20e0c61e0684 167
ganlikun 0:20e0c61e0684 168 #ifndef __ETM_PRESENT
ganlikun 0:20e0c61e0684 169 #define __ETM_PRESENT 0U
ganlikun 0:20e0c61e0684 170 #warning "__ETM_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 171 #endif
ganlikun 0:20e0c61e0684 172
ganlikun 0:20e0c61e0684 173 #ifndef __MTB_PRESENT
ganlikun 0:20e0c61e0684 174 #define __MTB_PRESENT 0U
ganlikun 0:20e0c61e0684 175 #warning "__MTB_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 176 #endif
ganlikun 0:20e0c61e0684 177
ganlikun 0:20e0c61e0684 178 #endif
ganlikun 0:20e0c61e0684 179
ganlikun 0:20e0c61e0684 180 /* IO definitions (access restrictions to peripheral registers) */
ganlikun 0:20e0c61e0684 181 /**
ganlikun 0:20e0c61e0684 182 \defgroup CMSIS_glob_defs CMSIS Global Defines
ganlikun 0:20e0c61e0684 183
ganlikun 0:20e0c61e0684 184 <strong>IO Type Qualifiers</strong> are used
ganlikun 0:20e0c61e0684 185 \li to specify the access to peripheral variables.
ganlikun 0:20e0c61e0684 186 \li for automatic generation of peripheral register debug information.
ganlikun 0:20e0c61e0684 187 */
ganlikun 0:20e0c61e0684 188 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 189 #define __I volatile /*!< Defines 'read only' permissions */
ganlikun 0:20e0c61e0684 190 #else
ganlikun 0:20e0c61e0684 191 #define __I volatile const /*!< Defines 'read only' permissions */
ganlikun 0:20e0c61e0684 192 #endif
ganlikun 0:20e0c61e0684 193 #define __O volatile /*!< Defines 'write only' permissions */
ganlikun 0:20e0c61e0684 194 #define __IO volatile /*!< Defines 'read / write' permissions */
ganlikun 0:20e0c61e0684 195
ganlikun 0:20e0c61e0684 196 /* following defines should be used for structure members */
ganlikun 0:20e0c61e0684 197 #define __IM volatile const /*! Defines 'read only' structure member permissions */
ganlikun 0:20e0c61e0684 198 #define __OM volatile /*! Defines 'write only' structure member permissions */
ganlikun 0:20e0c61e0684 199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
ganlikun 0:20e0c61e0684 200
ganlikun 0:20e0c61e0684 201 /*@} end of group Cortex_M23 */
ganlikun 0:20e0c61e0684 202
ganlikun 0:20e0c61e0684 203
ganlikun 0:20e0c61e0684 204
ganlikun 0:20e0c61e0684 205 /*******************************************************************************
ganlikun 0:20e0c61e0684 206 * Register Abstraction
ganlikun 0:20e0c61e0684 207 Core Register contain:
ganlikun 0:20e0c61e0684 208 - Core Register
ganlikun 0:20e0c61e0684 209 - Core NVIC Register
ganlikun 0:20e0c61e0684 210 - Core SCB Register
ganlikun 0:20e0c61e0684 211 - Core SysTick Register
ganlikun 0:20e0c61e0684 212 - Core Debug Register
ganlikun 0:20e0c61e0684 213 - Core MPU Register
ganlikun 0:20e0c61e0684 214 - Core SAU Register
ganlikun 0:20e0c61e0684 215 ******************************************************************************/
ganlikun 0:20e0c61e0684 216 /**
ganlikun 0:20e0c61e0684 217 \defgroup CMSIS_core_register Defines and Type Definitions
ganlikun 0:20e0c61e0684 218 \brief Type definitions and defines for Cortex-M processor based devices.
ganlikun 0:20e0c61e0684 219 */
ganlikun 0:20e0c61e0684 220
ganlikun 0:20e0c61e0684 221 /**
ganlikun 0:20e0c61e0684 222 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 223 \defgroup CMSIS_CORE Status and Control Registers
ganlikun 0:20e0c61e0684 224 \brief Core Register type definitions.
ganlikun 0:20e0c61e0684 225 @{
ganlikun 0:20e0c61e0684 226 */
ganlikun 0:20e0c61e0684 227
ganlikun 0:20e0c61e0684 228 /**
ganlikun 0:20e0c61e0684 229 \brief Union type to access the Application Program Status Register (APSR).
ganlikun 0:20e0c61e0684 230 */
ganlikun 0:20e0c61e0684 231 typedef union
ganlikun 0:20e0c61e0684 232 {
ganlikun 0:20e0c61e0684 233 struct
ganlikun 0:20e0c61e0684 234 {
ganlikun 0:20e0c61e0684 235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
ganlikun 0:20e0c61e0684 236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:20e0c61e0684 237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:20e0c61e0684 238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:20e0c61e0684 239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:20e0c61e0684 240 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 241 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 242 } APSR_Type;
ganlikun 0:20e0c61e0684 243
ganlikun 0:20e0c61e0684 244 /* APSR Register Definitions */
ganlikun 0:20e0c61e0684 245 #define APSR_N_Pos 31U /*!< APSR: N Position */
ganlikun 0:20e0c61e0684 246 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
ganlikun 0:20e0c61e0684 247
ganlikun 0:20e0c61e0684 248 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
ganlikun 0:20e0c61e0684 249 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
ganlikun 0:20e0c61e0684 250
ganlikun 0:20e0c61e0684 251 #define APSR_C_Pos 29U /*!< APSR: C Position */
ganlikun 0:20e0c61e0684 252 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
ganlikun 0:20e0c61e0684 253
ganlikun 0:20e0c61e0684 254 #define APSR_V_Pos 28U /*!< APSR: V Position */
ganlikun 0:20e0c61e0684 255 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
ganlikun 0:20e0c61e0684 256
ganlikun 0:20e0c61e0684 257
ganlikun 0:20e0c61e0684 258 /**
ganlikun 0:20e0c61e0684 259 \brief Union type to access the Interrupt Program Status Register (IPSR).
ganlikun 0:20e0c61e0684 260 */
ganlikun 0:20e0c61e0684 261 typedef union
ganlikun 0:20e0c61e0684 262 {
ganlikun 0:20e0c61e0684 263 struct
ganlikun 0:20e0c61e0684 264 {
ganlikun 0:20e0c61e0684 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:20e0c61e0684 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
ganlikun 0:20e0c61e0684 267 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 268 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 269 } IPSR_Type;
ganlikun 0:20e0c61e0684 270
ganlikun 0:20e0c61e0684 271 /* IPSR Register Definitions */
ganlikun 0:20e0c61e0684 272 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
ganlikun 0:20e0c61e0684 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
ganlikun 0:20e0c61e0684 274
ganlikun 0:20e0c61e0684 275
ganlikun 0:20e0c61e0684 276 /**
ganlikun 0:20e0c61e0684 277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ganlikun 0:20e0c61e0684 278 */
ganlikun 0:20e0c61e0684 279 typedef union
ganlikun 0:20e0c61e0684 280 {
ganlikun 0:20e0c61e0684 281 struct
ganlikun 0:20e0c61e0684 282 {
ganlikun 0:20e0c61e0684 283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ganlikun 0:20e0c61e0684 284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
ganlikun 0:20e0c61e0684 285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
ganlikun 0:20e0c61e0684 286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
ganlikun 0:20e0c61e0684 287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ganlikun 0:20e0c61e0684 288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ganlikun 0:20e0c61e0684 289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ganlikun 0:20e0c61e0684 290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ganlikun 0:20e0c61e0684 291 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 292 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 293 } xPSR_Type;
ganlikun 0:20e0c61e0684 294
ganlikun 0:20e0c61e0684 295 /* xPSR Register Definitions */
ganlikun 0:20e0c61e0684 296 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
ganlikun 0:20e0c61e0684 297 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
ganlikun 0:20e0c61e0684 298
ganlikun 0:20e0c61e0684 299 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
ganlikun 0:20e0c61e0684 300 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
ganlikun 0:20e0c61e0684 301
ganlikun 0:20e0c61e0684 302 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
ganlikun 0:20e0c61e0684 303 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
ganlikun 0:20e0c61e0684 304
ganlikun 0:20e0c61e0684 305 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
ganlikun 0:20e0c61e0684 306 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
ganlikun 0:20e0c61e0684 307
ganlikun 0:20e0c61e0684 308 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
ganlikun 0:20e0c61e0684 309 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
ganlikun 0:20e0c61e0684 310
ganlikun 0:20e0c61e0684 311 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
ganlikun 0:20e0c61e0684 312 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
ganlikun 0:20e0c61e0684 313
ganlikun 0:20e0c61e0684 314
ganlikun 0:20e0c61e0684 315 /**
ganlikun 0:20e0c61e0684 316 \brief Union type to access the Control Registers (CONTROL).
ganlikun 0:20e0c61e0684 317 */
ganlikun 0:20e0c61e0684 318 typedef union
ganlikun 0:20e0c61e0684 319 {
ganlikun 0:20e0c61e0684 320 struct
ganlikun 0:20e0c61e0684 321 {
ganlikun 0:20e0c61e0684 322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
ganlikun 0:20e0c61e0684 323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
ganlikun 0:20e0c61e0684 324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
ganlikun 0:20e0c61e0684 325 } b; /*!< Structure used for bit access */
ganlikun 0:20e0c61e0684 326 uint32_t w; /*!< Type used for word access */
ganlikun 0:20e0c61e0684 327 } CONTROL_Type;
ganlikun 0:20e0c61e0684 328
ganlikun 0:20e0c61e0684 329 /* CONTROL Register Definitions */
ganlikun 0:20e0c61e0684 330 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
ganlikun 0:20e0c61e0684 331 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
ganlikun 0:20e0c61e0684 332
ganlikun 0:20e0c61e0684 333 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
ganlikun 0:20e0c61e0684 334 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
ganlikun 0:20e0c61e0684 335
ganlikun 0:20e0c61e0684 336 /*@} end of group CMSIS_CORE */
ganlikun 0:20e0c61e0684 337
ganlikun 0:20e0c61e0684 338
ganlikun 0:20e0c61e0684 339 /**
ganlikun 0:20e0c61e0684 340 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
ganlikun 0:20e0c61e0684 342 \brief Type definitions for the NVIC Registers
ganlikun 0:20e0c61e0684 343 @{
ganlikun 0:20e0c61e0684 344 */
ganlikun 0:20e0c61e0684 345
ganlikun 0:20e0c61e0684 346 /**
ganlikun 0:20e0c61e0684 347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
ganlikun 0:20e0c61e0684 348 */
ganlikun 0:20e0c61e0684 349 typedef struct
ganlikun 0:20e0c61e0684 350 {
ganlikun 0:20e0c61e0684 351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
ganlikun 0:20e0c61e0684 352 uint32_t RESERVED0[16U];
ganlikun 0:20e0c61e0684 353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
ganlikun 0:20e0c61e0684 354 uint32_t RSERVED1[16U];
ganlikun 0:20e0c61e0684 355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
ganlikun 0:20e0c61e0684 356 uint32_t RESERVED2[16U];
ganlikun 0:20e0c61e0684 357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
ganlikun 0:20e0c61e0684 358 uint32_t RESERVED3[16U];
ganlikun 0:20e0c61e0684 359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
ganlikun 0:20e0c61e0684 360 uint32_t RESERVED4[16U];
ganlikun 0:20e0c61e0684 361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
ganlikun 0:20e0c61e0684 362 uint32_t RESERVED5[16U];
ganlikun 0:20e0c61e0684 363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
ganlikun 0:20e0c61e0684 364 } NVIC_Type;
ganlikun 0:20e0c61e0684 365
ganlikun 0:20e0c61e0684 366 /*@} end of group CMSIS_NVIC */
ganlikun 0:20e0c61e0684 367
ganlikun 0:20e0c61e0684 368
ganlikun 0:20e0c61e0684 369 /**
ganlikun 0:20e0c61e0684 370 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 371 \defgroup CMSIS_SCB System Control Block (SCB)
ganlikun 0:20e0c61e0684 372 \brief Type definitions for the System Control Block Registers
ganlikun 0:20e0c61e0684 373 @{
ganlikun 0:20e0c61e0684 374 */
ganlikun 0:20e0c61e0684 375
ganlikun 0:20e0c61e0684 376 /**
ganlikun 0:20e0c61e0684 377 \brief Structure type to access the System Control Block (SCB).
ganlikun 0:20e0c61e0684 378 */
ganlikun 0:20e0c61e0684 379 typedef struct
ganlikun 0:20e0c61e0684 380 {
ganlikun 0:20e0c61e0684 381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
ganlikun 0:20e0c61e0684 382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
ganlikun 0:20e0c61e0684 383 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:20e0c61e0684 384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
ganlikun 0:20e0c61e0684 385 #else
ganlikun 0:20e0c61e0684 386 uint32_t RESERVED0;
ganlikun 0:20e0c61e0684 387 #endif
ganlikun 0:20e0c61e0684 388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
ganlikun 0:20e0c61e0684 389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
ganlikun 0:20e0c61e0684 390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
ganlikun 0:20e0c61e0684 391 uint32_t RESERVED1;
ganlikun 0:20e0c61e0684 392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
ganlikun 0:20e0c61e0684 393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
ganlikun 0:20e0c61e0684 394 } SCB_Type;
ganlikun 0:20e0c61e0684 395
ganlikun 0:20e0c61e0684 396 /* SCB CPUID Register Definitions */
ganlikun 0:20e0c61e0684 397 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
ganlikun 0:20e0c61e0684 398 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
ganlikun 0:20e0c61e0684 399
ganlikun 0:20e0c61e0684 400 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
ganlikun 0:20e0c61e0684 401 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
ganlikun 0:20e0c61e0684 402
ganlikun 0:20e0c61e0684 403 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
ganlikun 0:20e0c61e0684 404 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
ganlikun 0:20e0c61e0684 405
ganlikun 0:20e0c61e0684 406 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
ganlikun 0:20e0c61e0684 407 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
ganlikun 0:20e0c61e0684 408
ganlikun 0:20e0c61e0684 409 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
ganlikun 0:20e0c61e0684 410 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
ganlikun 0:20e0c61e0684 411
ganlikun 0:20e0c61e0684 412 /* SCB Interrupt Control State Register Definitions */
ganlikun 0:20e0c61e0684 413 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
ganlikun 0:20e0c61e0684 414 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
ganlikun 0:20e0c61e0684 415
ganlikun 0:20e0c61e0684 416 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
ganlikun 0:20e0c61e0684 417 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
ganlikun 0:20e0c61e0684 418
ganlikun 0:20e0c61e0684 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
ganlikun 0:20e0c61e0684 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
ganlikun 0:20e0c61e0684 421
ganlikun 0:20e0c61e0684 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
ganlikun 0:20e0c61e0684 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
ganlikun 0:20e0c61e0684 424
ganlikun 0:20e0c61e0684 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
ganlikun 0:20e0c61e0684 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
ganlikun 0:20e0c61e0684 427
ganlikun 0:20e0c61e0684 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
ganlikun 0:20e0c61e0684 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
ganlikun 0:20e0c61e0684 430
ganlikun 0:20e0c61e0684 431 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
ganlikun 0:20e0c61e0684 432 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
ganlikun 0:20e0c61e0684 433
ganlikun 0:20e0c61e0684 434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
ganlikun 0:20e0c61e0684 435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
ganlikun 0:20e0c61e0684 436
ganlikun 0:20e0c61e0684 437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
ganlikun 0:20e0c61e0684 438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
ganlikun 0:20e0c61e0684 439
ganlikun 0:20e0c61e0684 440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
ganlikun 0:20e0c61e0684 441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
ganlikun 0:20e0c61e0684 442
ganlikun 0:20e0c61e0684 443 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
ganlikun 0:20e0c61e0684 444 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
ganlikun 0:20e0c61e0684 445
ganlikun 0:20e0c61e0684 446 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
ganlikun 0:20e0c61e0684 447 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
ganlikun 0:20e0c61e0684 448
ganlikun 0:20e0c61e0684 449 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:20e0c61e0684 450 /* SCB Vector Table Offset Register Definitions */
ganlikun 0:20e0c61e0684 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
ganlikun 0:20e0c61e0684 452 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
ganlikun 0:20e0c61e0684 453 #endif
ganlikun 0:20e0c61e0684 454
ganlikun 0:20e0c61e0684 455 /* SCB Application Interrupt and Reset Control Register Definitions */
ganlikun 0:20e0c61e0684 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
ganlikun 0:20e0c61e0684 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
ganlikun 0:20e0c61e0684 458
ganlikun 0:20e0c61e0684 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
ganlikun 0:20e0c61e0684 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
ganlikun 0:20e0c61e0684 461
ganlikun 0:20e0c61e0684 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
ganlikun 0:20e0c61e0684 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
ganlikun 0:20e0c61e0684 464
ganlikun 0:20e0c61e0684 465 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
ganlikun 0:20e0c61e0684 466 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
ganlikun 0:20e0c61e0684 467
ganlikun 0:20e0c61e0684 468 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
ganlikun 0:20e0c61e0684 469 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
ganlikun 0:20e0c61e0684 470
ganlikun 0:20e0c61e0684 471 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
ganlikun 0:20e0c61e0684 472 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
ganlikun 0:20e0c61e0684 473
ganlikun 0:20e0c61e0684 474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
ganlikun 0:20e0c61e0684 475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
ganlikun 0:20e0c61e0684 476
ganlikun 0:20e0c61e0684 477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
ganlikun 0:20e0c61e0684 478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
ganlikun 0:20e0c61e0684 479
ganlikun 0:20e0c61e0684 480 /* SCB System Control Register Definitions */
ganlikun 0:20e0c61e0684 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
ganlikun 0:20e0c61e0684 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
ganlikun 0:20e0c61e0684 483
ganlikun 0:20e0c61e0684 484 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
ganlikun 0:20e0c61e0684 485 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
ganlikun 0:20e0c61e0684 486
ganlikun 0:20e0c61e0684 487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
ganlikun 0:20e0c61e0684 488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
ganlikun 0:20e0c61e0684 489
ganlikun 0:20e0c61e0684 490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
ganlikun 0:20e0c61e0684 491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
ganlikun 0:20e0c61e0684 492
ganlikun 0:20e0c61e0684 493 /* SCB Configuration Control Register Definitions */
ganlikun 0:20e0c61e0684 494 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
ganlikun 0:20e0c61e0684 495 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
ganlikun 0:20e0c61e0684 496
ganlikun 0:20e0c61e0684 497 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
ganlikun 0:20e0c61e0684 498 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
ganlikun 0:20e0c61e0684 499
ganlikun 0:20e0c61e0684 500 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
ganlikun 0:20e0c61e0684 501 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
ganlikun 0:20e0c61e0684 502
ganlikun 0:20e0c61e0684 503 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
ganlikun 0:20e0c61e0684 504 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
ganlikun 0:20e0c61e0684 505
ganlikun 0:20e0c61e0684 506 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
ganlikun 0:20e0c61e0684 507 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
ganlikun 0:20e0c61e0684 508
ganlikun 0:20e0c61e0684 509 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
ganlikun 0:20e0c61e0684 510 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
ganlikun 0:20e0c61e0684 511
ganlikun 0:20e0c61e0684 512 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
ganlikun 0:20e0c61e0684 513 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
ganlikun 0:20e0c61e0684 514
ganlikun 0:20e0c61e0684 515 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
ganlikun 0:20e0c61e0684 516 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
ganlikun 0:20e0c61e0684 517
ganlikun 0:20e0c61e0684 518 /* SCB System Handler Control and State Register Definitions */
ganlikun 0:20e0c61e0684 519 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
ganlikun 0:20e0c61e0684 520 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
ganlikun 0:20e0c61e0684 521
ganlikun 0:20e0c61e0684 522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
ganlikun 0:20e0c61e0684 523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
ganlikun 0:20e0c61e0684 524
ganlikun 0:20e0c61e0684 525 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
ganlikun 0:20e0c61e0684 526 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
ganlikun 0:20e0c61e0684 527
ganlikun 0:20e0c61e0684 528 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
ganlikun 0:20e0c61e0684 529 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
ganlikun 0:20e0c61e0684 530
ganlikun 0:20e0c61e0684 531 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
ganlikun 0:20e0c61e0684 532 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
ganlikun 0:20e0c61e0684 533
ganlikun 0:20e0c61e0684 534 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
ganlikun 0:20e0c61e0684 535 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
ganlikun 0:20e0c61e0684 536
ganlikun 0:20e0c61e0684 537 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
ganlikun 0:20e0c61e0684 538 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
ganlikun 0:20e0c61e0684 539
ganlikun 0:20e0c61e0684 540 /*@} end of group CMSIS_SCB */
ganlikun 0:20e0c61e0684 541
ganlikun 0:20e0c61e0684 542
ganlikun 0:20e0c61e0684 543 /**
ganlikun 0:20e0c61e0684 544 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 545 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
ganlikun 0:20e0c61e0684 546 \brief Type definitions for the System Timer Registers.
ganlikun 0:20e0c61e0684 547 @{
ganlikun 0:20e0c61e0684 548 */
ganlikun 0:20e0c61e0684 549
ganlikun 0:20e0c61e0684 550 /**
ganlikun 0:20e0c61e0684 551 \brief Structure type to access the System Timer (SysTick).
ganlikun 0:20e0c61e0684 552 */
ganlikun 0:20e0c61e0684 553 typedef struct
ganlikun 0:20e0c61e0684 554 {
ganlikun 0:20e0c61e0684 555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
ganlikun 0:20e0c61e0684 556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
ganlikun 0:20e0c61e0684 557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
ganlikun 0:20e0c61e0684 558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
ganlikun 0:20e0c61e0684 559 } SysTick_Type;
ganlikun 0:20e0c61e0684 560
ganlikun 0:20e0c61e0684 561 /* SysTick Control / Status Register Definitions */
ganlikun 0:20e0c61e0684 562 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
ganlikun 0:20e0c61e0684 563 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
ganlikun 0:20e0c61e0684 564
ganlikun 0:20e0c61e0684 565 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
ganlikun 0:20e0c61e0684 566 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
ganlikun 0:20e0c61e0684 567
ganlikun 0:20e0c61e0684 568 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
ganlikun 0:20e0c61e0684 569 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
ganlikun 0:20e0c61e0684 570
ganlikun 0:20e0c61e0684 571 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
ganlikun 0:20e0c61e0684 572 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
ganlikun 0:20e0c61e0684 573
ganlikun 0:20e0c61e0684 574 /* SysTick Reload Register Definitions */
ganlikun 0:20e0c61e0684 575 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
ganlikun 0:20e0c61e0684 576 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
ganlikun 0:20e0c61e0684 577
ganlikun 0:20e0c61e0684 578 /* SysTick Current Register Definitions */
ganlikun 0:20e0c61e0684 579 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
ganlikun 0:20e0c61e0684 580 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
ganlikun 0:20e0c61e0684 581
ganlikun 0:20e0c61e0684 582 /* SysTick Calibration Register Definitions */
ganlikun 0:20e0c61e0684 583 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
ganlikun 0:20e0c61e0684 584 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
ganlikun 0:20e0c61e0684 585
ganlikun 0:20e0c61e0684 586 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
ganlikun 0:20e0c61e0684 587 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
ganlikun 0:20e0c61e0684 588
ganlikun 0:20e0c61e0684 589 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
ganlikun 0:20e0c61e0684 590 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
ganlikun 0:20e0c61e0684 591
ganlikun 0:20e0c61e0684 592 /*@} end of group CMSIS_SysTick */
ganlikun 0:20e0c61e0684 593
ganlikun 0:20e0c61e0684 594
ganlikun 0:20e0c61e0684 595 /**
ganlikun 0:20e0c61e0684 596 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
ganlikun 0:20e0c61e0684 598 \brief Type definitions for the Data Watchpoint and Trace (DWT)
ganlikun 0:20e0c61e0684 599 @{
ganlikun 0:20e0c61e0684 600 */
ganlikun 0:20e0c61e0684 601
ganlikun 0:20e0c61e0684 602 /**
ganlikun 0:20e0c61e0684 603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
ganlikun 0:20e0c61e0684 604 */
ganlikun 0:20e0c61e0684 605 typedef struct
ganlikun 0:20e0c61e0684 606 {
ganlikun 0:20e0c61e0684 607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
ganlikun 0:20e0c61e0684 608 uint32_t RESERVED0[6U];
ganlikun 0:20e0c61e0684 609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
ganlikun 0:20e0c61e0684 610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
ganlikun 0:20e0c61e0684 611 uint32_t RESERVED1[1U];
ganlikun 0:20e0c61e0684 612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
ganlikun 0:20e0c61e0684 613 uint32_t RESERVED2[1U];
ganlikun 0:20e0c61e0684 614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
ganlikun 0:20e0c61e0684 615 uint32_t RESERVED3[1U];
ganlikun 0:20e0c61e0684 616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
ganlikun 0:20e0c61e0684 617 uint32_t RESERVED4[1U];
ganlikun 0:20e0c61e0684 618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
ganlikun 0:20e0c61e0684 619 uint32_t RESERVED5[1U];
ganlikun 0:20e0c61e0684 620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
ganlikun 0:20e0c61e0684 621 uint32_t RESERVED6[1U];
ganlikun 0:20e0c61e0684 622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
ganlikun 0:20e0c61e0684 623 uint32_t RESERVED7[1U];
ganlikun 0:20e0c61e0684 624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
ganlikun 0:20e0c61e0684 625 uint32_t RESERVED8[1U];
ganlikun 0:20e0c61e0684 626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
ganlikun 0:20e0c61e0684 627 uint32_t RESERVED9[1U];
ganlikun 0:20e0c61e0684 628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
ganlikun 0:20e0c61e0684 629 uint32_t RESERVED10[1U];
ganlikun 0:20e0c61e0684 630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
ganlikun 0:20e0c61e0684 631 uint32_t RESERVED11[1U];
ganlikun 0:20e0c61e0684 632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
ganlikun 0:20e0c61e0684 633 uint32_t RESERVED12[1U];
ganlikun 0:20e0c61e0684 634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
ganlikun 0:20e0c61e0684 635 uint32_t RESERVED13[1U];
ganlikun 0:20e0c61e0684 636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
ganlikun 0:20e0c61e0684 637 uint32_t RESERVED14[1U];
ganlikun 0:20e0c61e0684 638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
ganlikun 0:20e0c61e0684 639 uint32_t RESERVED15[1U];
ganlikun 0:20e0c61e0684 640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
ganlikun 0:20e0c61e0684 641 uint32_t RESERVED16[1U];
ganlikun 0:20e0c61e0684 642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
ganlikun 0:20e0c61e0684 643 uint32_t RESERVED17[1U];
ganlikun 0:20e0c61e0684 644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
ganlikun 0:20e0c61e0684 645 uint32_t RESERVED18[1U];
ganlikun 0:20e0c61e0684 646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
ganlikun 0:20e0c61e0684 647 uint32_t RESERVED19[1U];
ganlikun 0:20e0c61e0684 648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
ganlikun 0:20e0c61e0684 649 uint32_t RESERVED20[1U];
ganlikun 0:20e0c61e0684 650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
ganlikun 0:20e0c61e0684 651 uint32_t RESERVED21[1U];
ganlikun 0:20e0c61e0684 652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
ganlikun 0:20e0c61e0684 653 uint32_t RESERVED22[1U];
ganlikun 0:20e0c61e0684 654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
ganlikun 0:20e0c61e0684 655 uint32_t RESERVED23[1U];
ganlikun 0:20e0c61e0684 656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
ganlikun 0:20e0c61e0684 657 uint32_t RESERVED24[1U];
ganlikun 0:20e0c61e0684 658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
ganlikun 0:20e0c61e0684 659 uint32_t RESERVED25[1U];
ganlikun 0:20e0c61e0684 660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
ganlikun 0:20e0c61e0684 661 uint32_t RESERVED26[1U];
ganlikun 0:20e0c61e0684 662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
ganlikun 0:20e0c61e0684 663 uint32_t RESERVED27[1U];
ganlikun 0:20e0c61e0684 664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
ganlikun 0:20e0c61e0684 665 uint32_t RESERVED28[1U];
ganlikun 0:20e0c61e0684 666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
ganlikun 0:20e0c61e0684 667 uint32_t RESERVED29[1U];
ganlikun 0:20e0c61e0684 668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
ganlikun 0:20e0c61e0684 669 uint32_t RESERVED30[1U];
ganlikun 0:20e0c61e0684 670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
ganlikun 0:20e0c61e0684 671 uint32_t RESERVED31[1U];
ganlikun 0:20e0c61e0684 672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
ganlikun 0:20e0c61e0684 673 } DWT_Type;
ganlikun 0:20e0c61e0684 674
ganlikun 0:20e0c61e0684 675 /* DWT Control Register Definitions */
ganlikun 0:20e0c61e0684 676 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
ganlikun 0:20e0c61e0684 677 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
ganlikun 0:20e0c61e0684 678
ganlikun 0:20e0c61e0684 679 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
ganlikun 0:20e0c61e0684 680 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
ganlikun 0:20e0c61e0684 681
ganlikun 0:20e0c61e0684 682 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
ganlikun 0:20e0c61e0684 683 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
ganlikun 0:20e0c61e0684 684
ganlikun 0:20e0c61e0684 685 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
ganlikun 0:20e0c61e0684 686 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
ganlikun 0:20e0c61e0684 687
ganlikun 0:20e0c61e0684 688 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
ganlikun 0:20e0c61e0684 689 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
ganlikun 0:20e0c61e0684 690
ganlikun 0:20e0c61e0684 691 /* DWT Comparator Function Register Definitions */
ganlikun 0:20e0c61e0684 692 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
ganlikun 0:20e0c61e0684 693 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
ganlikun 0:20e0c61e0684 694
ganlikun 0:20e0c61e0684 695 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
ganlikun 0:20e0c61e0684 696 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
ganlikun 0:20e0c61e0684 697
ganlikun 0:20e0c61e0684 698 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
ganlikun 0:20e0c61e0684 699 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
ganlikun 0:20e0c61e0684 700
ganlikun 0:20e0c61e0684 701 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
ganlikun 0:20e0c61e0684 702 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
ganlikun 0:20e0c61e0684 703
ganlikun 0:20e0c61e0684 704 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
ganlikun 0:20e0c61e0684 705 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
ganlikun 0:20e0c61e0684 706
ganlikun 0:20e0c61e0684 707 /*@}*/ /* end of group CMSIS_DWT */
ganlikun 0:20e0c61e0684 708
ganlikun 0:20e0c61e0684 709
ganlikun 0:20e0c61e0684 710 /**
ganlikun 0:20e0c61e0684 711 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 712 \defgroup CMSIS_TPI Trace Port Interface (TPI)
ganlikun 0:20e0c61e0684 713 \brief Type definitions for the Trace Port Interface (TPI)
ganlikun 0:20e0c61e0684 714 @{
ganlikun 0:20e0c61e0684 715 */
ganlikun 0:20e0c61e0684 716
ganlikun 0:20e0c61e0684 717 /**
ganlikun 0:20e0c61e0684 718 \brief Structure type to access the Trace Port Interface Register (TPI).
ganlikun 0:20e0c61e0684 719 */
ganlikun 0:20e0c61e0684 720 typedef struct
ganlikun 0:20e0c61e0684 721 {
ganlikun 0:20e0c61e0684 722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
ganlikun 0:20e0c61e0684 723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
ganlikun 0:20e0c61e0684 724 uint32_t RESERVED0[2U];
ganlikun 0:20e0c61e0684 725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
ganlikun 0:20e0c61e0684 726 uint32_t RESERVED1[55U];
ganlikun 0:20e0c61e0684 727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
ganlikun 0:20e0c61e0684 728 uint32_t RESERVED2[131U];
ganlikun 0:20e0c61e0684 729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
ganlikun 0:20e0c61e0684 730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
ganlikun 0:20e0c61e0684 731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
ganlikun 0:20e0c61e0684 732 uint32_t RESERVED3[759U];
ganlikun 0:20e0c61e0684 733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
ganlikun 0:20e0c61e0684 734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
ganlikun 0:20e0c61e0684 735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
ganlikun 0:20e0c61e0684 736 uint32_t RESERVED4[1U];
ganlikun 0:20e0c61e0684 737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
ganlikun 0:20e0c61e0684 738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
ganlikun 0:20e0c61e0684 739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
ganlikun 0:20e0c61e0684 740 uint32_t RESERVED5[39U];
ganlikun 0:20e0c61e0684 741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
ganlikun 0:20e0c61e0684 742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
ganlikun 0:20e0c61e0684 743 uint32_t RESERVED7[8U];
ganlikun 0:20e0c61e0684 744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
ganlikun 0:20e0c61e0684 745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
ganlikun 0:20e0c61e0684 746 } TPI_Type;
ganlikun 0:20e0c61e0684 747
ganlikun 0:20e0c61e0684 748 /* TPI Asynchronous Clock Prescaler Register Definitions */
ganlikun 0:20e0c61e0684 749 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
ganlikun 0:20e0c61e0684 750 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
ganlikun 0:20e0c61e0684 751
ganlikun 0:20e0c61e0684 752 /* TPI Selected Pin Protocol Register Definitions */
ganlikun 0:20e0c61e0684 753 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
ganlikun 0:20e0c61e0684 754 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
ganlikun 0:20e0c61e0684 755
ganlikun 0:20e0c61e0684 756 /* TPI Formatter and Flush Status Register Definitions */
ganlikun 0:20e0c61e0684 757 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
ganlikun 0:20e0c61e0684 758 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
ganlikun 0:20e0c61e0684 759
ganlikun 0:20e0c61e0684 760 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
ganlikun 0:20e0c61e0684 761 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
ganlikun 0:20e0c61e0684 762
ganlikun 0:20e0c61e0684 763 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
ganlikun 0:20e0c61e0684 764 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
ganlikun 0:20e0c61e0684 765
ganlikun 0:20e0c61e0684 766 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
ganlikun 0:20e0c61e0684 767 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
ganlikun 0:20e0c61e0684 768
ganlikun 0:20e0c61e0684 769 /* TPI Formatter and Flush Control Register Definitions */
ganlikun 0:20e0c61e0684 770 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
ganlikun 0:20e0c61e0684 771 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
ganlikun 0:20e0c61e0684 772
ganlikun 0:20e0c61e0684 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
ganlikun 0:20e0c61e0684 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
ganlikun 0:20e0c61e0684 775
ganlikun 0:20e0c61e0684 776 /* TPI TRIGGER Register Definitions */
ganlikun 0:20e0c61e0684 777 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
ganlikun 0:20e0c61e0684 778 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
ganlikun 0:20e0c61e0684 779
ganlikun 0:20e0c61e0684 780 /* TPI Integration ETM Data Register Definitions (FIFO0) */
ganlikun 0:20e0c61e0684 781 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
ganlikun 0:20e0c61e0684 782 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
ganlikun 0:20e0c61e0684 783
ganlikun 0:20e0c61e0684 784 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
ganlikun 0:20e0c61e0684 785 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
ganlikun 0:20e0c61e0684 786
ganlikun 0:20e0c61e0684 787 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
ganlikun 0:20e0c61e0684 788 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
ganlikun 0:20e0c61e0684 789
ganlikun 0:20e0c61e0684 790 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
ganlikun 0:20e0c61e0684 791 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
ganlikun 0:20e0c61e0684 792
ganlikun 0:20e0c61e0684 793 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
ganlikun 0:20e0c61e0684 794 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
ganlikun 0:20e0c61e0684 795
ganlikun 0:20e0c61e0684 796 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
ganlikun 0:20e0c61e0684 797 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
ganlikun 0:20e0c61e0684 798
ganlikun 0:20e0c61e0684 799 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
ganlikun 0:20e0c61e0684 800 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
ganlikun 0:20e0c61e0684 801
ganlikun 0:20e0c61e0684 802 /* TPI ITATBCTR2 Register Definitions */
ganlikun 0:20e0c61e0684 803 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
ganlikun 0:20e0c61e0684 804 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
ganlikun 0:20e0c61e0684 805
ganlikun 0:20e0c61e0684 806 /* TPI Integration ITM Data Register Definitions (FIFO1) */
ganlikun 0:20e0c61e0684 807 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
ganlikun 0:20e0c61e0684 808 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
ganlikun 0:20e0c61e0684 809
ganlikun 0:20e0c61e0684 810 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
ganlikun 0:20e0c61e0684 811 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
ganlikun 0:20e0c61e0684 812
ganlikun 0:20e0c61e0684 813 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
ganlikun 0:20e0c61e0684 814 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
ganlikun 0:20e0c61e0684 815
ganlikun 0:20e0c61e0684 816 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
ganlikun 0:20e0c61e0684 817 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
ganlikun 0:20e0c61e0684 818
ganlikun 0:20e0c61e0684 819 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
ganlikun 0:20e0c61e0684 820 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
ganlikun 0:20e0c61e0684 821
ganlikun 0:20e0c61e0684 822 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
ganlikun 0:20e0c61e0684 823 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
ganlikun 0:20e0c61e0684 824
ganlikun 0:20e0c61e0684 825 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
ganlikun 0:20e0c61e0684 826 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
ganlikun 0:20e0c61e0684 827
ganlikun 0:20e0c61e0684 828 /* TPI ITATBCTR0 Register Definitions */
ganlikun 0:20e0c61e0684 829 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
ganlikun 0:20e0c61e0684 830 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
ganlikun 0:20e0c61e0684 831
ganlikun 0:20e0c61e0684 832 /* TPI Integration Mode Control Register Definitions */
ganlikun 0:20e0c61e0684 833 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
ganlikun 0:20e0c61e0684 834 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
ganlikun 0:20e0c61e0684 835
ganlikun 0:20e0c61e0684 836 /* TPI DEVID Register Definitions */
ganlikun 0:20e0c61e0684 837 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
ganlikun 0:20e0c61e0684 838 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
ganlikun 0:20e0c61e0684 839
ganlikun 0:20e0c61e0684 840 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
ganlikun 0:20e0c61e0684 841 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
ganlikun 0:20e0c61e0684 842
ganlikun 0:20e0c61e0684 843 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
ganlikun 0:20e0c61e0684 844 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
ganlikun 0:20e0c61e0684 845
ganlikun 0:20e0c61e0684 846 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
ganlikun 0:20e0c61e0684 847 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
ganlikun 0:20e0c61e0684 848
ganlikun 0:20e0c61e0684 849 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
ganlikun 0:20e0c61e0684 850 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
ganlikun 0:20e0c61e0684 851
ganlikun 0:20e0c61e0684 852 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
ganlikun 0:20e0c61e0684 853 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
ganlikun 0:20e0c61e0684 854
ganlikun 0:20e0c61e0684 855 /* TPI DEVTYPE Register Definitions */
ganlikun 0:20e0c61e0684 856 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
ganlikun 0:20e0c61e0684 857 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
ganlikun 0:20e0c61e0684 858
ganlikun 0:20e0c61e0684 859 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
ganlikun 0:20e0c61e0684 860 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
ganlikun 0:20e0c61e0684 861
ganlikun 0:20e0c61e0684 862 /*@}*/ /* end of group CMSIS_TPI */
ganlikun 0:20e0c61e0684 863
ganlikun 0:20e0c61e0684 864
ganlikun 0:20e0c61e0684 865 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:20e0c61e0684 866 /**
ganlikun 0:20e0c61e0684 867 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 868 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
ganlikun 0:20e0c61e0684 869 \brief Type definitions for the Memory Protection Unit (MPU)
ganlikun 0:20e0c61e0684 870 @{
ganlikun 0:20e0c61e0684 871 */
ganlikun 0:20e0c61e0684 872
ganlikun 0:20e0c61e0684 873 /**
ganlikun 0:20e0c61e0684 874 \brief Structure type to access the Memory Protection Unit (MPU).
ganlikun 0:20e0c61e0684 875 */
ganlikun 0:20e0c61e0684 876 typedef struct
ganlikun 0:20e0c61e0684 877 {
ganlikun 0:20e0c61e0684 878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
ganlikun 0:20e0c61e0684 879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
ganlikun 0:20e0c61e0684 880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
ganlikun 0:20e0c61e0684 881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
ganlikun 0:20e0c61e0684 882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
ganlikun 0:20e0c61e0684 883 uint32_t RESERVED0[7U];
ganlikun 0:20e0c61e0684 884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
ganlikun 0:20e0c61e0684 885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
ganlikun 0:20e0c61e0684 886 } MPU_Type;
ganlikun 0:20e0c61e0684 887
ganlikun 0:20e0c61e0684 888 /* MPU Type Register Definitions */
ganlikun 0:20e0c61e0684 889 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
ganlikun 0:20e0c61e0684 890 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
ganlikun 0:20e0c61e0684 891
ganlikun 0:20e0c61e0684 892 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
ganlikun 0:20e0c61e0684 893 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
ganlikun 0:20e0c61e0684 894
ganlikun 0:20e0c61e0684 895 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
ganlikun 0:20e0c61e0684 896 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
ganlikun 0:20e0c61e0684 897
ganlikun 0:20e0c61e0684 898 /* MPU Control Register Definitions */
ganlikun 0:20e0c61e0684 899 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
ganlikun 0:20e0c61e0684 900 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
ganlikun 0:20e0c61e0684 901
ganlikun 0:20e0c61e0684 902 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
ganlikun 0:20e0c61e0684 903 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
ganlikun 0:20e0c61e0684 904
ganlikun 0:20e0c61e0684 905 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
ganlikun 0:20e0c61e0684 906 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
ganlikun 0:20e0c61e0684 907
ganlikun 0:20e0c61e0684 908 /* MPU Region Number Register Definitions */
ganlikun 0:20e0c61e0684 909 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
ganlikun 0:20e0c61e0684 910 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
ganlikun 0:20e0c61e0684 911
ganlikun 0:20e0c61e0684 912 /* MPU Region Base Address Register Definitions */
ganlikun 0:20e0c61e0684 913 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
ganlikun 0:20e0c61e0684 914 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
ganlikun 0:20e0c61e0684 915
ganlikun 0:20e0c61e0684 916 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
ganlikun 0:20e0c61e0684 917 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
ganlikun 0:20e0c61e0684 918
ganlikun 0:20e0c61e0684 919 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
ganlikun 0:20e0c61e0684 920 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
ganlikun 0:20e0c61e0684 921
ganlikun 0:20e0c61e0684 922 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
ganlikun 0:20e0c61e0684 923 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
ganlikun 0:20e0c61e0684 924
ganlikun 0:20e0c61e0684 925 /* MPU Region Limit Address Register Definitions */
ganlikun 0:20e0c61e0684 926 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
ganlikun 0:20e0c61e0684 927 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
ganlikun 0:20e0c61e0684 928
ganlikun 0:20e0c61e0684 929 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
ganlikun 0:20e0c61e0684 930 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
ganlikun 0:20e0c61e0684 931
ganlikun 0:20e0c61e0684 932 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
ganlikun 0:20e0c61e0684 933 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
ganlikun 0:20e0c61e0684 934
ganlikun 0:20e0c61e0684 935 /* MPU Memory Attribute Indirection Register 0 Definitions */
ganlikun 0:20e0c61e0684 936 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
ganlikun 0:20e0c61e0684 937 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
ganlikun 0:20e0c61e0684 938
ganlikun 0:20e0c61e0684 939 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
ganlikun 0:20e0c61e0684 940 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
ganlikun 0:20e0c61e0684 941
ganlikun 0:20e0c61e0684 942 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
ganlikun 0:20e0c61e0684 943 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
ganlikun 0:20e0c61e0684 944
ganlikun 0:20e0c61e0684 945 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
ganlikun 0:20e0c61e0684 946 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
ganlikun 0:20e0c61e0684 947
ganlikun 0:20e0c61e0684 948 /* MPU Memory Attribute Indirection Register 1 Definitions */
ganlikun 0:20e0c61e0684 949 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
ganlikun 0:20e0c61e0684 950 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
ganlikun 0:20e0c61e0684 951
ganlikun 0:20e0c61e0684 952 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
ganlikun 0:20e0c61e0684 953 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
ganlikun 0:20e0c61e0684 954
ganlikun 0:20e0c61e0684 955 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
ganlikun 0:20e0c61e0684 956 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
ganlikun 0:20e0c61e0684 957
ganlikun 0:20e0c61e0684 958 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
ganlikun 0:20e0c61e0684 959 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
ganlikun 0:20e0c61e0684 960
ganlikun 0:20e0c61e0684 961 /*@} end of group CMSIS_MPU */
ganlikun 0:20e0c61e0684 962 #endif
ganlikun 0:20e0c61e0684 963
ganlikun 0:20e0c61e0684 964
ganlikun 0:20e0c61e0684 965 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:20e0c61e0684 966 /**
ganlikun 0:20e0c61e0684 967 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 968 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
ganlikun 0:20e0c61e0684 969 \brief Type definitions for the Security Attribution Unit (SAU)
ganlikun 0:20e0c61e0684 970 @{
ganlikun 0:20e0c61e0684 971 */
ganlikun 0:20e0c61e0684 972
ganlikun 0:20e0c61e0684 973 /**
ganlikun 0:20e0c61e0684 974 \brief Structure type to access the Security Attribution Unit (SAU).
ganlikun 0:20e0c61e0684 975 */
ganlikun 0:20e0c61e0684 976 typedef struct
ganlikun 0:20e0c61e0684 977 {
ganlikun 0:20e0c61e0684 978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
ganlikun 0:20e0c61e0684 979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
ganlikun 0:20e0c61e0684 980 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
ganlikun 0:20e0c61e0684 981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
ganlikun 0:20e0c61e0684 982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
ganlikun 0:20e0c61e0684 983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
ganlikun 0:20e0c61e0684 984 #endif
ganlikun 0:20e0c61e0684 985 } SAU_Type;
ganlikun 0:20e0c61e0684 986
ganlikun 0:20e0c61e0684 987 /* SAU Control Register Definitions */
ganlikun 0:20e0c61e0684 988 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
ganlikun 0:20e0c61e0684 989 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
ganlikun 0:20e0c61e0684 990
ganlikun 0:20e0c61e0684 991 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
ganlikun 0:20e0c61e0684 992 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
ganlikun 0:20e0c61e0684 993
ganlikun 0:20e0c61e0684 994 /* SAU Type Register Definitions */
ganlikun 0:20e0c61e0684 995 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
ganlikun 0:20e0c61e0684 996 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
ganlikun 0:20e0c61e0684 997
ganlikun 0:20e0c61e0684 998 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
ganlikun 0:20e0c61e0684 999 /* SAU Region Number Register Definitions */
ganlikun 0:20e0c61e0684 1000 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
ganlikun 0:20e0c61e0684 1001 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
ganlikun 0:20e0c61e0684 1002
ganlikun 0:20e0c61e0684 1003 /* SAU Region Base Address Register Definitions */
ganlikun 0:20e0c61e0684 1004 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
ganlikun 0:20e0c61e0684 1005 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
ganlikun 0:20e0c61e0684 1006
ganlikun 0:20e0c61e0684 1007 /* SAU Region Limit Address Register Definitions */
ganlikun 0:20e0c61e0684 1008 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
ganlikun 0:20e0c61e0684 1009 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
ganlikun 0:20e0c61e0684 1010
ganlikun 0:20e0c61e0684 1011 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
ganlikun 0:20e0c61e0684 1012 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
ganlikun 0:20e0c61e0684 1013
ganlikun 0:20e0c61e0684 1014 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
ganlikun 0:20e0c61e0684 1015 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
ganlikun 0:20e0c61e0684 1016
ganlikun 0:20e0c61e0684 1017 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
ganlikun 0:20e0c61e0684 1018
ganlikun 0:20e0c61e0684 1019 /*@} end of group CMSIS_SAU */
ganlikun 0:20e0c61e0684 1020 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:20e0c61e0684 1021
ganlikun 0:20e0c61e0684 1022
ganlikun 0:20e0c61e0684 1023 /**
ganlikun 0:20e0c61e0684 1024 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 1025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
ganlikun 0:20e0c61e0684 1026 \brief Type definitions for the Core Debug Registers
ganlikun 0:20e0c61e0684 1027 @{
ganlikun 0:20e0c61e0684 1028 */
ganlikun 0:20e0c61e0684 1029
ganlikun 0:20e0c61e0684 1030 /**
ganlikun 0:20e0c61e0684 1031 \brief Structure type to access the Core Debug Register (CoreDebug).
ganlikun 0:20e0c61e0684 1032 */
ganlikun 0:20e0c61e0684 1033 typedef struct
ganlikun 0:20e0c61e0684 1034 {
ganlikun 0:20e0c61e0684 1035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
ganlikun 0:20e0c61e0684 1036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
ganlikun 0:20e0c61e0684 1037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
ganlikun 0:20e0c61e0684 1038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
ganlikun 0:20e0c61e0684 1039 uint32_t RESERVED4[1U];
ganlikun 0:20e0c61e0684 1040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
ganlikun 0:20e0c61e0684 1041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
ganlikun 0:20e0c61e0684 1042 } CoreDebug_Type;
ganlikun 0:20e0c61e0684 1043
ganlikun 0:20e0c61e0684 1044 /* Debug Halting Control and Status Register Definitions */
ganlikun 0:20e0c61e0684 1045 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
ganlikun 0:20e0c61e0684 1046 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
ganlikun 0:20e0c61e0684 1047
ganlikun 0:20e0c61e0684 1048 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
ganlikun 0:20e0c61e0684 1049 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
ganlikun 0:20e0c61e0684 1050
ganlikun 0:20e0c61e0684 1051 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
ganlikun 0:20e0c61e0684 1052 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
ganlikun 0:20e0c61e0684 1053
ganlikun 0:20e0c61e0684 1054 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
ganlikun 0:20e0c61e0684 1055 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
ganlikun 0:20e0c61e0684 1056
ganlikun 0:20e0c61e0684 1057 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
ganlikun 0:20e0c61e0684 1058 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
ganlikun 0:20e0c61e0684 1059
ganlikun 0:20e0c61e0684 1060 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
ganlikun 0:20e0c61e0684 1061 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
ganlikun 0:20e0c61e0684 1062
ganlikun 0:20e0c61e0684 1063 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
ganlikun 0:20e0c61e0684 1064 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
ganlikun 0:20e0c61e0684 1065
ganlikun 0:20e0c61e0684 1066 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
ganlikun 0:20e0c61e0684 1067 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
ganlikun 0:20e0c61e0684 1068
ganlikun 0:20e0c61e0684 1069 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
ganlikun 0:20e0c61e0684 1070 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
ganlikun 0:20e0c61e0684 1071
ganlikun 0:20e0c61e0684 1072 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
ganlikun 0:20e0c61e0684 1073 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
ganlikun 0:20e0c61e0684 1074
ganlikun 0:20e0c61e0684 1075 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
ganlikun 0:20e0c61e0684 1076 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
ganlikun 0:20e0c61e0684 1077
ganlikun 0:20e0c61e0684 1078 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
ganlikun 0:20e0c61e0684 1079 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
ganlikun 0:20e0c61e0684 1080
ganlikun 0:20e0c61e0684 1081 /* Debug Core Register Selector Register Definitions */
ganlikun 0:20e0c61e0684 1082 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
ganlikun 0:20e0c61e0684 1083 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
ganlikun 0:20e0c61e0684 1084
ganlikun 0:20e0c61e0684 1085 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
ganlikun 0:20e0c61e0684 1086 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
ganlikun 0:20e0c61e0684 1087
ganlikun 0:20e0c61e0684 1088 /* Debug Exception and Monitor Control Register */
ganlikun 0:20e0c61e0684 1089 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
ganlikun 0:20e0c61e0684 1090 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
ganlikun 0:20e0c61e0684 1091
ganlikun 0:20e0c61e0684 1092 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
ganlikun 0:20e0c61e0684 1093 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
ganlikun 0:20e0c61e0684 1094
ganlikun 0:20e0c61e0684 1095 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
ganlikun 0:20e0c61e0684 1096 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
ganlikun 0:20e0c61e0684 1097
ganlikun 0:20e0c61e0684 1098 /* Debug Authentication Control Register Definitions */
ganlikun 0:20e0c61e0684 1099 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
ganlikun 0:20e0c61e0684 1100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
ganlikun 0:20e0c61e0684 1101
ganlikun 0:20e0c61e0684 1102 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
ganlikun 0:20e0c61e0684 1103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
ganlikun 0:20e0c61e0684 1104
ganlikun 0:20e0c61e0684 1105 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
ganlikun 0:20e0c61e0684 1106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
ganlikun 0:20e0c61e0684 1107
ganlikun 0:20e0c61e0684 1108 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
ganlikun 0:20e0c61e0684 1109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
ganlikun 0:20e0c61e0684 1110
ganlikun 0:20e0c61e0684 1111 /* Debug Security Control and Status Register Definitions */
ganlikun 0:20e0c61e0684 1112 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
ganlikun 0:20e0c61e0684 1113 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
ganlikun 0:20e0c61e0684 1114
ganlikun 0:20e0c61e0684 1115 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
ganlikun 0:20e0c61e0684 1116 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
ganlikun 0:20e0c61e0684 1117
ganlikun 0:20e0c61e0684 1118 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
ganlikun 0:20e0c61e0684 1119 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
ganlikun 0:20e0c61e0684 1120
ganlikun 0:20e0c61e0684 1121 /*@} end of group CMSIS_CoreDebug */
ganlikun 0:20e0c61e0684 1122
ganlikun 0:20e0c61e0684 1123
ganlikun 0:20e0c61e0684 1124 /**
ganlikun 0:20e0c61e0684 1125 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 1126 \defgroup CMSIS_core_bitfield Core register bit field macros
ganlikun 0:20e0c61e0684 1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
ganlikun 0:20e0c61e0684 1128 @{
ganlikun 0:20e0c61e0684 1129 */
ganlikun 0:20e0c61e0684 1130
ganlikun 0:20e0c61e0684 1131 /**
ganlikun 0:20e0c61e0684 1132 \brief Mask and shift a bit field value for use in a register bit range.
ganlikun 0:20e0c61e0684 1133 \param[in] field Name of the register bit field.
ganlikun 0:20e0c61e0684 1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
ganlikun 0:20e0c61e0684 1135 \return Masked and shifted value.
ganlikun 0:20e0c61e0684 1136 */
ganlikun 0:20e0c61e0684 1137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
ganlikun 0:20e0c61e0684 1138
ganlikun 0:20e0c61e0684 1139 /**
ganlikun 0:20e0c61e0684 1140 \brief Mask and shift a register value to extract a bit filed value.
ganlikun 0:20e0c61e0684 1141 \param[in] field Name of the register bit field.
ganlikun 0:20e0c61e0684 1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
ganlikun 0:20e0c61e0684 1143 \return Masked and shifted bit field value.
ganlikun 0:20e0c61e0684 1144 */
ganlikun 0:20e0c61e0684 1145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ganlikun 0:20e0c61e0684 1146
ganlikun 0:20e0c61e0684 1147 /*@} end of group CMSIS_core_bitfield */
ganlikun 0:20e0c61e0684 1148
ganlikun 0:20e0c61e0684 1149
ganlikun 0:20e0c61e0684 1150 /**
ganlikun 0:20e0c61e0684 1151 \ingroup CMSIS_core_register
ganlikun 0:20e0c61e0684 1152 \defgroup CMSIS_core_base Core Definitions
ganlikun 0:20e0c61e0684 1153 \brief Definitions for base addresses, unions, and structures.
ganlikun 0:20e0c61e0684 1154 @{
ganlikun 0:20e0c61e0684 1155 */
ganlikun 0:20e0c61e0684 1156
ganlikun 0:20e0c61e0684 1157 /* Memory mapping of Core Hardware */
ganlikun 0:20e0c61e0684 1158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
ganlikun 0:20e0c61e0684 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
ganlikun 0:20e0c61e0684 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
ganlikun 0:20e0c61e0684 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
ganlikun 0:20e0c61e0684 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
ganlikun 0:20e0c61e0684 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
ganlikun 0:20e0c61e0684 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
ganlikun 0:20e0c61e0684 1165
ganlikun 0:20e0c61e0684 1166
ganlikun 0:20e0c61e0684 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
ganlikun 0:20e0c61e0684 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
ganlikun 0:20e0c61e0684 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
ganlikun 0:20e0c61e0684 1170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
ganlikun 0:20e0c61e0684 1171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
ganlikun 0:20e0c61e0684 1172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
ganlikun 0:20e0c61e0684 1173
ganlikun 0:20e0c61e0684 1174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:20e0c61e0684 1175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
ganlikun 0:20e0c61e0684 1176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
ganlikun 0:20e0c61e0684 1177 #endif
ganlikun 0:20e0c61e0684 1178
ganlikun 0:20e0c61e0684 1179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:20e0c61e0684 1180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
ganlikun 0:20e0c61e0684 1181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
ganlikun 0:20e0c61e0684 1182 #endif
ganlikun 0:20e0c61e0684 1183
ganlikun 0:20e0c61e0684 1184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:20e0c61e0684 1185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
ganlikun 0:20e0c61e0684 1186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
ganlikun 0:20e0c61e0684 1187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
ganlikun 0:20e0c61e0684 1188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
ganlikun 0:20e0c61e0684 1189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
ganlikun 0:20e0c61e0684 1190
ganlikun 0:20e0c61e0684 1191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
ganlikun 0:20e0c61e0684 1192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
ganlikun 0:20e0c61e0684 1193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
ganlikun 0:20e0c61e0684 1194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
ganlikun 0:20e0c61e0684 1195
ganlikun 0:20e0c61e0684 1196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ganlikun 0:20e0c61e0684 1197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
ganlikun 0:20e0c61e0684 1198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
ganlikun 0:20e0c61e0684 1199 #endif
ganlikun 0:20e0c61e0684 1200
ganlikun 0:20e0c61e0684 1201 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:20e0c61e0684 1202 /*@} */
ganlikun 0:20e0c61e0684 1203
ganlikun 0:20e0c61e0684 1204
ganlikun 0:20e0c61e0684 1205
ganlikun 0:20e0c61e0684 1206 /*******************************************************************************
ganlikun 0:20e0c61e0684 1207 * Hardware Abstraction Layer
ganlikun 0:20e0c61e0684 1208 Core Function Interface contains:
ganlikun 0:20e0c61e0684 1209 - Core NVIC Functions
ganlikun 0:20e0c61e0684 1210 - Core SysTick Functions
ganlikun 0:20e0c61e0684 1211 - Core Register Access Functions
ganlikun 0:20e0c61e0684 1212 ******************************************************************************/
ganlikun 0:20e0c61e0684 1213 /**
ganlikun 0:20e0c61e0684 1214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
ganlikun 0:20e0c61e0684 1215 */
ganlikun 0:20e0c61e0684 1216
ganlikun 0:20e0c61e0684 1217
ganlikun 0:20e0c61e0684 1218
ganlikun 0:20e0c61e0684 1219 /* ########################## NVIC functions #################################### */
ganlikun 0:20e0c61e0684 1220 /**
ganlikun 0:20e0c61e0684 1221 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:20e0c61e0684 1222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
ganlikun 0:20e0c61e0684 1223 \brief Functions that manage interrupts and exceptions via the NVIC.
ganlikun 0:20e0c61e0684 1224 @{
ganlikun 0:20e0c61e0684 1225 */
ganlikun 0:20e0c61e0684 1226
ganlikun 0:20e0c61e0684 1227 #ifdef CMSIS_NVIC_VIRTUAL
ganlikun 0:20e0c61e0684 1228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 1229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
ganlikun 0:20e0c61e0684 1230 #endif
ganlikun 0:20e0c61e0684 1231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 1232 #else
ganlikun 0:20e0c61e0684 1233 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
ganlikun 0:20e0c61e0684 1234 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
ganlikun 0:20e0c61e0684 1235 #define NVIC_EnableIRQ __NVIC_EnableIRQ
ganlikun 0:20e0c61e0684 1236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
ganlikun 0:20e0c61e0684 1237 #define NVIC_DisableIRQ __NVIC_DisableIRQ
ganlikun 0:20e0c61e0684 1238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
ganlikun 0:20e0c61e0684 1239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
ganlikun 0:20e0c61e0684 1240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
ganlikun 0:20e0c61e0684 1241 #define NVIC_GetActive __NVIC_GetActive
ganlikun 0:20e0c61e0684 1242 #define NVIC_SetPriority __NVIC_SetPriority
ganlikun 0:20e0c61e0684 1243 #define NVIC_GetPriority __NVIC_GetPriority
ganlikun 0:20e0c61e0684 1244 #define NVIC_SystemReset __NVIC_SystemReset
ganlikun 0:20e0c61e0684 1245 #endif /* CMSIS_NVIC_VIRTUAL */
ganlikun 0:20e0c61e0684 1246
ganlikun 0:20e0c61e0684 1247 #ifdef CMSIS_VECTAB_VIRTUAL
ganlikun 0:20e0c61e0684 1248 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 1249 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
ganlikun 0:20e0c61e0684 1250 #endif
ganlikun 0:20e0c61e0684 1251 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
ganlikun 0:20e0c61e0684 1252 #else
ganlikun 0:20e0c61e0684 1253 #define NVIC_SetVector __NVIC_SetVector
ganlikun 0:20e0c61e0684 1254 #define NVIC_GetVector __NVIC_GetVector
ganlikun 0:20e0c61e0684 1255 #endif /* (CMSIS_VECTAB_VIRTUAL) */
ganlikun 0:20e0c61e0684 1256
ganlikun 0:20e0c61e0684 1257 #define NVIC_USER_IRQ_OFFSET 16
ganlikun 0:20e0c61e0684 1258
ganlikun 0:20e0c61e0684 1259
ganlikun 0:20e0c61e0684 1260 /* Interrupt Priorities are WORD accessible only under ARMv6M */
ganlikun 0:20e0c61e0684 1261 /* The following MACROS handle generation of the register offset and byte masks */
ganlikun 0:20e0c61e0684 1262 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ganlikun 0:20e0c61e0684 1263 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
ganlikun 0:20e0c61e0684 1264 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
ganlikun 0:20e0c61e0684 1265
ganlikun 0:20e0c61e0684 1266
ganlikun 0:20e0c61e0684 1267 /**
ganlikun 0:20e0c61e0684 1268 \brief Enable Interrupt
ganlikun 0:20e0c61e0684 1269 \details Enables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:20e0c61e0684 1270 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1271 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1272 */
ganlikun 0:20e0c61e0684 1273 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1274 {
ganlikun 0:20e0c61e0684 1275 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1276 {
ganlikun 0:20e0c61e0684 1277 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1278 }
ganlikun 0:20e0c61e0684 1279 }
ganlikun 0:20e0c61e0684 1280
ganlikun 0:20e0c61e0684 1281
ganlikun 0:20e0c61e0684 1282 /**
ganlikun 0:20e0c61e0684 1283 \brief Get Interrupt Enable status
ganlikun 0:20e0c61e0684 1284 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
ganlikun 0:20e0c61e0684 1285 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1286 \return 0 Interrupt is not enabled.
ganlikun 0:20e0c61e0684 1287 \return 1 Interrupt is enabled.
ganlikun 0:20e0c61e0684 1288 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1289 */
ganlikun 0:20e0c61e0684 1290 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1291 {
ganlikun 0:20e0c61e0684 1292 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1293 {
ganlikun 0:20e0c61e0684 1294 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1295 }
ganlikun 0:20e0c61e0684 1296 else
ganlikun 0:20e0c61e0684 1297 {
ganlikun 0:20e0c61e0684 1298 return(0U);
ganlikun 0:20e0c61e0684 1299 }
ganlikun 0:20e0c61e0684 1300 }
ganlikun 0:20e0c61e0684 1301
ganlikun 0:20e0c61e0684 1302
ganlikun 0:20e0c61e0684 1303 /**
ganlikun 0:20e0c61e0684 1304 \brief Disable Interrupt
ganlikun 0:20e0c61e0684 1305 \details Disables a device specific interrupt in the NVIC interrupt controller.
ganlikun 0:20e0c61e0684 1306 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1307 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1308 */
ganlikun 0:20e0c61e0684 1309 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1310 {
ganlikun 0:20e0c61e0684 1311 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1312 {
ganlikun 0:20e0c61e0684 1313 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1314 __DSB();
ganlikun 0:20e0c61e0684 1315 __ISB();
ganlikun 0:20e0c61e0684 1316 }
ganlikun 0:20e0c61e0684 1317 }
ganlikun 0:20e0c61e0684 1318
ganlikun 0:20e0c61e0684 1319
ganlikun 0:20e0c61e0684 1320 /**
ganlikun 0:20e0c61e0684 1321 \brief Get Pending Interrupt
ganlikun 0:20e0c61e0684 1322 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
ganlikun 0:20e0c61e0684 1323 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1324 \return 0 Interrupt status is not pending.
ganlikun 0:20e0c61e0684 1325 \return 1 Interrupt status is pending.
ganlikun 0:20e0c61e0684 1326 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1327 */
ganlikun 0:20e0c61e0684 1328 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1329 {
ganlikun 0:20e0c61e0684 1330 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1331 {
ganlikun 0:20e0c61e0684 1332 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1333 }
ganlikun 0:20e0c61e0684 1334 else
ganlikun 0:20e0c61e0684 1335 {
ganlikun 0:20e0c61e0684 1336 return(0U);
ganlikun 0:20e0c61e0684 1337 }
ganlikun 0:20e0c61e0684 1338 }
ganlikun 0:20e0c61e0684 1339
ganlikun 0:20e0c61e0684 1340
ganlikun 0:20e0c61e0684 1341 /**
ganlikun 0:20e0c61e0684 1342 \brief Set Pending Interrupt
ganlikun 0:20e0c61e0684 1343 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:20e0c61e0684 1344 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1345 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1346 */
ganlikun 0:20e0c61e0684 1347 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1348 {
ganlikun 0:20e0c61e0684 1349 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1350 {
ganlikun 0:20e0c61e0684 1351 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1352 }
ganlikun 0:20e0c61e0684 1353 }
ganlikun 0:20e0c61e0684 1354
ganlikun 0:20e0c61e0684 1355
ganlikun 0:20e0c61e0684 1356 /**
ganlikun 0:20e0c61e0684 1357 \brief Clear Pending Interrupt
ganlikun 0:20e0c61e0684 1358 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
ganlikun 0:20e0c61e0684 1359 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1360 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1361 */
ganlikun 0:20e0c61e0684 1362 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1363 {
ganlikun 0:20e0c61e0684 1364 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1365 {
ganlikun 0:20e0c61e0684 1366 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1367 }
ganlikun 0:20e0c61e0684 1368 }
ganlikun 0:20e0c61e0684 1369
ganlikun 0:20e0c61e0684 1370
ganlikun 0:20e0c61e0684 1371 /**
ganlikun 0:20e0c61e0684 1372 \brief Get Active Interrupt
ganlikun 0:20e0c61e0684 1373 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
ganlikun 0:20e0c61e0684 1374 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1375 \return 0 Interrupt status is not active.
ganlikun 0:20e0c61e0684 1376 \return 1 Interrupt status is active.
ganlikun 0:20e0c61e0684 1377 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1378 */
ganlikun 0:20e0c61e0684 1379 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1380 {
ganlikun 0:20e0c61e0684 1381 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1382 {
ganlikun 0:20e0c61e0684 1383 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1384 }
ganlikun 0:20e0c61e0684 1385 else
ganlikun 0:20e0c61e0684 1386 {
ganlikun 0:20e0c61e0684 1387 return(0U);
ganlikun 0:20e0c61e0684 1388 }
ganlikun 0:20e0c61e0684 1389 }
ganlikun 0:20e0c61e0684 1390
ganlikun 0:20e0c61e0684 1391
ganlikun 0:20e0c61e0684 1392 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:20e0c61e0684 1393 /**
ganlikun 0:20e0c61e0684 1394 \brief Get Interrupt Target State
ganlikun 0:20e0c61e0684 1395 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
ganlikun 0:20e0c61e0684 1396 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1397 \return 0 if interrupt is assigned to Secure
ganlikun 0:20e0c61e0684 1398 \return 1 if interrupt is assigned to Non Secure
ganlikun 0:20e0c61e0684 1399 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1400 */
ganlikun 0:20e0c61e0684 1401 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1402 {
ganlikun 0:20e0c61e0684 1403 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1404 {
ganlikun 0:20e0c61e0684 1405 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1406 }
ganlikun 0:20e0c61e0684 1407 else
ganlikun 0:20e0c61e0684 1408 {
ganlikun 0:20e0c61e0684 1409 return(0U);
ganlikun 0:20e0c61e0684 1410 }
ganlikun 0:20e0c61e0684 1411 }
ganlikun 0:20e0c61e0684 1412
ganlikun 0:20e0c61e0684 1413
ganlikun 0:20e0c61e0684 1414 /**
ganlikun 0:20e0c61e0684 1415 \brief Set Interrupt Target State
ganlikun 0:20e0c61e0684 1416 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
ganlikun 0:20e0c61e0684 1417 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1418 \return 0 if interrupt is assigned to Secure
ganlikun 0:20e0c61e0684 1419 1 if interrupt is assigned to Non Secure
ganlikun 0:20e0c61e0684 1420 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1421 */
ganlikun 0:20e0c61e0684 1422 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1423 {
ganlikun 0:20e0c61e0684 1424 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1425 {
ganlikun 0:20e0c61e0684 1426 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
ganlikun 0:20e0c61e0684 1427 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1428 }
ganlikun 0:20e0c61e0684 1429 else
ganlikun 0:20e0c61e0684 1430 {
ganlikun 0:20e0c61e0684 1431 return(0U);
ganlikun 0:20e0c61e0684 1432 }
ganlikun 0:20e0c61e0684 1433 }
ganlikun 0:20e0c61e0684 1434
ganlikun 0:20e0c61e0684 1435
ganlikun 0:20e0c61e0684 1436 /**
ganlikun 0:20e0c61e0684 1437 \brief Clear Interrupt Target State
ganlikun 0:20e0c61e0684 1438 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
ganlikun 0:20e0c61e0684 1439 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1440 \return 0 if interrupt is assigned to Secure
ganlikun 0:20e0c61e0684 1441 1 if interrupt is assigned to Non Secure
ganlikun 0:20e0c61e0684 1442 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1443 */
ganlikun 0:20e0c61e0684 1444 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1445 {
ganlikun 0:20e0c61e0684 1446 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1447 {
ganlikun 0:20e0c61e0684 1448 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
ganlikun 0:20e0c61e0684 1449 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1450 }
ganlikun 0:20e0c61e0684 1451 else
ganlikun 0:20e0c61e0684 1452 {
ganlikun 0:20e0c61e0684 1453 return(0U);
ganlikun 0:20e0c61e0684 1454 }
ganlikun 0:20e0c61e0684 1455 }
ganlikun 0:20e0c61e0684 1456 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:20e0c61e0684 1457
ganlikun 0:20e0c61e0684 1458
ganlikun 0:20e0c61e0684 1459 /**
ganlikun 0:20e0c61e0684 1460 \brief Set Interrupt Priority
ganlikun 0:20e0c61e0684 1461 \details Sets the priority of a device specific interrupt or a processor exception.
ganlikun 0:20e0c61e0684 1462 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 1463 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 1464 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 1465 \param [in] priority Priority to set.
ganlikun 0:20e0c61e0684 1466 \note The priority cannot be set for every processor exception.
ganlikun 0:20e0c61e0684 1467 */
ganlikun 0:20e0c61e0684 1468 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ganlikun 0:20e0c61e0684 1469 {
ganlikun 0:20e0c61e0684 1470 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1471 {
ganlikun 0:20e0c61e0684 1472 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:20e0c61e0684 1473 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:20e0c61e0684 1474 }
ganlikun 0:20e0c61e0684 1475 else
ganlikun 0:20e0c61e0684 1476 {
ganlikun 0:20e0c61e0684 1477 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:20e0c61e0684 1478 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:20e0c61e0684 1479 }
ganlikun 0:20e0c61e0684 1480 }
ganlikun 0:20e0c61e0684 1481
ganlikun 0:20e0c61e0684 1482
ganlikun 0:20e0c61e0684 1483 /**
ganlikun 0:20e0c61e0684 1484 \brief Get Interrupt Priority
ganlikun 0:20e0c61e0684 1485 \details Reads the priority of a device specific interrupt or a processor exception.
ganlikun 0:20e0c61e0684 1486 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 1487 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 1488 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 1489 \return Interrupt Priority.
ganlikun 0:20e0c61e0684 1490 Value is aligned automatically to the implemented priority bits of the microcontroller.
ganlikun 0:20e0c61e0684 1491 */
ganlikun 0:20e0c61e0684 1492 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1493 {
ganlikun 0:20e0c61e0684 1494
ganlikun 0:20e0c61e0684 1495 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1496 {
ganlikun 0:20e0c61e0684 1497 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:20e0c61e0684 1498 }
ganlikun 0:20e0c61e0684 1499 else
ganlikun 0:20e0c61e0684 1500 {
ganlikun 0:20e0c61e0684 1501 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:20e0c61e0684 1502 }
ganlikun 0:20e0c61e0684 1503 }
ganlikun 0:20e0c61e0684 1504
ganlikun 0:20e0c61e0684 1505
ganlikun 0:20e0c61e0684 1506 /**
ganlikun 0:20e0c61e0684 1507 \brief Set Interrupt Vector
ganlikun 0:20e0c61e0684 1508 \details Sets an interrupt vector in SRAM based interrupt vector table.
ganlikun 0:20e0c61e0684 1509 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 1510 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 1511 VTOR must been relocated to SRAM before.
ganlikun 0:20e0c61e0684 1512 If VTOR is not present address 0 must be mapped to SRAM.
ganlikun 0:20e0c61e0684 1513 \param [in] IRQn Interrupt number
ganlikun 0:20e0c61e0684 1514 \param [in] vector Address of interrupt handler function
ganlikun 0:20e0c61e0684 1515 */
ganlikun 0:20e0c61e0684 1516 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
ganlikun 0:20e0c61e0684 1517 {
ganlikun 0:20e0c61e0684 1518 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:20e0c61e0684 1519 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:20e0c61e0684 1520 #else
ganlikun 0:20e0c61e0684 1521 uint32_t *vectors = (uint32_t *)0x0U;
ganlikun 0:20e0c61e0684 1522 #endif
ganlikun 0:20e0c61e0684 1523 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
ganlikun 0:20e0c61e0684 1524 }
ganlikun 0:20e0c61e0684 1525
ganlikun 0:20e0c61e0684 1526
ganlikun 0:20e0c61e0684 1527 /**
ganlikun 0:20e0c61e0684 1528 \brief Get Interrupt Vector
ganlikun 0:20e0c61e0684 1529 \details Reads an interrupt vector from interrupt vector table.
ganlikun 0:20e0c61e0684 1530 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 1531 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 1532 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 1533 \return Address of interrupt handler function
ganlikun 0:20e0c61e0684 1534 */
ganlikun 0:20e0c61e0684 1535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1536 {
ganlikun 0:20e0c61e0684 1537 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
ganlikun 0:20e0c61e0684 1538 uint32_t *vectors = (uint32_t *)SCB->VTOR;
ganlikun 0:20e0c61e0684 1539 #else
ganlikun 0:20e0c61e0684 1540 uint32_t *vectors = (uint32_t *)0x0U;
ganlikun 0:20e0c61e0684 1541 #endif
ganlikun 0:20e0c61e0684 1542 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
ganlikun 0:20e0c61e0684 1543 }
ganlikun 0:20e0c61e0684 1544
ganlikun 0:20e0c61e0684 1545
ganlikun 0:20e0c61e0684 1546 /**
ganlikun 0:20e0c61e0684 1547 \brief System Reset
ganlikun 0:20e0c61e0684 1548 \details Initiates a system reset request to reset the MCU.
ganlikun 0:20e0c61e0684 1549 */
ganlikun 0:20e0c61e0684 1550 __STATIC_INLINE void __NVIC_SystemReset(void)
ganlikun 0:20e0c61e0684 1551 {
ganlikun 0:20e0c61e0684 1552 __DSB(); /* Ensure all outstanding memory accesses included
ganlikun 0:20e0c61e0684 1553 buffered write are completed before reset */
ganlikun 0:20e0c61e0684 1554 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
ganlikun 0:20e0c61e0684 1555 SCB_AIRCR_SYSRESETREQ_Msk);
ganlikun 0:20e0c61e0684 1556 __DSB(); /* Ensure completion of memory access */
ganlikun 0:20e0c61e0684 1557
ganlikun 0:20e0c61e0684 1558 for(;;) /* wait until reset */
ganlikun 0:20e0c61e0684 1559 {
ganlikun 0:20e0c61e0684 1560 __NOP();
ganlikun 0:20e0c61e0684 1561 }
ganlikun 0:20e0c61e0684 1562 }
ganlikun 0:20e0c61e0684 1563
ganlikun 0:20e0c61e0684 1564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:20e0c61e0684 1565 /**
ganlikun 0:20e0c61e0684 1566 \brief Enable Interrupt (non-secure)
ganlikun 0:20e0c61e0684 1567 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
ganlikun 0:20e0c61e0684 1568 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1569 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1570 */
ganlikun 0:20e0c61e0684 1571 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1572 {
ganlikun 0:20e0c61e0684 1573 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1574 {
ganlikun 0:20e0c61e0684 1575 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1576 }
ganlikun 0:20e0c61e0684 1577 }
ganlikun 0:20e0c61e0684 1578
ganlikun 0:20e0c61e0684 1579
ganlikun 0:20e0c61e0684 1580 /**
ganlikun 0:20e0c61e0684 1581 \brief Get Interrupt Enable status (non-secure)
ganlikun 0:20e0c61e0684 1582 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
ganlikun 0:20e0c61e0684 1583 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1584 \return 0 Interrupt is not enabled.
ganlikun 0:20e0c61e0684 1585 \return 1 Interrupt is enabled.
ganlikun 0:20e0c61e0684 1586 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1587 */
ganlikun 0:20e0c61e0684 1588 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1589 {
ganlikun 0:20e0c61e0684 1590 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1591 {
ganlikun 0:20e0c61e0684 1592 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1593 }
ganlikun 0:20e0c61e0684 1594 else
ganlikun 0:20e0c61e0684 1595 {
ganlikun 0:20e0c61e0684 1596 return(0U);
ganlikun 0:20e0c61e0684 1597 }
ganlikun 0:20e0c61e0684 1598 }
ganlikun 0:20e0c61e0684 1599
ganlikun 0:20e0c61e0684 1600
ganlikun 0:20e0c61e0684 1601 /**
ganlikun 0:20e0c61e0684 1602 \brief Disable Interrupt (non-secure)
ganlikun 0:20e0c61e0684 1603 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
ganlikun 0:20e0c61e0684 1604 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1605 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1606 */
ganlikun 0:20e0c61e0684 1607 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1608 {
ganlikun 0:20e0c61e0684 1609 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1610 {
ganlikun 0:20e0c61e0684 1611 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1612 }
ganlikun 0:20e0c61e0684 1613 }
ganlikun 0:20e0c61e0684 1614
ganlikun 0:20e0c61e0684 1615
ganlikun 0:20e0c61e0684 1616 /**
ganlikun 0:20e0c61e0684 1617 \brief Get Pending Interrupt (non-secure)
ganlikun 0:20e0c61e0684 1618 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
ganlikun 0:20e0c61e0684 1619 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1620 \return 0 Interrupt status is not pending.
ganlikun 0:20e0c61e0684 1621 \return 1 Interrupt status is pending.
ganlikun 0:20e0c61e0684 1622 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1623 */
ganlikun 0:20e0c61e0684 1624 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1625 {
ganlikun 0:20e0c61e0684 1626 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1627 {
ganlikun 0:20e0c61e0684 1628 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1629 }
ganlikun 0:20e0c61e0684 1630 }
ganlikun 0:20e0c61e0684 1631
ganlikun 0:20e0c61e0684 1632
ganlikun 0:20e0c61e0684 1633 /**
ganlikun 0:20e0c61e0684 1634 \brief Set Pending Interrupt (non-secure)
ganlikun 0:20e0c61e0684 1635 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
ganlikun 0:20e0c61e0684 1636 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1637 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1638 */
ganlikun 0:20e0c61e0684 1639 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1640 {
ganlikun 0:20e0c61e0684 1641 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1642 {
ganlikun 0:20e0c61e0684 1643 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1644 }
ganlikun 0:20e0c61e0684 1645 }
ganlikun 0:20e0c61e0684 1646
ganlikun 0:20e0c61e0684 1647
ganlikun 0:20e0c61e0684 1648 /**
ganlikun 0:20e0c61e0684 1649 \brief Clear Pending Interrupt (non-secure)
ganlikun 0:20e0c61e0684 1650 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
ganlikun 0:20e0c61e0684 1651 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1652 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1653 */
ganlikun 0:20e0c61e0684 1654 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1655 {
ganlikun 0:20e0c61e0684 1656 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1657 {
ganlikun 0:20e0c61e0684 1658 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
ganlikun 0:20e0c61e0684 1659 }
ganlikun 0:20e0c61e0684 1660 }
ganlikun 0:20e0c61e0684 1661
ganlikun 0:20e0c61e0684 1662
ganlikun 0:20e0c61e0684 1663 /**
ganlikun 0:20e0c61e0684 1664 \brief Get Active Interrupt (non-secure)
ganlikun 0:20e0c61e0684 1665 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
ganlikun 0:20e0c61e0684 1666 \param [in] IRQn Device specific interrupt number.
ganlikun 0:20e0c61e0684 1667 \return 0 Interrupt status is not active.
ganlikun 0:20e0c61e0684 1668 \return 1 Interrupt status is active.
ganlikun 0:20e0c61e0684 1669 \note IRQn must not be negative.
ganlikun 0:20e0c61e0684 1670 */
ganlikun 0:20e0c61e0684 1671 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1672 {
ganlikun 0:20e0c61e0684 1673 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1674 {
ganlikun 0:20e0c61e0684 1675 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
ganlikun 0:20e0c61e0684 1676 }
ganlikun 0:20e0c61e0684 1677 else
ganlikun 0:20e0c61e0684 1678 {
ganlikun 0:20e0c61e0684 1679 return(0U);
ganlikun 0:20e0c61e0684 1680 }
ganlikun 0:20e0c61e0684 1681 }
ganlikun 0:20e0c61e0684 1682
ganlikun 0:20e0c61e0684 1683
ganlikun 0:20e0c61e0684 1684 /**
ganlikun 0:20e0c61e0684 1685 \brief Set Interrupt Priority (non-secure)
ganlikun 0:20e0c61e0684 1686 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
ganlikun 0:20e0c61e0684 1687 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 1688 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 1689 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 1690 \param [in] priority Priority to set.
ganlikun 0:20e0c61e0684 1691 \note The priority cannot be set for every non-secure processor exception.
ganlikun 0:20e0c61e0684 1692 */
ganlikun 0:20e0c61e0684 1693 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
ganlikun 0:20e0c61e0684 1694 {
ganlikun 0:20e0c61e0684 1695 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1696 {
ganlikun 0:20e0c61e0684 1697 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:20e0c61e0684 1698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:20e0c61e0684 1699 }
ganlikun 0:20e0c61e0684 1700 else
ganlikun 0:20e0c61e0684 1701 {
ganlikun 0:20e0c61e0684 1702 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
ganlikun 0:20e0c61e0684 1703 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ganlikun 0:20e0c61e0684 1704 }
ganlikun 0:20e0c61e0684 1705 }
ganlikun 0:20e0c61e0684 1706
ganlikun 0:20e0c61e0684 1707
ganlikun 0:20e0c61e0684 1708 /**
ganlikun 0:20e0c61e0684 1709 \brief Get Interrupt Priority (non-secure)
ganlikun 0:20e0c61e0684 1710 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
ganlikun 0:20e0c61e0684 1711 The interrupt number can be positive to specify a device specific interrupt,
ganlikun 0:20e0c61e0684 1712 or negative to specify a processor exception.
ganlikun 0:20e0c61e0684 1713 \param [in] IRQn Interrupt number.
ganlikun 0:20e0c61e0684 1714 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
ganlikun 0:20e0c61e0684 1715 */
ganlikun 0:20e0c61e0684 1716 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 1717 {
ganlikun 0:20e0c61e0684 1718
ganlikun 0:20e0c61e0684 1719 if ((int32_t)(IRQn) >= 0)
ganlikun 0:20e0c61e0684 1720 {
ganlikun 0:20e0c61e0684 1721 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:20e0c61e0684 1722 }
ganlikun 0:20e0c61e0684 1723 else
ganlikun 0:20e0c61e0684 1724 {
ganlikun 0:20e0c61e0684 1725 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
ganlikun 0:20e0c61e0684 1726 }
ganlikun 0:20e0c61e0684 1727 }
ganlikun 0:20e0c61e0684 1728 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:20e0c61e0684 1729
ganlikun 0:20e0c61e0684 1730 /*@} end of CMSIS_Core_NVICFunctions */
ganlikun 0:20e0c61e0684 1731
ganlikun 0:20e0c61e0684 1732
ganlikun 0:20e0c61e0684 1733 /* ########################## FPU functions #################################### */
ganlikun 0:20e0c61e0684 1734 /**
ganlikun 0:20e0c61e0684 1735 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:20e0c61e0684 1736 \defgroup CMSIS_Core_FpuFunctions FPU Functions
ganlikun 0:20e0c61e0684 1737 \brief Function that provides FPU type.
ganlikun 0:20e0c61e0684 1738 @{
ganlikun 0:20e0c61e0684 1739 */
ganlikun 0:20e0c61e0684 1740
ganlikun 0:20e0c61e0684 1741 /**
ganlikun 0:20e0c61e0684 1742 \brief get FPU type
ganlikun 0:20e0c61e0684 1743 \details returns the FPU type
ganlikun 0:20e0c61e0684 1744 \returns
ganlikun 0:20e0c61e0684 1745 - \b 0: No FPU
ganlikun 0:20e0c61e0684 1746 - \b 1: Single precision FPU
ganlikun 0:20e0c61e0684 1747 - \b 2: Double + Single precision FPU
ganlikun 0:20e0c61e0684 1748 */
ganlikun 0:20e0c61e0684 1749 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
ganlikun 0:20e0c61e0684 1750 {
ganlikun 0:20e0c61e0684 1751 return 0U; /* No FPU */
ganlikun 0:20e0c61e0684 1752 }
ganlikun 0:20e0c61e0684 1753
ganlikun 0:20e0c61e0684 1754
ganlikun 0:20e0c61e0684 1755 /*@} end of CMSIS_Core_FpuFunctions */
ganlikun 0:20e0c61e0684 1756
ganlikun 0:20e0c61e0684 1757
ganlikun 0:20e0c61e0684 1758
ganlikun 0:20e0c61e0684 1759 /* ########################## SAU functions #################################### */
ganlikun 0:20e0c61e0684 1760 /**
ganlikun 0:20e0c61e0684 1761 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:20e0c61e0684 1762 \defgroup CMSIS_Core_SAUFunctions SAU Functions
ganlikun 0:20e0c61e0684 1763 \brief Functions that configure the SAU.
ganlikun 0:20e0c61e0684 1764 @{
ganlikun 0:20e0c61e0684 1765 */
ganlikun 0:20e0c61e0684 1766
ganlikun 0:20e0c61e0684 1767 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:20e0c61e0684 1768
ganlikun 0:20e0c61e0684 1769 /**
ganlikun 0:20e0c61e0684 1770 \brief Enable SAU
ganlikun 0:20e0c61e0684 1771 \details Enables the Security Attribution Unit (SAU).
ganlikun 0:20e0c61e0684 1772 */
ganlikun 0:20e0c61e0684 1773 __STATIC_INLINE void TZ_SAU_Enable(void)
ganlikun 0:20e0c61e0684 1774 {
ganlikun 0:20e0c61e0684 1775 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
ganlikun 0:20e0c61e0684 1776 }
ganlikun 0:20e0c61e0684 1777
ganlikun 0:20e0c61e0684 1778
ganlikun 0:20e0c61e0684 1779
ganlikun 0:20e0c61e0684 1780 /**
ganlikun 0:20e0c61e0684 1781 \brief Disable SAU
ganlikun 0:20e0c61e0684 1782 \details Disables the Security Attribution Unit (SAU).
ganlikun 0:20e0c61e0684 1783 */
ganlikun 0:20e0c61e0684 1784 __STATIC_INLINE void TZ_SAU_Disable(void)
ganlikun 0:20e0c61e0684 1785 {
ganlikun 0:20e0c61e0684 1786 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
ganlikun 0:20e0c61e0684 1787 }
ganlikun 0:20e0c61e0684 1788
ganlikun 0:20e0c61e0684 1789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:20e0c61e0684 1790
ganlikun 0:20e0c61e0684 1791 /*@} end of CMSIS_Core_SAUFunctions */
ganlikun 0:20e0c61e0684 1792
ganlikun 0:20e0c61e0684 1793
ganlikun 0:20e0c61e0684 1794
ganlikun 0:20e0c61e0684 1795
ganlikun 0:20e0c61e0684 1796 /* ################################## SysTick function ############################################ */
ganlikun 0:20e0c61e0684 1797 /**
ganlikun 0:20e0c61e0684 1798 \ingroup CMSIS_Core_FunctionInterface
ganlikun 0:20e0c61e0684 1799 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
ganlikun 0:20e0c61e0684 1800 \brief Functions that configure the System.
ganlikun 0:20e0c61e0684 1801 @{
ganlikun 0:20e0c61e0684 1802 */
ganlikun 0:20e0c61e0684 1803
ganlikun 0:20e0c61e0684 1804 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
ganlikun 0:20e0c61e0684 1805
ganlikun 0:20e0c61e0684 1806 /**
ganlikun 0:20e0c61e0684 1807 \brief System Tick Configuration
ganlikun 0:20e0c61e0684 1808 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
ganlikun 0:20e0c61e0684 1809 Counter is in free running mode to generate periodic interrupts.
ganlikun 0:20e0c61e0684 1810 \param [in] ticks Number of ticks between two interrupts.
ganlikun 0:20e0c61e0684 1811 \return 0 Function succeeded.
ganlikun 0:20e0c61e0684 1812 \return 1 Function failed.
ganlikun 0:20e0c61e0684 1813 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ganlikun 0:20e0c61e0684 1814 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
ganlikun 0:20e0c61e0684 1815 must contain a vendor-specific implementation of this function.
ganlikun 0:20e0c61e0684 1816 */
ganlikun 0:20e0c61e0684 1817 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ganlikun 0:20e0c61e0684 1818 {
ganlikun 0:20e0c61e0684 1819 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
ganlikun 0:20e0c61e0684 1820 {
ganlikun 0:20e0c61e0684 1821 return (1UL); /* Reload value impossible */
ganlikun 0:20e0c61e0684 1822 }
ganlikun 0:20e0c61e0684 1823
ganlikun 0:20e0c61e0684 1824 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
ganlikun 0:20e0c61e0684 1825 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
ganlikun 0:20e0c61e0684 1826 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
ganlikun 0:20e0c61e0684 1827 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
ganlikun 0:20e0c61e0684 1828 SysTick_CTRL_TICKINT_Msk |
ganlikun 0:20e0c61e0684 1829 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ganlikun 0:20e0c61e0684 1830 return (0UL); /* Function successful */
ganlikun 0:20e0c61e0684 1831 }
ganlikun 0:20e0c61e0684 1832
ganlikun 0:20e0c61e0684 1833 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
ganlikun 0:20e0c61e0684 1834 /**
ganlikun 0:20e0c61e0684 1835 \brief System Tick Configuration (non-secure)
ganlikun 0:20e0c61e0684 1836 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
ganlikun 0:20e0c61e0684 1837 Counter is in free running mode to generate periodic interrupts.
ganlikun 0:20e0c61e0684 1838 \param [in] ticks Number of ticks between two interrupts.
ganlikun 0:20e0c61e0684 1839 \return 0 Function succeeded.
ganlikun 0:20e0c61e0684 1840 \return 1 Function failed.
ganlikun 0:20e0c61e0684 1841 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ganlikun 0:20e0c61e0684 1842 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
ganlikun 0:20e0c61e0684 1843 must contain a vendor-specific implementation of this function.
ganlikun 0:20e0c61e0684 1844
ganlikun 0:20e0c61e0684 1845 */
ganlikun 0:20e0c61e0684 1846 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
ganlikun 0:20e0c61e0684 1847 {
ganlikun 0:20e0c61e0684 1848 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
ganlikun 0:20e0c61e0684 1849 {
ganlikun 0:20e0c61e0684 1850 return (1UL); /* Reload value impossible */
ganlikun 0:20e0c61e0684 1851 }
ganlikun 0:20e0c61e0684 1852
ganlikun 0:20e0c61e0684 1853 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
ganlikun 0:20e0c61e0684 1854 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
ganlikun 0:20e0c61e0684 1855 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
ganlikun 0:20e0c61e0684 1856 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
ganlikun 0:20e0c61e0684 1857 SysTick_CTRL_TICKINT_Msk |
ganlikun 0:20e0c61e0684 1858 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ganlikun 0:20e0c61e0684 1859 return (0UL); /* Function successful */
ganlikun 0:20e0c61e0684 1860 }
ganlikun 0:20e0c61e0684 1861 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
ganlikun 0:20e0c61e0684 1862
ganlikun 0:20e0c61e0684 1863 #endif
ganlikun 0:20e0c61e0684 1864
ganlikun 0:20e0c61e0684 1865 /*@} end of CMSIS_Core_SysTickFunctions */
ganlikun 0:20e0c61e0684 1866
ganlikun 0:20e0c61e0684 1867
ganlikun 0:20e0c61e0684 1868
ganlikun 0:20e0c61e0684 1869
ganlikun 0:20e0c61e0684 1870 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 1871 }
ganlikun 0:20e0c61e0684 1872 #endif
ganlikun 0:20e0c61e0684 1873
ganlikun 0:20e0c61e0684 1874 #endif /* __CORE_CM23_H_DEPENDANT */
ganlikun 0:20e0c61e0684 1875
ganlikun 0:20e0c61e0684 1876 #endif /* __CMSIS_GENERIC */
ganlikun 0:20e0c61e0684 1877