Gan likun / The prosthetic control

The prosthetic control（MIT）

cmsis/core_ca.h@0:20e0c61e0684, 2022-06-23 (annotated)

Committer:
ganlikun
Date:
Thu Jun 23 05:23:34 2022 +0000
Revision:
0:20e0c61e0684
01

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ganlikun 0:20e0c61e0684 1 /**************************************************************************//**
ganlikun 0:20e0c61e0684 2 * @file core_ca.h
ganlikun 0:20e0c61e0684 3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
ganlikun 0:20e0c61e0684 4 * @version V1.00
ganlikun 0:20e0c61e0684 5 * @date 22. Feb 2017
ganlikun 0:20e0c61e0684 6 ******************************************************************************/
ganlikun 0:20e0c61e0684 7 /*
ganlikun 0:20e0c61e0684 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
ganlikun 0:20e0c61e0684 9 *
ganlikun 0:20e0c61e0684 10 * SPDX-License-Identifier: Apache-2.0
ganlikun 0:20e0c61e0684 11 *
ganlikun 0:20e0c61e0684 12 * Licensed under the Apache License, Version 2.0 (the License); you may
ganlikun 0:20e0c61e0684 13 * not use this file except in compliance with the License.
ganlikun 0:20e0c61e0684 14 * You may obtain a copy of the License at
ganlikun 0:20e0c61e0684 15 *
ganlikun 0:20e0c61e0684 16 * www.apache.org/licenses/LICENSE-2.0
ganlikun 0:20e0c61e0684 17 *
ganlikun 0:20e0c61e0684 18 * Unless required by applicable law or agreed to in writing, software
ganlikun 0:20e0c61e0684 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ganlikun 0:20e0c61e0684 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ganlikun 0:20e0c61e0684 21 * See the License for the specific language governing permissions and
ganlikun 0:20e0c61e0684 22 * limitations under the License.
ganlikun 0:20e0c61e0684 23 */
ganlikun 0:20e0c61e0684 24
ganlikun 0:20e0c61e0684 25 #if defined ( __ICCARM__ )
ganlikun 0:20e0c61e0684 26 #pragma system_include /* treat file as system include file for MISRA check */
ganlikun 0:20e0c61e0684 27 #endif
ganlikun 0:20e0c61e0684 28
ganlikun 0:20e0c61e0684 29 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 30 extern "C" {
ganlikun 0:20e0c61e0684 31 #endif
ganlikun 0:20e0c61e0684 32
ganlikun 0:20e0c61e0684 33 #ifndef __CORE_CA_H_GENERIC
ganlikun 0:20e0c61e0684 34 #define __CORE_CA_H_GENERIC
ganlikun 0:20e0c61e0684 35
ganlikun 0:20e0c61e0684 36
ganlikun 0:20e0c61e0684 37 /*******************************************************************************
ganlikun 0:20e0c61e0684 38 * CMSIS definitions
ganlikun 0:20e0c61e0684 39 ******************************************************************************/
ganlikun 0:20e0c61e0684 40
ganlikun 0:20e0c61e0684 41 /* CMSIS CA definitions */
ganlikun 0:20e0c61e0684 42 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS HAL main version */
ganlikun 0:20e0c61e0684 43 #define __CA_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS HAL sub version */
ganlikun 0:20e0c61e0684 44 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
ganlikun 0:20e0c61e0684 45 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS HAL version number */
ganlikun 0:20e0c61e0684 46
ganlikun 0:20e0c61e0684 47 #if defined ( __CC_ARM )
ganlikun 0:20e0c61e0684 48 #if defined __TARGET_FPU_VFP
ganlikun 0:20e0c61e0684 49 #if (__FPU_PRESENT == 1)
ganlikun 0:20e0c61e0684 50 #define __FPU_USED 1U
ganlikun 0:20e0c61e0684 51 #else
ganlikun 0:20e0c61e0684 52 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 53 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 54 #endif
ganlikun 0:20e0c61e0684 55 #else
ganlikun 0:20e0c61e0684 56 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 57 #endif
ganlikun 0:20e0c61e0684 58
ganlikun 0:20e0c61e0684 59 #elif defined ( __ICCARM__ )
ganlikun 0:20e0c61e0684 60 #if defined __ARMVFP__
ganlikun 0:20e0c61e0684 61 #if (__FPU_PRESENT == 1)
ganlikun 0:20e0c61e0684 62 #define __FPU_USED 1U
ganlikun 0:20e0c61e0684 63 #else
ganlikun 0:20e0c61e0684 64 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 65 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 66 #endif
ganlikun 0:20e0c61e0684 67 #else
ganlikun 0:20e0c61e0684 68 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 69 #endif
ganlikun 0:20e0c61e0684 70
ganlikun 0:20e0c61e0684 71 #elif defined ( __TMS470__ )
ganlikun 0:20e0c61e0684 72 #if defined __TI_VFP_SUPPORT__
ganlikun 0:20e0c61e0684 73 #if (__FPU_PRESENT == 1)
ganlikun 0:20e0c61e0684 74 #define __FPU_USED 1U
ganlikun 0:20e0c61e0684 75 #else
ganlikun 0:20e0c61e0684 76 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 77 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 78 #endif
ganlikun 0:20e0c61e0684 79 #else
ganlikun 0:20e0c61e0684 80 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 81 #endif
ganlikun 0:20e0c61e0684 82
ganlikun 0:20e0c61e0684 83 #elif defined ( __GNUC__ )
ganlikun 0:20e0c61e0684 84 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
ganlikun 0:20e0c61e0684 85 #if (__FPU_PRESENT == 1)
ganlikun 0:20e0c61e0684 86 #define __FPU_USED 1U
ganlikun 0:20e0c61e0684 87 #else
ganlikun 0:20e0c61e0684 88 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 89 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 90 #endif
ganlikun 0:20e0c61e0684 91 #else
ganlikun 0:20e0c61e0684 92 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 93 #endif
ganlikun 0:20e0c61e0684 94
ganlikun 0:20e0c61e0684 95 #elif defined ( __TASKING__ )
ganlikun 0:20e0c61e0684 96 #if defined __FPU_VFP__
ganlikun 0:20e0c61e0684 97 #if (__FPU_PRESENT == 1)
ganlikun 0:20e0c61e0684 98 #define __FPU_USED 1U
ganlikun 0:20e0c61e0684 99 #else
ganlikun 0:20e0c61e0684 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ganlikun 0:20e0c61e0684 101 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 102 #endif
ganlikun 0:20e0c61e0684 103 #else
ganlikun 0:20e0c61e0684 104 #define __FPU_USED 0U
ganlikun 0:20e0c61e0684 105 #endif
ganlikun 0:20e0c61e0684 106 #endif
ganlikun 0:20e0c61e0684 107
ganlikun 0:20e0c61e0684 108 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
ganlikun 0:20e0c61e0684 109
ganlikun 0:20e0c61e0684 110 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 111 }
ganlikun 0:20e0c61e0684 112 #endif
ganlikun 0:20e0c61e0684 113
ganlikun 0:20e0c61e0684 114 #endif /* __CORE_CA_H_GENERIC */
ganlikun 0:20e0c61e0684 115
ganlikun 0:20e0c61e0684 116 #ifndef __CMSIS_GENERIC
ganlikun 0:20e0c61e0684 117
ganlikun 0:20e0c61e0684 118 #ifndef __CORE_CA_H_DEPENDANT
ganlikun 0:20e0c61e0684 119 #define __CORE_CA_H_DEPENDANT
ganlikun 0:20e0c61e0684 120
ganlikun 0:20e0c61e0684 121 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 122 extern "C" {
ganlikun 0:20e0c61e0684 123 #endif
ganlikun 0:20e0c61e0684 124
ganlikun 0:20e0c61e0684 125 /* check device defines and use defaults */
ganlikun 0:20e0c61e0684 126 #if defined __CHECK_DEVICE_DEFINES
ganlikun 0:20e0c61e0684 127 #ifndef __CA_REV
ganlikun 0:20e0c61e0684 128 #define __CA_REV 0x0000U
ganlikun 0:20e0c61e0684 129 #warning "__CA_REV not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 130 #endif
ganlikun 0:20e0c61e0684 131
ganlikun 0:20e0c61e0684 132 #ifndef __FPU_PRESENT
ganlikun 0:20e0c61e0684 133 #define __FPU_PRESENT 0U
ganlikun 0:20e0c61e0684 134 #warning "__FPU_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 135 #endif
ganlikun 0:20e0c61e0684 136
ganlikun 0:20e0c61e0684 137 #ifndef __MPU_PRESENT
ganlikun 0:20e0c61e0684 138 #define __MPU_PRESENT 0U
ganlikun 0:20e0c61e0684 139 #warning "__MPU_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 140 #endif
ganlikun 0:20e0c61e0684 141
ganlikun 0:20e0c61e0684 142 #ifndef __GIC_PRESENT
ganlikun 0:20e0c61e0684 143 #define __GIC_PRESENT 1U
ganlikun 0:20e0c61e0684 144 #warning "__GIC_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 145 #endif
ganlikun 0:20e0c61e0684 146
ganlikun 0:20e0c61e0684 147 #ifndef __TIM_PRESENT
ganlikun 0:20e0c61e0684 148 #define __TIM_PRESENT 1U
ganlikun 0:20e0c61e0684 149 #warning "__TIM_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 150 #endif
ganlikun 0:20e0c61e0684 151
ganlikun 0:20e0c61e0684 152 #ifndef __L2C_PRESENT
ganlikun 0:20e0c61e0684 153 #define __L2C_PRESENT 0U
ganlikun 0:20e0c61e0684 154 #warning "__L2C_PRESENT not defined in device header file; using default!"
ganlikun 0:20e0c61e0684 155 #endif
ganlikun 0:20e0c61e0684 156 #endif
ganlikun 0:20e0c61e0684 157
ganlikun 0:20e0c61e0684 158 /* IO definitions (access restrictions to peripheral registers) */
ganlikun 0:20e0c61e0684 159 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 160 #define __I volatile /*!< \brief Defines 'read only' permissions */
ganlikun 0:20e0c61e0684 161 #else
ganlikun 0:20e0c61e0684 162 #define __I volatile const /*!< \brief Defines 'read only' permissions */
ganlikun 0:20e0c61e0684 163 #endif
ganlikun 0:20e0c61e0684 164 #define __O volatile /*!< \brief Defines 'write only' permissions */
ganlikun 0:20e0c61e0684 165 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
ganlikun 0:20e0c61e0684 166
ganlikun 0:20e0c61e0684 167 /* following defines should be used for structure members */
ganlikun 0:20e0c61e0684 168 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
ganlikun 0:20e0c61e0684 169 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
ganlikun 0:20e0c61e0684 170 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
ganlikun 0:20e0c61e0684 171
ganlikun 0:20e0c61e0684 172
ganlikun 0:20e0c61e0684 173 /*******************************************************************************
ganlikun 0:20e0c61e0684 174 * Register Abstraction
ganlikun 0:20e0c61e0684 175 Core Register contain:
ganlikun 0:20e0c61e0684 176 - CPSR
ganlikun 0:20e0c61e0684 177 - CP15 Registers
ganlikun 0:20e0c61e0684 178 - L2C-310 Cache Controller
ganlikun 0:20e0c61e0684 179 - Generic Interrupt Controller Distributor
ganlikun 0:20e0c61e0684 180 - Generic Interrupt Controller Interface
ganlikun 0:20e0c61e0684 181 ******************************************************************************/
ganlikun 0:20e0c61e0684 182
ganlikun 0:20e0c61e0684 183 /* Core Register CPSR */
ganlikun 0:20e0c61e0684 184 typedef union
ganlikun 0:20e0c61e0684 185 {
ganlikun 0:20e0c61e0684 186 struct
ganlikun 0:20e0c61e0684 187 {
ganlikun 0:20e0c61e0684 188 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
ganlikun 0:20e0c61e0684 189 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
ganlikun 0:20e0c61e0684 190 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
ganlikun 0:20e0c61e0684 191 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
ganlikun 0:20e0c61e0684 192 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
ganlikun 0:20e0c61e0684 193 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
ganlikun 0:20e0c61e0684 194 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
ganlikun 0:20e0c61e0684 195 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
ganlikun 0:20e0c61e0684 196 uint32_t _reserved0:4; /*!< \brief bit: 20..23 Reserved */
ganlikun 0:20e0c61e0684 197 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
ganlikun 0:20e0c61e0684 198 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
ganlikun 0:20e0c61e0684 199 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
ganlikun 0:20e0c61e0684 200 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
ganlikun 0:20e0c61e0684 201 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
ganlikun 0:20e0c61e0684 202 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
ganlikun 0:20e0c61e0684 203 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
ganlikun 0:20e0c61e0684 204 } b; /*!< \brief Structure used for bit access */
ganlikun 0:20e0c61e0684 205 uint32_t w; /*!< \brief Type used for word access */
ganlikun 0:20e0c61e0684 206 } CPSR_Type;
ganlikun 0:20e0c61e0684 207
ganlikun 0:20e0c61e0684 208 /* CPSR Register Definitions */
ganlikun 0:20e0c61e0684 209 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
ganlikun 0:20e0c61e0684 210 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
ganlikun 0:20e0c61e0684 211
ganlikun 0:20e0c61e0684 212 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
ganlikun 0:20e0c61e0684 213 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
ganlikun 0:20e0c61e0684 214
ganlikun 0:20e0c61e0684 215 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
ganlikun 0:20e0c61e0684 216 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
ganlikun 0:20e0c61e0684 217
ganlikun 0:20e0c61e0684 218 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
ganlikun 0:20e0c61e0684 219 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
ganlikun 0:20e0c61e0684 220
ganlikun 0:20e0c61e0684 221 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
ganlikun 0:20e0c61e0684 222 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
ganlikun 0:20e0c61e0684 223
ganlikun 0:20e0c61e0684 224 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
ganlikun 0:20e0c61e0684 225 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
ganlikun 0:20e0c61e0684 226
ganlikun 0:20e0c61e0684 227 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
ganlikun 0:20e0c61e0684 228 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
ganlikun 0:20e0c61e0684 229
ganlikun 0:20e0c61e0684 230 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
ganlikun 0:20e0c61e0684 231 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
ganlikun 0:20e0c61e0684 232
ganlikun 0:20e0c61e0684 233 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
ganlikun 0:20e0c61e0684 234 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
ganlikun 0:20e0c61e0684 235
ganlikun 0:20e0c61e0684 236 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
ganlikun 0:20e0c61e0684 237 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
ganlikun 0:20e0c61e0684 238
ganlikun 0:20e0c61e0684 239 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
ganlikun 0:20e0c61e0684 240 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
ganlikun 0:20e0c61e0684 241
ganlikun 0:20e0c61e0684 242 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
ganlikun 0:20e0c61e0684 243 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
ganlikun 0:20e0c61e0684 244
ganlikun 0:20e0c61e0684 245 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
ganlikun 0:20e0c61e0684 246 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
ganlikun 0:20e0c61e0684 247
ganlikun 0:20e0c61e0684 248 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
ganlikun 0:20e0c61e0684 249 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
ganlikun 0:20e0c61e0684 250
ganlikun 0:20e0c61e0684 251 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
ganlikun 0:20e0c61e0684 252 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
ganlikun 0:20e0c61e0684 253
ganlikun 0:20e0c61e0684 254 /* CP15 Register SCTLR */
ganlikun 0:20e0c61e0684 255 typedef union
ganlikun 0:20e0c61e0684 256 {
ganlikun 0:20e0c61e0684 257 struct
ganlikun 0:20e0c61e0684 258 {
ganlikun 0:20e0c61e0684 259 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
ganlikun 0:20e0c61e0684 260 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
ganlikun 0:20e0c61e0684 261 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
ganlikun 0:20e0c61e0684 262 uint32_t _reserved0:2; /*!< \brief bit: 3.. 4 Reserved */
ganlikun 0:20e0c61e0684 263 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
ganlikun 0:20e0c61e0684 264 uint32_t _reserved1:1; /*!< \brief bit: 6 Reserved */
ganlikun 0:20e0c61e0684 265 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
ganlikun 0:20e0c61e0684 266 uint32_t _reserved2:2; /*!< \brief bit: 8.. 9 Reserved */
ganlikun 0:20e0c61e0684 267 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
ganlikun 0:20e0c61e0684 268 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
ganlikun 0:20e0c61e0684 269 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
ganlikun 0:20e0c61e0684 270 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
ganlikun 0:20e0c61e0684 271 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
ganlikun 0:20e0c61e0684 272 uint32_t _reserved3:2; /*!< \brief bit:15..16 Reserved */
ganlikun 0:20e0c61e0684 273 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
ganlikun 0:20e0c61e0684 274 uint32_t _reserved4:1; /*!< \brief bit: 18 Reserved */
ganlikun 0:20e0c61e0684 275 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
ganlikun 0:20e0c61e0684 276 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
ganlikun 0:20e0c61e0684 277 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
ganlikun 0:20e0c61e0684 278 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
ganlikun 0:20e0c61e0684 279 uint32_t _reserved5:1; /*!< \brief bit: 23 Reserved */
ganlikun 0:20e0c61e0684 280 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
ganlikun 0:20e0c61e0684 281 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
ganlikun 0:20e0c61e0684 282 uint32_t _reserved6:1; /*!< \brief bit: 26 Reserved */
ganlikun 0:20e0c61e0684 283 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
ganlikun 0:20e0c61e0684 284 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
ganlikun 0:20e0c61e0684 285 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
ganlikun 0:20e0c61e0684 286 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
ganlikun 0:20e0c61e0684 287 uint32_t _reserved7:1; /*!< \brief bit: 31 Reserved */
ganlikun 0:20e0c61e0684 288 } b; /*!< \brief Structure used for bit access */
ganlikun 0:20e0c61e0684 289 uint32_t w; /*!< \brief Type used for word access */
ganlikun 0:20e0c61e0684 290 } SCTLR_Type;
ganlikun 0:20e0c61e0684 291
ganlikun 0:20e0c61e0684 292 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
ganlikun 0:20e0c61e0684 293 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
ganlikun 0:20e0c61e0684 294
ganlikun 0:20e0c61e0684 295 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
ganlikun 0:20e0c61e0684 296 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
ganlikun 0:20e0c61e0684 297
ganlikun 0:20e0c61e0684 298 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
ganlikun 0:20e0c61e0684 299 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
ganlikun 0:20e0c61e0684 300
ganlikun 0:20e0c61e0684 301 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
ganlikun 0:20e0c61e0684 302 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
ganlikun 0:20e0c61e0684 303
ganlikun 0:20e0c61e0684 304 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
ganlikun 0:20e0c61e0684 305 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
ganlikun 0:20e0c61e0684 306
ganlikun 0:20e0c61e0684 307 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
ganlikun 0:20e0c61e0684 308 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
ganlikun 0:20e0c61e0684 309
ganlikun 0:20e0c61e0684 310 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
ganlikun 0:20e0c61e0684 311 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
ganlikun 0:20e0c61e0684 312
ganlikun 0:20e0c61e0684 313 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
ganlikun 0:20e0c61e0684 314 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
ganlikun 0:20e0c61e0684 315
ganlikun 0:20e0c61e0684 316 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
ganlikun 0:20e0c61e0684 317 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
ganlikun 0:20e0c61e0684 318
ganlikun 0:20e0c61e0684 319 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
ganlikun 0:20e0c61e0684 320 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
ganlikun 0:20e0c61e0684 321
ganlikun 0:20e0c61e0684 322 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
ganlikun 0:20e0c61e0684 323 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
ganlikun 0:20e0c61e0684 324
ganlikun 0:20e0c61e0684 325 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
ganlikun 0:20e0c61e0684 326 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
ganlikun 0:20e0c61e0684 327
ganlikun 0:20e0c61e0684 328 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
ganlikun 0:20e0c61e0684 329 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
ganlikun 0:20e0c61e0684 330
ganlikun 0:20e0c61e0684 331 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
ganlikun 0:20e0c61e0684 332 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
ganlikun 0:20e0c61e0684 333
ganlikun 0:20e0c61e0684 334 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
ganlikun 0:20e0c61e0684 335 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
ganlikun 0:20e0c61e0684 336
ganlikun 0:20e0c61e0684 337 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
ganlikun 0:20e0c61e0684 338 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
ganlikun 0:20e0c61e0684 339
ganlikun 0:20e0c61e0684 340 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
ganlikun 0:20e0c61e0684 341 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
ganlikun 0:20e0c61e0684 342
ganlikun 0:20e0c61e0684 343 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
ganlikun 0:20e0c61e0684 344 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
ganlikun 0:20e0c61e0684 345
ganlikun 0:20e0c61e0684 346 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
ganlikun 0:20e0c61e0684 347 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
ganlikun 0:20e0c61e0684 348
ganlikun 0:20e0c61e0684 349 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
ganlikun 0:20e0c61e0684 350 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
ganlikun 0:20e0c61e0684 351
ganlikun 0:20e0c61e0684 352 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
ganlikun 0:20e0c61e0684 353 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
ganlikun 0:20e0c61e0684 354
ganlikun 0:20e0c61e0684 355 /* CP15 Register CPACR */
ganlikun 0:20e0c61e0684 356 typedef union
ganlikun 0:20e0c61e0684 357 {
ganlikun 0:20e0c61e0684 358 struct
ganlikun 0:20e0c61e0684 359 {
ganlikun 0:20e0c61e0684 360 uint32_t _reserved0:20; /*!< \brief bit: 0..19 Reserved */
ganlikun 0:20e0c61e0684 361 uint32_t cp10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
ganlikun 0:20e0c61e0684 362 uint32_t cp11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
ganlikun 0:20e0c61e0684 363 uint32_t _reserved1:6; /*!< \brief bit:24..29 Reserved */
ganlikun 0:20e0c61e0684 364 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
ganlikun 0:20e0c61e0684 365 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
ganlikun 0:20e0c61e0684 366 } b; /*!< \brief Structure used for bit access */
ganlikun 0:20e0c61e0684 367 uint32_t w; /*!< \brief Type used for word access */
ganlikun 0:20e0c61e0684 368 } CPACR_Type;
ganlikun 0:20e0c61e0684 369
ganlikun 0:20e0c61e0684 370 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
ganlikun 0:20e0c61e0684 371 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
ganlikun 0:20e0c61e0684 372
ganlikun 0:20e0c61e0684 373 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
ganlikun 0:20e0c61e0684 374 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
ganlikun 0:20e0c61e0684 375
ganlikun 0:20e0c61e0684 376 #define CPACR_cp11_Pos 22U /*!< \brief CPACR: cp11 Position */
ganlikun 0:20e0c61e0684 377 #define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< \brief CPACR: cp11 Mask */
ganlikun 0:20e0c61e0684 378
ganlikun 0:20e0c61e0684 379 #define CPACR_cp10_Pos 20U /*!< \brief CPACR: cp10 Position */
ganlikun 0:20e0c61e0684 380 #define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< \brief CPACR: cp10 Mask */
ganlikun 0:20e0c61e0684 381
ganlikun 0:20e0c61e0684 382 /* CP15 Register DFSR */
ganlikun 0:20e0c61e0684 383 typedef union
ganlikun 0:20e0c61e0684 384 {
ganlikun 0:20e0c61e0684 385 struct
ganlikun 0:20e0c61e0684 386 {
ganlikun 0:20e0c61e0684 387 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
ganlikun 0:20e0c61e0684 388 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
ganlikun 0:20e0c61e0684 389 uint32_t _reserved0:2; /*!< \brief bit: 8.. 9 Reserved */
ganlikun 0:20e0c61e0684 390 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
ganlikun 0:20e0c61e0684 391 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
ganlikun 0:20e0c61e0684 392 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
ganlikun 0:20e0c61e0684 393 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
ganlikun 0:20e0c61e0684 394 uint32_t _reserved1:18; /*!< \brief bit:14..31 Reserved */
ganlikun 0:20e0c61e0684 395 } b; /*!< \brief Structure used for bit access */
ganlikun 0:20e0c61e0684 396 uint32_t w; /*!< \brief Type used for word access */
ganlikun 0:20e0c61e0684 397 } DFSR_Type;
ganlikun 0:20e0c61e0684 398
ganlikun 0:20e0c61e0684 399 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
ganlikun 0:20e0c61e0684 400 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
ganlikun 0:20e0c61e0684 401
ganlikun 0:20e0c61e0684 402 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
ganlikun 0:20e0c61e0684 403 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
ganlikun 0:20e0c61e0684 404
ganlikun 0:20e0c61e0684 405 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
ganlikun 0:20e0c61e0684 406 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
ganlikun 0:20e0c61e0684 407
ganlikun 0:20e0c61e0684 408 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
ganlikun 0:20e0c61e0684 409 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
ganlikun 0:20e0c61e0684 410
ganlikun 0:20e0c61e0684 411 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
ganlikun 0:20e0c61e0684 412 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
ganlikun 0:20e0c61e0684 413
ganlikun 0:20e0c61e0684 414 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
ganlikun 0:20e0c61e0684 415 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
ganlikun 0:20e0c61e0684 416
ganlikun 0:20e0c61e0684 417 /* CP15 Register IFSR */
ganlikun 0:20e0c61e0684 418 typedef union
ganlikun 0:20e0c61e0684 419 {
ganlikun 0:20e0c61e0684 420 struct
ganlikun 0:20e0c61e0684 421 {
ganlikun 0:20e0c61e0684 422 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
ganlikun 0:20e0c61e0684 423 uint32_t _reserved0:6; /*!< \brief bit: 4.. 9 Reserved */
ganlikun 0:20e0c61e0684 424 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
ganlikun 0:20e0c61e0684 425 uint32_t _reserved1:1; /*!< \brief bit: 11 Reserved */
ganlikun 0:20e0c61e0684 426 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
ganlikun 0:20e0c61e0684 427 uint32_t _reserved2:19; /*!< \brief bit:13..31 Reserved */
ganlikun 0:20e0c61e0684 428 } b; /*!< \brief Structure used for bit access */
ganlikun 0:20e0c61e0684 429 uint32_t w; /*!< \brief Type used for word access */
ganlikun 0:20e0c61e0684 430 } IFSR_Type;
ganlikun 0:20e0c61e0684 431
ganlikun 0:20e0c61e0684 432 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
ganlikun 0:20e0c61e0684 433 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
ganlikun 0:20e0c61e0684 434
ganlikun 0:20e0c61e0684 435 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
ganlikun 0:20e0c61e0684 436 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
ganlikun 0:20e0c61e0684 437
ganlikun 0:20e0c61e0684 438 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
ganlikun 0:20e0c61e0684 439 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
ganlikun 0:20e0c61e0684 440
ganlikun 0:20e0c61e0684 441 /* CP15 Register ISR */
ganlikun 0:20e0c61e0684 442 typedef union
ganlikun 0:20e0c61e0684 443 {
ganlikun 0:20e0c61e0684 444 struct
ganlikun 0:20e0c61e0684 445 {
ganlikun 0:20e0c61e0684 446 uint32_t _reserved0:6; /*!< \brief bit: 0.. 5 Reserved */
ganlikun 0:20e0c61e0684 447 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
ganlikun 0:20e0c61e0684 448 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
ganlikun 0:20e0c61e0684 449 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
ganlikun 0:20e0c61e0684 450 uint32_t _reserved1:23; /*!< \brief bit:14..31 Reserved */
ganlikun 0:20e0c61e0684 451 } b; /*!< \brief Structure used for bit access */
ganlikun 0:20e0c61e0684 452 uint32_t w; /*!< \brief Type used for word access */
ganlikun 0:20e0c61e0684 453 } ISR_Type;
ganlikun 0:20e0c61e0684 454
ganlikun 0:20e0c61e0684 455 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
ganlikun 0:20e0c61e0684 456 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
ganlikun 0:20e0c61e0684 457
ganlikun 0:20e0c61e0684 458 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
ganlikun 0:20e0c61e0684 459 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
ganlikun 0:20e0c61e0684 460
ganlikun 0:20e0c61e0684 461 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
ganlikun 0:20e0c61e0684 462 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
ganlikun 0:20e0c61e0684 463
ganlikun 0:20e0c61e0684 464
ganlikun 0:20e0c61e0684 465 /**
ganlikun 0:20e0c61e0684 466 \brief Union type to access the L2C_310 Cache Controller.
ganlikun 0:20e0c61e0684 467 */
ganlikun 0:20e0c61e0684 468 #if (__L2C_PRESENT == 1U)
ganlikun 0:20e0c61e0684 469 typedef struct
ganlikun 0:20e0c61e0684 470 {
ganlikun 0:20e0c61e0684 471 __I uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 Cache ID Register */
ganlikun 0:20e0c61e0684 472 __I uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 Cache Type Register */
ganlikun 0:20e0c61e0684 473 uint32_t RESERVED0[0x3e];
ganlikun 0:20e0c61e0684 474 __IO uint32_t CONTROL; /*!< \brief Offset: 0x0100 Control Register */
ganlikun 0:20e0c61e0684 475 __IO uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 Auxiliary Control */
ganlikun 0:20e0c61e0684 476 uint32_t RESERVED1[0x3e];
ganlikun 0:20e0c61e0684 477 __IO uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 Event Counter Control */
ganlikun 0:20e0c61e0684 478 __IO uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 Event Counter 1 Configuration */
ganlikun 0:20e0c61e0684 479 __IO uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 Event Counter 1 Configuration */
ganlikun 0:20e0c61e0684 480 uint32_t RESERVED2[0x2];
ganlikun 0:20e0c61e0684 481 __IO uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 Interrupt Mask */
ganlikun 0:20e0c61e0684 482 __I uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 Masked Interrupt Status */
ganlikun 0:20e0c61e0684 483 __I uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c Raw Interrupt Status */
ganlikun 0:20e0c61e0684 484 __O uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 Interrupt Clear */
ganlikun 0:20e0c61e0684 485 uint32_t RESERVED3[0x143];
ganlikun 0:20e0c61e0684 486 __IO uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 Cache Sync */
ganlikun 0:20e0c61e0684 487 uint32_t RESERVED4[0xf];
ganlikun 0:20e0c61e0684 488 __IO uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 Invalidate Line By PA */
ganlikun 0:20e0c61e0684 489 uint32_t RESERVED6[2];
ganlikun 0:20e0c61e0684 490 __IO uint32_t INV_WAY; /*!< \brief Offset: 0x077c Invalidate by Way */
ganlikun 0:20e0c61e0684 491 uint32_t RESERVED5[0xc];
ganlikun 0:20e0c61e0684 492 __IO uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 Clean Line by PA */
ganlikun 0:20e0c61e0684 493 uint32_t RESERVED7[1];
ganlikun 0:20e0c61e0684 494 __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 Clean Line by Index/Way */
ganlikun 0:20e0c61e0684 495 __IO uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc Clean by Way */
ganlikun 0:20e0c61e0684 496 uint32_t RESERVED8[0xc];
ganlikun 0:20e0c61e0684 497 __IO uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA */
ganlikun 0:20e0c61e0684 498 uint32_t RESERVED9[1];
ganlikun 0:20e0c61e0684 499 __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
ganlikun 0:20e0c61e0684 500 __IO uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc Clean and Invalidate by Way */
ganlikun 0:20e0c61e0684 501 uint32_t RESERVED10[0x40];
ganlikun 0:20e0c61e0684 502 __IO uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 Data Lockdown 0 by Way */
ganlikun 0:20e0c61e0684 503 __IO uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way */
ganlikun 0:20e0c61e0684 504 __IO uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 Data Lockdown 1 by Way */
ganlikun 0:20e0c61e0684 505 __IO uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c Instruction Lockdown 1 by Way */
ganlikun 0:20e0c61e0684 506 __IO uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 Data Lockdown 2 by Way */
ganlikun 0:20e0c61e0684 507 __IO uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way */
ganlikun 0:20e0c61e0684 508 __IO uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 Data Lockdown 3 by Way */
ganlikun 0:20e0c61e0684 509 __IO uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c Instruction Lockdown 3 by Way */
ganlikun 0:20e0c61e0684 510 __IO uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 Data Lockdown 4 by Way */
ganlikun 0:20e0c61e0684 511 __IO uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way */
ganlikun 0:20e0c61e0684 512 __IO uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 Data Lockdown 5 by Way */
ganlikun 0:20e0c61e0684 513 __IO uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c Instruction Lockdown 5 by Way */
ganlikun 0:20e0c61e0684 514 __IO uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 Data Lockdown 5 by Way */
ganlikun 0:20e0c61e0684 515 __IO uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way */
ganlikun 0:20e0c61e0684 516 __IO uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 Data Lockdown 6 by Way */
ganlikun 0:20e0c61e0684 517 __IO uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c Instruction Lockdown 6 by Way */
ganlikun 0:20e0c61e0684 518 uint32_t RESERVED11[0x4];
ganlikun 0:20e0c61e0684 519 __IO uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 Lockdown by Line Enable */
ganlikun 0:20e0c61e0684 520 __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 Unlock All Lines by Way */
ganlikun 0:20e0c61e0684 521 uint32_t RESERVED12[0xaa];
ganlikun 0:20e0c61e0684 522 __IO uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 Address Filtering Start */
ganlikun 0:20e0c61e0684 523 __IO uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 Address Filtering End */
ganlikun 0:20e0c61e0684 524 uint32_t RESERVED13[0xce];
ganlikun 0:20e0c61e0684 525 __IO uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 Debug Control Register */
ganlikun 0:20e0c61e0684 526 } L2C_310_TypeDef;
ganlikun 0:20e0c61e0684 527
ganlikun 0:20e0c61e0684 528 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 Declaration */
ganlikun 0:20e0c61e0684 529 #endif
ganlikun 0:20e0c61e0684 530
ganlikun 0:20e0c61e0684 531 #if (__GIC_PRESENT == 1U)
ganlikun 0:20e0c61e0684 532 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
ganlikun 0:20e0c61e0684 533 */
ganlikun 0:20e0c61e0684 534 typedef struct
ganlikun 0:20e0c61e0684 535 {
ganlikun 0:20e0c61e0684 536 __IO uint32_t ICDDCR;
ganlikun 0:20e0c61e0684 537 __I uint32_t ICDICTR;
ganlikun 0:20e0c61e0684 538 __I uint32_t ICDIIDR;
ganlikun 0:20e0c61e0684 539 uint32_t RESERVED0[29];
ganlikun 0:20e0c61e0684 540 __IO uint32_t ICDISR[32];
ganlikun 0:20e0c61e0684 541 __IO uint32_t ICDISER[32];
ganlikun 0:20e0c61e0684 542 __IO uint32_t ICDICER[32];
ganlikun 0:20e0c61e0684 543 __IO uint32_t ICDISPR[32];
ganlikun 0:20e0c61e0684 544 __IO uint32_t ICDICPR[32];
ganlikun 0:20e0c61e0684 545 __I uint32_t ICDABR[32];
ganlikun 0:20e0c61e0684 546 uint32_t RESERVED1[32];
ganlikun 0:20e0c61e0684 547 __IO uint32_t ICDIPR[256];
ganlikun 0:20e0c61e0684 548 __IO uint32_t ICDIPTR[256];
ganlikun 0:20e0c61e0684 549 __IO uint32_t ICDICFR[64];
ganlikun 0:20e0c61e0684 550 uint32_t RESERVED2[128];
ganlikun 0:20e0c61e0684 551 __IO uint32_t ICDSGIR;
ganlikun 0:20e0c61e0684 552 } GICDistributor_Type;
ganlikun 0:20e0c61e0684 553
ganlikun 0:20e0c61e0684 554 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
ganlikun 0:20e0c61e0684 555
ganlikun 0:20e0c61e0684 556 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
ganlikun 0:20e0c61e0684 557 */
ganlikun 0:20e0c61e0684 558 typedef struct
ganlikun 0:20e0c61e0684 559 {
ganlikun 0:20e0c61e0684 560 __IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register
ganlikun 0:20e0c61e0684 561 __IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register
ganlikun 0:20e0c61e0684 562 __IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register
ganlikun 0:20e0c61e0684 563 __I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register
ganlikun 0:20e0c61e0684 564 __IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register
ganlikun 0:20e0c61e0684 565 __I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register
ganlikun 0:20e0c61e0684 566 __I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register
ganlikun 0:20e0c61e0684 567 __IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register
ganlikun 0:20e0c61e0684 568 uint32_t RESERVED[55];
ganlikun 0:20e0c61e0684 569 __I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register
ganlikun 0:20e0c61e0684 570 } GICInterface_Type;
ganlikun 0:20e0c61e0684 571
ganlikun 0:20e0c61e0684 572 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
ganlikun 0:20e0c61e0684 573 #endif
ganlikun 0:20e0c61e0684 574
ganlikun 0:20e0c61e0684 575 #if (__TIM_PRESENT == 1U)
ganlikun 0:20e0c61e0684 576 #if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
ganlikun 0:20e0c61e0684 577 /** \brief Structure type to access the Private Timer
ganlikun 0:20e0c61e0684 578 */
ganlikun 0:20e0c61e0684 579 typedef struct
ganlikun 0:20e0c61e0684 580 {
ganlikun 0:20e0c61e0684 581 __IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register
ganlikun 0:20e0c61e0684 582 __IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register
ganlikun 0:20e0c61e0684 583 __IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register
ganlikun 0:20e0c61e0684 584 __IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register
ganlikun 0:20e0c61e0684 585 uint32_t RESERVED[8];
ganlikun 0:20e0c61e0684 586 __IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register
ganlikun 0:20e0c61e0684 587 __IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register
ganlikun 0:20e0c61e0684 588 __IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register
ganlikun 0:20e0c61e0684 589 __IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register
ganlikun 0:20e0c61e0684 590 __IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register
ganlikun 0:20e0c61e0684 591 __I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register
ganlikun 0:20e0c61e0684 592 } Timer_Type;
ganlikun 0:20e0c61e0684 593 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer configuration struct */
ganlikun 0:20e0c61e0684 594 #endif
ganlikun 0:20e0c61e0684 595 #endif
ganlikun 0:20e0c61e0684 596
ganlikun 0:20e0c61e0684 597 /*******************************************************************************
ganlikun 0:20e0c61e0684 598 * Hardware Abstraction Layer
ganlikun 0:20e0c61e0684 599 Core Function Interface contains:
ganlikun 0:20e0c61e0684 600 - L1 Cache Functions
ganlikun 0:20e0c61e0684 601 - L2C-310 Cache Controller Functions
ganlikun 0:20e0c61e0684 602 - PL1 Timer Functions
ganlikun 0:20e0c61e0684 603 - GIC Functions
ganlikun 0:20e0c61e0684 604 - MMU Functions
ganlikun 0:20e0c61e0684 605 ******************************************************************************/
ganlikun 0:20e0c61e0684 606
ganlikun 0:20e0c61e0684 607 /* ########################## L1 Cache functions ################################# */
ganlikun 0:20e0c61e0684 608
ganlikun 0:20e0c61e0684 609 /** \brief Enable Caches
ganlikun 0:20e0c61e0684 610
ganlikun 0:20e0c61e0684 611 Enable Caches
ganlikun 0:20e0c61e0684 612 */
ganlikun 0:20e0c61e0684 613 __STATIC_INLINE void L1C_EnableCaches(void) {
ganlikun 0:20e0c61e0684 614 // Set I bit 12 to enable I Cache
ganlikun 0:20e0c61e0684 615 // Set C bit 2 to enable D Cache
ganlikun 0:20e0c61e0684 616 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
ganlikun 0:20e0c61e0684 617 }
ganlikun 0:20e0c61e0684 618
ganlikun 0:20e0c61e0684 619 /** \brief Disable Caches
ganlikun 0:20e0c61e0684 620
ganlikun 0:20e0c61e0684 621 Disable Caches
ganlikun 0:20e0c61e0684 622 */
ganlikun 0:20e0c61e0684 623 __STATIC_INLINE void L1C_DisableCaches(void) {
ganlikun 0:20e0c61e0684 624 // Clear I bit 12 to disable I Cache
ganlikun 0:20e0c61e0684 625 // Clear C bit 2 to disable D Cache
ganlikun 0:20e0c61e0684 626 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
ganlikun 0:20e0c61e0684 627 __ISB();
ganlikun 0:20e0c61e0684 628 }
ganlikun 0:20e0c61e0684 629
ganlikun 0:20e0c61e0684 630 /** \brief Enable BTAC
ganlikun 0:20e0c61e0684 631
ganlikun 0:20e0c61e0684 632 Enable BTAC
ganlikun 0:20e0c61e0684 633 */
ganlikun 0:20e0c61e0684 634 __STATIC_INLINE void L1C_EnableBTAC(void) {
ganlikun 0:20e0c61e0684 635 // Set Z bit 11 to enable branch prediction
ganlikun 0:20e0c61e0684 636 __set_SCTLR( __get_SCTLR() | (1 << 11));
ganlikun 0:20e0c61e0684 637 __ISB();
ganlikun 0:20e0c61e0684 638 }
ganlikun 0:20e0c61e0684 639
ganlikun 0:20e0c61e0684 640 /** \brief Disable BTAC
ganlikun 0:20e0c61e0684 641
ganlikun 0:20e0c61e0684 642 Disable BTAC
ganlikun 0:20e0c61e0684 643 */
ganlikun 0:20e0c61e0684 644 __STATIC_INLINE void L1C_DisableBTAC(void) {
ganlikun 0:20e0c61e0684 645 // Clear Z bit 11 to disable branch prediction
ganlikun 0:20e0c61e0684 646 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
ganlikun 0:20e0c61e0684 647 }
ganlikun 0:20e0c61e0684 648
ganlikun 0:20e0c61e0684 649 /** \brief Invalidate entire branch predictor array
ganlikun 0:20e0c61e0684 650
ganlikun 0:20e0c61e0684 651 BPIALL. Branch Predictor Invalidate All.
ganlikun 0:20e0c61e0684 652 */
ganlikun 0:20e0c61e0684 653
ganlikun 0:20e0c61e0684 654 __STATIC_INLINE void L1C_InvalidateBTAC(void) {
ganlikun 0:20e0c61e0684 655 __set_BPIALL(0);
ganlikun 0:20e0c61e0684 656 __DSB(); //ensure completion of the invalidation
ganlikun 0:20e0c61e0684 657 __ISB(); //ensure instruction fetch path sees new state
ganlikun 0:20e0c61e0684 658 }
ganlikun 0:20e0c61e0684 659
ganlikun 0:20e0c61e0684 660 /** \brief Invalidate the whole I$
ganlikun 0:20e0c61e0684 661
ganlikun 0:20e0c61e0684 662 ICIALLU. Instruction Cache Invalidate All to PoU
ganlikun 0:20e0c61e0684 663 */
ganlikun 0:20e0c61e0684 664 __STATIC_INLINE void L1C_InvalidateICacheAll(void) {
ganlikun 0:20e0c61e0684 665 __set_ICIALLU(0);
ganlikun 0:20e0c61e0684 666 __DSB(); //ensure completion of the invalidation
ganlikun 0:20e0c61e0684 667 __ISB(); //ensure instruction fetch path sees new I cache state
ganlikun 0:20e0c61e0684 668 }
ganlikun 0:20e0c61e0684 669
ganlikun 0:20e0c61e0684 670 /** \brief Clean D$ by MVA
ganlikun 0:20e0c61e0684 671
ganlikun 0:20e0c61e0684 672 DCCMVAC. Data cache clean by MVA to PoC
ganlikun 0:20e0c61e0684 673 */
ganlikun 0:20e0c61e0684 674 __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
ganlikun 0:20e0c61e0684 675 __set_DCCMVAC((uint32_t)va);
ganlikun 0:20e0c61e0684 676 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
ganlikun 0:20e0c61e0684 677 }
ganlikun 0:20e0c61e0684 678
ganlikun 0:20e0c61e0684 679 /** \brief Invalidate D$ by MVA
ganlikun 0:20e0c61e0684 680
ganlikun 0:20e0c61e0684 681 DCIMVAC. Data cache invalidate by MVA to PoC
ganlikun 0:20e0c61e0684 682 */
ganlikun 0:20e0c61e0684 683 __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
ganlikun 0:20e0c61e0684 684 __set_DCIMVAC((uint32_t)va);
ganlikun 0:20e0c61e0684 685 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
ganlikun 0:20e0c61e0684 686 }
ganlikun 0:20e0c61e0684 687
ganlikun 0:20e0c61e0684 688 /** \brief Clean and Invalidate D$ by MVA
ganlikun 0:20e0c61e0684 689
ganlikun 0:20e0c61e0684 690 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
ganlikun 0:20e0c61e0684 691 */
ganlikun 0:20e0c61e0684 692 __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
ganlikun 0:20e0c61e0684 693 __set_DCCIMVAC((uint32_t)va);
ganlikun 0:20e0c61e0684 694 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
ganlikun 0:20e0c61e0684 695 }
ganlikun 0:20e0c61e0684 696
ganlikun 0:20e0c61e0684 697 /** \brief Clean and Invalidate the entire data or unified cache
ganlikun 0:20e0c61e0684 698
ganlikun 0:20e0c61e0684 699 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
ganlikun 0:20e0c61e0684 700 */
ganlikun 0:20e0c61e0684 701 __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
ganlikun 0:20e0c61e0684 702 __L1C_CleanInvalidateCache(op); // compiler specific call
ganlikun 0:20e0c61e0684 703 }
ganlikun 0:20e0c61e0684 704
ganlikun 0:20e0c61e0684 705
ganlikun 0:20e0c61e0684 706 /** \brief Invalidate the whole D$
ganlikun 0:20e0c61e0684 707
ganlikun 0:20e0c61e0684 708 DCISW. Invalidate by Set/Way
ganlikun 0:20e0c61e0684 709 */
ganlikun 0:20e0c61e0684 710
ganlikun 0:20e0c61e0684 711 __STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
ganlikun 0:20e0c61e0684 712 L1C_CleanInvalidateCache(0);
ganlikun 0:20e0c61e0684 713 }
ganlikun 0:20e0c61e0684 714
ganlikun 0:20e0c61e0684 715 /** \brief Clean the whole D$
ganlikun 0:20e0c61e0684 716
ganlikun 0:20e0c61e0684 717 DCCSW. Clean by Set/Way
ganlikun 0:20e0c61e0684 718 */
ganlikun 0:20e0c61e0684 719
ganlikun 0:20e0c61e0684 720 __STATIC_INLINE void L1C_CleanDCacheAll(void) {
ganlikun 0:20e0c61e0684 721 L1C_CleanInvalidateCache(1);
ganlikun 0:20e0c61e0684 722 }
ganlikun 0:20e0c61e0684 723
ganlikun 0:20e0c61e0684 724 /** \brief Clean and invalidate the whole D$
ganlikun 0:20e0c61e0684 725
ganlikun 0:20e0c61e0684 726 DCCISW. Clean and Invalidate by Set/Way
ganlikun 0:20e0c61e0684 727 */
ganlikun 0:20e0c61e0684 728
ganlikun 0:20e0c61e0684 729 __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
ganlikun 0:20e0c61e0684 730 L1C_CleanInvalidateCache(2);
ganlikun 0:20e0c61e0684 731 }
ganlikun 0:20e0c61e0684 732
ganlikun 0:20e0c61e0684 733
ganlikun 0:20e0c61e0684 734 /* ########################## L2 Cache functions ################################# */
ganlikun 0:20e0c61e0684 735 #if (__L2C_PRESENT == 1U)
ganlikun 0:20e0c61e0684 736 //Cache Sync operation
ganlikun 0:20e0c61e0684 737 __STATIC_INLINE void L2C_Sync(void)
ganlikun 0:20e0c61e0684 738 {
ganlikun 0:20e0c61e0684 739 L2C_310->CACHE_SYNC = 0x0;
ganlikun 0:20e0c61e0684 740 }
ganlikun 0:20e0c61e0684 741
ganlikun 0:20e0c61e0684 742 //return Cache controller cache ID
ganlikun 0:20e0c61e0684 743 __STATIC_INLINE int L2C_GetID (void)
ganlikun 0:20e0c61e0684 744 {
ganlikun 0:20e0c61e0684 745 return L2C_310->CACHE_ID;
ganlikun 0:20e0c61e0684 746 }
ganlikun 0:20e0c61e0684 747
ganlikun 0:20e0c61e0684 748 //return Cache controller cache Type
ganlikun 0:20e0c61e0684 749 __STATIC_INLINE int L2C_GetType (void)
ganlikun 0:20e0c61e0684 750 {
ganlikun 0:20e0c61e0684 751 return L2C_310->CACHE_TYPE;
ganlikun 0:20e0c61e0684 752 }
ganlikun 0:20e0c61e0684 753
ganlikun 0:20e0c61e0684 754 //Invalidate all cache by way
ganlikun 0:20e0c61e0684 755 __STATIC_INLINE void L2C_InvAllByWay (void)
ganlikun 0:20e0c61e0684 756 {
ganlikun 0:20e0c61e0684 757 unsigned int assoc;
ganlikun 0:20e0c61e0684 758
ganlikun 0:20e0c61e0684 759 if (L2C_310->AUX_CNT & (1<<16))
ganlikun 0:20e0c61e0684 760 assoc = 16;
ganlikun 0:20e0c61e0684 761 else
ganlikun 0:20e0c61e0684 762 assoc = 8;
ganlikun 0:20e0c61e0684 763
ganlikun 0:20e0c61e0684 764 L2C_310->INV_WAY = (1 << assoc) - 1;
ganlikun 0:20e0c61e0684 765 while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
ganlikun 0:20e0c61e0684 766
ganlikun 0:20e0c61e0684 767 L2C_Sync();
ganlikun 0:20e0c61e0684 768 }
ganlikun 0:20e0c61e0684 769
ganlikun 0:20e0c61e0684 770 //Clean and Invalidate all cache by way
ganlikun 0:20e0c61e0684 771 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
ganlikun 0:20e0c61e0684 772 {
ganlikun 0:20e0c61e0684 773 unsigned int assoc;
ganlikun 0:20e0c61e0684 774
ganlikun 0:20e0c61e0684 775 if (L2C_310->AUX_CNT & (1<<16))
ganlikun 0:20e0c61e0684 776 assoc = 16;
ganlikun 0:20e0c61e0684 777 else
ganlikun 0:20e0c61e0684 778 assoc = 8;
ganlikun 0:20e0c61e0684 779
ganlikun 0:20e0c61e0684 780 L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
ganlikun 0:20e0c61e0684 781 while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
ganlikun 0:20e0c61e0684 782
ganlikun 0:20e0c61e0684 783 L2C_Sync();
ganlikun 0:20e0c61e0684 784 }
ganlikun 0:20e0c61e0684 785
ganlikun 0:20e0c61e0684 786 //Enable Cache
ganlikun 0:20e0c61e0684 787 __STATIC_INLINE void L2C_Enable(void)
ganlikun 0:20e0c61e0684 788 {
ganlikun 0:20e0c61e0684 789 L2C_310->CONTROL = 0;
ganlikun 0:20e0c61e0684 790 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
ganlikun 0:20e0c61e0684 791 L2C_310->DEBUG_CONTROL = 0;
ganlikun 0:20e0c61e0684 792 L2C_310->DATA_LOCK_0_WAY = 0;
ganlikun 0:20e0c61e0684 793 L2C_310->CACHE_SYNC = 0;
ganlikun 0:20e0c61e0684 794 L2C_310->CONTROL = 0x01;
ganlikun 0:20e0c61e0684 795 L2C_Sync();
ganlikun 0:20e0c61e0684 796 }
ganlikun 0:20e0c61e0684 797 //Disable Cache
ganlikun 0:20e0c61e0684 798 __STATIC_INLINE void L2C_Disable(void)
ganlikun 0:20e0c61e0684 799 {
ganlikun 0:20e0c61e0684 800 L2C_310->CONTROL = 0x00;
ganlikun 0:20e0c61e0684 801 L2C_Sync();
ganlikun 0:20e0c61e0684 802 }
ganlikun 0:20e0c61e0684 803
ganlikun 0:20e0c61e0684 804 //Invalidate cache by physical address
ganlikun 0:20e0c61e0684 805 __STATIC_INLINE void L2C_InvPa (void *pa)
ganlikun 0:20e0c61e0684 806 {
ganlikun 0:20e0c61e0684 807 L2C_310->INV_LINE_PA = (unsigned int)pa;
ganlikun 0:20e0c61e0684 808 L2C_Sync();
ganlikun 0:20e0c61e0684 809 }
ganlikun 0:20e0c61e0684 810
ganlikun 0:20e0c61e0684 811 //Clean cache by physical address
ganlikun 0:20e0c61e0684 812 __STATIC_INLINE void L2C_CleanPa (void *pa)
ganlikun 0:20e0c61e0684 813 {
ganlikun 0:20e0c61e0684 814 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
ganlikun 0:20e0c61e0684 815 L2C_Sync();
ganlikun 0:20e0c61e0684 816 }
ganlikun 0:20e0c61e0684 817
ganlikun 0:20e0c61e0684 818 //Clean and invalidate cache by physical address
ganlikun 0:20e0c61e0684 819 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
ganlikun 0:20e0c61e0684 820 {
ganlikun 0:20e0c61e0684 821 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
ganlikun 0:20e0c61e0684 822 L2C_Sync();
ganlikun 0:20e0c61e0684 823 }
ganlikun 0:20e0c61e0684 824 #endif
ganlikun 0:20e0c61e0684 825
ganlikun 0:20e0c61e0684 826 /* ########################## GIC functions ###################################### */
ganlikun 0:20e0c61e0684 827 #if (__GIC_PRESENT == 1U)
ganlikun 0:20e0c61e0684 828
ganlikun 0:20e0c61e0684 829 __STATIC_INLINE void GIC_EnableDistributor(void)
ganlikun 0:20e0c61e0684 830 {
ganlikun 0:20e0c61e0684 831 GICDistributor->ICDDCR |= 1; //enable distributor
ganlikun 0:20e0c61e0684 832 }
ganlikun 0:20e0c61e0684 833
ganlikun 0:20e0c61e0684 834 __STATIC_INLINE void GIC_DisableDistributor(void)
ganlikun 0:20e0c61e0684 835 {
ganlikun 0:20e0c61e0684 836 GICDistributor->ICDDCR &=~1; //disable distributor
ganlikun 0:20e0c61e0684 837 }
ganlikun 0:20e0c61e0684 838
ganlikun 0:20e0c61e0684 839 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
ganlikun 0:20e0c61e0684 840 {
ganlikun 0:20e0c61e0684 841 return (uint32_t)(GICDistributor->ICDICTR);
ganlikun 0:20e0c61e0684 842 }
ganlikun 0:20e0c61e0684 843
ganlikun 0:20e0c61e0684 844 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
ganlikun 0:20e0c61e0684 845 {
ganlikun 0:20e0c61e0684 846 return (uint32_t)(GICDistributor->ICDIIDR);
ganlikun 0:20e0c61e0684 847 }
ganlikun 0:20e0c61e0684 848
ganlikun 0:20e0c61e0684 849 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
ganlikun 0:20e0c61e0684 850 {
ganlikun 0:20e0c61e0684 851 char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
ganlikun 0:20e0c61e0684 852 field += IRQn % 4;
ganlikun 0:20e0c61e0684 853 *field = (char)cpu_target & 0xf;
ganlikun 0:20e0c61e0684 854 }
ganlikun 0:20e0c61e0684 855
ganlikun 0:20e0c61e0684 856 __STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
ganlikun 0:20e0c61e0684 857 {
ganlikun 0:20e0c61e0684 858 uint32_t i, num_irq;
ganlikun 0:20e0c61e0684 859
ganlikun 0:20e0c61e0684 860 //Get the maximum number of interrupts that the GIC supports
ganlikun 0:20e0c61e0684 861 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
ganlikun 0:20e0c61e0684 862
ganlikun 0:20e0c61e0684 863 for (i = 0; i < (num_irq/16); i++)
ganlikun 0:20e0c61e0684 864 {
ganlikun 0:20e0c61e0684 865 GICDistributor->ICDISPR[i] = *ICDICFRn++;
ganlikun 0:20e0c61e0684 866 }
ganlikun 0:20e0c61e0684 867 }
ganlikun 0:20e0c61e0684 868
ganlikun 0:20e0c61e0684 869 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 870 {
ganlikun 0:20e0c61e0684 871 char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
ganlikun 0:20e0c61e0684 872 field += IRQn % 4;
ganlikun 0:20e0c61e0684 873 return ((uint32_t)*field & 0xf);
ganlikun 0:20e0c61e0684 874 }
ganlikun 0:20e0c61e0684 875
ganlikun 0:20e0c61e0684 876 __STATIC_INLINE void GIC_EnableInterface(void)
ganlikun 0:20e0c61e0684 877 {
ganlikun 0:20e0c61e0684 878 GICInterface->ICCICR |= 1; //enable interface
ganlikun 0:20e0c61e0684 879 }
ganlikun 0:20e0c61e0684 880
ganlikun 0:20e0c61e0684 881 __STATIC_INLINE void GIC_DisableInterface(void)
ganlikun 0:20e0c61e0684 882 {
ganlikun 0:20e0c61e0684 883 GICInterface->ICCICR &=~1; //disable distributor
ganlikun 0:20e0c61e0684 884 }
ganlikun 0:20e0c61e0684 885
ganlikun 0:20e0c61e0684 886 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
ganlikun 0:20e0c61e0684 887 {
ganlikun 0:20e0c61e0684 888 return (IRQn_Type)(GICInterface->ICCIAR);
ganlikun 0:20e0c61e0684 889 }
ganlikun 0:20e0c61e0684 890
ganlikun 0:20e0c61e0684 891 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 892 {
ganlikun 0:20e0c61e0684 893 GICInterface->ICCEOIR = IRQn;
ganlikun 0:20e0c61e0684 894 }
ganlikun 0:20e0c61e0684 895
ganlikun 0:20e0c61e0684 896 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 897 {
ganlikun 0:20e0c61e0684 898 GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
ganlikun 0:20e0c61e0684 899 }
ganlikun 0:20e0c61e0684 900
ganlikun 0:20e0c61e0684 901 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 902 {
ganlikun 0:20e0c61e0684 903 GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
ganlikun 0:20e0c61e0684 904 }
ganlikun 0:20e0c61e0684 905
ganlikun 0:20e0c61e0684 906 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 907 {
ganlikun 0:20e0c61e0684 908 GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
ganlikun 0:20e0c61e0684 909 }
ganlikun 0:20e0c61e0684 910
ganlikun 0:20e0c61e0684 911 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 912 {
ganlikun 0:20e0c61e0684 913 GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
ganlikun 0:20e0c61e0684 914 }
ganlikun 0:20e0c61e0684 915
ganlikun 0:20e0c61e0684 916 __STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
ganlikun 0:20e0c61e0684 917 {
ganlikun 0:20e0c61e0684 918 // Word-size read/writes must be used to access this register
ganlikun 0:20e0c61e0684 919 volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
ganlikun 0:20e0c61e0684 920 unsigned bit_shift = (IRQn % 16)<<1;
ganlikun 0:20e0c61e0684 921 unsigned int save_word;
ganlikun 0:20e0c61e0684 922
ganlikun 0:20e0c61e0684 923 save_word = *field;
ganlikun 0:20e0c61e0684 924 save_word &= (~(3 << bit_shift));
ganlikun 0:20e0c61e0684 925
ganlikun 0:20e0c61e0684 926 *field = (save_word | (((edge_level<<1) | model) << bit_shift));
ganlikun 0:20e0c61e0684 927 }
ganlikun 0:20e0c61e0684 928
ganlikun 0:20e0c61e0684 929 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ganlikun 0:20e0c61e0684 930 {
ganlikun 0:20e0c61e0684 931 char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
ganlikun 0:20e0c61e0684 932 field += IRQn % 4;
ganlikun 0:20e0c61e0684 933 *field = (char)priority;
ganlikun 0:20e0c61e0684 934 }
ganlikun 0:20e0c61e0684 935
ganlikun 0:20e0c61e0684 936 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 937 {
ganlikun 0:20e0c61e0684 938 char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
ganlikun 0:20e0c61e0684 939 field += IRQn % 4;
ganlikun 0:20e0c61e0684 940 return (uint32_t)*field;
ganlikun 0:20e0c61e0684 941 }
ganlikun 0:20e0c61e0684 942
ganlikun 0:20e0c61e0684 943 __STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
ganlikun 0:20e0c61e0684 944 {
ganlikun 0:20e0c61e0684 945 GICInterface->ICCPMR = priority & 0xff; //set priority mask
ganlikun 0:20e0c61e0684 946 }
ganlikun 0:20e0c61e0684 947
ganlikun 0:20e0c61e0684 948 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
ganlikun 0:20e0c61e0684 949 {
ganlikun 0:20e0c61e0684 950 GICInterface->ICCBPR = binary_point & 0x07; //set binary point
ganlikun 0:20e0c61e0684 951 }
ganlikun 0:20e0c61e0684 952
ganlikun 0:20e0c61e0684 953 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
ganlikun 0:20e0c61e0684 954 {
ganlikun 0:20e0c61e0684 955 return (uint32_t)GICInterface->ICCBPR;
ganlikun 0:20e0c61e0684 956 }
ganlikun 0:20e0c61e0684 957
ganlikun 0:20e0c61e0684 958 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
ganlikun 0:20e0c61e0684 959 {
ganlikun 0:20e0c61e0684 960 uint32_t pending, active;
ganlikun 0:20e0c61e0684 961
ganlikun 0:20e0c61e0684 962 active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
ganlikun 0:20e0c61e0684 963 pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
ganlikun 0:20e0c61e0684 964
ganlikun 0:20e0c61e0684 965 return ((active<<1) | pending);
ganlikun 0:20e0c61e0684 966 }
ganlikun 0:20e0c61e0684 967
ganlikun 0:20e0c61e0684 968 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
ganlikun 0:20e0c61e0684 969 {
ganlikun 0:20e0c61e0684 970 GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
ganlikun 0:20e0c61e0684 971 }
ganlikun 0:20e0c61e0684 972
ganlikun 0:20e0c61e0684 973 __STATIC_INLINE void GIC_DistInit(void)
ganlikun 0:20e0c61e0684 974 {
ganlikun 0:20e0c61e0684 975 IRQn_Type i;
ganlikun 0:20e0c61e0684 976 uint32_t num_irq = 0;
ganlikun 0:20e0c61e0684 977 uint32_t priority_field;
ganlikun 0:20e0c61e0684 978
ganlikun 0:20e0c61e0684 979 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
ganlikun 0:20e0c61e0684 980 //configuring all of the interrupts as Secure.
ganlikun 0:20e0c61e0684 981
ganlikun 0:20e0c61e0684 982 //Disable interrupt forwarding
ganlikun 0:20e0c61e0684 983 GIC_DisableDistributor();
ganlikun 0:20e0c61e0684 984 //Get the maximum number of interrupts that the GIC supports
ganlikun 0:20e0c61e0684 985 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
ganlikun 0:20e0c61e0684 986
ganlikun 0:20e0c61e0684 987 /* Priority level is implementation defined.
ganlikun 0:20e0c61e0684 988 To determine the number of priority bits implemented write 0xFF to an ICDIPR
ganlikun 0:20e0c61e0684 989 priority field and read back the value stored.*/
ganlikun 0:20e0c61e0684 990 GIC_SetPriority((IRQn_Type)0, 0xff);
ganlikun 0:20e0c61e0684 991 priority_field = GIC_GetPriority((IRQn_Type)0);
ganlikun 0:20e0c61e0684 992
ganlikun 0:20e0c61e0684 993 for (i = (IRQn_Type)32; i < num_irq; i++)
ganlikun 0:20e0c61e0684 994 {
ganlikun 0:20e0c61e0684 995 //Disable the SPI interrupt
ganlikun 0:20e0c61e0684 996 GIC_DisableIRQ(i);
ganlikun 0:20e0c61e0684 997 //Set level-sensitive and 1-N model
ganlikun 0:20e0c61e0684 998 GIC_SetLevelModel(i, 0, 1);
ganlikun 0:20e0c61e0684 999 //Set priority
ganlikun 0:20e0c61e0684 1000 GIC_SetPriority(i, priority_field/2);
ganlikun 0:20e0c61e0684 1001 //Set target list to CPU0
ganlikun 0:20e0c61e0684 1002 GIC_SetTarget(i, 1);
ganlikun 0:20e0c61e0684 1003 }
ganlikun 0:20e0c61e0684 1004 //Enable distributor
ganlikun 0:20e0c61e0684 1005 GIC_EnableDistributor();
ganlikun 0:20e0c61e0684 1006 }
ganlikun 0:20e0c61e0684 1007
ganlikun 0:20e0c61e0684 1008 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
ganlikun 0:20e0c61e0684 1009 {
ganlikun 0:20e0c61e0684 1010 IRQn_Type i;
ganlikun 0:20e0c61e0684 1011 uint32_t priority_field;
ganlikun 0:20e0c61e0684 1012
ganlikun 0:20e0c61e0684 1013 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
ganlikun 0:20e0c61e0684 1014 //configuring all of the interrupts as Secure.
ganlikun 0:20e0c61e0684 1015
ganlikun 0:20e0c61e0684 1016 //Disable interrupt forwarding
ganlikun 0:20e0c61e0684 1017 GIC_DisableInterface();
ganlikun 0:20e0c61e0684 1018
ganlikun 0:20e0c61e0684 1019 /* Priority level is implementation defined.
ganlikun 0:20e0c61e0684 1020 To determine the number of priority bits implemented write 0xFF to an ICDIPR
ganlikun 0:20e0c61e0684 1021 priority field and read back the value stored.*/
ganlikun 0:20e0c61e0684 1022 GIC_SetPriority((IRQn_Type)0, 0xff);
ganlikun 0:20e0c61e0684 1023 priority_field = GIC_GetPriority((IRQn_Type)0);
ganlikun 0:20e0c61e0684 1024
ganlikun 0:20e0c61e0684 1025 //SGI and PPI
ganlikun 0:20e0c61e0684 1026 for (i = (IRQn_Type)0; i < 32; i++)
ganlikun 0:20e0c61e0684 1027 {
ganlikun 0:20e0c61e0684 1028 //Set level-sensitive and 1-N model for PPI
ganlikun 0:20e0c61e0684 1029 if(i > 15)
ganlikun 0:20e0c61e0684 1030 GIC_SetLevelModel(i, 0, 1);
ganlikun 0:20e0c61e0684 1031 //Disable SGI and PPI interrupts
ganlikun 0:20e0c61e0684 1032 GIC_DisableIRQ(i);
ganlikun 0:20e0c61e0684 1033 //Set priority
ganlikun 0:20e0c61e0684 1034 GIC_SetPriority(i, priority_field/2);
ganlikun 0:20e0c61e0684 1035 }
ganlikun 0:20e0c61e0684 1036 //Enable interface
ganlikun 0:20e0c61e0684 1037 GIC_EnableInterface();
ganlikun 0:20e0c61e0684 1038 //Set binary point to 0
ganlikun 0:20e0c61e0684 1039 GIC_SetBinaryPoint(0);
ganlikun 0:20e0c61e0684 1040 //Set priority mask
ganlikun 0:20e0c61e0684 1041 GIC_InterfacePriorityMask(0xff);
ganlikun 0:20e0c61e0684 1042 }
ganlikun 0:20e0c61e0684 1043
ganlikun 0:20e0c61e0684 1044 __STATIC_INLINE void GIC_Enable(void)
ganlikun 0:20e0c61e0684 1045 {
ganlikun 0:20e0c61e0684 1046 GIC_DistInit();
ganlikun 0:20e0c61e0684 1047 GIC_CPUInterfaceInit(); //per CPU
ganlikun 0:20e0c61e0684 1048 }
ganlikun 0:20e0c61e0684 1049 #endif
ganlikun 0:20e0c61e0684 1050
ganlikun 0:20e0c61e0684 1051 /* ########################## Generic Timer functions ############################ */
ganlikun 0:20e0c61e0684 1052 #if (__TIM_PRESENT == 1U)
ganlikun 0:20e0c61e0684 1053
ganlikun 0:20e0c61e0684 1054 /* PL1 Physical Timer */
ganlikun 0:20e0c61e0684 1055 #if (__CORTEX_A == 7U)
ganlikun 0:20e0c61e0684 1056 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
ganlikun 0:20e0c61e0684 1057 __set_CNTP_TVAL(value);
ganlikun 0:20e0c61e0684 1058 __ISB();
ganlikun 0:20e0c61e0684 1059 }
ganlikun 0:20e0c61e0684 1060
ganlikun 0:20e0c61e0684 1061 __STATIC_INLINE uint32_t PL1_GetCurrentValue() {
ganlikun 0:20e0c61e0684 1062 return(__get_CNTP_TVAL());
ganlikun 0:20e0c61e0684 1063 }
ganlikun 0:20e0c61e0684 1064
ganlikun 0:20e0c61e0684 1065 __STATIC_INLINE void PL1_SetControl(uint32_t value) {
ganlikun 0:20e0c61e0684 1066 __set_CNTP_CTL(value);
ganlikun 0:20e0c61e0684 1067 __ISB();
ganlikun 0:20e0c61e0684 1068 }
ganlikun 0:20e0c61e0684 1069
ganlikun 0:20e0c61e0684 1070 /* Private Timer */
ganlikun 0:20e0c61e0684 1071 #elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
ganlikun 0:20e0c61e0684 1072 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
ganlikun 0:20e0c61e0684 1073 PTIM->LOAD = value;
ganlikun 0:20e0c61e0684 1074 }
ganlikun 0:20e0c61e0684 1075
ganlikun 0:20e0c61e0684 1076 __STATIC_INLINE uint32_t PTIM_GetLoadValue() {
ganlikun 0:20e0c61e0684 1077 return(PTIM->LOAD);
ganlikun 0:20e0c61e0684 1078 }
ganlikun 0:20e0c61e0684 1079
ganlikun 0:20e0c61e0684 1080 __STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
ganlikun 0:20e0c61e0684 1081 return(PTIM->COUNTER);
ganlikun 0:20e0c61e0684 1082 }
ganlikun 0:20e0c61e0684 1083
ganlikun 0:20e0c61e0684 1084 __STATIC_INLINE void PTIM_SetControl(uint32_t value) {
ganlikun 0:20e0c61e0684 1085 PTIM->CONTROL = value;
ganlikun 0:20e0c61e0684 1086 }
ganlikun 0:20e0c61e0684 1087
ganlikun 0:20e0c61e0684 1088 __STATIC_INLINE uint32_t PTIM_GetControl(void) {
ganlikun 0:20e0c61e0684 1089 return(PTIM->CONTROL);
ganlikun 0:20e0c61e0684 1090 }
ganlikun 0:20e0c61e0684 1091
ganlikun 0:20e0c61e0684 1092 __STATIC_INLINE void PTIM_ClearEventFlag(void) {
ganlikun 0:20e0c61e0684 1093 PTIM->ISR = 1;
ganlikun 0:20e0c61e0684 1094 }
ganlikun 0:20e0c61e0684 1095 #endif
ganlikun 0:20e0c61e0684 1096 #endif
ganlikun 0:20e0c61e0684 1097
ganlikun 0:20e0c61e0684 1098 /* ########################## MMU functions ###################################### */
ganlikun 0:20e0c61e0684 1099
ganlikun 0:20e0c61e0684 1100 #define SECTION_DESCRIPTOR (0x2)
ganlikun 0:20e0c61e0684 1101 #define SECTION_MASK (0xFFFFFFFC)
ganlikun 0:20e0c61e0684 1102
ganlikun 0:20e0c61e0684 1103 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
ganlikun 0:20e0c61e0684 1104 #define SECTION_B_SHIFT (2)
ganlikun 0:20e0c61e0684 1105 #define SECTION_C_SHIFT (3)
ganlikun 0:20e0c61e0684 1106 #define SECTION_TEX0_SHIFT (12)
ganlikun 0:20e0c61e0684 1107 #define SECTION_TEX1_SHIFT (13)
ganlikun 0:20e0c61e0684 1108 #define SECTION_TEX2_SHIFT (14)
ganlikun 0:20e0c61e0684 1109
ganlikun 0:20e0c61e0684 1110 #define SECTION_XN_MASK (0xFFFFFFEF)
ganlikun 0:20e0c61e0684 1111 #define SECTION_XN_SHIFT (4)
ganlikun 0:20e0c61e0684 1112
ganlikun 0:20e0c61e0684 1113 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
ganlikun 0:20e0c61e0684 1114 #define SECTION_DOMAIN_SHIFT (5)
ganlikun 0:20e0c61e0684 1115
ganlikun 0:20e0c61e0684 1116 #define SECTION_P_MASK (0xFFFFFDFF)
ganlikun 0:20e0c61e0684 1117 #define SECTION_P_SHIFT (9)
ganlikun 0:20e0c61e0684 1118
ganlikun 0:20e0c61e0684 1119 #define SECTION_AP_MASK (0xFFFF73FF)
ganlikun 0:20e0c61e0684 1120 #define SECTION_AP_SHIFT (10)
ganlikun 0:20e0c61e0684 1121 #define SECTION_AP2_SHIFT (15)
ganlikun 0:20e0c61e0684 1122
ganlikun 0:20e0c61e0684 1123 #define SECTION_S_MASK (0xFFFEFFFF)
ganlikun 0:20e0c61e0684 1124 #define SECTION_S_SHIFT (16)
ganlikun 0:20e0c61e0684 1125
ganlikun 0:20e0c61e0684 1126 #define SECTION_NG_MASK (0xFFFDFFFF)
ganlikun 0:20e0c61e0684 1127 #define SECTION_NG_SHIFT (17)
ganlikun 0:20e0c61e0684 1128
ganlikun 0:20e0c61e0684 1129 #define SECTION_NS_MASK (0xFFF7FFFF)
ganlikun 0:20e0c61e0684 1130 #define SECTION_NS_SHIFT (19)
ganlikun 0:20e0c61e0684 1131
ganlikun 0:20e0c61e0684 1132 #define PAGE_L1_DESCRIPTOR (0x1)
ganlikun 0:20e0c61e0684 1133 #define PAGE_L1_MASK (0xFFFFFFFC)
ganlikun 0:20e0c61e0684 1134
ganlikun 0:20e0c61e0684 1135 #define PAGE_L2_4K_DESC (0x2)
ganlikun 0:20e0c61e0684 1136 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
ganlikun 0:20e0c61e0684 1137
ganlikun 0:20e0c61e0684 1138 #define PAGE_L2_64K_DESC (0x1)
ganlikun 0:20e0c61e0684 1139 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
ganlikun 0:20e0c61e0684 1140
ganlikun 0:20e0c61e0684 1141 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
ganlikun 0:20e0c61e0684 1142 #define PAGE_4K_B_SHIFT (2)
ganlikun 0:20e0c61e0684 1143 #define PAGE_4K_C_SHIFT (3)
ganlikun 0:20e0c61e0684 1144 #define PAGE_4K_TEX0_SHIFT (6)
ganlikun 0:20e0c61e0684 1145 #define PAGE_4K_TEX1_SHIFT (7)
ganlikun 0:20e0c61e0684 1146 #define PAGE_4K_TEX2_SHIFT (8)
ganlikun 0:20e0c61e0684 1147
ganlikun 0:20e0c61e0684 1148 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
ganlikun 0:20e0c61e0684 1149 #define PAGE_64K_B_SHIFT (2)
ganlikun 0:20e0c61e0684 1150 #define PAGE_64K_C_SHIFT (3)
ganlikun 0:20e0c61e0684 1151 #define PAGE_64K_TEX0_SHIFT (12)
ganlikun 0:20e0c61e0684 1152 #define PAGE_64K_TEX1_SHIFT (13)
ganlikun 0:20e0c61e0684 1153 #define PAGE_64K_TEX2_SHIFT (14)
ganlikun 0:20e0c61e0684 1154
ganlikun 0:20e0c61e0684 1155 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
ganlikun 0:20e0c61e0684 1156 #define PAGE_B_SHIFT (2)
ganlikun 0:20e0c61e0684 1157 #define PAGE_C_SHIFT (3)
ganlikun 0:20e0c61e0684 1158 #define PAGE_TEX_SHIFT (12)
ganlikun 0:20e0c61e0684 1159
ganlikun 0:20e0c61e0684 1160 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
ganlikun 0:20e0c61e0684 1161 #define PAGE_XN_4K_SHIFT (0)
ganlikun 0:20e0c61e0684 1162 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
ganlikun 0:20e0c61e0684 1163 #define PAGE_XN_64K_SHIFT (15)
ganlikun 0:20e0c61e0684 1164
ganlikun 0:20e0c61e0684 1165 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
ganlikun 0:20e0c61e0684 1166 #define PAGE_DOMAIN_SHIFT (5)
ganlikun 0:20e0c61e0684 1167
ganlikun 0:20e0c61e0684 1168 #define PAGE_P_MASK (0xFFFFFDFF)
ganlikun 0:20e0c61e0684 1169 #define PAGE_P_SHIFT (9)
ganlikun 0:20e0c61e0684 1170
ganlikun 0:20e0c61e0684 1171 #define PAGE_AP_MASK (0xFFFFFDCF)
ganlikun 0:20e0c61e0684 1172 #define PAGE_AP_SHIFT (4)
ganlikun 0:20e0c61e0684 1173 #define PAGE_AP2_SHIFT (9)
ganlikun 0:20e0c61e0684 1174
ganlikun 0:20e0c61e0684 1175 #define PAGE_S_MASK (0xFFFFFBFF)
ganlikun 0:20e0c61e0684 1176 #define PAGE_S_SHIFT (10)
ganlikun 0:20e0c61e0684 1177
ganlikun 0:20e0c61e0684 1178 #define PAGE_NG_MASK (0xFFFFF7FF)
ganlikun 0:20e0c61e0684 1179 #define PAGE_NG_SHIFT (11)
ganlikun 0:20e0c61e0684 1180
ganlikun 0:20e0c61e0684 1181 #define PAGE_NS_MASK (0xFFFFFFF7)
ganlikun 0:20e0c61e0684 1182 #define PAGE_NS_SHIFT (3)
ganlikun 0:20e0c61e0684 1183
ganlikun 0:20e0c61e0684 1184 #define OFFSET_1M (0x00100000)
ganlikun 0:20e0c61e0684 1185 #define OFFSET_64K (0x00010000)
ganlikun 0:20e0c61e0684 1186 #define OFFSET_4K (0x00001000)
ganlikun 0:20e0c61e0684 1187
ganlikun 0:20e0c61e0684 1188 #define DESCRIPTOR_FAULT (0x00000000)
ganlikun 0:20e0c61e0684 1189
ganlikun 0:20e0c61e0684 1190 /* Attributes enumerations */
ganlikun 0:20e0c61e0684 1191
ganlikun 0:20e0c61e0684 1192 /* Region size attributes */
ganlikun 0:20e0c61e0684 1193 typedef enum
ganlikun 0:20e0c61e0684 1194 {
ganlikun 0:20e0c61e0684 1195 SECTION,
ganlikun 0:20e0c61e0684 1196 PAGE_4k,
ganlikun 0:20e0c61e0684 1197 PAGE_64k,
ganlikun 0:20e0c61e0684 1198 } mmu_region_size_Type;
ganlikun 0:20e0c61e0684 1199
ganlikun 0:20e0c61e0684 1200 /* Region type attributes */
ganlikun 0:20e0c61e0684 1201 typedef enum
ganlikun 0:20e0c61e0684 1202 {
ganlikun 0:20e0c61e0684 1203 NORMAL,
ganlikun 0:20e0c61e0684 1204 DEVICE,
ganlikun 0:20e0c61e0684 1205 SHARED_DEVICE,
ganlikun 0:20e0c61e0684 1206 NON_SHARED_DEVICE,
ganlikun 0:20e0c61e0684 1207 STRONGLY_ORDERED
ganlikun 0:20e0c61e0684 1208 } mmu_memory_Type;
ganlikun 0:20e0c61e0684 1209
ganlikun 0:20e0c61e0684 1210 /* Region cacheability attributes */
ganlikun 0:20e0c61e0684 1211 typedef enum
ganlikun 0:20e0c61e0684 1212 {
ganlikun 0:20e0c61e0684 1213 NON_CACHEABLE,
ganlikun 0:20e0c61e0684 1214 WB_WA,
ganlikun 0:20e0c61e0684 1215 WT,
ganlikun 0:20e0c61e0684 1216 WB_NO_WA,
ganlikun 0:20e0c61e0684 1217 } mmu_cacheability_Type;
ganlikun 0:20e0c61e0684 1218
ganlikun 0:20e0c61e0684 1219 /* Region parity check attributes */
ganlikun 0:20e0c61e0684 1220 typedef enum
ganlikun 0:20e0c61e0684 1221 {
ganlikun 0:20e0c61e0684 1222 ECC_DISABLED,
ganlikun 0:20e0c61e0684 1223 ECC_ENABLED,
ganlikun 0:20e0c61e0684 1224 } mmu_ecc_check_Type;
ganlikun 0:20e0c61e0684 1225
ganlikun 0:20e0c61e0684 1226 /* Region execution attributes */
ganlikun 0:20e0c61e0684 1227 typedef enum
ganlikun 0:20e0c61e0684 1228 {
ganlikun 0:20e0c61e0684 1229 EXECUTE,
ganlikun 0:20e0c61e0684 1230 NON_EXECUTE,
ganlikun 0:20e0c61e0684 1231 } mmu_execute_Type;
ganlikun 0:20e0c61e0684 1232
ganlikun 0:20e0c61e0684 1233 /* Region global attributes */
ganlikun 0:20e0c61e0684 1234 typedef enum
ganlikun 0:20e0c61e0684 1235 {
ganlikun 0:20e0c61e0684 1236 GLOBAL,
ganlikun 0:20e0c61e0684 1237 NON_GLOBAL,
ganlikun 0:20e0c61e0684 1238 } mmu_global_Type;
ganlikun 0:20e0c61e0684 1239
ganlikun 0:20e0c61e0684 1240 /* Region shareability attributes */
ganlikun 0:20e0c61e0684 1241 typedef enum
ganlikun 0:20e0c61e0684 1242 {
ganlikun 0:20e0c61e0684 1243 NON_SHARED,
ganlikun 0:20e0c61e0684 1244 SHARED,
ganlikun 0:20e0c61e0684 1245 } mmu_shared_Type;
ganlikun 0:20e0c61e0684 1246
ganlikun 0:20e0c61e0684 1247 /* Region security attributes */
ganlikun 0:20e0c61e0684 1248 typedef enum
ganlikun 0:20e0c61e0684 1249 {
ganlikun 0:20e0c61e0684 1250 SECURE,
ganlikun 0:20e0c61e0684 1251 NON_SECURE,
ganlikun 0:20e0c61e0684 1252 } mmu_secure_Type;
ganlikun 0:20e0c61e0684 1253
ganlikun 0:20e0c61e0684 1254 /* Region access attributes */
ganlikun 0:20e0c61e0684 1255 typedef enum
ganlikun 0:20e0c61e0684 1256 {
ganlikun 0:20e0c61e0684 1257 NO_ACCESS,
ganlikun 0:20e0c61e0684 1258 RW,
ganlikun 0:20e0c61e0684 1259 READ,
ganlikun 0:20e0c61e0684 1260 } mmu_access_Type;
ganlikun 0:20e0c61e0684 1261
ganlikun 0:20e0c61e0684 1262 /* Memory Region definition */
ganlikun 0:20e0c61e0684 1263 typedef struct RegionStruct {
ganlikun 0:20e0c61e0684 1264 mmu_region_size_Type rg_t;
ganlikun 0:20e0c61e0684 1265 mmu_memory_Type mem_t;
ganlikun 0:20e0c61e0684 1266 uint8_t domain;
ganlikun 0:20e0c61e0684 1267 mmu_cacheability_Type inner_norm_t;
ganlikun 0:20e0c61e0684 1268 mmu_cacheability_Type outer_norm_t;
ganlikun 0:20e0c61e0684 1269 mmu_ecc_check_Type e_t;
ganlikun 0:20e0c61e0684 1270 mmu_execute_Type xn_t;
ganlikun 0:20e0c61e0684 1271 mmu_global_Type g_t;
ganlikun 0:20e0c61e0684 1272 mmu_secure_Type sec_t;
ganlikun 0:20e0c61e0684 1273 mmu_access_Type priv_t;
ganlikun 0:20e0c61e0684 1274 mmu_access_Type user_t;
ganlikun 0:20e0c61e0684 1275 mmu_shared_Type sh_t;
ganlikun 0:20e0c61e0684 1276
ganlikun 0:20e0c61e0684 1277 } mmu_region_attributes_Type;
ganlikun 0:20e0c61e0684 1278
ganlikun 0:20e0c61e0684 1279 //Following macros define the descriptors and attributes
ganlikun 0:20e0c61e0684 1280 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
ganlikun 0:20e0c61e0684 1281 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
ganlikun 0:20e0c61e0684 1282 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1283 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1284 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1285 region.inner_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1286 region.outer_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1287 region.mem_t = NORMAL; \
ganlikun 0:20e0c61e0684 1288 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1289 region.xn_t = EXECUTE; \
ganlikun 0:20e0c61e0684 1290 region.priv_t = RW; \
ganlikun 0:20e0c61e0684 1291 region.user_t = RW; \
ganlikun 0:20e0c61e0684 1292 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1293 MMU_GetSectionDescriptor(&descriptor_l1, region);
ganlikun 0:20e0c61e0684 1294
ganlikun 0:20e0c61e0684 1295 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
ganlikun 0:20e0c61e0684 1296 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
ganlikun 0:20e0c61e0684 1297 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1298 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1299 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1300 region.inner_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1301 region.outer_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1302 region.mem_t = NORMAL; \
ganlikun 0:20e0c61e0684 1303 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1304 region.xn_t = EXECUTE; \
ganlikun 0:20e0c61e0684 1305 region.priv_t = READ; \
ganlikun 0:20e0c61e0684 1306 region.user_t = READ; \
ganlikun 0:20e0c61e0684 1307 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1308 MMU_GetSectionDescriptor(&descriptor_l1, region);
ganlikun 0:20e0c61e0684 1309
ganlikun 0:20e0c61e0684 1310 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
ganlikun 0:20e0c61e0684 1311 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
ganlikun 0:20e0c61e0684 1312 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1313 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1314 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1315 region.inner_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1316 region.outer_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1317 region.mem_t = NORMAL; \
ganlikun 0:20e0c61e0684 1318 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1319 region.xn_t = NON_EXECUTE; \
ganlikun 0:20e0c61e0684 1320 region.priv_t = READ; \
ganlikun 0:20e0c61e0684 1321 region.user_t = READ; \
ganlikun 0:20e0c61e0684 1322 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1323 MMU_GetSectionDescriptor(&descriptor_l1, region);
ganlikun 0:20e0c61e0684 1324
ganlikun 0:20e0c61e0684 1325 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
ganlikun 0:20e0c61e0684 1326 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
ganlikun 0:20e0c61e0684 1327 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1328 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1329 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1330 region.inner_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1331 region.outer_norm_t = WB_WA; \
ganlikun 0:20e0c61e0684 1332 region.mem_t = NORMAL; \
ganlikun 0:20e0c61e0684 1333 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1334 region.xn_t = NON_EXECUTE; \
ganlikun 0:20e0c61e0684 1335 region.priv_t = RW; \
ganlikun 0:20e0c61e0684 1336 region.user_t = RW; \
ganlikun 0:20e0c61e0684 1337 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1338 MMU_GetSectionDescriptor(&descriptor_l1, region);
ganlikun 0:20e0c61e0684 1339 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
ganlikun 0:20e0c61e0684 1340 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
ganlikun 0:20e0c61e0684 1341 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1342 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1343 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1344 region.inner_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1345 region.outer_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1346 region.mem_t = STRONGLY_ORDERED; \
ganlikun 0:20e0c61e0684 1347 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1348 region.xn_t = NON_EXECUTE; \
ganlikun 0:20e0c61e0684 1349 region.priv_t = RW; \
ganlikun 0:20e0c61e0684 1350 region.user_t = RW; \
ganlikun 0:20e0c61e0684 1351 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1352 MMU_GetSectionDescriptor(&descriptor_l1, region);
ganlikun 0:20e0c61e0684 1353
ganlikun 0:20e0c61e0684 1354 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
ganlikun 0:20e0c61e0684 1355 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
ganlikun 0:20e0c61e0684 1356 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1357 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1358 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1359 region.inner_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1360 region.outer_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1361 region.mem_t = STRONGLY_ORDERED; \
ganlikun 0:20e0c61e0684 1362 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1363 region.xn_t = NON_EXECUTE; \
ganlikun 0:20e0c61e0684 1364 region.priv_t = READ; \
ganlikun 0:20e0c61e0684 1365 region.user_t = READ; \
ganlikun 0:20e0c61e0684 1366 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1367 MMU_GetSectionDescriptor(&descriptor_l1, region);
ganlikun 0:20e0c61e0684 1368
ganlikun 0:20e0c61e0684 1369 //Sect_Device_RW. Sect_Device_RO, but writeable
ganlikun 0:20e0c61e0684 1370 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
ganlikun 0:20e0c61e0684 1371 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1372 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1373 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1374 region.inner_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1375 region.outer_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1376 region.mem_t = STRONGLY_ORDERED; \
ganlikun 0:20e0c61e0684 1377 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1378 region.xn_t = NON_EXECUTE; \
ganlikun 0:20e0c61e0684 1379 region.priv_t = RW; \
ganlikun 0:20e0c61e0684 1380 region.user_t = RW; \
ganlikun 0:20e0c61e0684 1381 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1382 MMU_GetSectionDescriptor(&descriptor_l1, region);
ganlikun 0:20e0c61e0684 1383 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
ganlikun 0:20e0c61e0684 1384 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
ganlikun 0:20e0c61e0684 1385 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1386 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1387 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1388 region.inner_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1389 region.outer_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1390 region.mem_t = SHARED_DEVICE; \
ganlikun 0:20e0c61e0684 1391 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1392 region.xn_t = NON_EXECUTE; \
ganlikun 0:20e0c61e0684 1393 region.priv_t = RW; \
ganlikun 0:20e0c61e0684 1394 region.user_t = RW; \
ganlikun 0:20e0c61e0684 1395 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1396 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
ganlikun 0:20e0c61e0684 1397
ganlikun 0:20e0c61e0684 1398 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
ganlikun 0:20e0c61e0684 1399 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
ganlikun 0:20e0c61e0684 1400 region.domain = 0x0; \
ganlikun 0:20e0c61e0684 1401 region.e_t = ECC_DISABLED; \
ganlikun 0:20e0c61e0684 1402 region.g_t = GLOBAL; \
ganlikun 0:20e0c61e0684 1403 region.inner_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1404 region.outer_norm_t = NON_CACHEABLE; \
ganlikun 0:20e0c61e0684 1405 region.mem_t = SHARED_DEVICE; \
ganlikun 0:20e0c61e0684 1406 region.sec_t = SECURE; \
ganlikun 0:20e0c61e0684 1407 region.xn_t = NON_EXECUTE; \
ganlikun 0:20e0c61e0684 1408 region.priv_t = RW; \
ganlikun 0:20e0c61e0684 1409 region.user_t = RW; \
ganlikun 0:20e0c61e0684 1410 region.sh_t = NON_SHARED; \
ganlikun 0:20e0c61e0684 1411 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
ganlikun 0:20e0c61e0684 1412
ganlikun 0:20e0c61e0684 1413 /** \brief Set section execution-never attribute
ganlikun 0:20e0c61e0684 1414
ganlikun 0:20e0c61e0684 1415 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1416 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
ganlikun 0:20e0c61e0684 1417
ganlikun 0:20e0c61e0684 1418 \return 0
ganlikun 0:20e0c61e0684 1419 */
ganlikun 0:20e0c61e0684 1420 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
ganlikun 0:20e0c61e0684 1421 {
ganlikun 0:20e0c61e0684 1422 *descriptor_l1 &= SECTION_XN_MASK;
ganlikun 0:20e0c61e0684 1423 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
ganlikun 0:20e0c61e0684 1424 return 0;
ganlikun 0:20e0c61e0684 1425 }
ganlikun 0:20e0c61e0684 1426
ganlikun 0:20e0c61e0684 1427 /** \brief Set section domain
ganlikun 0:20e0c61e0684 1428
ganlikun 0:20e0c61e0684 1429 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1430 \param [in] domain Section domain
ganlikun 0:20e0c61e0684 1431
ganlikun 0:20e0c61e0684 1432 \return 0
ganlikun 0:20e0c61e0684 1433 */
ganlikun 0:20e0c61e0684 1434 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
ganlikun 0:20e0c61e0684 1435 {
ganlikun 0:20e0c61e0684 1436 *descriptor_l1 &= SECTION_DOMAIN_MASK;
ganlikun 0:20e0c61e0684 1437 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
ganlikun 0:20e0c61e0684 1438 return 0;
ganlikun 0:20e0c61e0684 1439 }
ganlikun 0:20e0c61e0684 1440
ganlikun 0:20e0c61e0684 1441 /** \brief Set section parity check
ganlikun 0:20e0c61e0684 1442
ganlikun 0:20e0c61e0684 1443 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1444 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
ganlikun 0:20e0c61e0684 1445
ganlikun 0:20e0c61e0684 1446 \return 0
ganlikun 0:20e0c61e0684 1447 */
ganlikun 0:20e0c61e0684 1448 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
ganlikun 0:20e0c61e0684 1449 {
ganlikun 0:20e0c61e0684 1450 *descriptor_l1 &= SECTION_P_MASK;
ganlikun 0:20e0c61e0684 1451 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
ganlikun 0:20e0c61e0684 1452 return 0;
ganlikun 0:20e0c61e0684 1453 }
ganlikun 0:20e0c61e0684 1454
ganlikun 0:20e0c61e0684 1455 /** \brief Set section access privileges
ganlikun 0:20e0c61e0684 1456
ganlikun 0:20e0c61e0684 1457 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1458 \param [in] user User Level Access: NO_ACCESS, RW, READ
ganlikun 0:20e0c61e0684 1459 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
ganlikun 0:20e0c61e0684 1460 \param [in] afe Access flag enable
ganlikun 0:20e0c61e0684 1461
ganlikun 0:20e0c61e0684 1462 \return 0
ganlikun 0:20e0c61e0684 1463 */
ganlikun 0:20e0c61e0684 1464 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
ganlikun 0:20e0c61e0684 1465 {
ganlikun 0:20e0c61e0684 1466 uint32_t ap = 0;
ganlikun 0:20e0c61e0684 1467
ganlikun 0:20e0c61e0684 1468 if (afe == 0) { //full access
ganlikun 0:20e0c61e0684 1469 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
ganlikun 0:20e0c61e0684 1470 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
ganlikun 0:20e0c61e0684 1471 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
ganlikun 0:20e0c61e0684 1472 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
ganlikun 0:20e0c61e0684 1473 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
ganlikun 0:20e0c61e0684 1474 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
ganlikun 0:20e0c61e0684 1475 }
ganlikun 0:20e0c61e0684 1476
ganlikun 0:20e0c61e0684 1477 else { //Simplified access
ganlikun 0:20e0c61e0684 1478 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
ganlikun 0:20e0c61e0684 1479 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
ganlikun 0:20e0c61e0684 1480 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
ganlikun 0:20e0c61e0684 1481 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
ganlikun 0:20e0c61e0684 1482 }
ganlikun 0:20e0c61e0684 1483
ganlikun 0:20e0c61e0684 1484 *descriptor_l1 &= SECTION_AP_MASK;
ganlikun 0:20e0c61e0684 1485 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
ganlikun 0:20e0c61e0684 1486 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
ganlikun 0:20e0c61e0684 1487
ganlikun 0:20e0c61e0684 1488 return 0;
ganlikun 0:20e0c61e0684 1489 }
ganlikun 0:20e0c61e0684 1490
ganlikun 0:20e0c61e0684 1491 /** \brief Set section shareability
ganlikun 0:20e0c61e0684 1492
ganlikun 0:20e0c61e0684 1493 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1494 \param [in] s_bit Section shareability: NON_SHARED, SHARED
ganlikun 0:20e0c61e0684 1495
ganlikun 0:20e0c61e0684 1496 \return 0
ganlikun 0:20e0c61e0684 1497 */
ganlikun 0:20e0c61e0684 1498 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
ganlikun 0:20e0c61e0684 1499 {
ganlikun 0:20e0c61e0684 1500 *descriptor_l1 &= SECTION_S_MASK;
ganlikun 0:20e0c61e0684 1501 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
ganlikun 0:20e0c61e0684 1502 return 0;
ganlikun 0:20e0c61e0684 1503 }
ganlikun 0:20e0c61e0684 1504
ganlikun 0:20e0c61e0684 1505 /** \brief Set section Global attribute
ganlikun 0:20e0c61e0684 1506
ganlikun 0:20e0c61e0684 1507 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1508 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
ganlikun 0:20e0c61e0684 1509
ganlikun 0:20e0c61e0684 1510 \return 0
ganlikun 0:20e0c61e0684 1511 */
ganlikun 0:20e0c61e0684 1512 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
ganlikun 0:20e0c61e0684 1513 {
ganlikun 0:20e0c61e0684 1514 *descriptor_l1 &= SECTION_NG_MASK;
ganlikun 0:20e0c61e0684 1515 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
ganlikun 0:20e0c61e0684 1516 return 0;
ganlikun 0:20e0c61e0684 1517 }
ganlikun 0:20e0c61e0684 1518
ganlikun 0:20e0c61e0684 1519 /** \brief Set section Security attribute
ganlikun 0:20e0c61e0684 1520
ganlikun 0:20e0c61e0684 1521 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1522 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
ganlikun 0:20e0c61e0684 1523
ganlikun 0:20e0c61e0684 1524 \return 0
ganlikun 0:20e0c61e0684 1525 */
ganlikun 0:20e0c61e0684 1526 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
ganlikun 0:20e0c61e0684 1527 {
ganlikun 0:20e0c61e0684 1528 *descriptor_l1 &= SECTION_NS_MASK;
ganlikun 0:20e0c61e0684 1529 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
ganlikun 0:20e0c61e0684 1530 return 0;
ganlikun 0:20e0c61e0684 1531 }
ganlikun 0:20e0c61e0684 1532
ganlikun 0:20e0c61e0684 1533 /* Page 4k or 64k */
ganlikun 0:20e0c61e0684 1534 /** \brief Set 4k/64k page execution-never attribute
ganlikun 0:20e0c61e0684 1535
ganlikun 0:20e0c61e0684 1536 \param [out] descriptor_l2 L2 descriptor.
ganlikun 0:20e0c61e0684 1537 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
ganlikun 0:20e0c61e0684 1538 \param [in] page Page size: PAGE_4k, PAGE_64k,
ganlikun 0:20e0c61e0684 1539
ganlikun 0:20e0c61e0684 1540 \return 0
ganlikun 0:20e0c61e0684 1541 */
ganlikun 0:20e0c61e0684 1542 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
ganlikun 0:20e0c61e0684 1543 {
ganlikun 0:20e0c61e0684 1544 if (page == PAGE_4k)
ganlikun 0:20e0c61e0684 1545 {
ganlikun 0:20e0c61e0684 1546 *descriptor_l2 &= PAGE_XN_4K_MASK;
ganlikun 0:20e0c61e0684 1547 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
ganlikun 0:20e0c61e0684 1548 }
ganlikun 0:20e0c61e0684 1549 else
ganlikun 0:20e0c61e0684 1550 {
ganlikun 0:20e0c61e0684 1551 *descriptor_l2 &= PAGE_XN_64K_MASK;
ganlikun 0:20e0c61e0684 1552 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
ganlikun 0:20e0c61e0684 1553 }
ganlikun 0:20e0c61e0684 1554 return 0;
ganlikun 0:20e0c61e0684 1555 }
ganlikun 0:20e0c61e0684 1556
ganlikun 0:20e0c61e0684 1557 /** \brief Set 4k/64k page domain
ganlikun 0:20e0c61e0684 1558
ganlikun 0:20e0c61e0684 1559 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1560 \param [in] domain Page domain
ganlikun 0:20e0c61e0684 1561
ganlikun 0:20e0c61e0684 1562 \return 0
ganlikun 0:20e0c61e0684 1563 */
ganlikun 0:20e0c61e0684 1564 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
ganlikun 0:20e0c61e0684 1565 {
ganlikun 0:20e0c61e0684 1566 *descriptor_l1 &= PAGE_DOMAIN_MASK;
ganlikun 0:20e0c61e0684 1567 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
ganlikun 0:20e0c61e0684 1568 return 0;
ganlikun 0:20e0c61e0684 1569 }
ganlikun 0:20e0c61e0684 1570
ganlikun 0:20e0c61e0684 1571 /** \brief Set 4k/64k page parity check
ganlikun 0:20e0c61e0684 1572
ganlikun 0:20e0c61e0684 1573 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1574 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
ganlikun 0:20e0c61e0684 1575
ganlikun 0:20e0c61e0684 1576 \return 0
ganlikun 0:20e0c61e0684 1577 */
ganlikun 0:20e0c61e0684 1578 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
ganlikun 0:20e0c61e0684 1579 {
ganlikun 0:20e0c61e0684 1580 *descriptor_l1 &= SECTION_P_MASK;
ganlikun 0:20e0c61e0684 1581 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
ganlikun 0:20e0c61e0684 1582 return 0;
ganlikun 0:20e0c61e0684 1583 }
ganlikun 0:20e0c61e0684 1584
ganlikun 0:20e0c61e0684 1585 /** \brief Set 4k/64k page access privileges
ganlikun 0:20e0c61e0684 1586
ganlikun 0:20e0c61e0684 1587 \param [out] descriptor_l2 L2 descriptor.
ganlikun 0:20e0c61e0684 1588 \param [in] user User Level Access: NO_ACCESS, RW, READ
ganlikun 0:20e0c61e0684 1589 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
ganlikun 0:20e0c61e0684 1590 \param [in] afe Access flag enable
ganlikun 0:20e0c61e0684 1591
ganlikun 0:20e0c61e0684 1592 \return 0
ganlikun 0:20e0c61e0684 1593 */
ganlikun 0:20e0c61e0684 1594 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
ganlikun 0:20e0c61e0684 1595 {
ganlikun 0:20e0c61e0684 1596 uint32_t ap = 0;
ganlikun 0:20e0c61e0684 1597
ganlikun 0:20e0c61e0684 1598 if (afe == 0) { //full access
ganlikun 0:20e0c61e0684 1599 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
ganlikun 0:20e0c61e0684 1600 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
ganlikun 0:20e0c61e0684 1601 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
ganlikun 0:20e0c61e0684 1602 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
ganlikun 0:20e0c61e0684 1603 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
ganlikun 0:20e0c61e0684 1604 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
ganlikun 0:20e0c61e0684 1605 }
ganlikun 0:20e0c61e0684 1606
ganlikun 0:20e0c61e0684 1607 else { //Simplified access
ganlikun 0:20e0c61e0684 1608 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
ganlikun 0:20e0c61e0684 1609 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
ganlikun 0:20e0c61e0684 1610 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
ganlikun 0:20e0c61e0684 1611 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
ganlikun 0:20e0c61e0684 1612 }
ganlikun 0:20e0c61e0684 1613
ganlikun 0:20e0c61e0684 1614 *descriptor_l2 &= PAGE_AP_MASK;
ganlikun 0:20e0c61e0684 1615 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
ganlikun 0:20e0c61e0684 1616 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
ganlikun 0:20e0c61e0684 1617
ganlikun 0:20e0c61e0684 1618 return 0;
ganlikun 0:20e0c61e0684 1619 }
ganlikun 0:20e0c61e0684 1620
ganlikun 0:20e0c61e0684 1621 /** \brief Set 4k/64k page shareability
ganlikun 0:20e0c61e0684 1622
ganlikun 0:20e0c61e0684 1623 \param [out] descriptor_l2 L2 descriptor.
ganlikun 0:20e0c61e0684 1624 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
ganlikun 0:20e0c61e0684 1625
ganlikun 0:20e0c61e0684 1626 \return 0
ganlikun 0:20e0c61e0684 1627 */
ganlikun 0:20e0c61e0684 1628 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
ganlikun 0:20e0c61e0684 1629 {
ganlikun 0:20e0c61e0684 1630 *descriptor_l2 &= PAGE_S_MASK;
ganlikun 0:20e0c61e0684 1631 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
ganlikun 0:20e0c61e0684 1632 return 0;
ganlikun 0:20e0c61e0684 1633 }
ganlikun 0:20e0c61e0684 1634
ganlikun 0:20e0c61e0684 1635 /** \brief Set 4k/64k page Global attribute
ganlikun 0:20e0c61e0684 1636
ganlikun 0:20e0c61e0684 1637 \param [out] descriptor_l2 L2 descriptor.
ganlikun 0:20e0c61e0684 1638 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
ganlikun 0:20e0c61e0684 1639
ganlikun 0:20e0c61e0684 1640 \return 0
ganlikun 0:20e0c61e0684 1641 */
ganlikun 0:20e0c61e0684 1642 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
ganlikun 0:20e0c61e0684 1643 {
ganlikun 0:20e0c61e0684 1644 *descriptor_l2 &= PAGE_NG_MASK;
ganlikun 0:20e0c61e0684 1645 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
ganlikun 0:20e0c61e0684 1646 return 0;
ganlikun 0:20e0c61e0684 1647 }
ganlikun 0:20e0c61e0684 1648
ganlikun 0:20e0c61e0684 1649 /** \brief Set 4k/64k page Security attribute
ganlikun 0:20e0c61e0684 1650
ganlikun 0:20e0c61e0684 1651 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1652 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
ganlikun 0:20e0c61e0684 1653
ganlikun 0:20e0c61e0684 1654 \return 0
ganlikun 0:20e0c61e0684 1655 */
ganlikun 0:20e0c61e0684 1656 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
ganlikun 0:20e0c61e0684 1657 {
ganlikun 0:20e0c61e0684 1658 *descriptor_l1 &= PAGE_NS_MASK;
ganlikun 0:20e0c61e0684 1659 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
ganlikun 0:20e0c61e0684 1660 return 0;
ganlikun 0:20e0c61e0684 1661 }
ganlikun 0:20e0c61e0684 1662
ganlikun 0:20e0c61e0684 1663 /** \brief Set Section memory attributes
ganlikun 0:20e0c61e0684 1664
ganlikun 0:20e0c61e0684 1665 \param [out] descriptor_l1 L1 descriptor.
ganlikun 0:20e0c61e0684 1666 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
ganlikun 0:20e0c61e0684 1667 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
ganlikun 0:20e0c61e0684 1668 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
ganlikun 0:20e0c61e0684 1669
ganlikun 0:20e0c61e0684 1670 \return 0
ganlikun 0:20e0c61e0684 1671 */
ganlikun 0:20e0c61e0684 1672 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
ganlikun 0:20e0c61e0684 1673 {
ganlikun 0:20e0c61e0684 1674 *descriptor_l1 &= SECTION_TEXCB_MASK;
ganlikun 0:20e0c61e0684 1675
ganlikun 0:20e0c61e0684 1676 if (STRONGLY_ORDERED == mem)
ganlikun 0:20e0c61e0684 1677 {
ganlikun 0:20e0c61e0684 1678 return 0;
ganlikun 0:20e0c61e0684 1679 }
ganlikun 0:20e0c61e0684 1680 else if (SHARED_DEVICE == mem)
ganlikun 0:20e0c61e0684 1681 {
ganlikun 0:20e0c61e0684 1682 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
ganlikun 0:20e0c61e0684 1683 }
ganlikun 0:20e0c61e0684 1684 else if (NON_SHARED_DEVICE == mem)
ganlikun 0:20e0c61e0684 1685 {
ganlikun 0:20e0c61e0684 1686 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
ganlikun 0:20e0c61e0684 1687 }
ganlikun 0:20e0c61e0684 1688 else if (NORMAL == mem)
ganlikun 0:20e0c61e0684 1689 {
ganlikun 0:20e0c61e0684 1690 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
ganlikun 0:20e0c61e0684 1691 switch(inner)
ganlikun 0:20e0c61e0684 1692 {
ganlikun 0:20e0c61e0684 1693 case NON_CACHEABLE:
ganlikun 0:20e0c61e0684 1694 break;
ganlikun 0:20e0c61e0684 1695 case WB_WA:
ganlikun 0:20e0c61e0684 1696 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
ganlikun 0:20e0c61e0684 1697 break;
ganlikun 0:20e0c61e0684 1698 case WT:
ganlikun 0:20e0c61e0684 1699 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
ganlikun 0:20e0c61e0684 1700 break;
ganlikun 0:20e0c61e0684 1701 case WB_NO_WA:
ganlikun 0:20e0c61e0684 1702 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
ganlikun 0:20e0c61e0684 1703 break;
ganlikun 0:20e0c61e0684 1704 }
ganlikun 0:20e0c61e0684 1705 switch(outer)
ganlikun 0:20e0c61e0684 1706 {
ganlikun 0:20e0c61e0684 1707 case NON_CACHEABLE:
ganlikun 0:20e0c61e0684 1708 break;
ganlikun 0:20e0c61e0684 1709 case WB_WA:
ganlikun 0:20e0c61e0684 1710 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
ganlikun 0:20e0c61e0684 1711 break;
ganlikun 0:20e0c61e0684 1712 case WT:
ganlikun 0:20e0c61e0684 1713 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
ganlikun 0:20e0c61e0684 1714 break;
ganlikun 0:20e0c61e0684 1715 case WB_NO_WA:
ganlikun 0:20e0c61e0684 1716 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
ganlikun 0:20e0c61e0684 1717 break;
ganlikun 0:20e0c61e0684 1718 }
ganlikun 0:20e0c61e0684 1719 }
ganlikun 0:20e0c61e0684 1720 return 0;
ganlikun 0:20e0c61e0684 1721 }
ganlikun 0:20e0c61e0684 1722
ganlikun 0:20e0c61e0684 1723 /** \brief Set 4k/64k page memory attributes
ganlikun 0:20e0c61e0684 1724
ganlikun 0:20e0c61e0684 1725 \param [out] descriptor_l2 L2 descriptor.
ganlikun 0:20e0c61e0684 1726 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
ganlikun 0:20e0c61e0684 1727 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
ganlikun 0:20e0c61e0684 1728 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
ganlikun 0:20e0c61e0684 1729 \param [in] page Page size
ganlikun 0:20e0c61e0684 1730
ganlikun 0:20e0c61e0684 1731 \return 0
ganlikun 0:20e0c61e0684 1732 */
ganlikun 0:20e0c61e0684 1733 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
ganlikun 0:20e0c61e0684 1734 {
ganlikun 0:20e0c61e0684 1735 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
ganlikun 0:20e0c61e0684 1736
ganlikun 0:20e0c61e0684 1737 if (page == PAGE_64k)
ganlikun 0:20e0c61e0684 1738 {
ganlikun 0:20e0c61e0684 1739 //same as section
ganlikun 0:20e0c61e0684 1740 MMU_MemorySection(descriptor_l2, mem, outer, inner);
ganlikun 0:20e0c61e0684 1741 }
ganlikun 0:20e0c61e0684 1742 else
ganlikun 0:20e0c61e0684 1743 {
ganlikun 0:20e0c61e0684 1744 if (STRONGLY_ORDERED == mem)
ganlikun 0:20e0c61e0684 1745 {
ganlikun 0:20e0c61e0684 1746 return 0;
ganlikun 0:20e0c61e0684 1747 }
ganlikun 0:20e0c61e0684 1748 else if (SHARED_DEVICE == mem)
ganlikun 0:20e0c61e0684 1749 {
ganlikun 0:20e0c61e0684 1750 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
ganlikun 0:20e0c61e0684 1751 }
ganlikun 0:20e0c61e0684 1752 else if (NON_SHARED_DEVICE == mem)
ganlikun 0:20e0c61e0684 1753 {
ganlikun 0:20e0c61e0684 1754 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
ganlikun 0:20e0c61e0684 1755 }
ganlikun 0:20e0c61e0684 1756 else if (NORMAL == mem)
ganlikun 0:20e0c61e0684 1757 {
ganlikun 0:20e0c61e0684 1758 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
ganlikun 0:20e0c61e0684 1759 switch(inner)
ganlikun 0:20e0c61e0684 1760 {
ganlikun 0:20e0c61e0684 1761 case NON_CACHEABLE:
ganlikun 0:20e0c61e0684 1762 break;
ganlikun 0:20e0c61e0684 1763 case WB_WA:
ganlikun 0:20e0c61e0684 1764 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
ganlikun 0:20e0c61e0684 1765 break;
ganlikun 0:20e0c61e0684 1766 case WT:
ganlikun 0:20e0c61e0684 1767 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
ganlikun 0:20e0c61e0684 1768 break;
ganlikun 0:20e0c61e0684 1769 case WB_NO_WA:
ganlikun 0:20e0c61e0684 1770 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
ganlikun 0:20e0c61e0684 1771 break;
ganlikun 0:20e0c61e0684 1772 }
ganlikun 0:20e0c61e0684 1773 switch(outer)
ganlikun 0:20e0c61e0684 1774 {
ganlikun 0:20e0c61e0684 1775 case NON_CACHEABLE:
ganlikun 0:20e0c61e0684 1776 break;
ganlikun 0:20e0c61e0684 1777 case WB_WA:
ganlikun 0:20e0c61e0684 1778 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
ganlikun 0:20e0c61e0684 1779 break;
ganlikun 0:20e0c61e0684 1780 case WT:
ganlikun 0:20e0c61e0684 1781 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
ganlikun 0:20e0c61e0684 1782 break;
ganlikun 0:20e0c61e0684 1783 case WB_NO_WA:
ganlikun 0:20e0c61e0684 1784 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
ganlikun 0:20e0c61e0684 1785 break;
ganlikun 0:20e0c61e0684 1786 }
ganlikun 0:20e0c61e0684 1787 }
ganlikun 0:20e0c61e0684 1788 }
ganlikun 0:20e0c61e0684 1789
ganlikun 0:20e0c61e0684 1790 return 0;
ganlikun 0:20e0c61e0684 1791 }
ganlikun 0:20e0c61e0684 1792
ganlikun 0:20e0c61e0684 1793 /** \brief Create a L1 section descriptor
ganlikun 0:20e0c61e0684 1794
ganlikun 0:20e0c61e0684 1795 \param [out] descriptor L1 descriptor
ganlikun 0:20e0c61e0684 1796 \param [in] reg Section attributes
ganlikun 0:20e0c61e0684 1797
ganlikun 0:20e0c61e0684 1798 \return 0
ganlikun 0:20e0c61e0684 1799 */
ganlikun 0:20e0c61e0684 1800 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
ganlikun 0:20e0c61e0684 1801 {
ganlikun 0:20e0c61e0684 1802 *descriptor = 0;
ganlikun 0:20e0c61e0684 1803
ganlikun 0:20e0c61e0684 1804 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
ganlikun 0:20e0c61e0684 1805 MMU_XNSection(descriptor,reg.xn_t);
ganlikun 0:20e0c61e0684 1806 MMU_DomainSection(descriptor, reg.domain);
ganlikun 0:20e0c61e0684 1807 MMU_PSection(descriptor, reg.e_t);
ganlikun 0:20e0c61e0684 1808 MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
ganlikun 0:20e0c61e0684 1809 MMU_SharedSection(descriptor,reg.sh_t);
ganlikun 0:20e0c61e0684 1810 MMU_GlobalSection(descriptor,reg.g_t);
ganlikun 0:20e0c61e0684 1811 MMU_SecureSection(descriptor,reg.sec_t);
ganlikun 0:20e0c61e0684 1812 *descriptor &= SECTION_MASK;
ganlikun 0:20e0c61e0684 1813 *descriptor |= SECTION_DESCRIPTOR;
ganlikun 0:20e0c61e0684 1814
ganlikun 0:20e0c61e0684 1815 return 0;
ganlikun 0:20e0c61e0684 1816 }
ganlikun 0:20e0c61e0684 1817
ganlikun 0:20e0c61e0684 1818
ganlikun 0:20e0c61e0684 1819 /** \brief Create a L1 and L2 4k/64k page descriptor
ganlikun 0:20e0c61e0684 1820
ganlikun 0:20e0c61e0684 1821 \param [out] descriptor L1 descriptor
ganlikun 0:20e0c61e0684 1822 \param [out] descriptor2 L2 descriptor
ganlikun 0:20e0c61e0684 1823 \param [in] reg 4k/64k page attributes
ganlikun 0:20e0c61e0684 1824
ganlikun 0:20e0c61e0684 1825 \return 0
ganlikun 0:20e0c61e0684 1826 */
ganlikun 0:20e0c61e0684 1827 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
ganlikun 0:20e0c61e0684 1828 {
ganlikun 0:20e0c61e0684 1829 *descriptor = 0;
ganlikun 0:20e0c61e0684 1830 *descriptor2 = 0;
ganlikun 0:20e0c61e0684 1831
ganlikun 0:20e0c61e0684 1832 switch (reg.rg_t)
ganlikun 0:20e0c61e0684 1833 {
ganlikun 0:20e0c61e0684 1834 case PAGE_4k:
ganlikun 0:20e0c61e0684 1835 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
ganlikun 0:20e0c61e0684 1836 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
ganlikun 0:20e0c61e0684 1837 MMU_DomainPage(descriptor, reg.domain);
ganlikun 0:20e0c61e0684 1838 MMU_PPage(descriptor, reg.e_t);
ganlikun 0:20e0c61e0684 1839 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
ganlikun 0:20e0c61e0684 1840 MMU_SharedPage(descriptor2,reg.sh_t);
ganlikun 0:20e0c61e0684 1841 MMU_GlobalPage(descriptor2,reg.g_t);
ganlikun 0:20e0c61e0684 1842 MMU_SecurePage(descriptor,reg.sec_t);
ganlikun 0:20e0c61e0684 1843 *descriptor &= PAGE_L1_MASK;
ganlikun 0:20e0c61e0684 1844 *descriptor |= PAGE_L1_DESCRIPTOR;
ganlikun 0:20e0c61e0684 1845 *descriptor2 &= PAGE_L2_4K_MASK;
ganlikun 0:20e0c61e0684 1846 *descriptor2 |= PAGE_L2_4K_DESC;
ganlikun 0:20e0c61e0684 1847 break;
ganlikun 0:20e0c61e0684 1848
ganlikun 0:20e0c61e0684 1849 case PAGE_64k:
ganlikun 0:20e0c61e0684 1850 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
ganlikun 0:20e0c61e0684 1851 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
ganlikun 0:20e0c61e0684 1852 MMU_DomainPage(descriptor, reg.domain);
ganlikun 0:20e0c61e0684 1853 MMU_PPage(descriptor, reg.e_t);
ganlikun 0:20e0c61e0684 1854 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
ganlikun 0:20e0c61e0684 1855 MMU_SharedPage(descriptor2,reg.sh_t);
ganlikun 0:20e0c61e0684 1856 MMU_GlobalPage(descriptor2,reg.g_t);
ganlikun 0:20e0c61e0684 1857 MMU_SecurePage(descriptor,reg.sec_t);
ganlikun 0:20e0c61e0684 1858 *descriptor &= PAGE_L1_MASK;
ganlikun 0:20e0c61e0684 1859 *descriptor |= PAGE_L1_DESCRIPTOR;
ganlikun 0:20e0c61e0684 1860 *descriptor2 &= PAGE_L2_64K_MASK;
ganlikun 0:20e0c61e0684 1861 *descriptor2 |= PAGE_L2_64K_DESC;
ganlikun 0:20e0c61e0684 1862 break;
ganlikun 0:20e0c61e0684 1863
ganlikun 0:20e0c61e0684 1864 case SECTION:
ganlikun 0:20e0c61e0684 1865 //error
ganlikun 0:20e0c61e0684 1866 break;
ganlikun 0:20e0c61e0684 1867 }
ganlikun 0:20e0c61e0684 1868
ganlikun 0:20e0c61e0684 1869 return 0;
ganlikun 0:20e0c61e0684 1870 }
ganlikun 0:20e0c61e0684 1871
ganlikun 0:20e0c61e0684 1872 /** \brief Create a 1MB Section
ganlikun 0:20e0c61e0684 1873
ganlikun 0:20e0c61e0684 1874 \param [in] ttb Translation table base address
ganlikun 0:20e0c61e0684 1875 \param [in] base_address Section base address
ganlikun 0:20e0c61e0684 1876 \param [in] count Number of sections to create
ganlikun 0:20e0c61e0684 1877 \param [in] descriptor_l1 L1 descriptor (region attributes)
ganlikun 0:20e0c61e0684 1878
ganlikun 0:20e0c61e0684 1879 */
ganlikun 0:20e0c61e0684 1880 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
ganlikun 0:20e0c61e0684 1881 {
ganlikun 0:20e0c61e0684 1882 uint32_t offset;
ganlikun 0:20e0c61e0684 1883 uint32_t entry;
ganlikun 0:20e0c61e0684 1884 uint32_t i;
ganlikun 0:20e0c61e0684 1885
ganlikun 0:20e0c61e0684 1886 offset = base_address >> 20;
ganlikun 0:20e0c61e0684 1887 entry = (base_address & 0xFFF00000) | descriptor_l1;
ganlikun 0:20e0c61e0684 1888
ganlikun 0:20e0c61e0684 1889 //4 bytes aligned
ganlikun 0:20e0c61e0684 1890 ttb = ttb + offset;
ganlikun 0:20e0c61e0684 1891
ganlikun 0:20e0c61e0684 1892 for (i = 0; i < count; i++ )
ganlikun 0:20e0c61e0684 1893 {
ganlikun 0:20e0c61e0684 1894 //4 bytes aligned
ganlikun 0:20e0c61e0684 1895 *ttb++ = entry;
ganlikun 0:20e0c61e0684 1896 entry += OFFSET_1M;
ganlikun 0:20e0c61e0684 1897 }
ganlikun 0:20e0c61e0684 1898 }
ganlikun 0:20e0c61e0684 1899
ganlikun 0:20e0c61e0684 1900 /** \brief Create a 4k page entry
ganlikun 0:20e0c61e0684 1901
ganlikun 0:20e0c61e0684 1902 \param [in] ttb L1 table base address
ganlikun 0:20e0c61e0684 1903 \param [in] base_address 4k base address
ganlikun 0:20e0c61e0684 1904 \param [in] count Number of 4k pages to create
ganlikun 0:20e0c61e0684 1905 \param [in] descriptor_l1 L1 descriptor (region attributes)
ganlikun 0:20e0c61e0684 1906 \param [in] ttb_l2 L2 table base address
ganlikun 0:20e0c61e0684 1907 \param [in] descriptor_l2 L2 descriptor (region attributes)
ganlikun 0:20e0c61e0684 1908
ganlikun 0:20e0c61e0684 1909 */
ganlikun 0:20e0c61e0684 1910 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
ganlikun 0:20e0c61e0684 1911 {
ganlikun 0:20e0c61e0684 1912
ganlikun 0:20e0c61e0684 1913 uint32_t offset, offset2;
ganlikun 0:20e0c61e0684 1914 uint32_t entry, entry2;
ganlikun 0:20e0c61e0684 1915 uint32_t i;
ganlikun 0:20e0c61e0684 1916
ganlikun 0:20e0c61e0684 1917 offset = base_address >> 20;
ganlikun 0:20e0c61e0684 1918 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
ganlikun 0:20e0c61e0684 1919
ganlikun 0:20e0c61e0684 1920 //4 bytes aligned
ganlikun 0:20e0c61e0684 1921 ttb += offset;
ganlikun 0:20e0c61e0684 1922 //create l1_entry
ganlikun 0:20e0c61e0684 1923 *ttb = entry;
ganlikun 0:20e0c61e0684 1924
ganlikun 0:20e0c61e0684 1925 offset2 = (base_address & 0xff000) >> 12;
ganlikun 0:20e0c61e0684 1926 ttb_l2 += offset2;
ganlikun 0:20e0c61e0684 1927 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
ganlikun 0:20e0c61e0684 1928 for (i = 0; i < count; i++ )
ganlikun 0:20e0c61e0684 1929 {
ganlikun 0:20e0c61e0684 1930 //4 bytes aligned
ganlikun 0:20e0c61e0684 1931 *ttb_l2++ = entry2;
ganlikun 0:20e0c61e0684 1932 entry2 += OFFSET_4K;
ganlikun 0:20e0c61e0684 1933 }
ganlikun 0:20e0c61e0684 1934 }
ganlikun 0:20e0c61e0684 1935
ganlikun 0:20e0c61e0684 1936 /** \brief Create a 64k page entry
ganlikun 0:20e0c61e0684 1937
ganlikun 0:20e0c61e0684 1938 \param [in] ttb L1 table base address
ganlikun 0:20e0c61e0684 1939 \param [in] base_address 64k base address
ganlikun 0:20e0c61e0684 1940 \param [in] count Number of 64k pages to create
ganlikun 0:20e0c61e0684 1941 \param [in] descriptor_l1 L1 descriptor (region attributes)
ganlikun 0:20e0c61e0684 1942 \param [in] ttb_l2 L2 table base address
ganlikun 0:20e0c61e0684 1943 \param [in] descriptor_l2 L2 descriptor (region attributes)
ganlikun 0:20e0c61e0684 1944
ganlikun 0:20e0c61e0684 1945 */
ganlikun 0:20e0c61e0684 1946 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
ganlikun 0:20e0c61e0684 1947 {
ganlikun 0:20e0c61e0684 1948 uint32_t offset, offset2;
ganlikun 0:20e0c61e0684 1949 uint32_t entry, entry2;
ganlikun 0:20e0c61e0684 1950 uint32_t i,j;
ganlikun 0:20e0c61e0684 1951
ganlikun 0:20e0c61e0684 1952
ganlikun 0:20e0c61e0684 1953 offset = base_address >> 20;
ganlikun 0:20e0c61e0684 1954 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
ganlikun 0:20e0c61e0684 1955
ganlikun 0:20e0c61e0684 1956 //4 bytes aligned
ganlikun 0:20e0c61e0684 1957 ttb += offset;
ganlikun 0:20e0c61e0684 1958 //create l1_entry
ganlikun 0:20e0c61e0684 1959 *ttb = entry;
ganlikun 0:20e0c61e0684 1960
ganlikun 0:20e0c61e0684 1961 offset2 = (base_address & 0xff000) >> 12;
ganlikun 0:20e0c61e0684 1962 ttb_l2 += offset2;
ganlikun 0:20e0c61e0684 1963 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
ganlikun 0:20e0c61e0684 1964 for (i = 0; i < count; i++ )
ganlikun 0:20e0c61e0684 1965 {
ganlikun 0:20e0c61e0684 1966 //create 16 entries
ganlikun 0:20e0c61e0684 1967 for (j = 0; j < 16; j++)
ganlikun 0:20e0c61e0684 1968 {
ganlikun 0:20e0c61e0684 1969 //4 bytes aligned
ganlikun 0:20e0c61e0684 1970 *ttb_l2++ = entry2;
ganlikun 0:20e0c61e0684 1971 }
ganlikun 0:20e0c61e0684 1972 entry2 += OFFSET_64K;
ganlikun 0:20e0c61e0684 1973 }
ganlikun 0:20e0c61e0684 1974 }
ganlikun 0:20e0c61e0684 1975
ganlikun 0:20e0c61e0684 1976 /** \brief Enable MMU
ganlikun 0:20e0c61e0684 1977
ganlikun 0:20e0c61e0684 1978 Enable MMU
ganlikun 0:20e0c61e0684 1979 */
ganlikun 0:20e0c61e0684 1980 __STATIC_INLINE void MMU_Enable(void) {
ganlikun 0:20e0c61e0684 1981 // Set M bit 0 to enable the MMU
ganlikun 0:20e0c61e0684 1982 // Set AFE bit to enable simplified access permissions model
ganlikun 0:20e0c61e0684 1983 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
ganlikun 0:20e0c61e0684 1984 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
ganlikun 0:20e0c61e0684 1985 __ISB();
ganlikun 0:20e0c61e0684 1986 }
ganlikun 0:20e0c61e0684 1987
ganlikun 0:20e0c61e0684 1988 /** \brief Disable MMU
ganlikun 0:20e0c61e0684 1989
ganlikun 0:20e0c61e0684 1990 Disable MMU
ganlikun 0:20e0c61e0684 1991 */
ganlikun 0:20e0c61e0684 1992 __STATIC_INLINE void MMU_Disable(void) {
ganlikun 0:20e0c61e0684 1993 // Clear M bit 0 to disable the MMU
ganlikun 0:20e0c61e0684 1994 __set_SCTLR( __get_SCTLR() & ~1);
ganlikun 0:20e0c61e0684 1995 __ISB();
ganlikun 0:20e0c61e0684 1996 }
ganlikun 0:20e0c61e0684 1997
ganlikun 0:20e0c61e0684 1998 /** \brief Invalidate entire unified TLB
ganlikun 0:20e0c61e0684 1999
ganlikun 0:20e0c61e0684 2000 TLBIALL. Invalidate entire unified TLB
ganlikun 0:20e0c61e0684 2001 */
ganlikun 0:20e0c61e0684 2002
ganlikun 0:20e0c61e0684 2003 __STATIC_INLINE void MMU_InvalidateTLB(void) {
ganlikun 0:20e0c61e0684 2004 __set_TLBIALL(0);
ganlikun 0:20e0c61e0684 2005 __DSB(); //ensure completion of the invalidation
ganlikun 0:20e0c61e0684 2006 __ISB(); //ensure instruction fetch path sees new state
ganlikun 0:20e0c61e0684 2007 }
ganlikun 0:20e0c61e0684 2008
ganlikun 0:20e0c61e0684 2009
ganlikun 0:20e0c61e0684 2010 #ifdef __cplusplus
ganlikun 0:20e0c61e0684 2011 }
ganlikun 0:20e0c61e0684 2012 #endif
ganlikun 0:20e0c61e0684 2013
ganlikun 0:20e0c61e0684 2014 #endif /* __CORE_CA_H_DEPENDANT */
ganlikun 0:20e0c61e0684 2015
ganlikun 0:20e0c61e0684 2016 #endif /* __CMSIS_GENERIC */
ganlikun 0:20e0c61e0684 2017