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source/nordic_sdk/components/device/nrf51_bitfields.h@607:e98331f1d6b5, 2016-01-11 (annotated)

Committer:: vcoubard
Date:: Mon Jan 11 10:29:13 2016 +0000
Revision:: 607:e98331f1d6b5

Import nordic sdk from https://github.com/ARMmbed/nrf51-sdk.git#a0faa63aae1f6351ac36cd70f28ce037d6f4ae11

Who changed what in which revision?

User	Revision	Line number	New contents of line
vcoubard	607:e98331f1d6b5	1	/*
vcoubard	607:e98331f1d6b5	2	* Copyright (c) Nordic Semiconductor ASA
vcoubard	607:e98331f1d6b5	3	* All rights reserved.
vcoubard	607:e98331f1d6b5	4	*
vcoubard	607:e98331f1d6b5	5	* Redistribution and use in source and binary forms, with or without modification,
vcoubard	607:e98331f1d6b5	6	* are permitted provided that the following conditions are met:
vcoubard	607:e98331f1d6b5	7	*
vcoubard	607:e98331f1d6b5	8	* 1. Redistributions of source code must retain the above copyright notice, this
vcoubard	607:e98331f1d6b5	9	* list of conditions and the following disclaimer.
vcoubard	607:e98331f1d6b5	10	*
vcoubard	607:e98331f1d6b5	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
vcoubard	607:e98331f1d6b5	12	* list of conditions and the following disclaimer in the documentation and/or
vcoubard	607:e98331f1d6b5	13	* other materials provided with the distribution.
vcoubard	607:e98331f1d6b5	14	*
vcoubard	607:e98331f1d6b5	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
vcoubard	607:e98331f1d6b5	16	* contributors to this software may be used to endorse or promote products
vcoubard	607:e98331f1d6b5	17	* derived from this software without specific prior written permission.
vcoubard	607:e98331f1d6b5	18	*
vcoubard	607:e98331f1d6b5	19	*
vcoubard	607:e98331f1d6b5	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vcoubard	607:e98331f1d6b5	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vcoubard	607:e98331f1d6b5	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard	607:e98331f1d6b5	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vcoubard	607:e98331f1d6b5	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vcoubard	607:e98331f1d6b5	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vcoubard	607:e98331f1d6b5	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vcoubard	607:e98331f1d6b5	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vcoubard	607:e98331f1d6b5	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vcoubard	607:e98331f1d6b5	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard	607:e98331f1d6b5	30	*
vcoubard	607:e98331f1d6b5	31	*/
vcoubard	607:e98331f1d6b5	32	#ifndef __NRF51_BITS_H
vcoubard	607:e98331f1d6b5	33	#define __NRF51_BITS_H
vcoubard	607:e98331f1d6b5	34
vcoubard	607:e98331f1d6b5	35	/lint ++flb "Enter library region" /
vcoubard	607:e98331f1d6b5	36
vcoubard	607:e98331f1d6b5	37	/* Peripheral: AAR */
vcoubard	607:e98331f1d6b5	38	/* Description: Accelerated Address Resolver. */
vcoubard	607:e98331f1d6b5	39
vcoubard	607:e98331f1d6b5	40	/* Register: AAR_INTENSET */
vcoubard	607:e98331f1d6b5	41	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	42
vcoubard	607:e98331f1d6b5	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
vcoubard	607:e98331f1d6b5	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
vcoubard	607:e98331f1d6b5	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
vcoubard	607:e98331f1d6b5	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	49
vcoubard	607:e98331f1d6b5	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
vcoubard	607:e98331f1d6b5	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
vcoubard	607:e98331f1d6b5	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
vcoubard	607:e98331f1d6b5	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	56
vcoubard	607:e98331f1d6b5	57	/* Bit 0 : Enable interrupt on END event. */
vcoubard	607:e98331f1d6b5	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	63
vcoubard	607:e98331f1d6b5	64	/* Register: AAR_INTENCLR */
vcoubard	607:e98331f1d6b5	65	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	66
vcoubard	607:e98331f1d6b5	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
vcoubard	607:e98331f1d6b5	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
vcoubard	607:e98331f1d6b5	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
vcoubard	607:e98331f1d6b5	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	73
vcoubard	607:e98331f1d6b5	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
vcoubard	607:e98331f1d6b5	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
vcoubard	607:e98331f1d6b5	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
vcoubard	607:e98331f1d6b5	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	80
vcoubard	607:e98331f1d6b5	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
vcoubard	607:e98331f1d6b5	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	87
vcoubard	607:e98331f1d6b5	88	/* Register: AAR_STATUS */
vcoubard	607:e98331f1d6b5	89	/* Description: Resolution status. */
vcoubard	607:e98331f1d6b5	90
vcoubard	607:e98331f1d6b5	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
vcoubard	607:e98331f1d6b5	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	607:e98331f1d6b5	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	607:e98331f1d6b5	94
vcoubard	607:e98331f1d6b5	95	/* Register: AAR_ENABLE */
vcoubard	607:e98331f1d6b5	96	/* Description: Enable AAR. */
vcoubard	607:e98331f1d6b5	97
vcoubard	607:e98331f1d6b5	98	/* Bits 1..0 : Enable AAR. */
vcoubard	607:e98331f1d6b5	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
vcoubard	607:e98331f1d6b5	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
vcoubard	607:e98331f1d6b5	103
vcoubard	607:e98331f1d6b5	104	/* Register: AAR_NIRK */
vcoubard	607:e98331f1d6b5	105	/* Description: Number of Identity root Keys in the IRK data structure. */
vcoubard	607:e98331f1d6b5	106
vcoubard	607:e98331f1d6b5	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
vcoubard	607:e98331f1d6b5	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
vcoubard	607:e98331f1d6b5	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
vcoubard	607:e98331f1d6b5	110
vcoubard	607:e98331f1d6b5	111	/* Register: AAR_POWER */
vcoubard	607:e98331f1d6b5	112	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	113
vcoubard	607:e98331f1d6b5	114	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	119
vcoubard	607:e98331f1d6b5	120
vcoubard	607:e98331f1d6b5	121	/* Peripheral: ADC */
vcoubard	607:e98331f1d6b5	122	/* Description: Analog to digital converter. */
vcoubard	607:e98331f1d6b5	123
vcoubard	607:e98331f1d6b5	124	/* Register: ADC_INTENSET */
vcoubard	607:e98331f1d6b5	125	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	126
vcoubard	607:e98331f1d6b5	127	/* Bit 0 : Enable interrupt on END event. */
vcoubard	607:e98331f1d6b5	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	133
vcoubard	607:e98331f1d6b5	134	/* Register: ADC_INTENCLR */
vcoubard	607:e98331f1d6b5	135	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	136
vcoubard	607:e98331f1d6b5	137	/* Bit 0 : Disable interrupt on END event. */
vcoubard	607:e98331f1d6b5	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	143
vcoubard	607:e98331f1d6b5	144	/* Register: ADC_BUSY */
vcoubard	607:e98331f1d6b5	145	/* Description: ADC busy register. */
vcoubard	607:e98331f1d6b5	146
vcoubard	607:e98331f1d6b5	147	/* Bit 0 : ADC busy register. */
vcoubard	607:e98331f1d6b5	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
vcoubard	607:e98331f1d6b5	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
vcoubard	607:e98331f1d6b5	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
vcoubard	607:e98331f1d6b5	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
vcoubard	607:e98331f1d6b5	152
vcoubard	607:e98331f1d6b5	153	/* Register: ADC_ENABLE */
vcoubard	607:e98331f1d6b5	154	/* Description: ADC enable. */
vcoubard	607:e98331f1d6b5	155
vcoubard	607:e98331f1d6b5	156	/* Bits 1..0 : ADC enable. */
vcoubard	607:e98331f1d6b5	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
vcoubard	607:e98331f1d6b5	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
vcoubard	607:e98331f1d6b5	161
vcoubard	607:e98331f1d6b5	162	/* Register: ADC_CONFIG */
vcoubard	607:e98331f1d6b5	163	/* Description: ADC configuration register. */
vcoubard	607:e98331f1d6b5	164
vcoubard	607:e98331f1d6b5	165	/* Bits 17..16 : ADC external reference pin selection. */
vcoubard	607:e98331f1d6b5	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
vcoubard	607:e98331f1d6b5	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
vcoubard	607:e98331f1d6b5	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
vcoubard	607:e98331f1d6b5	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
vcoubard	607:e98331f1d6b5	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
vcoubard	607:e98331f1d6b5	171
vcoubard	607:e98331f1d6b5	172	/* Bits 15..8 : ADC analog pin selection. */
vcoubard	607:e98331f1d6b5	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
vcoubard	607:e98331f1d6b5	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	607:e98331f1d6b5	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
vcoubard	607:e98331f1d6b5	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
vcoubard	607:e98331f1d6b5	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
vcoubard	607:e98331f1d6b5	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
vcoubard	607:e98331f1d6b5	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
vcoubard	607:e98331f1d6b5	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
vcoubard	607:e98331f1d6b5	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
vcoubard	607:e98331f1d6b5	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
vcoubard	607:e98331f1d6b5	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
vcoubard	607:e98331f1d6b5	184
vcoubard	607:e98331f1d6b5	185	/* Bits 6..5 : ADC reference selection. */
vcoubard	607:e98331f1d6b5	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
vcoubard	607:e98331f1d6b5	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
vcoubard	607:e98331f1d6b5	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
vcoubard	607:e98331f1d6b5	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
vcoubard	607:e98331f1d6b5	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
vcoubard	607:e98331f1d6b5	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
vcoubard	607:e98331f1d6b5	192
vcoubard	607:e98331f1d6b5	193	/* Bits 4..2 : ADC input selection. */
vcoubard	607:e98331f1d6b5	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
vcoubard	607:e98331f1d6b5	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
vcoubard	607:e98331f1d6b5	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
vcoubard	607:e98331f1d6b5	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
vcoubard	607:e98331f1d6b5	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
vcoubard	607:e98331f1d6b5	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
vcoubard	607:e98331f1d6b5	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
vcoubard	607:e98331f1d6b5	201
vcoubard	607:e98331f1d6b5	202	/* Bits 1..0 : ADC resolution. */
vcoubard	607:e98331f1d6b5	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
vcoubard	607:e98331f1d6b5	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
vcoubard	607:e98331f1d6b5	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
vcoubard	607:e98331f1d6b5	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
vcoubard	607:e98331f1d6b5	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
vcoubard	607:e98331f1d6b5	208
vcoubard	607:e98331f1d6b5	209	/* Register: ADC_RESULT */
vcoubard	607:e98331f1d6b5	210	/* Description: Result of ADC conversion. */
vcoubard	607:e98331f1d6b5	211
vcoubard	607:e98331f1d6b5	212	/* Bits 9..0 : Result of ADC conversion. */
vcoubard	607:e98331f1d6b5	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
vcoubard	607:e98331f1d6b5	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
vcoubard	607:e98331f1d6b5	215
vcoubard	607:e98331f1d6b5	216	/* Register: ADC_POWER */
vcoubard	607:e98331f1d6b5	217	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	218
vcoubard	607:e98331f1d6b5	219	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	224
vcoubard	607:e98331f1d6b5	225
vcoubard	607:e98331f1d6b5	226	/* Peripheral: AMLI */
vcoubard	607:e98331f1d6b5	227	/* Description: AHB Multi-Layer Interface. */
vcoubard	607:e98331f1d6b5	228
vcoubard	607:e98331f1d6b5	229	/* Register: AMLI_RAMPRI_CPU0 */
vcoubard	607:e98331f1d6b5	230	/* Description: Configurable priority configuration register for CPU0. */
vcoubard	607:e98331f1d6b5	231
vcoubard	607:e98331f1d6b5	232	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	607:e98331f1d6b5	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	607:e98331f1d6b5	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	607:e98331f1d6b5	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	243
vcoubard	607:e98331f1d6b5	244	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	607:e98331f1d6b5	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	607:e98331f1d6b5	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	607:e98331f1d6b5	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	255
vcoubard	607:e98331f1d6b5	256	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	607:e98331f1d6b5	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	607:e98331f1d6b5	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	607:e98331f1d6b5	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	267
vcoubard	607:e98331f1d6b5	268	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	607:e98331f1d6b5	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	607:e98331f1d6b5	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	607:e98331f1d6b5	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	279
vcoubard	607:e98331f1d6b5	280	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	607:e98331f1d6b5	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	607:e98331f1d6b5	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	607:e98331f1d6b5	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	291
vcoubard	607:e98331f1d6b5	292	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	607:e98331f1d6b5	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	607:e98331f1d6b5	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	607:e98331f1d6b5	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	303
vcoubard	607:e98331f1d6b5	304	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	607:e98331f1d6b5	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	607:e98331f1d6b5	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	607:e98331f1d6b5	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	315
vcoubard	607:e98331f1d6b5	316	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	607:e98331f1d6b5	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	607:e98331f1d6b5	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	607:e98331f1d6b5	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	327
vcoubard	607:e98331f1d6b5	328	/* Register: AMLI_RAMPRI_SPIS1 */
vcoubard	607:e98331f1d6b5	329	/* Description: Configurable priority configuration register for SPIS1. */
vcoubard	607:e98331f1d6b5	330
vcoubard	607:e98331f1d6b5	331	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	607:e98331f1d6b5	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	607:e98331f1d6b5	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	607:e98331f1d6b5	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	342
vcoubard	607:e98331f1d6b5	343	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	607:e98331f1d6b5	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	607:e98331f1d6b5	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	607:e98331f1d6b5	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	354
vcoubard	607:e98331f1d6b5	355	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	607:e98331f1d6b5	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	607:e98331f1d6b5	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	607:e98331f1d6b5	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	366
vcoubard	607:e98331f1d6b5	367	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	607:e98331f1d6b5	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	607:e98331f1d6b5	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	607:e98331f1d6b5	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	378
vcoubard	607:e98331f1d6b5	379	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	607:e98331f1d6b5	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	607:e98331f1d6b5	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	607:e98331f1d6b5	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	390
vcoubard	607:e98331f1d6b5	391	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	607:e98331f1d6b5	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	607:e98331f1d6b5	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	607:e98331f1d6b5	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	402
vcoubard	607:e98331f1d6b5	403	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	607:e98331f1d6b5	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	607:e98331f1d6b5	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	607:e98331f1d6b5	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	414
vcoubard	607:e98331f1d6b5	415	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	607:e98331f1d6b5	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	607:e98331f1d6b5	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	607:e98331f1d6b5	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	426
vcoubard	607:e98331f1d6b5	427	/* Register: AMLI_RAMPRI_RADIO */
vcoubard	607:e98331f1d6b5	428	/* Description: Configurable priority configuration register for RADIO. */
vcoubard	607:e98331f1d6b5	429
vcoubard	607:e98331f1d6b5	430	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	607:e98331f1d6b5	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	607:e98331f1d6b5	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	607:e98331f1d6b5	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	441
vcoubard	607:e98331f1d6b5	442	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	607:e98331f1d6b5	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	607:e98331f1d6b5	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	607:e98331f1d6b5	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	453
vcoubard	607:e98331f1d6b5	454	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	607:e98331f1d6b5	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	607:e98331f1d6b5	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	607:e98331f1d6b5	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	465
vcoubard	607:e98331f1d6b5	466	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	607:e98331f1d6b5	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	607:e98331f1d6b5	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	607:e98331f1d6b5	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	477
vcoubard	607:e98331f1d6b5	478	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	607:e98331f1d6b5	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	607:e98331f1d6b5	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	607:e98331f1d6b5	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	489
vcoubard	607:e98331f1d6b5	490	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	607:e98331f1d6b5	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	607:e98331f1d6b5	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	607:e98331f1d6b5	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	501
vcoubard	607:e98331f1d6b5	502	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	607:e98331f1d6b5	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	607:e98331f1d6b5	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	607:e98331f1d6b5	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	513
vcoubard	607:e98331f1d6b5	514	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	607:e98331f1d6b5	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	607:e98331f1d6b5	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	607:e98331f1d6b5	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	525
vcoubard	607:e98331f1d6b5	526	/* Register: AMLI_RAMPRI_ECB */
vcoubard	607:e98331f1d6b5	527	/* Description: Configurable priority configuration register for ECB. */
vcoubard	607:e98331f1d6b5	528
vcoubard	607:e98331f1d6b5	529	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	607:e98331f1d6b5	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	607:e98331f1d6b5	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	607:e98331f1d6b5	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	540
vcoubard	607:e98331f1d6b5	541	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	607:e98331f1d6b5	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	607:e98331f1d6b5	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	607:e98331f1d6b5	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	552
vcoubard	607:e98331f1d6b5	553	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	607:e98331f1d6b5	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	607:e98331f1d6b5	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	607:e98331f1d6b5	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	564
vcoubard	607:e98331f1d6b5	565	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	607:e98331f1d6b5	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	607:e98331f1d6b5	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	607:e98331f1d6b5	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	576
vcoubard	607:e98331f1d6b5	577	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	607:e98331f1d6b5	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	607:e98331f1d6b5	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	607:e98331f1d6b5	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	588
vcoubard	607:e98331f1d6b5	589	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	607:e98331f1d6b5	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	607:e98331f1d6b5	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	607:e98331f1d6b5	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	600
vcoubard	607:e98331f1d6b5	601	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	607:e98331f1d6b5	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	607:e98331f1d6b5	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	607:e98331f1d6b5	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	612
vcoubard	607:e98331f1d6b5	613	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	607:e98331f1d6b5	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	607:e98331f1d6b5	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	607:e98331f1d6b5	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	624
vcoubard	607:e98331f1d6b5	625	/* Register: AMLI_RAMPRI_CCM */
vcoubard	607:e98331f1d6b5	626	/* Description: Configurable priority configuration register for CCM. */
vcoubard	607:e98331f1d6b5	627
vcoubard	607:e98331f1d6b5	628	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	607:e98331f1d6b5	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	607:e98331f1d6b5	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	607:e98331f1d6b5	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	639
vcoubard	607:e98331f1d6b5	640	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	607:e98331f1d6b5	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	607:e98331f1d6b5	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	607:e98331f1d6b5	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	651
vcoubard	607:e98331f1d6b5	652	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	607:e98331f1d6b5	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	607:e98331f1d6b5	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	607:e98331f1d6b5	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	663
vcoubard	607:e98331f1d6b5	664	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	607:e98331f1d6b5	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	607:e98331f1d6b5	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	607:e98331f1d6b5	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	675
vcoubard	607:e98331f1d6b5	676	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	607:e98331f1d6b5	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	607:e98331f1d6b5	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	607:e98331f1d6b5	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	687
vcoubard	607:e98331f1d6b5	688	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	607:e98331f1d6b5	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	607:e98331f1d6b5	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	607:e98331f1d6b5	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	699
vcoubard	607:e98331f1d6b5	700	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	607:e98331f1d6b5	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	607:e98331f1d6b5	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	607:e98331f1d6b5	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	711
vcoubard	607:e98331f1d6b5	712	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	607:e98331f1d6b5	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	607:e98331f1d6b5	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	607:e98331f1d6b5	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	723
vcoubard	607:e98331f1d6b5	724	/* Register: AMLI_RAMPRI_AAR */
vcoubard	607:e98331f1d6b5	725	/* Description: Configurable priority configuration register for AAR. */
vcoubard	607:e98331f1d6b5	726
vcoubard	607:e98331f1d6b5	727	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	607:e98331f1d6b5	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	607:e98331f1d6b5	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	607:e98331f1d6b5	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	738
vcoubard	607:e98331f1d6b5	739	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	607:e98331f1d6b5	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	607:e98331f1d6b5	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	607:e98331f1d6b5	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	750
vcoubard	607:e98331f1d6b5	751	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	607:e98331f1d6b5	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	607:e98331f1d6b5	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	607:e98331f1d6b5	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	762
vcoubard	607:e98331f1d6b5	763	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	607:e98331f1d6b5	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	607:e98331f1d6b5	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	607:e98331f1d6b5	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	774
vcoubard	607:e98331f1d6b5	775	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	607:e98331f1d6b5	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	607:e98331f1d6b5	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	607:e98331f1d6b5	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	786
vcoubard	607:e98331f1d6b5	787	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	607:e98331f1d6b5	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	607:e98331f1d6b5	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	607:e98331f1d6b5	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	798
vcoubard	607:e98331f1d6b5	799	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	607:e98331f1d6b5	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	607:e98331f1d6b5	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	607:e98331f1d6b5	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	810
vcoubard	607:e98331f1d6b5	811	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	607:e98331f1d6b5	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	607:e98331f1d6b5	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	607:e98331f1d6b5	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	607:e98331f1d6b5	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	607:e98331f1d6b5	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	607:e98331f1d6b5	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	607:e98331f1d6b5	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	607:e98331f1d6b5	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	607:e98331f1d6b5	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	607:e98331f1d6b5	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	607:e98331f1d6b5	822
vcoubard	607:e98331f1d6b5	823
vcoubard	607:e98331f1d6b5	824	/* Peripheral: CCM */
vcoubard	607:e98331f1d6b5	825	/* Description: AES CCM Mode Encryption. */
vcoubard	607:e98331f1d6b5	826
vcoubard	607:e98331f1d6b5	827	/* Register: CCM_SHORTS */
vcoubard	607:e98331f1d6b5	828	/* Description: Shortcuts for the CCM. */
vcoubard	607:e98331f1d6b5	829
vcoubard	607:e98331f1d6b5	830	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
vcoubard	607:e98331f1d6b5	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
vcoubard	607:e98331f1d6b5	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
vcoubard	607:e98331f1d6b5	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	834	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	835
vcoubard	607:e98331f1d6b5	836	/* Register: CCM_INTENSET */
vcoubard	607:e98331f1d6b5	837	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	838
vcoubard	607:e98331f1d6b5	839	/* Bit 2 : Enable interrupt on ERROR event. */
vcoubard	607:e98331f1d6b5	840	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
vcoubard	607:e98331f1d6b5	841	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	607:e98331f1d6b5	842	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	843	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	844	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	845
vcoubard	607:e98331f1d6b5	846	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
vcoubard	607:e98331f1d6b5	847	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
vcoubard	607:e98331f1d6b5	848	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
vcoubard	607:e98331f1d6b5	849	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	850	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	851	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	852
vcoubard	607:e98331f1d6b5	853	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
vcoubard	607:e98331f1d6b5	854	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
vcoubard	607:e98331f1d6b5	855	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
vcoubard	607:e98331f1d6b5	856	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	857	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	858	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	859
vcoubard	607:e98331f1d6b5	860	/* Register: CCM_INTENCLR */
vcoubard	607:e98331f1d6b5	861	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	862
vcoubard	607:e98331f1d6b5	863	/* Bit 2 : Disable interrupt on ERROR event. */
vcoubard	607:e98331f1d6b5	864	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
vcoubard	607:e98331f1d6b5	865	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	607:e98331f1d6b5	866	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	867	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	868	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	869
vcoubard	607:e98331f1d6b5	870	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
vcoubard	607:e98331f1d6b5	871	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
vcoubard	607:e98331f1d6b5	872	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
vcoubard	607:e98331f1d6b5	873	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	874	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	875	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	876
vcoubard	607:e98331f1d6b5	877	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
vcoubard	607:e98331f1d6b5	878	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
vcoubard	607:e98331f1d6b5	879	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
vcoubard	607:e98331f1d6b5	880	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	881	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	882	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	883
vcoubard	607:e98331f1d6b5	884	/* Register: CCM_MICSTATUS */
vcoubard	607:e98331f1d6b5	885	/* Description: CCM RX MIC check result. */
vcoubard	607:e98331f1d6b5	886
vcoubard	607:e98331f1d6b5	887	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
vcoubard	607:e98331f1d6b5	888	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
vcoubard	607:e98331f1d6b5	889	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
vcoubard	607:e98331f1d6b5	890	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
vcoubard	607:e98331f1d6b5	891	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
vcoubard	607:e98331f1d6b5	892
vcoubard	607:e98331f1d6b5	893	/* Register: CCM_ENABLE */
vcoubard	607:e98331f1d6b5	894	/* Description: CCM enable. */
vcoubard	607:e98331f1d6b5	895
vcoubard	607:e98331f1d6b5	896	/* Bits 1..0 : CCM enable. */
vcoubard	607:e98331f1d6b5	897	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	898	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	899	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
vcoubard	607:e98331f1d6b5	900	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
vcoubard	607:e98331f1d6b5	901
vcoubard	607:e98331f1d6b5	902	/* Register: CCM_MODE */
vcoubard	607:e98331f1d6b5	903	/* Description: Operation mode. */
vcoubard	607:e98331f1d6b5	904
vcoubard	607:e98331f1d6b5	905	/* Bit 0 : CCM mode operation. */
vcoubard	607:e98331f1d6b5	906	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	607:e98331f1d6b5	907	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	607:e98331f1d6b5	908	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
vcoubard	607:e98331f1d6b5	909	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
vcoubard	607:e98331f1d6b5	910
vcoubard	607:e98331f1d6b5	911	/* Register: CCM_POWER */
vcoubard	607:e98331f1d6b5	912	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	913
vcoubard	607:e98331f1d6b5	914	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	915	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	916	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	917	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	918	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	919
vcoubard	607:e98331f1d6b5	920
vcoubard	607:e98331f1d6b5	921	/* Peripheral: CLOCK */
vcoubard	607:e98331f1d6b5	922	/* Description: Clock control. */
vcoubard	607:e98331f1d6b5	923
vcoubard	607:e98331f1d6b5	924	/* Register: CLOCK_INTENSET */
vcoubard	607:e98331f1d6b5	925	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	926
vcoubard	607:e98331f1d6b5	927	/* Bit 4 : Enable interrupt on CTTO event. */
vcoubard	607:e98331f1d6b5	928	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
vcoubard	607:e98331f1d6b5	929	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
vcoubard	607:e98331f1d6b5	930	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	931	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	932	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	933
vcoubard	607:e98331f1d6b5	934	/* Bit 3 : Enable interrupt on DONE event. */
vcoubard	607:e98331f1d6b5	935	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
vcoubard	607:e98331f1d6b5	936	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
vcoubard	607:e98331f1d6b5	937	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	938	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	939	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	940
vcoubard	607:e98331f1d6b5	941	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
vcoubard	607:e98331f1d6b5	942	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	943	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	944	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	945	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	946	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	947
vcoubard	607:e98331f1d6b5	948	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
vcoubard	607:e98331f1d6b5	949	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	950	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	951	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	952	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	953	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	954
vcoubard	607:e98331f1d6b5	955	/* Register: CLOCK_INTENCLR */
vcoubard	607:e98331f1d6b5	956	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	957
vcoubard	607:e98331f1d6b5	958	/* Bit 4 : Disable interrupt on CTTO event. */
vcoubard	607:e98331f1d6b5	959	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
vcoubard	607:e98331f1d6b5	960	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
vcoubard	607:e98331f1d6b5	961	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	962	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	963	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	964
vcoubard	607:e98331f1d6b5	965	/* Bit 3 : Disable interrupt on DONE event. */
vcoubard	607:e98331f1d6b5	966	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
vcoubard	607:e98331f1d6b5	967	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
vcoubard	607:e98331f1d6b5	968	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	969	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	970	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	971
vcoubard	607:e98331f1d6b5	972	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
vcoubard	607:e98331f1d6b5	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	977	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	978
vcoubard	607:e98331f1d6b5	979	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
vcoubard	607:e98331f1d6b5	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
vcoubard	607:e98331f1d6b5	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	984	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	985
vcoubard	607:e98331f1d6b5	986	/* Register: CLOCK_HFCLKRUN */
vcoubard	607:e98331f1d6b5	987	/* Description: Task HFCLKSTART trigger status. */
vcoubard	607:e98331f1d6b5	988
vcoubard	607:e98331f1d6b5	989	/* Bit 0 : Task HFCLKSTART trigger status. */
vcoubard	607:e98331f1d6b5	990	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	607:e98331f1d6b5	991	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	607:e98331f1d6b5	992	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
vcoubard	607:e98331f1d6b5	993	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
vcoubard	607:e98331f1d6b5	994
vcoubard	607:e98331f1d6b5	995	/* Register: CLOCK_HFCLKSTAT */
vcoubard	607:e98331f1d6b5	996	/* Description: High frequency clock status. */
vcoubard	607:e98331f1d6b5	997
vcoubard	607:e98331f1d6b5	998	/* Bit 16 : State for the HFCLK. */
vcoubard	607:e98331f1d6b5	999	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
vcoubard	607:e98331f1d6b5	1000	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	607:e98331f1d6b5	1001	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
vcoubard	607:e98331f1d6b5	1002	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
vcoubard	607:e98331f1d6b5	1003
vcoubard	607:e98331f1d6b5	1004	/* Bit 0 : Active clock source for the HF clock. */
vcoubard	607:e98331f1d6b5	1005	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	607:e98331f1d6b5	1006	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	607:e98331f1d6b5	1007	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
vcoubard	607:e98331f1d6b5	1008	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
vcoubard	607:e98331f1d6b5	1009
vcoubard	607:e98331f1d6b5	1010	/* Register: CLOCK_LFCLKRUN */
vcoubard	607:e98331f1d6b5	1011	/* Description: Task LFCLKSTART triggered status. */
vcoubard	607:e98331f1d6b5	1012
vcoubard	607:e98331f1d6b5	1013	/* Bit 0 : Task LFCLKSTART triggered status. */
vcoubard	607:e98331f1d6b5	1014	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	607:e98331f1d6b5	1015	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	607:e98331f1d6b5	1016	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
vcoubard	607:e98331f1d6b5	1017	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
vcoubard	607:e98331f1d6b5	1018
vcoubard	607:e98331f1d6b5	1019	/* Register: CLOCK_LFCLKSTAT */
vcoubard	607:e98331f1d6b5	1020	/* Description: Low frequency clock status. */
vcoubard	607:e98331f1d6b5	1021
vcoubard	607:e98331f1d6b5	1022	/* Bit 16 : State for the LF clock. */
vcoubard	607:e98331f1d6b5	1023	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
vcoubard	607:e98331f1d6b5	1024	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	607:e98331f1d6b5	1025	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
vcoubard	607:e98331f1d6b5	1026	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
vcoubard	607:e98331f1d6b5	1027
vcoubard	607:e98331f1d6b5	1028	/* Bits 1..0 : Active clock source for the LF clock. */
vcoubard	607:e98331f1d6b5	1029	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	607:e98331f1d6b5	1030	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	607:e98331f1d6b5	1031	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
vcoubard	607:e98331f1d6b5	1032	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
vcoubard	607:e98331f1d6b5	1033	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
vcoubard	607:e98331f1d6b5	1034
vcoubard	607:e98331f1d6b5	1035	/* Register: CLOCK_LFCLKSRCCOPY */
vcoubard	607:e98331f1d6b5	1036	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
vcoubard	607:e98331f1d6b5	1037
vcoubard	607:e98331f1d6b5	1038	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
vcoubard	607:e98331f1d6b5	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	607:e98331f1d6b5	1040	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	607:e98331f1d6b5	1041	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
vcoubard	607:e98331f1d6b5	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
vcoubard	607:e98331f1d6b5	1043	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
vcoubard	607:e98331f1d6b5	1044
vcoubard	607:e98331f1d6b5	1045	/* Register: CLOCK_LFCLKSRC */
vcoubard	607:e98331f1d6b5	1046	/* Description: Clock source for the LFCLK clock. */
vcoubard	607:e98331f1d6b5	1047
vcoubard	607:e98331f1d6b5	1048	/* Bits 1..0 : Clock source. */
vcoubard	607:e98331f1d6b5	1049	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	607:e98331f1d6b5	1050	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	607:e98331f1d6b5	1051	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
vcoubard	607:e98331f1d6b5	1052	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
vcoubard	607:e98331f1d6b5	1053	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
vcoubard	607:e98331f1d6b5	1054
vcoubard	607:e98331f1d6b5	1055	/* Register: CLOCK_CTIV */
vcoubard	607:e98331f1d6b5	1056	/* Description: Calibration timer interval. */
vcoubard	607:e98331f1d6b5	1057
vcoubard	607:e98331f1d6b5	1058	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
vcoubard	607:e98331f1d6b5	1059	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
vcoubard	607:e98331f1d6b5	1060	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
vcoubard	607:e98331f1d6b5	1061
vcoubard	607:e98331f1d6b5	1062	/* Register: CLOCK_XTALFREQ */
vcoubard	607:e98331f1d6b5	1063	/* Description: Crystal frequency. */
vcoubard	607:e98331f1d6b5	1064
vcoubard	607:e98331f1d6b5	1065	/* Bits 7..0 : External Xtal frequency selection. */
vcoubard	607:e98331f1d6b5	1066	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
vcoubard	607:e98331f1d6b5	1067	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
vcoubard	607:e98331f1d6b5	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
vcoubard	607:e98331f1d6b5	1069	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
vcoubard	607:e98331f1d6b5	1070
vcoubard	607:e98331f1d6b5	1071
vcoubard	607:e98331f1d6b5	1072	/* Peripheral: ECB */
vcoubard	607:e98331f1d6b5	1073	/* Description: AES ECB Mode Encryption. */
vcoubard	607:e98331f1d6b5	1074
vcoubard	607:e98331f1d6b5	1075	/* Register: ECB_INTENSET */
vcoubard	607:e98331f1d6b5	1076	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	1077
vcoubard	607:e98331f1d6b5	1078	/* Bit 1 : Enable interrupt on ERRORECB event. */
vcoubard	607:e98331f1d6b5	1079	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
vcoubard	607:e98331f1d6b5	1080	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
vcoubard	607:e98331f1d6b5	1081	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	1082	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	1083	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	1084
vcoubard	607:e98331f1d6b5	1085	/* Bit 0 : Enable interrupt on ENDECB event. */
vcoubard	607:e98331f1d6b5	1086	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
vcoubard	607:e98331f1d6b5	1087	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
vcoubard	607:e98331f1d6b5	1088	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	1089	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	1090	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	1091
vcoubard	607:e98331f1d6b5	1092	/* Register: ECB_INTENCLR */
vcoubard	607:e98331f1d6b5	1093	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	1094
vcoubard	607:e98331f1d6b5	1095	/* Bit 1 : Disable interrupt on ERRORECB event. */
vcoubard	607:e98331f1d6b5	1096	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
vcoubard	607:e98331f1d6b5	1097	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
vcoubard	607:e98331f1d6b5	1098	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	1099	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	1100	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	1101
vcoubard	607:e98331f1d6b5	1102	/* Bit 0 : Disable interrupt on ENDECB event. */
vcoubard	607:e98331f1d6b5	1103	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
vcoubard	607:e98331f1d6b5	1104	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
vcoubard	607:e98331f1d6b5	1105	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	1106	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	1107	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	1108
vcoubard	607:e98331f1d6b5	1109	/* Register: ECB_POWER */
vcoubard	607:e98331f1d6b5	1110	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	1111
vcoubard	607:e98331f1d6b5	1112	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	1113	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	1114	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	1115	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	1116	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	1117
vcoubard	607:e98331f1d6b5	1118
vcoubard	607:e98331f1d6b5	1119	/* Peripheral: FICR */
vcoubard	607:e98331f1d6b5	1120	/* Description: Factory Information Configuration. */
vcoubard	607:e98331f1d6b5	1121
vcoubard	607:e98331f1d6b5	1122	/* Register: FICR_PPFC */
vcoubard	607:e98331f1d6b5	1123	/* Description: Pre-programmed factory code present. */
vcoubard	607:e98331f1d6b5	1124
vcoubard	607:e98331f1d6b5	1125	/* Bits 7..0 : Pre-programmed factory code present. */
vcoubard	607:e98331f1d6b5	1126	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
vcoubard	607:e98331f1d6b5	1127	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
vcoubard	607:e98331f1d6b5	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
vcoubard	607:e98331f1d6b5	1129	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
vcoubard	607:e98331f1d6b5	1130
vcoubard	607:e98331f1d6b5	1131	/* Register: FICR_CONFIGID */
vcoubard	607:e98331f1d6b5	1132	/* Description: Configuration identifier. */
vcoubard	607:e98331f1d6b5	1133
vcoubard	607:e98331f1d6b5	1134	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
vcoubard	607:e98331f1d6b5	1135	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
vcoubard	607:e98331f1d6b5	1136	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
vcoubard	607:e98331f1d6b5	1137
vcoubard	607:e98331f1d6b5	1138	/* Bits 15..0 : Hardware Identification Number. */
vcoubard	607:e98331f1d6b5	1139	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
vcoubard	607:e98331f1d6b5	1140	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
vcoubard	607:e98331f1d6b5	1141
vcoubard	607:e98331f1d6b5	1142	/* Register: FICR_DEVICEADDRTYPE */
vcoubard	607:e98331f1d6b5	1143	/* Description: Device address type. */
vcoubard	607:e98331f1d6b5	1144
vcoubard	607:e98331f1d6b5	1145	/* Bit 0 : Device address type. */
vcoubard	607:e98331f1d6b5	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
vcoubard	607:e98331f1d6b5	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
vcoubard	607:e98331f1d6b5	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
vcoubard	607:e98331f1d6b5	1149	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
vcoubard	607:e98331f1d6b5	1150
vcoubard	607:e98331f1d6b5	1151	/* Register: FICR_OVERRIDEEN */
vcoubard	607:e98331f1d6b5	1152	/* Description: Radio calibration override enable. */
vcoubard	607:e98331f1d6b5	1153
vcoubard	607:e98331f1d6b5	1154	/* Bit 3 : Override default values for BLE_1Mbit mode. */
vcoubard	607:e98331f1d6b5	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
vcoubard	607:e98331f1d6b5	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
vcoubard	607:e98331f1d6b5	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
vcoubard	607:e98331f1d6b5	1158	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
vcoubard	607:e98331f1d6b5	1159
vcoubard	607:e98331f1d6b5	1160	/* Bit 0 : Override default values for NRF_1Mbit mode. */
vcoubard	607:e98331f1d6b5	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
vcoubard	607:e98331f1d6b5	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
vcoubard	607:e98331f1d6b5	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
vcoubard	607:e98331f1d6b5	1164	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
vcoubard	607:e98331f1d6b5	1165
vcoubard	607:e98331f1d6b5	1166
vcoubard	607:e98331f1d6b5	1167	/* Peripheral: GPIO */
vcoubard	607:e98331f1d6b5	1168	/* Description: General purpose input and output. */
vcoubard	607:e98331f1d6b5	1169
vcoubard	607:e98331f1d6b5	1170	/* Register: GPIO_OUT */
vcoubard	607:e98331f1d6b5	1171	/* Description: Write GPIO port. */
vcoubard	607:e98331f1d6b5	1172
vcoubard	607:e98331f1d6b5	1173	/* Bit 31 : Pin 31. */
vcoubard	607:e98331f1d6b5	1174	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	607:e98331f1d6b5	1175	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	607:e98331f1d6b5	1176	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1177	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1178
vcoubard	607:e98331f1d6b5	1179	/* Bit 30 : Pin 30. */
vcoubard	607:e98331f1d6b5	1180	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	607:e98331f1d6b5	1181	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	607:e98331f1d6b5	1182	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1183	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1184
vcoubard	607:e98331f1d6b5	1185	/* Bit 29 : Pin 29. */
vcoubard	607:e98331f1d6b5	1186	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	607:e98331f1d6b5	1187	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	607:e98331f1d6b5	1188	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1189	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1190
vcoubard	607:e98331f1d6b5	1191	/* Bit 28 : Pin 28. */
vcoubard	607:e98331f1d6b5	1192	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	607:e98331f1d6b5	1193	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	607:e98331f1d6b5	1194	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1195	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1196
vcoubard	607:e98331f1d6b5	1197	/* Bit 27 : Pin 27. */
vcoubard	607:e98331f1d6b5	1198	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	607:e98331f1d6b5	1199	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	607:e98331f1d6b5	1200	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1201	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1202
vcoubard	607:e98331f1d6b5	1203	/* Bit 26 : Pin 26. */
vcoubard	607:e98331f1d6b5	1204	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	607:e98331f1d6b5	1205	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	607:e98331f1d6b5	1206	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1207	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1208
vcoubard	607:e98331f1d6b5	1209	/* Bit 25 : Pin 25. */
vcoubard	607:e98331f1d6b5	1210	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	607:e98331f1d6b5	1211	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	607:e98331f1d6b5	1212	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1213	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1214
vcoubard	607:e98331f1d6b5	1215	/* Bit 24 : Pin 24. */
vcoubard	607:e98331f1d6b5	1216	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	607:e98331f1d6b5	1217	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	607:e98331f1d6b5	1218	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1219	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1220
vcoubard	607:e98331f1d6b5	1221	/* Bit 23 : Pin 23. */
vcoubard	607:e98331f1d6b5	1222	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	607:e98331f1d6b5	1223	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	607:e98331f1d6b5	1224	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1225	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1226
vcoubard	607:e98331f1d6b5	1227	/* Bit 22 : Pin 22. */
vcoubard	607:e98331f1d6b5	1228	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	607:e98331f1d6b5	1229	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	607:e98331f1d6b5	1230	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1231	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1232
vcoubard	607:e98331f1d6b5	1233	/* Bit 21 : Pin 21. */
vcoubard	607:e98331f1d6b5	1234	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	607:e98331f1d6b5	1235	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	607:e98331f1d6b5	1236	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1237	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1238
vcoubard	607:e98331f1d6b5	1239	/* Bit 20 : Pin 20. */
vcoubard	607:e98331f1d6b5	1240	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	607:e98331f1d6b5	1241	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	607:e98331f1d6b5	1242	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1243	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1244
vcoubard	607:e98331f1d6b5	1245	/* Bit 19 : Pin 19. */
vcoubard	607:e98331f1d6b5	1246	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	607:e98331f1d6b5	1247	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	607:e98331f1d6b5	1248	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1249	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1250
vcoubard	607:e98331f1d6b5	1251	/* Bit 18 : Pin 18. */
vcoubard	607:e98331f1d6b5	1252	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	607:e98331f1d6b5	1253	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	607:e98331f1d6b5	1254	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1255	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1256
vcoubard	607:e98331f1d6b5	1257	/* Bit 17 : Pin 17. */
vcoubard	607:e98331f1d6b5	1258	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	607:e98331f1d6b5	1259	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	607:e98331f1d6b5	1260	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1261	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1262
vcoubard	607:e98331f1d6b5	1263	/* Bit 16 : Pin 16. */
vcoubard	607:e98331f1d6b5	1264	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	607:e98331f1d6b5	1265	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	607:e98331f1d6b5	1266	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1267	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1268
vcoubard	607:e98331f1d6b5	1269	/* Bit 15 : Pin 15. */
vcoubard	607:e98331f1d6b5	1270	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	607:e98331f1d6b5	1271	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	607:e98331f1d6b5	1272	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1273	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1274
vcoubard	607:e98331f1d6b5	1275	/* Bit 14 : Pin 14. */
vcoubard	607:e98331f1d6b5	1276	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	607:e98331f1d6b5	1277	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	607:e98331f1d6b5	1278	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1279	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1280
vcoubard	607:e98331f1d6b5	1281	/* Bit 13 : Pin 13. */
vcoubard	607:e98331f1d6b5	1282	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	607:e98331f1d6b5	1283	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	607:e98331f1d6b5	1284	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1285	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1286
vcoubard	607:e98331f1d6b5	1287	/* Bit 12 : Pin 12. */
vcoubard	607:e98331f1d6b5	1288	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	607:e98331f1d6b5	1289	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	607:e98331f1d6b5	1290	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1291	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1292
vcoubard	607:e98331f1d6b5	1293	/* Bit 11 : Pin 11. */
vcoubard	607:e98331f1d6b5	1294	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	607:e98331f1d6b5	1295	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	607:e98331f1d6b5	1296	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1297	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1298
vcoubard	607:e98331f1d6b5	1299	/* Bit 10 : Pin 10. */
vcoubard	607:e98331f1d6b5	1300	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	607:e98331f1d6b5	1301	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	607:e98331f1d6b5	1302	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1303	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1304
vcoubard	607:e98331f1d6b5	1305	/* Bit 9 : Pin 9. */
vcoubard	607:e98331f1d6b5	1306	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	607:e98331f1d6b5	1307	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	607:e98331f1d6b5	1308	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1309	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1310
vcoubard	607:e98331f1d6b5	1311	/* Bit 8 : Pin 8. */
vcoubard	607:e98331f1d6b5	1312	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	607:e98331f1d6b5	1313	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	607:e98331f1d6b5	1314	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1315	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1316
vcoubard	607:e98331f1d6b5	1317	/* Bit 7 : Pin 7. */
vcoubard	607:e98331f1d6b5	1318	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	607:e98331f1d6b5	1319	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	607:e98331f1d6b5	1320	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1321	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1322
vcoubard	607:e98331f1d6b5	1323	/* Bit 6 : Pin 6. */
vcoubard	607:e98331f1d6b5	1324	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	607:e98331f1d6b5	1325	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	607:e98331f1d6b5	1326	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1327	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1328
vcoubard	607:e98331f1d6b5	1329	/* Bit 5 : Pin 5. */
vcoubard	607:e98331f1d6b5	1330	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	607:e98331f1d6b5	1331	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	607:e98331f1d6b5	1332	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1333	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1334
vcoubard	607:e98331f1d6b5	1335	/* Bit 4 : Pin 4. */
vcoubard	607:e98331f1d6b5	1336	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	607:e98331f1d6b5	1337	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	607:e98331f1d6b5	1338	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1339	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1340
vcoubard	607:e98331f1d6b5	1341	/* Bit 3 : Pin 3. */
vcoubard	607:e98331f1d6b5	1342	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	607:e98331f1d6b5	1343	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	607:e98331f1d6b5	1344	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1345	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1346
vcoubard	607:e98331f1d6b5	1347	/* Bit 2 : Pin 2. */
vcoubard	607:e98331f1d6b5	1348	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	607:e98331f1d6b5	1349	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	607:e98331f1d6b5	1350	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1351	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1352
vcoubard	607:e98331f1d6b5	1353	/* Bit 1 : Pin 1. */
vcoubard	607:e98331f1d6b5	1354	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	607:e98331f1d6b5	1355	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	607:e98331f1d6b5	1356	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1357	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1358
vcoubard	607:e98331f1d6b5	1359	/* Bit 0 : Pin 0. */
vcoubard	607:e98331f1d6b5	1360	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	607:e98331f1d6b5	1361	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	607:e98331f1d6b5	1362	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1363	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1364
vcoubard	607:e98331f1d6b5	1365	/* Register: GPIO_OUTSET */
vcoubard	607:e98331f1d6b5	1366	/* Description: Set individual bits in GPIO port. */
vcoubard	607:e98331f1d6b5	1367
vcoubard	607:e98331f1d6b5	1368	/* Bit 31 : Pin 31. */
vcoubard	607:e98331f1d6b5	1369	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	607:e98331f1d6b5	1370	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	607:e98331f1d6b5	1371	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1372	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1373	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1374
vcoubard	607:e98331f1d6b5	1375	/* Bit 30 : Pin 30. */
vcoubard	607:e98331f1d6b5	1376	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	607:e98331f1d6b5	1377	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	607:e98331f1d6b5	1378	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1379	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1380	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1381
vcoubard	607:e98331f1d6b5	1382	/* Bit 29 : Pin 29. */
vcoubard	607:e98331f1d6b5	1383	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	607:e98331f1d6b5	1384	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	607:e98331f1d6b5	1385	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1386	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1387	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1388
vcoubard	607:e98331f1d6b5	1389	/* Bit 28 : Pin 28. */
vcoubard	607:e98331f1d6b5	1390	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	607:e98331f1d6b5	1391	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	607:e98331f1d6b5	1392	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1393	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1394	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1395
vcoubard	607:e98331f1d6b5	1396	/* Bit 27 : Pin 27. */
vcoubard	607:e98331f1d6b5	1397	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	607:e98331f1d6b5	1398	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	607:e98331f1d6b5	1399	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1400	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1401	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1402
vcoubard	607:e98331f1d6b5	1403	/* Bit 26 : Pin 26. */
vcoubard	607:e98331f1d6b5	1404	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	607:e98331f1d6b5	1405	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	607:e98331f1d6b5	1406	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1407	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1408	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1409
vcoubard	607:e98331f1d6b5	1410	/* Bit 25 : Pin 25. */
vcoubard	607:e98331f1d6b5	1411	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	607:e98331f1d6b5	1412	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	607:e98331f1d6b5	1413	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1414	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1415	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1416
vcoubard	607:e98331f1d6b5	1417	/* Bit 24 : Pin 24. */
vcoubard	607:e98331f1d6b5	1418	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	607:e98331f1d6b5	1419	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	607:e98331f1d6b5	1420	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1421	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1422	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1423
vcoubard	607:e98331f1d6b5	1424	/* Bit 23 : Pin 23. */
vcoubard	607:e98331f1d6b5	1425	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	607:e98331f1d6b5	1426	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	607:e98331f1d6b5	1427	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1428	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1429	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1430
vcoubard	607:e98331f1d6b5	1431	/* Bit 22 : Pin 22. */
vcoubard	607:e98331f1d6b5	1432	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	607:e98331f1d6b5	1433	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	607:e98331f1d6b5	1434	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1435	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1436	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1437
vcoubard	607:e98331f1d6b5	1438	/* Bit 21 : Pin 21. */
vcoubard	607:e98331f1d6b5	1439	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	607:e98331f1d6b5	1440	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	607:e98331f1d6b5	1441	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1442	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1443	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1444
vcoubard	607:e98331f1d6b5	1445	/* Bit 20 : Pin 20. */
vcoubard	607:e98331f1d6b5	1446	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	607:e98331f1d6b5	1447	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	607:e98331f1d6b5	1448	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1449	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1450	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1451
vcoubard	607:e98331f1d6b5	1452	/* Bit 19 : Pin 19. */
vcoubard	607:e98331f1d6b5	1453	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	607:e98331f1d6b5	1454	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	607:e98331f1d6b5	1455	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1456	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1457	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1458
vcoubard	607:e98331f1d6b5	1459	/* Bit 18 : Pin 18. */
vcoubard	607:e98331f1d6b5	1460	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	607:e98331f1d6b5	1461	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	607:e98331f1d6b5	1462	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1463	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1464	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1465
vcoubard	607:e98331f1d6b5	1466	/* Bit 17 : Pin 17. */
vcoubard	607:e98331f1d6b5	1467	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	607:e98331f1d6b5	1468	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	607:e98331f1d6b5	1469	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1470	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1471	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1472
vcoubard	607:e98331f1d6b5	1473	/* Bit 16 : Pin 16. */
vcoubard	607:e98331f1d6b5	1474	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	607:e98331f1d6b5	1475	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	607:e98331f1d6b5	1476	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1477	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1478	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1479
vcoubard	607:e98331f1d6b5	1480	/* Bit 15 : Pin 15. */
vcoubard	607:e98331f1d6b5	1481	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	607:e98331f1d6b5	1482	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	607:e98331f1d6b5	1483	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1484	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1485	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1486
vcoubard	607:e98331f1d6b5	1487	/* Bit 14 : Pin 14. */
vcoubard	607:e98331f1d6b5	1488	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	607:e98331f1d6b5	1489	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	607:e98331f1d6b5	1490	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1491	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1492	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1493
vcoubard	607:e98331f1d6b5	1494	/* Bit 13 : Pin 13. */
vcoubard	607:e98331f1d6b5	1495	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	607:e98331f1d6b5	1496	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	607:e98331f1d6b5	1497	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1498	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1499	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1500
vcoubard	607:e98331f1d6b5	1501	/* Bit 12 : Pin 12. */
vcoubard	607:e98331f1d6b5	1502	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	607:e98331f1d6b5	1503	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	607:e98331f1d6b5	1504	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1505	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1506	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1507
vcoubard	607:e98331f1d6b5	1508	/* Bit 11 : Pin 11. */
vcoubard	607:e98331f1d6b5	1509	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	607:e98331f1d6b5	1510	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	607:e98331f1d6b5	1511	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1512	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1513	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1514
vcoubard	607:e98331f1d6b5	1515	/* Bit 10 : Pin 10. */
vcoubard	607:e98331f1d6b5	1516	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	607:e98331f1d6b5	1517	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	607:e98331f1d6b5	1518	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1519	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1520	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1521
vcoubard	607:e98331f1d6b5	1522	/* Bit 9 : Pin 9. */
vcoubard	607:e98331f1d6b5	1523	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	607:e98331f1d6b5	1524	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	607:e98331f1d6b5	1525	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1526	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1527	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1528
vcoubard	607:e98331f1d6b5	1529	/* Bit 8 : Pin 8. */
vcoubard	607:e98331f1d6b5	1530	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	607:e98331f1d6b5	1531	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	607:e98331f1d6b5	1532	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1533	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1534	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1535
vcoubard	607:e98331f1d6b5	1536	/* Bit 7 : Pin 7. */
vcoubard	607:e98331f1d6b5	1537	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	607:e98331f1d6b5	1538	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	607:e98331f1d6b5	1539	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1540	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1541	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1542
vcoubard	607:e98331f1d6b5	1543	/* Bit 6 : Pin 6. */
vcoubard	607:e98331f1d6b5	1544	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	607:e98331f1d6b5	1545	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	607:e98331f1d6b5	1546	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1547	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1548	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1549
vcoubard	607:e98331f1d6b5	1550	/* Bit 5 : Pin 5. */
vcoubard	607:e98331f1d6b5	1551	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	607:e98331f1d6b5	1552	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	607:e98331f1d6b5	1553	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1554	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1555	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1556
vcoubard	607:e98331f1d6b5	1557	/* Bit 4 : Pin 4. */
vcoubard	607:e98331f1d6b5	1558	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	607:e98331f1d6b5	1559	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	607:e98331f1d6b5	1560	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1561	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1562	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1563
vcoubard	607:e98331f1d6b5	1564	/* Bit 3 : Pin 3. */
vcoubard	607:e98331f1d6b5	1565	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	607:e98331f1d6b5	1566	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	607:e98331f1d6b5	1567	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1568	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1569	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1570
vcoubard	607:e98331f1d6b5	1571	/* Bit 2 : Pin 2. */
vcoubard	607:e98331f1d6b5	1572	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	607:e98331f1d6b5	1573	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	607:e98331f1d6b5	1574	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1575	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1576	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1577
vcoubard	607:e98331f1d6b5	1578	/* Bit 1 : Pin 1. */
vcoubard	607:e98331f1d6b5	1579	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	607:e98331f1d6b5	1580	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	607:e98331f1d6b5	1581	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1582	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1583	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1584
vcoubard	607:e98331f1d6b5	1585	/* Bit 0 : Pin 0. */
vcoubard	607:e98331f1d6b5	1586	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	607:e98331f1d6b5	1587	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	607:e98331f1d6b5	1588	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1589	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1590	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
vcoubard	607:e98331f1d6b5	1591
vcoubard	607:e98331f1d6b5	1592	/* Register: GPIO_OUTCLR */
vcoubard	607:e98331f1d6b5	1593	/* Description: Clear individual bits in GPIO port. */
vcoubard	607:e98331f1d6b5	1594
vcoubard	607:e98331f1d6b5	1595	/* Bit 31 : Pin 31. */
vcoubard	607:e98331f1d6b5	1596	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	607:e98331f1d6b5	1597	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	607:e98331f1d6b5	1598	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1599	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1600	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1601
vcoubard	607:e98331f1d6b5	1602	/* Bit 30 : Pin 30. */
vcoubard	607:e98331f1d6b5	1603	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	607:e98331f1d6b5	1604	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	607:e98331f1d6b5	1605	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1606	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1607	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1608
vcoubard	607:e98331f1d6b5	1609	/* Bit 29 : Pin 29. */
vcoubard	607:e98331f1d6b5	1610	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	607:e98331f1d6b5	1611	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	607:e98331f1d6b5	1612	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1613	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1614	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1615
vcoubard	607:e98331f1d6b5	1616	/* Bit 28 : Pin 28. */
vcoubard	607:e98331f1d6b5	1617	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	607:e98331f1d6b5	1618	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	607:e98331f1d6b5	1619	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1620	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1621	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1622
vcoubard	607:e98331f1d6b5	1623	/* Bit 27 : Pin 27. */
vcoubard	607:e98331f1d6b5	1624	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	607:e98331f1d6b5	1625	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	607:e98331f1d6b5	1626	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1627	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1628	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1629
vcoubard	607:e98331f1d6b5	1630	/* Bit 26 : Pin 26. */
vcoubard	607:e98331f1d6b5	1631	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	607:e98331f1d6b5	1632	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	607:e98331f1d6b5	1633	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1634	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1635	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1636
vcoubard	607:e98331f1d6b5	1637	/* Bit 25 : Pin 25. */
vcoubard	607:e98331f1d6b5	1638	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	607:e98331f1d6b5	1639	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	607:e98331f1d6b5	1640	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1641	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1642	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1643
vcoubard	607:e98331f1d6b5	1644	/* Bit 24 : Pin 24. */
vcoubard	607:e98331f1d6b5	1645	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	607:e98331f1d6b5	1646	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	607:e98331f1d6b5	1647	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1648	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1649	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1650
vcoubard	607:e98331f1d6b5	1651	/* Bit 23 : Pin 23. */
vcoubard	607:e98331f1d6b5	1652	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	607:e98331f1d6b5	1653	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	607:e98331f1d6b5	1654	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1655	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1656	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1657
vcoubard	607:e98331f1d6b5	1658	/* Bit 22 : Pin 22. */
vcoubard	607:e98331f1d6b5	1659	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	607:e98331f1d6b5	1660	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	607:e98331f1d6b5	1661	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1662	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1663	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1664
vcoubard	607:e98331f1d6b5	1665	/* Bit 21 : Pin 21. */
vcoubard	607:e98331f1d6b5	1666	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	607:e98331f1d6b5	1667	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	607:e98331f1d6b5	1668	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1669	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1670	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1671
vcoubard	607:e98331f1d6b5	1672	/* Bit 20 : Pin 20. */
vcoubard	607:e98331f1d6b5	1673	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	607:e98331f1d6b5	1674	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	607:e98331f1d6b5	1675	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1676	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1677	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1678
vcoubard	607:e98331f1d6b5	1679	/* Bit 19 : Pin 19. */
vcoubard	607:e98331f1d6b5	1680	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	607:e98331f1d6b5	1681	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	607:e98331f1d6b5	1682	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1683	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1684	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1685
vcoubard	607:e98331f1d6b5	1686	/* Bit 18 : Pin 18. */
vcoubard	607:e98331f1d6b5	1687	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	607:e98331f1d6b5	1688	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	607:e98331f1d6b5	1689	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1690	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1691	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1692
vcoubard	607:e98331f1d6b5	1693	/* Bit 17 : Pin 17. */
vcoubard	607:e98331f1d6b5	1694	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	607:e98331f1d6b5	1695	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	607:e98331f1d6b5	1696	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1697	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1698	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1699
vcoubard	607:e98331f1d6b5	1700	/* Bit 16 : Pin 16. */
vcoubard	607:e98331f1d6b5	1701	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	607:e98331f1d6b5	1702	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	607:e98331f1d6b5	1703	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1704	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1705	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1706
vcoubard	607:e98331f1d6b5	1707	/* Bit 15 : Pin 15. */
vcoubard	607:e98331f1d6b5	1708	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	607:e98331f1d6b5	1709	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	607:e98331f1d6b5	1710	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1711	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1712	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1713
vcoubard	607:e98331f1d6b5	1714	/* Bit 14 : Pin 14. */
vcoubard	607:e98331f1d6b5	1715	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	607:e98331f1d6b5	1716	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	607:e98331f1d6b5	1717	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1718	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1719	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1720
vcoubard	607:e98331f1d6b5	1721	/* Bit 13 : Pin 13. */
vcoubard	607:e98331f1d6b5	1722	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	607:e98331f1d6b5	1723	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	607:e98331f1d6b5	1724	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1725	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1726	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1727
vcoubard	607:e98331f1d6b5	1728	/* Bit 12 : Pin 12. */
vcoubard	607:e98331f1d6b5	1729	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	607:e98331f1d6b5	1730	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	607:e98331f1d6b5	1731	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1732	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1733	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1734
vcoubard	607:e98331f1d6b5	1735	/* Bit 11 : Pin 11. */
vcoubard	607:e98331f1d6b5	1736	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	607:e98331f1d6b5	1737	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	607:e98331f1d6b5	1738	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1739	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1740	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1741
vcoubard	607:e98331f1d6b5	1742	/* Bit 10 : Pin 10. */
vcoubard	607:e98331f1d6b5	1743	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	607:e98331f1d6b5	1744	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	607:e98331f1d6b5	1745	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1746	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1747	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1748
vcoubard	607:e98331f1d6b5	1749	/* Bit 9 : Pin 9. */
vcoubard	607:e98331f1d6b5	1750	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	607:e98331f1d6b5	1751	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	607:e98331f1d6b5	1752	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1753	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1754	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1755
vcoubard	607:e98331f1d6b5	1756	/* Bit 8 : Pin 8. */
vcoubard	607:e98331f1d6b5	1757	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	607:e98331f1d6b5	1758	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	607:e98331f1d6b5	1759	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1760	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1761	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1762
vcoubard	607:e98331f1d6b5	1763	/* Bit 7 : Pin 7. */
vcoubard	607:e98331f1d6b5	1764	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	607:e98331f1d6b5	1765	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	607:e98331f1d6b5	1766	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1767	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1768	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1769
vcoubard	607:e98331f1d6b5	1770	/* Bit 6 : Pin 6. */
vcoubard	607:e98331f1d6b5	1771	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	607:e98331f1d6b5	1772	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	607:e98331f1d6b5	1773	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1774	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1775	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1776
vcoubard	607:e98331f1d6b5	1777	/* Bit 5 : Pin 5. */
vcoubard	607:e98331f1d6b5	1778	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	607:e98331f1d6b5	1779	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	607:e98331f1d6b5	1780	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1781	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1782	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1783
vcoubard	607:e98331f1d6b5	1784	/* Bit 4 : Pin 4. */
vcoubard	607:e98331f1d6b5	1785	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	607:e98331f1d6b5	1786	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	607:e98331f1d6b5	1787	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1788	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1789	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1790
vcoubard	607:e98331f1d6b5	1791	/* Bit 3 : Pin 3. */
vcoubard	607:e98331f1d6b5	1792	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	607:e98331f1d6b5	1793	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	607:e98331f1d6b5	1794	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1795	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1796	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1797
vcoubard	607:e98331f1d6b5	1798	/* Bit 2 : Pin 2. */
vcoubard	607:e98331f1d6b5	1799	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	607:e98331f1d6b5	1800	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	607:e98331f1d6b5	1801	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1802	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1803	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1804
vcoubard	607:e98331f1d6b5	1805	/* Bit 1 : Pin 1. */
vcoubard	607:e98331f1d6b5	1806	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	607:e98331f1d6b5	1807	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	607:e98331f1d6b5	1808	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1809	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1810	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1811
vcoubard	607:e98331f1d6b5	1812	/* Bit 0 : Pin 0. */
vcoubard	607:e98331f1d6b5	1813	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	607:e98331f1d6b5	1814	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	607:e98331f1d6b5	1815	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	607:e98331f1d6b5	1816	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	607:e98331f1d6b5	1817	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
vcoubard	607:e98331f1d6b5	1818
vcoubard	607:e98331f1d6b5	1819	/* Register: GPIO_IN */
vcoubard	607:e98331f1d6b5	1820	/* Description: Read GPIO port. */
vcoubard	607:e98331f1d6b5	1821
vcoubard	607:e98331f1d6b5	1822	/* Bit 31 : Pin 31. */
vcoubard	607:e98331f1d6b5	1823	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	607:e98331f1d6b5	1824	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	607:e98331f1d6b5	1825	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1826	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1827
vcoubard	607:e98331f1d6b5	1828	/* Bit 30 : Pin 30. */
vcoubard	607:e98331f1d6b5	1829	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	607:e98331f1d6b5	1830	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	607:e98331f1d6b5	1831	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1832	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1833
vcoubard	607:e98331f1d6b5	1834	/* Bit 29 : Pin 29. */
vcoubard	607:e98331f1d6b5	1835	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	607:e98331f1d6b5	1836	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	607:e98331f1d6b5	1837	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1838	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1839
vcoubard	607:e98331f1d6b5	1840	/* Bit 28 : Pin 28. */
vcoubard	607:e98331f1d6b5	1841	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	607:e98331f1d6b5	1842	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	607:e98331f1d6b5	1843	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1844	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1845
vcoubard	607:e98331f1d6b5	1846	/* Bit 27 : Pin 27. */
vcoubard	607:e98331f1d6b5	1847	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	607:e98331f1d6b5	1848	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	607:e98331f1d6b5	1849	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1850	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1851
vcoubard	607:e98331f1d6b5	1852	/* Bit 26 : Pin 26. */
vcoubard	607:e98331f1d6b5	1853	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	607:e98331f1d6b5	1854	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	607:e98331f1d6b5	1855	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1856	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1857
vcoubard	607:e98331f1d6b5	1858	/* Bit 25 : Pin 25. */
vcoubard	607:e98331f1d6b5	1859	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	607:e98331f1d6b5	1860	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	607:e98331f1d6b5	1861	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1862	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1863
vcoubard	607:e98331f1d6b5	1864	/* Bit 24 : Pin 24. */
vcoubard	607:e98331f1d6b5	1865	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	607:e98331f1d6b5	1866	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	607:e98331f1d6b5	1867	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1868	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1869
vcoubard	607:e98331f1d6b5	1870	/* Bit 23 : Pin 23. */
vcoubard	607:e98331f1d6b5	1871	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	607:e98331f1d6b5	1872	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	607:e98331f1d6b5	1873	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1874	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1875
vcoubard	607:e98331f1d6b5	1876	/* Bit 22 : Pin 22. */
vcoubard	607:e98331f1d6b5	1877	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	607:e98331f1d6b5	1878	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	607:e98331f1d6b5	1879	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1880	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1881
vcoubard	607:e98331f1d6b5	1882	/* Bit 21 : Pin 21. */
vcoubard	607:e98331f1d6b5	1883	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	607:e98331f1d6b5	1884	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	607:e98331f1d6b5	1885	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1886	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1887
vcoubard	607:e98331f1d6b5	1888	/* Bit 20 : Pin 20. */
vcoubard	607:e98331f1d6b5	1889	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	607:e98331f1d6b5	1890	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	607:e98331f1d6b5	1891	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1892	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1893
vcoubard	607:e98331f1d6b5	1894	/* Bit 19 : Pin 19. */
vcoubard	607:e98331f1d6b5	1895	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	607:e98331f1d6b5	1896	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	607:e98331f1d6b5	1897	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1898	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1899
vcoubard	607:e98331f1d6b5	1900	/* Bit 18 : Pin 18. */
vcoubard	607:e98331f1d6b5	1901	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	607:e98331f1d6b5	1902	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	607:e98331f1d6b5	1903	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1904	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1905
vcoubard	607:e98331f1d6b5	1906	/* Bit 17 : Pin 17. */
vcoubard	607:e98331f1d6b5	1907	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	607:e98331f1d6b5	1908	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	607:e98331f1d6b5	1909	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1910	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1911
vcoubard	607:e98331f1d6b5	1912	/* Bit 16 : Pin 16. */
vcoubard	607:e98331f1d6b5	1913	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	607:e98331f1d6b5	1914	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	607:e98331f1d6b5	1915	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1916	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1917
vcoubard	607:e98331f1d6b5	1918	/* Bit 15 : Pin 15. */
vcoubard	607:e98331f1d6b5	1919	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	607:e98331f1d6b5	1920	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	607:e98331f1d6b5	1921	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1922	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1923
vcoubard	607:e98331f1d6b5	1924	/* Bit 14 : Pin 14. */
vcoubard	607:e98331f1d6b5	1925	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	607:e98331f1d6b5	1926	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	607:e98331f1d6b5	1927	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1928	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1929
vcoubard	607:e98331f1d6b5	1930	/* Bit 13 : Pin 13. */
vcoubard	607:e98331f1d6b5	1931	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	607:e98331f1d6b5	1932	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	607:e98331f1d6b5	1933	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1934	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1935
vcoubard	607:e98331f1d6b5	1936	/* Bit 12 : Pin 12. */
vcoubard	607:e98331f1d6b5	1937	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	607:e98331f1d6b5	1938	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	607:e98331f1d6b5	1939	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1940	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1941
vcoubard	607:e98331f1d6b5	1942	/* Bit 11 : Pin 11. */
vcoubard	607:e98331f1d6b5	1943	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	607:e98331f1d6b5	1944	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	607:e98331f1d6b5	1945	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1946	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1947
vcoubard	607:e98331f1d6b5	1948	/* Bit 10 : Pin 10. */
vcoubard	607:e98331f1d6b5	1949	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	607:e98331f1d6b5	1950	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	607:e98331f1d6b5	1951	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1952	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1953
vcoubard	607:e98331f1d6b5	1954	/* Bit 9 : Pin 9. */
vcoubard	607:e98331f1d6b5	1955	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	607:e98331f1d6b5	1956	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	607:e98331f1d6b5	1957	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1958	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1959
vcoubard	607:e98331f1d6b5	1960	/* Bit 8 : Pin 8. */
vcoubard	607:e98331f1d6b5	1961	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	607:e98331f1d6b5	1962	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	607:e98331f1d6b5	1963	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1964	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1965
vcoubard	607:e98331f1d6b5	1966	/* Bit 7 : Pin 7. */
vcoubard	607:e98331f1d6b5	1967	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	607:e98331f1d6b5	1968	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	607:e98331f1d6b5	1969	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1970	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1971
vcoubard	607:e98331f1d6b5	1972	/* Bit 6 : Pin 6. */
vcoubard	607:e98331f1d6b5	1973	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	607:e98331f1d6b5	1974	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	607:e98331f1d6b5	1975	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1976	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1977
vcoubard	607:e98331f1d6b5	1978	/* Bit 5 : Pin 5. */
vcoubard	607:e98331f1d6b5	1979	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	607:e98331f1d6b5	1980	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	607:e98331f1d6b5	1981	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1982	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1983
vcoubard	607:e98331f1d6b5	1984	/* Bit 4 : Pin 4. */
vcoubard	607:e98331f1d6b5	1985	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	607:e98331f1d6b5	1986	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	607:e98331f1d6b5	1987	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1988	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1989
vcoubard	607:e98331f1d6b5	1990	/* Bit 3 : Pin 3. */
vcoubard	607:e98331f1d6b5	1991	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	607:e98331f1d6b5	1992	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	607:e98331f1d6b5	1993	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	1994	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	1995
vcoubard	607:e98331f1d6b5	1996	/* Bit 2 : Pin 2. */
vcoubard	607:e98331f1d6b5	1997	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	607:e98331f1d6b5	1998	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	607:e98331f1d6b5	1999	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	2000	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	2001
vcoubard	607:e98331f1d6b5	2002	/* Bit 1 : Pin 1. */
vcoubard	607:e98331f1d6b5	2003	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	607:e98331f1d6b5	2004	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	607:e98331f1d6b5	2005	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	2006	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	2007
vcoubard	607:e98331f1d6b5	2008	/* Bit 0 : Pin 0. */
vcoubard	607:e98331f1d6b5	2009	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	607:e98331f1d6b5	2010	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	607:e98331f1d6b5	2011	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
vcoubard	607:e98331f1d6b5	2012	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
vcoubard	607:e98331f1d6b5	2013
vcoubard	607:e98331f1d6b5	2014	/* Register: GPIO_DIR */
vcoubard	607:e98331f1d6b5	2015	/* Description: Direction of GPIO pins. */
vcoubard	607:e98331f1d6b5	2016
vcoubard	607:e98331f1d6b5	2017	/* Bit 31 : Pin 31. */
vcoubard	607:e98331f1d6b5	2018	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	607:e98331f1d6b5	2019	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	607:e98331f1d6b5	2020	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2021	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2022
vcoubard	607:e98331f1d6b5	2023	/* Bit 30 : Pin 30. */
vcoubard	607:e98331f1d6b5	2024	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	607:e98331f1d6b5	2025	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	607:e98331f1d6b5	2026	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2027	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2028
vcoubard	607:e98331f1d6b5	2029	/* Bit 29 : Pin 29. */
vcoubard	607:e98331f1d6b5	2030	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	607:e98331f1d6b5	2031	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	607:e98331f1d6b5	2032	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2033	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2034
vcoubard	607:e98331f1d6b5	2035	/* Bit 28 : Pin 28. */
vcoubard	607:e98331f1d6b5	2036	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	607:e98331f1d6b5	2037	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	607:e98331f1d6b5	2038	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2039	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2040
vcoubard	607:e98331f1d6b5	2041	/* Bit 27 : Pin 27. */
vcoubard	607:e98331f1d6b5	2042	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	607:e98331f1d6b5	2043	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	607:e98331f1d6b5	2044	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2045	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2046
vcoubard	607:e98331f1d6b5	2047	/* Bit 26 : Pin 26. */
vcoubard	607:e98331f1d6b5	2048	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	607:e98331f1d6b5	2049	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	607:e98331f1d6b5	2050	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2051	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2052
vcoubard	607:e98331f1d6b5	2053	/* Bit 25 : Pin 25. */
vcoubard	607:e98331f1d6b5	2054	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	607:e98331f1d6b5	2055	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	607:e98331f1d6b5	2056	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2057	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2058
vcoubard	607:e98331f1d6b5	2059	/* Bit 24 : Pin 24. */
vcoubard	607:e98331f1d6b5	2060	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	607:e98331f1d6b5	2061	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	607:e98331f1d6b5	2062	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2063	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2064
vcoubard	607:e98331f1d6b5	2065	/* Bit 23 : Pin 23. */
vcoubard	607:e98331f1d6b5	2066	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	607:e98331f1d6b5	2067	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	607:e98331f1d6b5	2068	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2069	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2070
vcoubard	607:e98331f1d6b5	2071	/* Bit 22 : Pin 22. */
vcoubard	607:e98331f1d6b5	2072	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	607:e98331f1d6b5	2073	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	607:e98331f1d6b5	2074	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2075	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2076
vcoubard	607:e98331f1d6b5	2077	/* Bit 21 : Pin 21. */
vcoubard	607:e98331f1d6b5	2078	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	607:e98331f1d6b5	2079	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	607:e98331f1d6b5	2080	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2081	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2082
vcoubard	607:e98331f1d6b5	2083	/* Bit 20 : Pin 20. */
vcoubard	607:e98331f1d6b5	2084	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	607:e98331f1d6b5	2085	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	607:e98331f1d6b5	2086	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2087	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2088
vcoubard	607:e98331f1d6b5	2089	/* Bit 19 : Pin 19. */
vcoubard	607:e98331f1d6b5	2090	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	607:e98331f1d6b5	2091	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	607:e98331f1d6b5	2092	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2093	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2094
vcoubard	607:e98331f1d6b5	2095	/* Bit 18 : Pin 18. */
vcoubard	607:e98331f1d6b5	2096	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	607:e98331f1d6b5	2097	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	607:e98331f1d6b5	2098	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2099	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2100
vcoubard	607:e98331f1d6b5	2101	/* Bit 17 : Pin 17. */
vcoubard	607:e98331f1d6b5	2102	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	607:e98331f1d6b5	2103	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	607:e98331f1d6b5	2104	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2105	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2106
vcoubard	607:e98331f1d6b5	2107	/* Bit 16 : Pin 16. */
vcoubard	607:e98331f1d6b5	2108	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	607:e98331f1d6b5	2109	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	607:e98331f1d6b5	2110	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2111	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2112
vcoubard	607:e98331f1d6b5	2113	/* Bit 15 : Pin 15. */
vcoubard	607:e98331f1d6b5	2114	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	607:e98331f1d6b5	2115	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	607:e98331f1d6b5	2116	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2117	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2118
vcoubard	607:e98331f1d6b5	2119	/* Bit 14 : Pin 14. */
vcoubard	607:e98331f1d6b5	2120	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	607:e98331f1d6b5	2121	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	607:e98331f1d6b5	2122	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2123	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2124
vcoubard	607:e98331f1d6b5	2125	/* Bit 13 : Pin 13. */
vcoubard	607:e98331f1d6b5	2126	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	607:e98331f1d6b5	2127	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	607:e98331f1d6b5	2128	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2129	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2130
vcoubard	607:e98331f1d6b5	2131	/* Bit 12 : Pin 12. */
vcoubard	607:e98331f1d6b5	2132	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	607:e98331f1d6b5	2133	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	607:e98331f1d6b5	2134	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2135	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2136
vcoubard	607:e98331f1d6b5	2137	/* Bit 11 : Pin 11. */
vcoubard	607:e98331f1d6b5	2138	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	607:e98331f1d6b5	2139	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	607:e98331f1d6b5	2140	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2141	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2142
vcoubard	607:e98331f1d6b5	2143	/* Bit 10 : Pin 10. */
vcoubard	607:e98331f1d6b5	2144	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	607:e98331f1d6b5	2145	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	607:e98331f1d6b5	2146	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2147	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2148
vcoubard	607:e98331f1d6b5	2149	/* Bit 9 : Pin 9. */
vcoubard	607:e98331f1d6b5	2150	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	607:e98331f1d6b5	2151	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	607:e98331f1d6b5	2152	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2153	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2154
vcoubard	607:e98331f1d6b5	2155	/* Bit 8 : Pin 8. */
vcoubard	607:e98331f1d6b5	2156	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	607:e98331f1d6b5	2157	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	607:e98331f1d6b5	2158	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2159	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2160
vcoubard	607:e98331f1d6b5	2161	/* Bit 7 : Pin 7. */
vcoubard	607:e98331f1d6b5	2162	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	607:e98331f1d6b5	2163	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	607:e98331f1d6b5	2164	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2165	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2166
vcoubard	607:e98331f1d6b5	2167	/* Bit 6 : Pin 6. */
vcoubard	607:e98331f1d6b5	2168	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	607:e98331f1d6b5	2169	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	607:e98331f1d6b5	2170	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2171	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2172
vcoubard	607:e98331f1d6b5	2173	/* Bit 5 : Pin 5. */
vcoubard	607:e98331f1d6b5	2174	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	607:e98331f1d6b5	2175	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	607:e98331f1d6b5	2176	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2177	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2178
vcoubard	607:e98331f1d6b5	2179	/* Bit 4 : Pin 4. */
vcoubard	607:e98331f1d6b5	2180	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	607:e98331f1d6b5	2181	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	607:e98331f1d6b5	2182	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2183	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2184
vcoubard	607:e98331f1d6b5	2185	/* Bit 3 : Pin 3. */
vcoubard	607:e98331f1d6b5	2186	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	607:e98331f1d6b5	2187	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	607:e98331f1d6b5	2188	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2189	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2190
vcoubard	607:e98331f1d6b5	2191	/* Bit 2 : Pin 2. */
vcoubard	607:e98331f1d6b5	2192	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	607:e98331f1d6b5	2193	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	607:e98331f1d6b5	2194	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2195	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2196
vcoubard	607:e98331f1d6b5	2197	/* Bit 1 : Pin 1. */
vcoubard	607:e98331f1d6b5	2198	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	607:e98331f1d6b5	2199	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	607:e98331f1d6b5	2200	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2201	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2202
vcoubard	607:e98331f1d6b5	2203	/* Bit 0 : Pin 0. */
vcoubard	607:e98331f1d6b5	2204	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	607:e98331f1d6b5	2205	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	607:e98331f1d6b5	2206	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2207	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2208
vcoubard	607:e98331f1d6b5	2209	/* Register: GPIO_DIRSET */
vcoubard	607:e98331f1d6b5	2210	/* Description: DIR set register. */
vcoubard	607:e98331f1d6b5	2211
vcoubard	607:e98331f1d6b5	2212	/* Bit 31 : Set as output pin 31. */
vcoubard	607:e98331f1d6b5	2213	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	607:e98331f1d6b5	2214	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	607:e98331f1d6b5	2215	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2216	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2217	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2218
vcoubard	607:e98331f1d6b5	2219	/* Bit 30 : Set as output pin 30. */
vcoubard	607:e98331f1d6b5	2220	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	607:e98331f1d6b5	2221	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	607:e98331f1d6b5	2222	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2223	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2224	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2225
vcoubard	607:e98331f1d6b5	2226	/* Bit 29 : Set as output pin 29. */
vcoubard	607:e98331f1d6b5	2227	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	607:e98331f1d6b5	2228	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	607:e98331f1d6b5	2229	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2230	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2231	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2232
vcoubard	607:e98331f1d6b5	2233	/* Bit 28 : Set as output pin 28. */
vcoubard	607:e98331f1d6b5	2234	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	607:e98331f1d6b5	2235	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	607:e98331f1d6b5	2236	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2237	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2238	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2239
vcoubard	607:e98331f1d6b5	2240	/* Bit 27 : Set as output pin 27. */
vcoubard	607:e98331f1d6b5	2241	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	607:e98331f1d6b5	2242	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	607:e98331f1d6b5	2243	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2244	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2245	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2246
vcoubard	607:e98331f1d6b5	2247	/* Bit 26 : Set as output pin 26. */
vcoubard	607:e98331f1d6b5	2248	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	607:e98331f1d6b5	2249	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	607:e98331f1d6b5	2250	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2251	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2252	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2253
vcoubard	607:e98331f1d6b5	2254	/* Bit 25 : Set as output pin 25. */
vcoubard	607:e98331f1d6b5	2255	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	607:e98331f1d6b5	2256	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	607:e98331f1d6b5	2257	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2258	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2259	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2260
vcoubard	607:e98331f1d6b5	2261	/* Bit 24 : Set as output pin 24. */
vcoubard	607:e98331f1d6b5	2262	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	607:e98331f1d6b5	2263	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	607:e98331f1d6b5	2264	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2265	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2266	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2267
vcoubard	607:e98331f1d6b5	2268	/* Bit 23 : Set as output pin 23. */
vcoubard	607:e98331f1d6b5	2269	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	607:e98331f1d6b5	2270	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	607:e98331f1d6b5	2271	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2272	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2273	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2274
vcoubard	607:e98331f1d6b5	2275	/* Bit 22 : Set as output pin 22. */
vcoubard	607:e98331f1d6b5	2276	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	607:e98331f1d6b5	2277	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	607:e98331f1d6b5	2278	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2279	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2280	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2281
vcoubard	607:e98331f1d6b5	2282	/* Bit 21 : Set as output pin 21. */
vcoubard	607:e98331f1d6b5	2283	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	607:e98331f1d6b5	2284	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	607:e98331f1d6b5	2285	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2286	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2287	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2288
vcoubard	607:e98331f1d6b5	2289	/* Bit 20 : Set as output pin 20. */
vcoubard	607:e98331f1d6b5	2290	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	607:e98331f1d6b5	2291	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	607:e98331f1d6b5	2292	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2293	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2294	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2295
vcoubard	607:e98331f1d6b5	2296	/* Bit 19 : Set as output pin 19. */
vcoubard	607:e98331f1d6b5	2297	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	607:e98331f1d6b5	2298	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	607:e98331f1d6b5	2299	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2300	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2301	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2302
vcoubard	607:e98331f1d6b5	2303	/* Bit 18 : Set as output pin 18. */
vcoubard	607:e98331f1d6b5	2304	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	607:e98331f1d6b5	2305	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	607:e98331f1d6b5	2306	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2307	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2308	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2309
vcoubard	607:e98331f1d6b5	2310	/* Bit 17 : Set as output pin 17. */
vcoubard	607:e98331f1d6b5	2311	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	607:e98331f1d6b5	2312	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	607:e98331f1d6b5	2313	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2314	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2315	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2316
vcoubard	607:e98331f1d6b5	2317	/* Bit 16 : Set as output pin 16. */
vcoubard	607:e98331f1d6b5	2318	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	607:e98331f1d6b5	2319	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	607:e98331f1d6b5	2320	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2321	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2322	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2323
vcoubard	607:e98331f1d6b5	2324	/* Bit 15 : Set as output pin 15. */
vcoubard	607:e98331f1d6b5	2325	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	607:e98331f1d6b5	2326	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	607:e98331f1d6b5	2327	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2328	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2329	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2330
vcoubard	607:e98331f1d6b5	2331	/* Bit 14 : Set as output pin 14. */
vcoubard	607:e98331f1d6b5	2332	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	607:e98331f1d6b5	2333	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	607:e98331f1d6b5	2334	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2335	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2336	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2337
vcoubard	607:e98331f1d6b5	2338	/* Bit 13 : Set as output pin 13. */
vcoubard	607:e98331f1d6b5	2339	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	607:e98331f1d6b5	2340	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	607:e98331f1d6b5	2341	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2342	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2343	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2344
vcoubard	607:e98331f1d6b5	2345	/* Bit 12 : Set as output pin 12. */
vcoubard	607:e98331f1d6b5	2346	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	607:e98331f1d6b5	2347	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	607:e98331f1d6b5	2348	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2349	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2350	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2351
vcoubard	607:e98331f1d6b5	2352	/* Bit 11 : Set as output pin 11. */
vcoubard	607:e98331f1d6b5	2353	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	607:e98331f1d6b5	2354	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	607:e98331f1d6b5	2355	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2356	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2357	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2358
vcoubard	607:e98331f1d6b5	2359	/* Bit 10 : Set as output pin 10. */
vcoubard	607:e98331f1d6b5	2360	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	607:e98331f1d6b5	2361	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	607:e98331f1d6b5	2362	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2363	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2364	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2365
vcoubard	607:e98331f1d6b5	2366	/* Bit 9 : Set as output pin 9. */
vcoubard	607:e98331f1d6b5	2367	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	607:e98331f1d6b5	2368	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	607:e98331f1d6b5	2369	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2370	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2371	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2372
vcoubard	607:e98331f1d6b5	2373	/* Bit 8 : Set as output pin 8. */
vcoubard	607:e98331f1d6b5	2374	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	607:e98331f1d6b5	2375	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	607:e98331f1d6b5	2376	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2377	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2378	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2379
vcoubard	607:e98331f1d6b5	2380	/* Bit 7 : Set as output pin 7. */
vcoubard	607:e98331f1d6b5	2381	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	607:e98331f1d6b5	2382	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	607:e98331f1d6b5	2383	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2384	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2385	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2386
vcoubard	607:e98331f1d6b5	2387	/* Bit 6 : Set as output pin 6. */
vcoubard	607:e98331f1d6b5	2388	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	607:e98331f1d6b5	2389	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	607:e98331f1d6b5	2390	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2391	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2392	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2393
vcoubard	607:e98331f1d6b5	2394	/* Bit 5 : Set as output pin 5. */
vcoubard	607:e98331f1d6b5	2395	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	607:e98331f1d6b5	2396	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	607:e98331f1d6b5	2397	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2398	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2399	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2400
vcoubard	607:e98331f1d6b5	2401	/* Bit 4 : Set as output pin 4. */
vcoubard	607:e98331f1d6b5	2402	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	607:e98331f1d6b5	2403	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	607:e98331f1d6b5	2404	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2405	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2406	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2407
vcoubard	607:e98331f1d6b5	2408	/* Bit 3 : Set as output pin 3. */
vcoubard	607:e98331f1d6b5	2409	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	607:e98331f1d6b5	2410	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	607:e98331f1d6b5	2411	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2412	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2413	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2414
vcoubard	607:e98331f1d6b5	2415	/* Bit 2 : Set as output pin 2. */
vcoubard	607:e98331f1d6b5	2416	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	607:e98331f1d6b5	2417	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	607:e98331f1d6b5	2418	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2419	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2420	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2421
vcoubard	607:e98331f1d6b5	2422	/* Bit 1 : Set as output pin 1. */
vcoubard	607:e98331f1d6b5	2423	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	607:e98331f1d6b5	2424	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	607:e98331f1d6b5	2425	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2426	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2427	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2428
vcoubard	607:e98331f1d6b5	2429	/* Bit 0 : Set as output pin 0. */
vcoubard	607:e98331f1d6b5	2430	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	607:e98331f1d6b5	2431	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	607:e98331f1d6b5	2432	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2433	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2434	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
vcoubard	607:e98331f1d6b5	2435
vcoubard	607:e98331f1d6b5	2436	/* Register: GPIO_DIRCLR */
vcoubard	607:e98331f1d6b5	2437	/* Description: DIR clear register. */
vcoubard	607:e98331f1d6b5	2438
vcoubard	607:e98331f1d6b5	2439	/* Bit 31 : Set as input pin 31. */
vcoubard	607:e98331f1d6b5	2440	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	607:e98331f1d6b5	2441	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	607:e98331f1d6b5	2442	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2443	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2444	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2445
vcoubard	607:e98331f1d6b5	2446	/* Bit 30 : Set as input pin 30. */
vcoubard	607:e98331f1d6b5	2447	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	607:e98331f1d6b5	2448	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	607:e98331f1d6b5	2449	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2450	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2451	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2452
vcoubard	607:e98331f1d6b5	2453	/* Bit 29 : Set as input pin 29. */
vcoubard	607:e98331f1d6b5	2454	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	607:e98331f1d6b5	2455	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	607:e98331f1d6b5	2456	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2457	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2458	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2459
vcoubard	607:e98331f1d6b5	2460	/* Bit 28 : Set as input pin 28. */
vcoubard	607:e98331f1d6b5	2461	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	607:e98331f1d6b5	2462	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	607:e98331f1d6b5	2463	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2464	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2465	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2466
vcoubard	607:e98331f1d6b5	2467	/* Bit 27 : Set as input pin 27. */
vcoubard	607:e98331f1d6b5	2468	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	607:e98331f1d6b5	2469	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	607:e98331f1d6b5	2470	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2471	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2472	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2473
vcoubard	607:e98331f1d6b5	2474	/* Bit 26 : Set as input pin 26. */
vcoubard	607:e98331f1d6b5	2475	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	607:e98331f1d6b5	2476	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	607:e98331f1d6b5	2477	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2478	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2479	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2480
vcoubard	607:e98331f1d6b5	2481	/* Bit 25 : Set as input pin 25. */
vcoubard	607:e98331f1d6b5	2482	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	607:e98331f1d6b5	2483	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	607:e98331f1d6b5	2484	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2485	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2486	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2487
vcoubard	607:e98331f1d6b5	2488	/* Bit 24 : Set as input pin 24. */
vcoubard	607:e98331f1d6b5	2489	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	607:e98331f1d6b5	2490	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	607:e98331f1d6b5	2491	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2492	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2493	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2494
vcoubard	607:e98331f1d6b5	2495	/* Bit 23 : Set as input pin 23. */
vcoubard	607:e98331f1d6b5	2496	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	607:e98331f1d6b5	2497	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	607:e98331f1d6b5	2498	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2499	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2500	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2501
vcoubard	607:e98331f1d6b5	2502	/* Bit 22 : Set as input pin 22. */
vcoubard	607:e98331f1d6b5	2503	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	607:e98331f1d6b5	2504	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	607:e98331f1d6b5	2505	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2506	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2507	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2508
vcoubard	607:e98331f1d6b5	2509	/* Bit 21 : Set as input pin 21. */
vcoubard	607:e98331f1d6b5	2510	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	607:e98331f1d6b5	2511	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	607:e98331f1d6b5	2512	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2513	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2514	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2515
vcoubard	607:e98331f1d6b5	2516	/* Bit 20 : Set as input pin 20. */
vcoubard	607:e98331f1d6b5	2517	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	607:e98331f1d6b5	2518	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	607:e98331f1d6b5	2519	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2520	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2521	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2522
vcoubard	607:e98331f1d6b5	2523	/* Bit 19 : Set as input pin 19. */
vcoubard	607:e98331f1d6b5	2524	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	607:e98331f1d6b5	2525	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	607:e98331f1d6b5	2526	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2527	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2528	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2529
vcoubard	607:e98331f1d6b5	2530	/* Bit 18 : Set as input pin 18. */
vcoubard	607:e98331f1d6b5	2531	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	607:e98331f1d6b5	2532	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	607:e98331f1d6b5	2533	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2534	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2535	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2536
vcoubard	607:e98331f1d6b5	2537	/* Bit 17 : Set as input pin 17. */
vcoubard	607:e98331f1d6b5	2538	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	607:e98331f1d6b5	2539	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	607:e98331f1d6b5	2540	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2541	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2542	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2543
vcoubard	607:e98331f1d6b5	2544	/* Bit 16 : Set as input pin 16. */
vcoubard	607:e98331f1d6b5	2545	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	607:e98331f1d6b5	2546	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	607:e98331f1d6b5	2547	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2548	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2549	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2550
vcoubard	607:e98331f1d6b5	2551	/* Bit 15 : Set as input pin 15. */
vcoubard	607:e98331f1d6b5	2552	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	607:e98331f1d6b5	2553	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	607:e98331f1d6b5	2554	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2555	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2556	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2557
vcoubard	607:e98331f1d6b5	2558	/* Bit 14 : Set as input pin 14. */
vcoubard	607:e98331f1d6b5	2559	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	607:e98331f1d6b5	2560	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	607:e98331f1d6b5	2561	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2562	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2563	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2564
vcoubard	607:e98331f1d6b5	2565	/* Bit 13 : Set as input pin 13. */
vcoubard	607:e98331f1d6b5	2566	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	607:e98331f1d6b5	2567	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	607:e98331f1d6b5	2568	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2569	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2570	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2571
vcoubard	607:e98331f1d6b5	2572	/* Bit 12 : Set as input pin 12. */
vcoubard	607:e98331f1d6b5	2573	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	607:e98331f1d6b5	2574	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	607:e98331f1d6b5	2575	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2576	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2577	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2578
vcoubard	607:e98331f1d6b5	2579	/* Bit 11 : Set as input pin 11. */
vcoubard	607:e98331f1d6b5	2580	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	607:e98331f1d6b5	2581	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	607:e98331f1d6b5	2582	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2583	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2584	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2585
vcoubard	607:e98331f1d6b5	2586	/* Bit 10 : Set as input pin 10. */
vcoubard	607:e98331f1d6b5	2587	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	607:e98331f1d6b5	2588	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	607:e98331f1d6b5	2589	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2590	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2591	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2592
vcoubard	607:e98331f1d6b5	2593	/* Bit 9 : Set as input pin 9. */
vcoubard	607:e98331f1d6b5	2594	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	607:e98331f1d6b5	2595	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	607:e98331f1d6b5	2596	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2597	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2598	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2599
vcoubard	607:e98331f1d6b5	2600	/* Bit 8 : Set as input pin 8. */
vcoubard	607:e98331f1d6b5	2601	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	607:e98331f1d6b5	2602	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	607:e98331f1d6b5	2603	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2604	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2605	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2606
vcoubard	607:e98331f1d6b5	2607	/* Bit 7 : Set as input pin 7. */
vcoubard	607:e98331f1d6b5	2608	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	607:e98331f1d6b5	2609	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	607:e98331f1d6b5	2610	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2611	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2612	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2613
vcoubard	607:e98331f1d6b5	2614	/* Bit 6 : Set as input pin 6. */
vcoubard	607:e98331f1d6b5	2615	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	607:e98331f1d6b5	2616	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	607:e98331f1d6b5	2617	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2618	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2619	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2620
vcoubard	607:e98331f1d6b5	2621	/* Bit 5 : Set as input pin 5. */
vcoubard	607:e98331f1d6b5	2622	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	607:e98331f1d6b5	2623	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	607:e98331f1d6b5	2624	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2625	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2626	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2627
vcoubard	607:e98331f1d6b5	2628	/* Bit 4 : Set as input pin 4. */
vcoubard	607:e98331f1d6b5	2629	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	607:e98331f1d6b5	2630	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	607:e98331f1d6b5	2631	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2632	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2633	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2634
vcoubard	607:e98331f1d6b5	2635	/* Bit 3 : Set as input pin 3. */
vcoubard	607:e98331f1d6b5	2636	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	607:e98331f1d6b5	2637	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	607:e98331f1d6b5	2638	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2639	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2640	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2641
vcoubard	607:e98331f1d6b5	2642	/* Bit 2 : Set as input pin 2. */
vcoubard	607:e98331f1d6b5	2643	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	607:e98331f1d6b5	2644	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	607:e98331f1d6b5	2645	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2646	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2647	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2648
vcoubard	607:e98331f1d6b5	2649	/* Bit 1 : Set as input pin 1. */
vcoubard	607:e98331f1d6b5	2650	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	607:e98331f1d6b5	2651	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	607:e98331f1d6b5	2652	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2653	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2654	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2655
vcoubard	607:e98331f1d6b5	2656	/* Bit 0 : Set as input pin 0. */
vcoubard	607:e98331f1d6b5	2657	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	607:e98331f1d6b5	2658	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	607:e98331f1d6b5	2659	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	607:e98331f1d6b5	2660	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	607:e98331f1d6b5	2661	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
vcoubard	607:e98331f1d6b5	2662
vcoubard	607:e98331f1d6b5	2663	/* Register: GPIO_PIN_CNF */
vcoubard	607:e98331f1d6b5	2664	/* Description: Configuration of GPIO pins. */
vcoubard	607:e98331f1d6b5	2665
vcoubard	607:e98331f1d6b5	2666	/* Bits 17..16 : Pin sensing mechanism. */
vcoubard	607:e98331f1d6b5	2667	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
vcoubard	607:e98331f1d6b5	2668	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
vcoubard	607:e98331f1d6b5	2669	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	2670	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
vcoubard	607:e98331f1d6b5	2671	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
vcoubard	607:e98331f1d6b5	2672
vcoubard	607:e98331f1d6b5	2673	/* Bits 10..8 : Drive configuration. */
vcoubard	607:e98331f1d6b5	2674	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
vcoubard	607:e98331f1d6b5	2675	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
vcoubard	607:e98331f1d6b5	2676	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
vcoubard	607:e98331f1d6b5	2677	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
vcoubard	607:e98331f1d6b5	2678	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
vcoubard	607:e98331f1d6b5	2679	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
vcoubard	607:e98331f1d6b5	2680	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
vcoubard	607:e98331f1d6b5	2681	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
vcoubard	607:e98331f1d6b5	2682	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
vcoubard	607:e98331f1d6b5	2683	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
vcoubard	607:e98331f1d6b5	2684
vcoubard	607:e98331f1d6b5	2685	/* Bits 3..2 : Pull-up or -down configuration. */
vcoubard	607:e98331f1d6b5	2686	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
vcoubard	607:e98331f1d6b5	2687	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
vcoubard	607:e98331f1d6b5	2688	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
vcoubard	607:e98331f1d6b5	2689	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
vcoubard	607:e98331f1d6b5	2690	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
vcoubard	607:e98331f1d6b5	2691
vcoubard	607:e98331f1d6b5	2692	/* Bit 1 : Connect or disconnect input path. */
vcoubard	607:e98331f1d6b5	2693	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
vcoubard	607:e98331f1d6b5	2694	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
vcoubard	607:e98331f1d6b5	2695	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
vcoubard	607:e98331f1d6b5	2696	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
vcoubard	607:e98331f1d6b5	2697
vcoubard	607:e98331f1d6b5	2698	/* Bit 0 : Pin direction. */
vcoubard	607:e98331f1d6b5	2699	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
vcoubard	607:e98331f1d6b5	2700	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
vcoubard	607:e98331f1d6b5	2701	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
vcoubard	607:e98331f1d6b5	2702	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
vcoubard	607:e98331f1d6b5	2703
vcoubard	607:e98331f1d6b5	2704
vcoubard	607:e98331f1d6b5	2705	/* Peripheral: GPIOTE */
vcoubard	607:e98331f1d6b5	2706	/* Description: GPIO tasks and events. */
vcoubard	607:e98331f1d6b5	2707
vcoubard	607:e98331f1d6b5	2708	/* Register: GPIOTE_INTENSET */
vcoubard	607:e98331f1d6b5	2709	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	2710
vcoubard	607:e98331f1d6b5	2711	/* Bit 31 : Enable interrupt on PORT event. */
vcoubard	607:e98331f1d6b5	2712	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
vcoubard	607:e98331f1d6b5	2713	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
vcoubard	607:e98331f1d6b5	2714	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2715	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2716	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2717
vcoubard	607:e98331f1d6b5	2718	/* Bit 3 : Enable interrupt on IN[3] event. */
vcoubard	607:e98331f1d6b5	2719	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
vcoubard	607:e98331f1d6b5	2720	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
vcoubard	607:e98331f1d6b5	2721	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2722	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2723	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2724
vcoubard	607:e98331f1d6b5	2725	/* Bit 2 : Enable interrupt on IN[2] event. */
vcoubard	607:e98331f1d6b5	2726	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
vcoubard	607:e98331f1d6b5	2727	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
vcoubard	607:e98331f1d6b5	2728	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2729	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2730	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2731
vcoubard	607:e98331f1d6b5	2732	/* Bit 1 : Enable interrupt on IN[1] event. */
vcoubard	607:e98331f1d6b5	2733	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
vcoubard	607:e98331f1d6b5	2734	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
vcoubard	607:e98331f1d6b5	2735	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2736	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2737	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2738
vcoubard	607:e98331f1d6b5	2739	/* Bit 0 : Enable interrupt on IN[0] event. */
vcoubard	607:e98331f1d6b5	2740	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
vcoubard	607:e98331f1d6b5	2741	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
vcoubard	607:e98331f1d6b5	2742	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2743	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2744	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2745
vcoubard	607:e98331f1d6b5	2746	/* Register: GPIOTE_INTENCLR */
vcoubard	607:e98331f1d6b5	2747	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	2748
vcoubard	607:e98331f1d6b5	2749	/* Bit 31 : Disable interrupt on PORT event. */
vcoubard	607:e98331f1d6b5	2750	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
vcoubard	607:e98331f1d6b5	2751	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
vcoubard	607:e98331f1d6b5	2752	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2753	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2754	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2755
vcoubard	607:e98331f1d6b5	2756	/* Bit 3 : Disable interrupt on IN[3] event. */
vcoubard	607:e98331f1d6b5	2757	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
vcoubard	607:e98331f1d6b5	2758	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
vcoubard	607:e98331f1d6b5	2759	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2760	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2761	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2762
vcoubard	607:e98331f1d6b5	2763	/* Bit 2 : Disable interrupt on IN[2] event. */
vcoubard	607:e98331f1d6b5	2764	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
vcoubard	607:e98331f1d6b5	2765	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
vcoubard	607:e98331f1d6b5	2766	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2767	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2768	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2769
vcoubard	607:e98331f1d6b5	2770	/* Bit 1 : Disable interrupt on IN[1] event. */
vcoubard	607:e98331f1d6b5	2771	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
vcoubard	607:e98331f1d6b5	2772	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
vcoubard	607:e98331f1d6b5	2773	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2774	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2775	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2776
vcoubard	607:e98331f1d6b5	2777	/* Bit 0 : Disable interrupt on IN[0] event. */
vcoubard	607:e98331f1d6b5	2778	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
vcoubard	607:e98331f1d6b5	2779	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
vcoubard	607:e98331f1d6b5	2780	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2781	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2782	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2783
vcoubard	607:e98331f1d6b5	2784	/* Register: GPIOTE_CONFIG */
vcoubard	607:e98331f1d6b5	2785	/* Description: Channel configuration registers. */
vcoubard	607:e98331f1d6b5	2786
vcoubard	607:e98331f1d6b5	2787	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
vcoubard	607:e98331f1d6b5	2788	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
vcoubard	607:e98331f1d6b5	2789	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
vcoubard	607:e98331f1d6b5	2790	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
vcoubard	607:e98331f1d6b5	2791	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
vcoubard	607:e98331f1d6b5	2792
vcoubard	607:e98331f1d6b5	2793	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
vcoubard	607:e98331f1d6b5	2794	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
vcoubard	607:e98331f1d6b5	2795	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
vcoubard	607:e98331f1d6b5	2796	#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /!< No task or event. /
vcoubard	607:e98331f1d6b5	2797	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
vcoubard	607:e98331f1d6b5	2798	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
vcoubard	607:e98331f1d6b5	2799	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
vcoubard	607:e98331f1d6b5	2800
vcoubard	607:e98331f1d6b5	2801	/* Bits 12..8 : Pin select. */
vcoubard	607:e98331f1d6b5	2802	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
vcoubard	607:e98331f1d6b5	2803	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	607:e98331f1d6b5	2804
vcoubard	607:e98331f1d6b5	2805	/* Bits 1..0 : Mode */
vcoubard	607:e98331f1d6b5	2806	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	607:e98331f1d6b5	2807	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	607:e98331f1d6b5	2808	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	2809	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
vcoubard	607:e98331f1d6b5	2810	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
vcoubard	607:e98331f1d6b5	2811
vcoubard	607:e98331f1d6b5	2812	/* Register: GPIOTE_POWER */
vcoubard	607:e98331f1d6b5	2813	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	2814
vcoubard	607:e98331f1d6b5	2815	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	2816	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	2817	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	2818	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	2819	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	2820
vcoubard	607:e98331f1d6b5	2821
vcoubard	607:e98331f1d6b5	2822	/* Peripheral: LPCOMP */
vcoubard	607:e98331f1d6b5	2823	/* Description: Low power comparator. */
vcoubard	607:e98331f1d6b5	2824
vcoubard	607:e98331f1d6b5	2825	/* Register: LPCOMP_SHORTS */
vcoubard	607:e98331f1d6b5	2826	/* Description: Shortcuts for the LPCOMP. */
vcoubard	607:e98331f1d6b5	2827
vcoubard	607:e98331f1d6b5	2828	/* Bit 4 : Shortcut between CROSS event and STOP task. */
vcoubard	607:e98331f1d6b5	2829	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
vcoubard	607:e98331f1d6b5	2830	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
vcoubard	607:e98331f1d6b5	2831	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	2832	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	2833
vcoubard	607:e98331f1d6b5	2834	/* Bit 3 : Shortcut between UP event and STOP task. */
vcoubard	607:e98331f1d6b5	2835	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
vcoubard	607:e98331f1d6b5	2836	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
vcoubard	607:e98331f1d6b5	2837	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	2838	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	2839
vcoubard	607:e98331f1d6b5	2840	/* Bit 2 : Shortcut between DOWN event and STOP task. */
vcoubard	607:e98331f1d6b5	2841	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
vcoubard	607:e98331f1d6b5	2842	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
vcoubard	607:e98331f1d6b5	2843	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	2844	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	2845
vcoubard	607:e98331f1d6b5	2846	/* Bit 1 : Shortcut between RADY event and STOP task. */
vcoubard	607:e98331f1d6b5	2847	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
vcoubard	607:e98331f1d6b5	2848	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
vcoubard	607:e98331f1d6b5	2849	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	2850	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	2851
vcoubard	607:e98331f1d6b5	2852	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
vcoubard	607:e98331f1d6b5	2853	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
vcoubard	607:e98331f1d6b5	2854	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
vcoubard	607:e98331f1d6b5	2855	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	2856	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	2857
vcoubard	607:e98331f1d6b5	2858	/* Register: LPCOMP_INTENSET */
vcoubard	607:e98331f1d6b5	2859	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	2860
vcoubard	607:e98331f1d6b5	2861	/* Bit 3 : Enable interrupt on CROSS event. */
vcoubard	607:e98331f1d6b5	2862	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
vcoubard	607:e98331f1d6b5	2863	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
vcoubard	607:e98331f1d6b5	2864	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2865	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2866	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2867
vcoubard	607:e98331f1d6b5	2868	/* Bit 2 : Enable interrupt on UP event. */
vcoubard	607:e98331f1d6b5	2869	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
vcoubard	607:e98331f1d6b5	2870	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
vcoubard	607:e98331f1d6b5	2871	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2872	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2873	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2874
vcoubard	607:e98331f1d6b5	2875	/* Bit 1 : Enable interrupt on DOWN event. */
vcoubard	607:e98331f1d6b5	2876	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
vcoubard	607:e98331f1d6b5	2877	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
vcoubard	607:e98331f1d6b5	2878	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2879	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2880	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2881
vcoubard	607:e98331f1d6b5	2882	/* Bit 0 : Enable interrupt on READY event. */
vcoubard	607:e98331f1d6b5	2883	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	607:e98331f1d6b5	2884	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	607:e98331f1d6b5	2885	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2886	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2887	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	2888
vcoubard	607:e98331f1d6b5	2889	/* Register: LPCOMP_INTENCLR */
vcoubard	607:e98331f1d6b5	2890	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	2891
vcoubard	607:e98331f1d6b5	2892	/* Bit 3 : Disable interrupt on CROSS event. */
vcoubard	607:e98331f1d6b5	2893	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
vcoubard	607:e98331f1d6b5	2894	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
vcoubard	607:e98331f1d6b5	2895	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2896	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2897	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2898
vcoubard	607:e98331f1d6b5	2899	/* Bit 2 : Disable interrupt on UP event. */
vcoubard	607:e98331f1d6b5	2900	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
vcoubard	607:e98331f1d6b5	2901	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
vcoubard	607:e98331f1d6b5	2902	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2903	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2904	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2905
vcoubard	607:e98331f1d6b5	2906	/* Bit 1 : Disable interrupt on DOWN event. */
vcoubard	607:e98331f1d6b5	2907	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
vcoubard	607:e98331f1d6b5	2908	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
vcoubard	607:e98331f1d6b5	2909	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2910	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2911	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2912
vcoubard	607:e98331f1d6b5	2913	/* Bit 0 : Disable interrupt on READY event. */
vcoubard	607:e98331f1d6b5	2914	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	607:e98331f1d6b5	2915	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	607:e98331f1d6b5	2916	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	2917	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	2918	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	2919
vcoubard	607:e98331f1d6b5	2920	/* Register: LPCOMP_RESULT */
vcoubard	607:e98331f1d6b5	2921	/* Description: Result of last compare. */
vcoubard	607:e98331f1d6b5	2922
vcoubard	607:e98331f1d6b5	2923	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
vcoubard	607:e98331f1d6b5	2924	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
vcoubard	607:e98331f1d6b5	2925	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
vcoubard	607:e98331f1d6b5	2926	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
vcoubard	607:e98331f1d6b5	2927	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
vcoubard	607:e98331f1d6b5	2928
vcoubard	607:e98331f1d6b5	2929	/* Register: LPCOMP_ENABLE */
vcoubard	607:e98331f1d6b5	2930	/* Description: Enable the LPCOMP. */
vcoubard	607:e98331f1d6b5	2931
vcoubard	607:e98331f1d6b5	2932	/* Bits 1..0 : Enable or disable LPCOMP. */
vcoubard	607:e98331f1d6b5	2933	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	2934	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	2935	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
vcoubard	607:e98331f1d6b5	2936	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
vcoubard	607:e98331f1d6b5	2937
vcoubard	607:e98331f1d6b5	2938	/* Register: LPCOMP_PSEL */
vcoubard	607:e98331f1d6b5	2939	/* Description: Input pin select. */
vcoubard	607:e98331f1d6b5	2940
vcoubard	607:e98331f1d6b5	2941	/* Bits 2..0 : Analog input pin select. */
vcoubard	607:e98331f1d6b5	2942	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
vcoubard	607:e98331f1d6b5	2943	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	607:e98331f1d6b5	2944	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
vcoubard	607:e98331f1d6b5	2945	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
vcoubard	607:e98331f1d6b5	2946	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
vcoubard	607:e98331f1d6b5	2947	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
vcoubard	607:e98331f1d6b5	2948	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
vcoubard	607:e98331f1d6b5	2949	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
vcoubard	607:e98331f1d6b5	2950	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
vcoubard	607:e98331f1d6b5	2951	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
vcoubard	607:e98331f1d6b5	2952
vcoubard	607:e98331f1d6b5	2953	/* Register: LPCOMP_REFSEL */
vcoubard	607:e98331f1d6b5	2954	/* Description: Reference select. */
vcoubard	607:e98331f1d6b5	2955
vcoubard	607:e98331f1d6b5	2956	/* Bits 2..0 : Reference select. */
vcoubard	607:e98331f1d6b5	2957	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
vcoubard	607:e98331f1d6b5	2958	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
vcoubard	607:e98331f1d6b5	2959	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
vcoubard	607:e98331f1d6b5	2960	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
vcoubard	607:e98331f1d6b5	2961	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
vcoubard	607:e98331f1d6b5	2962	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
vcoubard	607:e98331f1d6b5	2963	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
vcoubard	607:e98331f1d6b5	2964	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
vcoubard	607:e98331f1d6b5	2965	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
vcoubard	607:e98331f1d6b5	2966	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
vcoubard	607:e98331f1d6b5	2967
vcoubard	607:e98331f1d6b5	2968	/* Register: LPCOMP_EXTREFSEL */
vcoubard	607:e98331f1d6b5	2969	/* Description: External reference select. */
vcoubard	607:e98331f1d6b5	2970
vcoubard	607:e98331f1d6b5	2971	/* Bit 0 : External analog reference pin selection. */
vcoubard	607:e98331f1d6b5	2972	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
vcoubard	607:e98331f1d6b5	2973	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
vcoubard	607:e98331f1d6b5	2974	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
vcoubard	607:e98331f1d6b5	2975	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
vcoubard	607:e98331f1d6b5	2976
vcoubard	607:e98331f1d6b5	2977	/* Register: LPCOMP_ANADETECT */
vcoubard	607:e98331f1d6b5	2978	/* Description: Analog detect configuration. */
vcoubard	607:e98331f1d6b5	2979
vcoubard	607:e98331f1d6b5	2980	/* Bits 1..0 : Analog detect configuration. */
vcoubard	607:e98331f1d6b5	2981	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
vcoubard	607:e98331f1d6b5	2982	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
vcoubard	607:e98331f1d6b5	2983	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
vcoubard	607:e98331f1d6b5	2984	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
vcoubard	607:e98331f1d6b5	2985	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
vcoubard	607:e98331f1d6b5	2986
vcoubard	607:e98331f1d6b5	2987	/* Register: LPCOMP_POWER */
vcoubard	607:e98331f1d6b5	2988	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	2989
vcoubard	607:e98331f1d6b5	2990	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	2991	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	2992	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	2993	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	2994	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	2995
vcoubard	607:e98331f1d6b5	2996
vcoubard	607:e98331f1d6b5	2997	/* Peripheral: MPU */
vcoubard	607:e98331f1d6b5	2998	/* Description: Memory Protection Unit. */
vcoubard	607:e98331f1d6b5	2999
vcoubard	607:e98331f1d6b5	3000	/* Register: MPU_PERR0 */
vcoubard	607:e98331f1d6b5	3001	/* Description: Configuration of peripherals in mpu regions. */
vcoubard	607:e98331f1d6b5	3002
vcoubard	607:e98331f1d6b5	3003	/* Bit 31 : PPI region configuration. */
vcoubard	607:e98331f1d6b5	3004	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
vcoubard	607:e98331f1d6b5	3005	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
vcoubard	607:e98331f1d6b5	3006	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3007	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3008
vcoubard	607:e98331f1d6b5	3009	/* Bit 30 : NVMC region configuration. */
vcoubard	607:e98331f1d6b5	3010	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
vcoubard	607:e98331f1d6b5	3011	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
vcoubard	607:e98331f1d6b5	3012	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3013	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3014
vcoubard	607:e98331f1d6b5	3015	/* Bit 19 : LPCOMP region configuration. */
vcoubard	607:e98331f1d6b5	3016	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
vcoubard	607:e98331f1d6b5	3017	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
vcoubard	607:e98331f1d6b5	3018	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3019	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3020
vcoubard	607:e98331f1d6b5	3021	/* Bit 18 : QDEC region configuration. */
vcoubard	607:e98331f1d6b5	3022	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
vcoubard	607:e98331f1d6b5	3023	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
vcoubard	607:e98331f1d6b5	3024	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3025	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3026
vcoubard	607:e98331f1d6b5	3027	/* Bit 17 : RTC1 region configuration. */
vcoubard	607:e98331f1d6b5	3028	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
vcoubard	607:e98331f1d6b5	3029	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
vcoubard	607:e98331f1d6b5	3030	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3031	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3032
vcoubard	607:e98331f1d6b5	3033	/* Bit 16 : WDT region configuration. */
vcoubard	607:e98331f1d6b5	3034	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
vcoubard	607:e98331f1d6b5	3035	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
vcoubard	607:e98331f1d6b5	3036	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3037	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3038
vcoubard	607:e98331f1d6b5	3039	/* Bit 15 : CCM and AAR region configuration. */
vcoubard	607:e98331f1d6b5	3040	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
vcoubard	607:e98331f1d6b5	3041	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
vcoubard	607:e98331f1d6b5	3042	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3043	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3044
vcoubard	607:e98331f1d6b5	3045	/* Bit 14 : ECB region configuration. */
vcoubard	607:e98331f1d6b5	3046	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
vcoubard	607:e98331f1d6b5	3047	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
vcoubard	607:e98331f1d6b5	3048	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3049	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3050
vcoubard	607:e98331f1d6b5	3051	/* Bit 13 : RNG region configuration. */
vcoubard	607:e98331f1d6b5	3052	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
vcoubard	607:e98331f1d6b5	3053	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
vcoubard	607:e98331f1d6b5	3054	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3055	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3056
vcoubard	607:e98331f1d6b5	3057	/* Bit 12 : TEMP region configuration. */
vcoubard	607:e98331f1d6b5	3058	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
vcoubard	607:e98331f1d6b5	3059	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
vcoubard	607:e98331f1d6b5	3060	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3061	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3062
vcoubard	607:e98331f1d6b5	3063	/* Bit 11 : RTC0 region configuration. */
vcoubard	607:e98331f1d6b5	3064	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
vcoubard	607:e98331f1d6b5	3065	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
vcoubard	607:e98331f1d6b5	3066	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3067	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3068
vcoubard	607:e98331f1d6b5	3069	/* Bit 10 : TIMER2 region configuration. */
vcoubard	607:e98331f1d6b5	3070	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
vcoubard	607:e98331f1d6b5	3071	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
vcoubard	607:e98331f1d6b5	3072	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3073	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3074
vcoubard	607:e98331f1d6b5	3075	/* Bit 9 : TIMER1 region configuration. */
vcoubard	607:e98331f1d6b5	3076	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
vcoubard	607:e98331f1d6b5	3077	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
vcoubard	607:e98331f1d6b5	3078	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3079	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3080
vcoubard	607:e98331f1d6b5	3081	/* Bit 8 : TIMER0 region configuration. */
vcoubard	607:e98331f1d6b5	3082	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
vcoubard	607:e98331f1d6b5	3083	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
vcoubard	607:e98331f1d6b5	3084	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3085	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3086
vcoubard	607:e98331f1d6b5	3087	/* Bit 7 : ADC region configuration. */
vcoubard	607:e98331f1d6b5	3088	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
vcoubard	607:e98331f1d6b5	3089	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
vcoubard	607:e98331f1d6b5	3090	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3091	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3092
vcoubard	607:e98331f1d6b5	3093	/* Bit 6 : GPIOTE region configuration. */
vcoubard	607:e98331f1d6b5	3094	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
vcoubard	607:e98331f1d6b5	3095	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
vcoubard	607:e98331f1d6b5	3096	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3097	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3098
vcoubard	607:e98331f1d6b5	3099	/* Bit 4 : SPI1 and TWI1 region configuration. */
vcoubard	607:e98331f1d6b5	3100	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
vcoubard	607:e98331f1d6b5	3101	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
vcoubard	607:e98331f1d6b5	3102	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3103	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3104
vcoubard	607:e98331f1d6b5	3105	/* Bit 3 : SPI0 and TWI0 region configuration. */
vcoubard	607:e98331f1d6b5	3106	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
vcoubard	607:e98331f1d6b5	3107	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
vcoubard	607:e98331f1d6b5	3108	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3109	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3110
vcoubard	607:e98331f1d6b5	3111	/* Bit 2 : UART0 region configuration. */
vcoubard	607:e98331f1d6b5	3112	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
vcoubard	607:e98331f1d6b5	3113	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
vcoubard	607:e98331f1d6b5	3114	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3115	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3116
vcoubard	607:e98331f1d6b5	3117	/* Bit 1 : RADIO region configuration. */
vcoubard	607:e98331f1d6b5	3118	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
vcoubard	607:e98331f1d6b5	3119	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
vcoubard	607:e98331f1d6b5	3120	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3121	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3122
vcoubard	607:e98331f1d6b5	3123	/* Bit 0 : POWER_CLOCK region configuration. */
vcoubard	607:e98331f1d6b5	3124	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
vcoubard	607:e98331f1d6b5	3125	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
vcoubard	607:e98331f1d6b5	3126	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	607:e98331f1d6b5	3127	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	607:e98331f1d6b5	3128
vcoubard	607:e98331f1d6b5	3129	/* Register: MPU_PROTENSET0 */
vcoubard	607:e98331f1d6b5	3130	/* Description: Erase and write protection bit enable set register. */
vcoubard	607:e98331f1d6b5	3131
vcoubard	607:e98331f1d6b5	3132	/* Bit 31 : Protection enable for region 31. */
vcoubard	607:e98331f1d6b5	3133	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
vcoubard	607:e98331f1d6b5	3134	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
vcoubard	607:e98331f1d6b5	3135	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3136	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3137	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3138
vcoubard	607:e98331f1d6b5	3139	/* Bit 30 : Protection enable for region 30. */
vcoubard	607:e98331f1d6b5	3140	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
vcoubard	607:e98331f1d6b5	3141	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
vcoubard	607:e98331f1d6b5	3142	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3143	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3144	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3145
vcoubard	607:e98331f1d6b5	3146	/* Bit 29 : Protection enable for region 29. */
vcoubard	607:e98331f1d6b5	3147	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
vcoubard	607:e98331f1d6b5	3148	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
vcoubard	607:e98331f1d6b5	3149	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3150	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3151	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3152
vcoubard	607:e98331f1d6b5	3153	/* Bit 28 : Protection enable for region 28. */
vcoubard	607:e98331f1d6b5	3154	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
vcoubard	607:e98331f1d6b5	3155	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
vcoubard	607:e98331f1d6b5	3156	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3157	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3158	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3159
vcoubard	607:e98331f1d6b5	3160	/* Bit 27 : Protection enable for region 27. */
vcoubard	607:e98331f1d6b5	3161	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
vcoubard	607:e98331f1d6b5	3162	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
vcoubard	607:e98331f1d6b5	3163	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3164	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3165	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3166
vcoubard	607:e98331f1d6b5	3167	/* Bit 26 : Protection enable for region 26. */
vcoubard	607:e98331f1d6b5	3168	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
vcoubard	607:e98331f1d6b5	3169	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
vcoubard	607:e98331f1d6b5	3170	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3171	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3172	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3173
vcoubard	607:e98331f1d6b5	3174	/* Bit 25 : Protection enable for region 25. */
vcoubard	607:e98331f1d6b5	3175	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
vcoubard	607:e98331f1d6b5	3176	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
vcoubard	607:e98331f1d6b5	3177	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3178	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3179	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3180
vcoubard	607:e98331f1d6b5	3181	/* Bit 24 : Protection enable for region 24. */
vcoubard	607:e98331f1d6b5	3182	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
vcoubard	607:e98331f1d6b5	3183	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
vcoubard	607:e98331f1d6b5	3184	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3185	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3186	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3187
vcoubard	607:e98331f1d6b5	3188	/* Bit 23 : Protection enable for region 23. */
vcoubard	607:e98331f1d6b5	3189	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
vcoubard	607:e98331f1d6b5	3190	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
vcoubard	607:e98331f1d6b5	3191	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3192	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3193	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3194
vcoubard	607:e98331f1d6b5	3195	/* Bit 22 : Protection enable for region 22. */
vcoubard	607:e98331f1d6b5	3196	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
vcoubard	607:e98331f1d6b5	3197	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
vcoubard	607:e98331f1d6b5	3198	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3199	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3200	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3201
vcoubard	607:e98331f1d6b5	3202	/* Bit 21 : Protection enable for region 21. */
vcoubard	607:e98331f1d6b5	3203	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
vcoubard	607:e98331f1d6b5	3204	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
vcoubard	607:e98331f1d6b5	3205	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3206	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3207	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3208
vcoubard	607:e98331f1d6b5	3209	/* Bit 20 : Protection enable for region 20. */
vcoubard	607:e98331f1d6b5	3210	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
vcoubard	607:e98331f1d6b5	3211	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
vcoubard	607:e98331f1d6b5	3212	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3213	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3214	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3215
vcoubard	607:e98331f1d6b5	3216	/* Bit 19 : Protection enable for region 19. */
vcoubard	607:e98331f1d6b5	3217	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
vcoubard	607:e98331f1d6b5	3218	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
vcoubard	607:e98331f1d6b5	3219	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3220	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3221	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3222
vcoubard	607:e98331f1d6b5	3223	/* Bit 18 : Protection enable for region 18. */
vcoubard	607:e98331f1d6b5	3224	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
vcoubard	607:e98331f1d6b5	3225	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
vcoubard	607:e98331f1d6b5	3226	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3227	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3228	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3229
vcoubard	607:e98331f1d6b5	3230	/* Bit 17 : Protection enable for region 17. */
vcoubard	607:e98331f1d6b5	3231	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
vcoubard	607:e98331f1d6b5	3232	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
vcoubard	607:e98331f1d6b5	3233	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3234	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3235	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3236
vcoubard	607:e98331f1d6b5	3237	/* Bit 16 : Protection enable for region 16. */
vcoubard	607:e98331f1d6b5	3238	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
vcoubard	607:e98331f1d6b5	3239	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
vcoubard	607:e98331f1d6b5	3240	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3241	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3242	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3243
vcoubard	607:e98331f1d6b5	3244	/* Bit 15 : Protection enable for region 15. */
vcoubard	607:e98331f1d6b5	3245	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
vcoubard	607:e98331f1d6b5	3246	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
vcoubard	607:e98331f1d6b5	3247	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3248	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3249	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3250
vcoubard	607:e98331f1d6b5	3251	/* Bit 14 : Protection enable for region 14. */
vcoubard	607:e98331f1d6b5	3252	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
vcoubard	607:e98331f1d6b5	3253	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
vcoubard	607:e98331f1d6b5	3254	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3255	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3256	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3257
vcoubard	607:e98331f1d6b5	3258	/* Bit 13 : Protection enable for region 13. */
vcoubard	607:e98331f1d6b5	3259	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
vcoubard	607:e98331f1d6b5	3260	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
vcoubard	607:e98331f1d6b5	3261	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3262	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3263	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3264
vcoubard	607:e98331f1d6b5	3265	/* Bit 12 : Protection enable for region 12. */
vcoubard	607:e98331f1d6b5	3266	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
vcoubard	607:e98331f1d6b5	3267	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
vcoubard	607:e98331f1d6b5	3268	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3269	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3270	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3271
vcoubard	607:e98331f1d6b5	3272	/* Bit 11 : Protection enable for region 11. */
vcoubard	607:e98331f1d6b5	3273	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
vcoubard	607:e98331f1d6b5	3274	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
vcoubard	607:e98331f1d6b5	3275	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3276	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3277	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3278
vcoubard	607:e98331f1d6b5	3279	/* Bit 10 : Protection enable for region 10. */
vcoubard	607:e98331f1d6b5	3280	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
vcoubard	607:e98331f1d6b5	3281	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
vcoubard	607:e98331f1d6b5	3282	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3283	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3284	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3285
vcoubard	607:e98331f1d6b5	3286	/* Bit 9 : Protection enable for region 9. */
vcoubard	607:e98331f1d6b5	3287	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
vcoubard	607:e98331f1d6b5	3288	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
vcoubard	607:e98331f1d6b5	3289	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3290	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3291	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3292
vcoubard	607:e98331f1d6b5	3293	/* Bit 8 : Protection enable for region 8. */
vcoubard	607:e98331f1d6b5	3294	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
vcoubard	607:e98331f1d6b5	3295	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
vcoubard	607:e98331f1d6b5	3296	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3297	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3298	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3299
vcoubard	607:e98331f1d6b5	3300	/* Bit 7 : Protection enable for region 7. */
vcoubard	607:e98331f1d6b5	3301	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
vcoubard	607:e98331f1d6b5	3302	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
vcoubard	607:e98331f1d6b5	3303	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3304	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3305	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3306
vcoubard	607:e98331f1d6b5	3307	/* Bit 6 : Protection enable for region 6. */
vcoubard	607:e98331f1d6b5	3308	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
vcoubard	607:e98331f1d6b5	3309	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
vcoubard	607:e98331f1d6b5	3310	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3311	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3312	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3313
vcoubard	607:e98331f1d6b5	3314	/* Bit 5 : Protection enable for region 5. */
vcoubard	607:e98331f1d6b5	3315	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
vcoubard	607:e98331f1d6b5	3316	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
vcoubard	607:e98331f1d6b5	3317	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3318	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3319	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3320
vcoubard	607:e98331f1d6b5	3321	/* Bit 4 : Protection enable for region 4. */
vcoubard	607:e98331f1d6b5	3322	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
vcoubard	607:e98331f1d6b5	3323	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
vcoubard	607:e98331f1d6b5	3324	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3325	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3326	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3327
vcoubard	607:e98331f1d6b5	3328	/* Bit 3 : Protection enable for region 3. */
vcoubard	607:e98331f1d6b5	3329	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
vcoubard	607:e98331f1d6b5	3330	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
vcoubard	607:e98331f1d6b5	3331	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3332	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3333	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3334
vcoubard	607:e98331f1d6b5	3335	/* Bit 2 : Protection enable for region 2. */
vcoubard	607:e98331f1d6b5	3336	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
vcoubard	607:e98331f1d6b5	3337	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
vcoubard	607:e98331f1d6b5	3338	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3339	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3340	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3341
vcoubard	607:e98331f1d6b5	3342	/* Bit 1 : Protection enable for region 1. */
vcoubard	607:e98331f1d6b5	3343	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
vcoubard	607:e98331f1d6b5	3344	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
vcoubard	607:e98331f1d6b5	3345	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3346	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3347	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3348
vcoubard	607:e98331f1d6b5	3349	/* Bit 0 : Protection enable for region 0. */
vcoubard	607:e98331f1d6b5	3350	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
vcoubard	607:e98331f1d6b5	3351	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
vcoubard	607:e98331f1d6b5	3352	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3353	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3354	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3355
vcoubard	607:e98331f1d6b5	3356	/* Register: MPU_PROTENSET1 */
vcoubard	607:e98331f1d6b5	3357	/* Description: Erase and write protection bit enable set register. */
vcoubard	607:e98331f1d6b5	3358
vcoubard	607:e98331f1d6b5	3359	/* Bit 31 : Protection enable for region 63. */
vcoubard	607:e98331f1d6b5	3360	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
vcoubard	607:e98331f1d6b5	3361	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
vcoubard	607:e98331f1d6b5	3362	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3363	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3364	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3365
vcoubard	607:e98331f1d6b5	3366	/* Bit 30 : Protection enable for region 62. */
vcoubard	607:e98331f1d6b5	3367	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
vcoubard	607:e98331f1d6b5	3368	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
vcoubard	607:e98331f1d6b5	3369	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3370	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3371	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3372
vcoubard	607:e98331f1d6b5	3373	/* Bit 29 : Protection enable for region 61. */
vcoubard	607:e98331f1d6b5	3374	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
vcoubard	607:e98331f1d6b5	3375	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
vcoubard	607:e98331f1d6b5	3376	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3377	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3378	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3379
vcoubard	607:e98331f1d6b5	3380	/* Bit 28 : Protection enable for region 60. */
vcoubard	607:e98331f1d6b5	3381	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
vcoubard	607:e98331f1d6b5	3382	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
vcoubard	607:e98331f1d6b5	3383	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3384	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3385	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3386
vcoubard	607:e98331f1d6b5	3387	/* Bit 27 : Protection enable for region 59. */
vcoubard	607:e98331f1d6b5	3388	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
vcoubard	607:e98331f1d6b5	3389	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
vcoubard	607:e98331f1d6b5	3390	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3391	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3392	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3393
vcoubard	607:e98331f1d6b5	3394	/* Bit 26 : Protection enable for region 58. */
vcoubard	607:e98331f1d6b5	3395	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
vcoubard	607:e98331f1d6b5	3396	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
vcoubard	607:e98331f1d6b5	3397	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3398	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3399	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3400
vcoubard	607:e98331f1d6b5	3401	/* Bit 25 : Protection enable for region 57. */
vcoubard	607:e98331f1d6b5	3402	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
vcoubard	607:e98331f1d6b5	3403	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
vcoubard	607:e98331f1d6b5	3404	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3405	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3406	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3407
vcoubard	607:e98331f1d6b5	3408	/* Bit 24 : Protection enable for region 56. */
vcoubard	607:e98331f1d6b5	3409	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
vcoubard	607:e98331f1d6b5	3410	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
vcoubard	607:e98331f1d6b5	3411	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3412	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3413	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3414
vcoubard	607:e98331f1d6b5	3415	/* Bit 23 : Protection enable for region 55. */
vcoubard	607:e98331f1d6b5	3416	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
vcoubard	607:e98331f1d6b5	3417	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
vcoubard	607:e98331f1d6b5	3418	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3419	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3420	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3421
vcoubard	607:e98331f1d6b5	3422	/* Bit 22 : Protection enable for region 54. */
vcoubard	607:e98331f1d6b5	3423	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
vcoubard	607:e98331f1d6b5	3424	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
vcoubard	607:e98331f1d6b5	3425	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3426	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3427	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3428
vcoubard	607:e98331f1d6b5	3429	/* Bit 21 : Protection enable for region 53. */
vcoubard	607:e98331f1d6b5	3430	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
vcoubard	607:e98331f1d6b5	3431	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
vcoubard	607:e98331f1d6b5	3432	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3433	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3434	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3435
vcoubard	607:e98331f1d6b5	3436	/* Bit 20 : Protection enable for region 52. */
vcoubard	607:e98331f1d6b5	3437	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
vcoubard	607:e98331f1d6b5	3438	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
vcoubard	607:e98331f1d6b5	3439	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3440	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3441	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3442
vcoubard	607:e98331f1d6b5	3443	/* Bit 19 : Protection enable for region 51. */
vcoubard	607:e98331f1d6b5	3444	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
vcoubard	607:e98331f1d6b5	3445	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
vcoubard	607:e98331f1d6b5	3446	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3447	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3448	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3449
vcoubard	607:e98331f1d6b5	3450	/* Bit 18 : Protection enable for region 50. */
vcoubard	607:e98331f1d6b5	3451	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
vcoubard	607:e98331f1d6b5	3452	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
vcoubard	607:e98331f1d6b5	3453	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3454	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3455	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3456
vcoubard	607:e98331f1d6b5	3457	/* Bit 17 : Protection enable for region 49. */
vcoubard	607:e98331f1d6b5	3458	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
vcoubard	607:e98331f1d6b5	3459	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
vcoubard	607:e98331f1d6b5	3460	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3461	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3462	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3463
vcoubard	607:e98331f1d6b5	3464	/* Bit 16 : Protection enable for region 48. */
vcoubard	607:e98331f1d6b5	3465	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
vcoubard	607:e98331f1d6b5	3466	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
vcoubard	607:e98331f1d6b5	3467	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3468	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3469	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3470
vcoubard	607:e98331f1d6b5	3471	/* Bit 15 : Protection enable for region 47. */
vcoubard	607:e98331f1d6b5	3472	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
vcoubard	607:e98331f1d6b5	3473	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
vcoubard	607:e98331f1d6b5	3474	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3475	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3476	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3477
vcoubard	607:e98331f1d6b5	3478	/* Bit 14 : Protection enable for region 46. */
vcoubard	607:e98331f1d6b5	3479	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
vcoubard	607:e98331f1d6b5	3480	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
vcoubard	607:e98331f1d6b5	3481	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3482	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3483	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3484
vcoubard	607:e98331f1d6b5	3485	/* Bit 13 : Protection enable for region 45. */
vcoubard	607:e98331f1d6b5	3486	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
vcoubard	607:e98331f1d6b5	3487	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
vcoubard	607:e98331f1d6b5	3488	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3489	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3490	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3491
vcoubard	607:e98331f1d6b5	3492	/* Bit 12 : Protection enable for region 44. */
vcoubard	607:e98331f1d6b5	3493	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
vcoubard	607:e98331f1d6b5	3494	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
vcoubard	607:e98331f1d6b5	3495	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3496	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3497	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3498
vcoubard	607:e98331f1d6b5	3499	/* Bit 11 : Protection enable for region 43. */
vcoubard	607:e98331f1d6b5	3500	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
vcoubard	607:e98331f1d6b5	3501	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
vcoubard	607:e98331f1d6b5	3502	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3503	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3504	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3505
vcoubard	607:e98331f1d6b5	3506	/* Bit 10 : Protection enable for region 42. */
vcoubard	607:e98331f1d6b5	3507	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
vcoubard	607:e98331f1d6b5	3508	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
vcoubard	607:e98331f1d6b5	3509	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3510	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3511	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3512
vcoubard	607:e98331f1d6b5	3513	/* Bit 9 : Protection enable for region 41. */
vcoubard	607:e98331f1d6b5	3514	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
vcoubard	607:e98331f1d6b5	3515	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
vcoubard	607:e98331f1d6b5	3516	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3517	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3518	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3519
vcoubard	607:e98331f1d6b5	3520	/* Bit 8 : Protection enable for region 40. */
vcoubard	607:e98331f1d6b5	3521	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
vcoubard	607:e98331f1d6b5	3522	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
vcoubard	607:e98331f1d6b5	3523	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3524	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3525	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3526
vcoubard	607:e98331f1d6b5	3527	/* Bit 7 : Protection enable for region 39. */
vcoubard	607:e98331f1d6b5	3528	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
vcoubard	607:e98331f1d6b5	3529	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
vcoubard	607:e98331f1d6b5	3530	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3531	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3532	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3533
vcoubard	607:e98331f1d6b5	3534	/* Bit 6 : Protection enable for region 38. */
vcoubard	607:e98331f1d6b5	3535	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
vcoubard	607:e98331f1d6b5	3536	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
vcoubard	607:e98331f1d6b5	3537	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3538	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3539	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3540
vcoubard	607:e98331f1d6b5	3541	/* Bit 5 : Protection enable for region 37. */
vcoubard	607:e98331f1d6b5	3542	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
vcoubard	607:e98331f1d6b5	3543	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
vcoubard	607:e98331f1d6b5	3544	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3545	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3546	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3547
vcoubard	607:e98331f1d6b5	3548	/* Bit 4 : Protection enable for region 36. */
vcoubard	607:e98331f1d6b5	3549	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
vcoubard	607:e98331f1d6b5	3550	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
vcoubard	607:e98331f1d6b5	3551	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3552	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3553	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3554
vcoubard	607:e98331f1d6b5	3555	/* Bit 3 : Protection enable for region 35. */
vcoubard	607:e98331f1d6b5	3556	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
vcoubard	607:e98331f1d6b5	3557	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
vcoubard	607:e98331f1d6b5	3558	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3559	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3560	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3561
vcoubard	607:e98331f1d6b5	3562	/* Bit 2 : Protection enable for region 34. */
vcoubard	607:e98331f1d6b5	3563	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
vcoubard	607:e98331f1d6b5	3564	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
vcoubard	607:e98331f1d6b5	3565	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3566	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3567	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3568
vcoubard	607:e98331f1d6b5	3569	/* Bit 1 : Protection enable for region 33. */
vcoubard	607:e98331f1d6b5	3570	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
vcoubard	607:e98331f1d6b5	3571	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
vcoubard	607:e98331f1d6b5	3572	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3573	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3574	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3575
vcoubard	607:e98331f1d6b5	3576	/* Bit 0 : Protection enable for region 32. */
vcoubard	607:e98331f1d6b5	3577	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
vcoubard	607:e98331f1d6b5	3578	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
vcoubard	607:e98331f1d6b5	3579	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3580	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3581	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
vcoubard	607:e98331f1d6b5	3582
vcoubard	607:e98331f1d6b5	3583	/* Register: MPU_DISABLEINDEBUG */
vcoubard	607:e98331f1d6b5	3584	/* Description: Disable erase and write protection mechanism in debug mode. */
vcoubard	607:e98331f1d6b5	3585
vcoubard	607:e98331f1d6b5	3586	/* Bit 0 : Disable protection mechanism in debug mode. */
vcoubard	607:e98331f1d6b5	3587	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
vcoubard	607:e98331f1d6b5	3588	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
vcoubard	607:e98331f1d6b5	3589	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
vcoubard	607:e98331f1d6b5	3590	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
vcoubard	607:e98331f1d6b5	3591
vcoubard	607:e98331f1d6b5	3592	/* Register: MPU_PROTBLOCKSIZE */
vcoubard	607:e98331f1d6b5	3593	/* Description: Erase and write protection block size. */
vcoubard	607:e98331f1d6b5	3594
vcoubard	607:e98331f1d6b5	3595	/* Bits 1..0 : Erase and write protection block size. */
vcoubard	607:e98331f1d6b5	3596	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
vcoubard	607:e98331f1d6b5	3597	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
vcoubard	607:e98331f1d6b5	3598	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
vcoubard	607:e98331f1d6b5	3599
vcoubard	607:e98331f1d6b5	3600
vcoubard	607:e98331f1d6b5	3601	/* Peripheral: NVMC */
vcoubard	607:e98331f1d6b5	3602	/* Description: Non Volatile Memory Controller. */
vcoubard	607:e98331f1d6b5	3603
vcoubard	607:e98331f1d6b5	3604	/* Register: NVMC_READY */
vcoubard	607:e98331f1d6b5	3605	/* Description: Ready flag. */
vcoubard	607:e98331f1d6b5	3606
vcoubard	607:e98331f1d6b5	3607	/* Bit 0 : NVMC ready. */
vcoubard	607:e98331f1d6b5	3608	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	607:e98331f1d6b5	3609	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
vcoubard	607:e98331f1d6b5	3610	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
vcoubard	607:e98331f1d6b5	3611	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
vcoubard	607:e98331f1d6b5	3612
vcoubard	607:e98331f1d6b5	3613	/* Register: NVMC_CONFIG */
vcoubard	607:e98331f1d6b5	3614	/* Description: Configuration register. */
vcoubard	607:e98331f1d6b5	3615
vcoubard	607:e98331f1d6b5	3616	/* Bits 1..0 : Program write enable. */
vcoubard	607:e98331f1d6b5	3617	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
vcoubard	607:e98331f1d6b5	3618	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
vcoubard	607:e98331f1d6b5	3619	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
vcoubard	607:e98331f1d6b5	3620	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
vcoubard	607:e98331f1d6b5	3621	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
vcoubard	607:e98331f1d6b5	3622
vcoubard	607:e98331f1d6b5	3623	/* Register: NVMC_ERASEALL */
vcoubard	607:e98331f1d6b5	3624	/* Description: Register for erasing all non-volatile user memory. */
vcoubard	607:e98331f1d6b5	3625
vcoubard	607:e98331f1d6b5	3626	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
vcoubard	607:e98331f1d6b5	3627	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
vcoubard	607:e98331f1d6b5	3628	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
vcoubard	607:e98331f1d6b5	3629	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
vcoubard	607:e98331f1d6b5	3630	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
vcoubard	607:e98331f1d6b5	3631
vcoubard	607:e98331f1d6b5	3632	/* Register: NVMC_ERASEUICR */
vcoubard	607:e98331f1d6b5	3633	/* Description: Register for start erasing User Information Congfiguration Registers. */
vcoubard	607:e98331f1d6b5	3634
vcoubard	607:e98331f1d6b5	3635	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
vcoubard	607:e98331f1d6b5	3636	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
vcoubard	607:e98331f1d6b5	3637	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
vcoubard	607:e98331f1d6b5	3638	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
vcoubard	607:e98331f1d6b5	3639	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
vcoubard	607:e98331f1d6b5	3640
vcoubard	607:e98331f1d6b5	3641
vcoubard	607:e98331f1d6b5	3642	/* Peripheral: POWER */
vcoubard	607:e98331f1d6b5	3643	/* Description: Power Control. */
vcoubard	607:e98331f1d6b5	3644
vcoubard	607:e98331f1d6b5	3645	/* Register: POWER_INTENSET */
vcoubard	607:e98331f1d6b5	3646	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	3647
vcoubard	607:e98331f1d6b5	3648	/* Bit 2 : Enable interrupt on POFWARN event. */
vcoubard	607:e98331f1d6b5	3649	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
vcoubard	607:e98331f1d6b5	3650	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
vcoubard	607:e98331f1d6b5	3651	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	3652	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	3653	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	3654
vcoubard	607:e98331f1d6b5	3655	/* Register: POWER_INTENCLR */
vcoubard	607:e98331f1d6b5	3656	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	3657
vcoubard	607:e98331f1d6b5	3658	/* Bit 2 : Disable interrupt on POFWARN event. */
vcoubard	607:e98331f1d6b5	3659	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
vcoubard	607:e98331f1d6b5	3660	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
vcoubard	607:e98331f1d6b5	3661	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	3662	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	3663	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	3664
vcoubard	607:e98331f1d6b5	3665	/* Register: POWER_RESETREAS */
vcoubard	607:e98331f1d6b5	3666	/* Description: Reset reason. */
vcoubard	607:e98331f1d6b5	3667
vcoubard	607:e98331f1d6b5	3668	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
vcoubard	607:e98331f1d6b5	3669	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
vcoubard	607:e98331f1d6b5	3670	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
vcoubard	607:e98331f1d6b5	3671	#define POWER_RESETREAS_DIF_NotDetected (0UL) /!< Reset not detected. /
vcoubard	607:e98331f1d6b5	3672	#define POWER_RESETREAS_DIF_Detected (1UL) /!< Reset detected. /
vcoubard	607:e98331f1d6b5	3673
vcoubard	607:e98331f1d6b5	3674	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
vcoubard	607:e98331f1d6b5	3675	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
vcoubard	607:e98331f1d6b5	3676	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
vcoubard	607:e98331f1d6b5	3677	#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /!< Reset not detected. /
vcoubard	607:e98331f1d6b5	3678	#define POWER_RESETREAS_LPCOMP_Detected (1UL) /!< Reset detected. /
vcoubard	607:e98331f1d6b5	3679
vcoubard	607:e98331f1d6b5	3680	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
vcoubard	607:e98331f1d6b5	3681	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
vcoubard	607:e98331f1d6b5	3682	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
vcoubard	607:e98331f1d6b5	3683	#define POWER_RESETREAS_OFF_NotDetected (0UL) /!< Reset not detected. /
vcoubard	607:e98331f1d6b5	3684	#define POWER_RESETREAS_OFF_Detected (1UL) /!< Reset detected. /
vcoubard	607:e98331f1d6b5	3685
vcoubard	607:e98331f1d6b5	3686	/* Bit 3 : Reset from CPU lock-up detected. */
vcoubard	607:e98331f1d6b5	3687	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
vcoubard	607:e98331f1d6b5	3688	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
vcoubard	607:e98331f1d6b5	3689	#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /!< Reset not detected. /
vcoubard	607:e98331f1d6b5	3690	#define POWER_RESETREAS_LOCKUP_Detected (1UL) /!< Reset detected. /
vcoubard	607:e98331f1d6b5	3691
vcoubard	607:e98331f1d6b5	3692	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
vcoubard	607:e98331f1d6b5	3693	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
vcoubard	607:e98331f1d6b5	3694	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
vcoubard	607:e98331f1d6b5	3695	#define POWER_RESETREAS_SREQ_NotDetected (0UL) /!< Reset not detected. /
vcoubard	607:e98331f1d6b5	3696	#define POWER_RESETREAS_SREQ_Detected (1UL) /!< Reset detected. /
vcoubard	607:e98331f1d6b5	3697
vcoubard	607:e98331f1d6b5	3698	/* Bit 1 : Reset from watchdog detected. */
vcoubard	607:e98331f1d6b5	3699	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
vcoubard	607:e98331f1d6b5	3700	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
vcoubard	607:e98331f1d6b5	3701	#define POWER_RESETREAS_DOG_NotDetected (0UL) /!< Reset not detected. /
vcoubard	607:e98331f1d6b5	3702	#define POWER_RESETREAS_DOG_Detected (1UL) /!< Reset detected. /
vcoubard	607:e98331f1d6b5	3703
vcoubard	607:e98331f1d6b5	3704	/* Bit 0 : Reset from pin-reset detected. */
vcoubard	607:e98331f1d6b5	3705	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
vcoubard	607:e98331f1d6b5	3706	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
vcoubard	607:e98331f1d6b5	3707	#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /!< Reset not detected. /
vcoubard	607:e98331f1d6b5	3708	#define POWER_RESETREAS_RESETPIN_Detected (1UL) /!< Reset detected. /
vcoubard	607:e98331f1d6b5	3709
vcoubard	607:e98331f1d6b5	3710	/* Register: POWER_RAMSTATUS */
vcoubard	607:e98331f1d6b5	3711	/* Description: Ram status register. */
vcoubard	607:e98331f1d6b5	3712
vcoubard	607:e98331f1d6b5	3713	/* Bit 3 : RAM block 3 status. */
vcoubard	607:e98331f1d6b5	3714	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
vcoubard	607:e98331f1d6b5	3715	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
vcoubard	607:e98331f1d6b5	3716	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
vcoubard	607:e98331f1d6b5	3717	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
vcoubard	607:e98331f1d6b5	3718
vcoubard	607:e98331f1d6b5	3719	/* Bit 2 : RAM block 2 status. */
vcoubard	607:e98331f1d6b5	3720	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
vcoubard	607:e98331f1d6b5	3721	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
vcoubard	607:e98331f1d6b5	3722	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
vcoubard	607:e98331f1d6b5	3723	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
vcoubard	607:e98331f1d6b5	3724
vcoubard	607:e98331f1d6b5	3725	/* Bit 1 : RAM block 1 status. */
vcoubard	607:e98331f1d6b5	3726	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
vcoubard	607:e98331f1d6b5	3727	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
vcoubard	607:e98331f1d6b5	3728	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
vcoubard	607:e98331f1d6b5	3729	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
vcoubard	607:e98331f1d6b5	3730
vcoubard	607:e98331f1d6b5	3731	/* Bit 0 : RAM block 0 status. */
vcoubard	607:e98331f1d6b5	3732	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
vcoubard	607:e98331f1d6b5	3733	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
vcoubard	607:e98331f1d6b5	3734	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
vcoubard	607:e98331f1d6b5	3735	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
vcoubard	607:e98331f1d6b5	3736
vcoubard	607:e98331f1d6b5	3737	/* Register: POWER_SYSTEMOFF */
vcoubard	607:e98331f1d6b5	3738	/* Description: System off register. */
vcoubard	607:e98331f1d6b5	3739
vcoubard	607:e98331f1d6b5	3740	/* Bit 0 : Enter system off mode. */
vcoubard	607:e98331f1d6b5	3741	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
vcoubard	607:e98331f1d6b5	3742	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
vcoubard	607:e98331f1d6b5	3743	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
vcoubard	607:e98331f1d6b5	3744
vcoubard	607:e98331f1d6b5	3745	/* Register: POWER_POFCON */
vcoubard	607:e98331f1d6b5	3746	/* Description: Power failure configuration. */
vcoubard	607:e98331f1d6b5	3747
vcoubard	607:e98331f1d6b5	3748	/* Bits 2..1 : Set threshold level. */
vcoubard	607:e98331f1d6b5	3749	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
vcoubard	607:e98331f1d6b5	3750	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
vcoubard	607:e98331f1d6b5	3751	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
vcoubard	607:e98331f1d6b5	3752	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
vcoubard	607:e98331f1d6b5	3753	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
vcoubard	607:e98331f1d6b5	3754	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
vcoubard	607:e98331f1d6b5	3755
vcoubard	607:e98331f1d6b5	3756	/* Bit 0 : Power failure comparator enable. */
vcoubard	607:e98331f1d6b5	3757	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
vcoubard	607:e98331f1d6b5	3758	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
vcoubard	607:e98331f1d6b5	3759	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	3760	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	3761
vcoubard	607:e98331f1d6b5	3762	/* Register: POWER_GPREGRET */
vcoubard	607:e98331f1d6b5	3763	/* Description: General purpose retention register. This register is a retained register. */
vcoubard	607:e98331f1d6b5	3764
vcoubard	607:e98331f1d6b5	3765	/* Bits 7..0 : General purpose retention register. */
vcoubard	607:e98331f1d6b5	3766	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
vcoubard	607:e98331f1d6b5	3767	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
vcoubard	607:e98331f1d6b5	3768
vcoubard	607:e98331f1d6b5	3769	/* Register: POWER_RAMON */
vcoubard	607:e98331f1d6b5	3770	/* Description: Ram on/off. */
vcoubard	607:e98331f1d6b5	3771
vcoubard	607:e98331f1d6b5	3772	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
vcoubard	607:e98331f1d6b5	3773	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
vcoubard	607:e98331f1d6b5	3774	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
vcoubard	607:e98331f1d6b5	3775	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
vcoubard	607:e98331f1d6b5	3776	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
vcoubard	607:e98331f1d6b5	3777
vcoubard	607:e98331f1d6b5	3778	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
vcoubard	607:e98331f1d6b5	3779	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
vcoubard	607:e98331f1d6b5	3780	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
vcoubard	607:e98331f1d6b5	3781	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
vcoubard	607:e98331f1d6b5	3782	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
vcoubard	607:e98331f1d6b5	3783
vcoubard	607:e98331f1d6b5	3784	/* Bit 1 : RAM block 1 behaviour in ON mode. */
vcoubard	607:e98331f1d6b5	3785	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
vcoubard	607:e98331f1d6b5	3786	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
vcoubard	607:e98331f1d6b5	3787	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
vcoubard	607:e98331f1d6b5	3788	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
vcoubard	607:e98331f1d6b5	3789
vcoubard	607:e98331f1d6b5	3790	/* Bit 0 : RAM block 0 behaviour in ON mode. */
vcoubard	607:e98331f1d6b5	3791	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
vcoubard	607:e98331f1d6b5	3792	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
vcoubard	607:e98331f1d6b5	3793	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
vcoubard	607:e98331f1d6b5	3794	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
vcoubard	607:e98331f1d6b5	3795
vcoubard	607:e98331f1d6b5	3796	/* Register: POWER_RESET */
vcoubard	607:e98331f1d6b5	3797	/* Description: Pin reset functionality configuration register. This register is a retained register. */
vcoubard	607:e98331f1d6b5	3798
vcoubard	607:e98331f1d6b5	3799	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
vcoubard	607:e98331f1d6b5	3800	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
vcoubard	607:e98331f1d6b5	3801	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
vcoubard	607:e98331f1d6b5	3802	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
vcoubard	607:e98331f1d6b5	3803	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
vcoubard	607:e98331f1d6b5	3804
vcoubard	607:e98331f1d6b5	3805	/* Register: POWER_RAMONB */
vcoubard	607:e98331f1d6b5	3806	/* Description: Ram on/off. */
vcoubard	607:e98331f1d6b5	3807
vcoubard	607:e98331f1d6b5	3808	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
vcoubard	607:e98331f1d6b5	3809	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
vcoubard	607:e98331f1d6b5	3810	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
vcoubard	607:e98331f1d6b5	3811	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
vcoubard	607:e98331f1d6b5	3812	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
vcoubard	607:e98331f1d6b5	3813
vcoubard	607:e98331f1d6b5	3814	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
vcoubard	607:e98331f1d6b5	3815	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
vcoubard	607:e98331f1d6b5	3816	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
vcoubard	607:e98331f1d6b5	3817	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
vcoubard	607:e98331f1d6b5	3818	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
vcoubard	607:e98331f1d6b5	3819
vcoubard	607:e98331f1d6b5	3820	/* Bit 1 : RAM block 3 behaviour in ON mode. */
vcoubard	607:e98331f1d6b5	3821	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
vcoubard	607:e98331f1d6b5	3822	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
vcoubard	607:e98331f1d6b5	3823	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
vcoubard	607:e98331f1d6b5	3824	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
vcoubard	607:e98331f1d6b5	3825
vcoubard	607:e98331f1d6b5	3826	/* Bit 0 : RAM block 2 behaviour in ON mode. */
vcoubard	607:e98331f1d6b5	3827	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
vcoubard	607:e98331f1d6b5	3828	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
vcoubard	607:e98331f1d6b5	3829	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
vcoubard	607:e98331f1d6b5	3830	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
vcoubard	607:e98331f1d6b5	3831
vcoubard	607:e98331f1d6b5	3832	/* Register: POWER_DCDCEN */
vcoubard	607:e98331f1d6b5	3833	/* Description: DCDC converter enable configuration register. */
vcoubard	607:e98331f1d6b5	3834
vcoubard	607:e98331f1d6b5	3835	/* Bit 0 : Enable DCDC converter. */
vcoubard	607:e98331f1d6b5	3836	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
vcoubard	607:e98331f1d6b5	3837	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
vcoubard	607:e98331f1d6b5	3838	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
vcoubard	607:e98331f1d6b5	3839	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
vcoubard	607:e98331f1d6b5	3840
vcoubard	607:e98331f1d6b5	3841	/* Register: POWER_DCDCFORCE */
vcoubard	607:e98331f1d6b5	3842	/* Description: DCDC power-up force register. */
vcoubard	607:e98331f1d6b5	3843
vcoubard	607:e98331f1d6b5	3844	/* Bit 1 : DCDC power-up force on. */
vcoubard	607:e98331f1d6b5	3845	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
vcoubard	607:e98331f1d6b5	3846	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
vcoubard	607:e98331f1d6b5	3847	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
vcoubard	607:e98331f1d6b5	3848	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
vcoubard	607:e98331f1d6b5	3849
vcoubard	607:e98331f1d6b5	3850	/* Bit 0 : DCDC power-up force off. */
vcoubard	607:e98331f1d6b5	3851	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
vcoubard	607:e98331f1d6b5	3852	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
vcoubard	607:e98331f1d6b5	3853	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
vcoubard	607:e98331f1d6b5	3854	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
vcoubard	607:e98331f1d6b5	3855
vcoubard	607:e98331f1d6b5	3856
vcoubard	607:e98331f1d6b5	3857	/* Peripheral: PPI */
vcoubard	607:e98331f1d6b5	3858	/* Description: PPI controller. */
vcoubard	607:e98331f1d6b5	3859
vcoubard	607:e98331f1d6b5	3860	/* Register: PPI_CHEN */
vcoubard	607:e98331f1d6b5	3861	/* Description: Channel enable. */
vcoubard	607:e98331f1d6b5	3862
vcoubard	607:e98331f1d6b5	3863	/* Bit 31 : Enable PPI channel 31. */
vcoubard	607:e98331f1d6b5	3864	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	607:e98331f1d6b5	3865	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	607:e98331f1d6b5	3866	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3867	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3868
vcoubard	607:e98331f1d6b5	3869	/* Bit 30 : Enable PPI channel 30. */
vcoubard	607:e98331f1d6b5	3870	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	607:e98331f1d6b5	3871	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	607:e98331f1d6b5	3872	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3873	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3874
vcoubard	607:e98331f1d6b5	3875	/* Bit 29 : Enable PPI channel 29. */
vcoubard	607:e98331f1d6b5	3876	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	607:e98331f1d6b5	3877	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	607:e98331f1d6b5	3878	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3879	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3880
vcoubard	607:e98331f1d6b5	3881	/* Bit 28 : Enable PPI channel 28. */
vcoubard	607:e98331f1d6b5	3882	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	607:e98331f1d6b5	3883	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	607:e98331f1d6b5	3884	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3885	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3886
vcoubard	607:e98331f1d6b5	3887	/* Bit 27 : Enable PPI channel 27. */
vcoubard	607:e98331f1d6b5	3888	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	607:e98331f1d6b5	3889	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	607:e98331f1d6b5	3890	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3891	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3892
vcoubard	607:e98331f1d6b5	3893	/* Bit 26 : Enable PPI channel 26. */
vcoubard	607:e98331f1d6b5	3894	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	607:e98331f1d6b5	3895	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	607:e98331f1d6b5	3896	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3897	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3898
vcoubard	607:e98331f1d6b5	3899	/* Bit 25 : Enable PPI channel 25. */
vcoubard	607:e98331f1d6b5	3900	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	607:e98331f1d6b5	3901	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	607:e98331f1d6b5	3902	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3903	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3904
vcoubard	607:e98331f1d6b5	3905	/* Bit 24 : Enable PPI channel 24. */
vcoubard	607:e98331f1d6b5	3906	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	607:e98331f1d6b5	3907	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	607:e98331f1d6b5	3908	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3909	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3910
vcoubard	607:e98331f1d6b5	3911	/* Bit 23 : Enable PPI channel 23. */
vcoubard	607:e98331f1d6b5	3912	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	607:e98331f1d6b5	3913	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	607:e98331f1d6b5	3914	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3915	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3916
vcoubard	607:e98331f1d6b5	3917	/* Bit 22 : Enable PPI channel 22. */
vcoubard	607:e98331f1d6b5	3918	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	607:e98331f1d6b5	3919	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	607:e98331f1d6b5	3920	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3921	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3922
vcoubard	607:e98331f1d6b5	3923	/* Bit 21 : Enable PPI channel 21. */
vcoubard	607:e98331f1d6b5	3924	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	607:e98331f1d6b5	3925	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	607:e98331f1d6b5	3926	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3927	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3928
vcoubard	607:e98331f1d6b5	3929	/* Bit 20 : Enable PPI channel 20. */
vcoubard	607:e98331f1d6b5	3930	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	607:e98331f1d6b5	3931	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	607:e98331f1d6b5	3932	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3933	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3934
vcoubard	607:e98331f1d6b5	3935	/* Bit 15 : Enable PPI channel 15. */
vcoubard	607:e98331f1d6b5	3936	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	607:e98331f1d6b5	3937	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	607:e98331f1d6b5	3938	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3939	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3940
vcoubard	607:e98331f1d6b5	3941	/* Bit 14 : Enable PPI channel 14. */
vcoubard	607:e98331f1d6b5	3942	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	607:e98331f1d6b5	3943	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	607:e98331f1d6b5	3944	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3945	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3946
vcoubard	607:e98331f1d6b5	3947	/* Bit 13 : Enable PPI channel 13. */
vcoubard	607:e98331f1d6b5	3948	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	607:e98331f1d6b5	3949	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	607:e98331f1d6b5	3950	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3951	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3952
vcoubard	607:e98331f1d6b5	3953	/* Bit 12 : Enable PPI channel 12. */
vcoubard	607:e98331f1d6b5	3954	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	607:e98331f1d6b5	3955	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	607:e98331f1d6b5	3956	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3957	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3958
vcoubard	607:e98331f1d6b5	3959	/* Bit 11 : Enable PPI channel 11. */
vcoubard	607:e98331f1d6b5	3960	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	607:e98331f1d6b5	3961	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	607:e98331f1d6b5	3962	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3963	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3964
vcoubard	607:e98331f1d6b5	3965	/* Bit 10 : Enable PPI channel 10. */
vcoubard	607:e98331f1d6b5	3966	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	607:e98331f1d6b5	3967	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	607:e98331f1d6b5	3968	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3969	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3970
vcoubard	607:e98331f1d6b5	3971	/* Bit 9 : Enable PPI channel 9. */
vcoubard	607:e98331f1d6b5	3972	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	607:e98331f1d6b5	3973	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	607:e98331f1d6b5	3974	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3975	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3976
vcoubard	607:e98331f1d6b5	3977	/* Bit 8 : Enable PPI channel 8. */
vcoubard	607:e98331f1d6b5	3978	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	607:e98331f1d6b5	3979	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	607:e98331f1d6b5	3980	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3981	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3982
vcoubard	607:e98331f1d6b5	3983	/* Bit 7 : Enable PPI channel 7. */
vcoubard	607:e98331f1d6b5	3984	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	607:e98331f1d6b5	3985	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	607:e98331f1d6b5	3986	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3987	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3988
vcoubard	607:e98331f1d6b5	3989	/* Bit 6 : Enable PPI channel 6. */
vcoubard	607:e98331f1d6b5	3990	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	607:e98331f1d6b5	3991	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	607:e98331f1d6b5	3992	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3993	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	3994
vcoubard	607:e98331f1d6b5	3995	/* Bit 5 : Enable PPI channel 5. */
vcoubard	607:e98331f1d6b5	3996	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	607:e98331f1d6b5	3997	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	607:e98331f1d6b5	3998	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	3999	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4000
vcoubard	607:e98331f1d6b5	4001	/* Bit 4 : Enable PPI channel 4. */
vcoubard	607:e98331f1d6b5	4002	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	607:e98331f1d6b5	4003	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	607:e98331f1d6b5	4004	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4005	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4006
vcoubard	607:e98331f1d6b5	4007	/* Bit 3 : Enable PPI channel 3. */
vcoubard	607:e98331f1d6b5	4008	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	607:e98331f1d6b5	4009	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	607:e98331f1d6b5	4010	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
vcoubard	607:e98331f1d6b5	4011	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
vcoubard	607:e98331f1d6b5	4012
vcoubard	607:e98331f1d6b5	4013	/* Bit 2 : Enable PPI channel 2. */
vcoubard	607:e98331f1d6b5	4014	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	607:e98331f1d6b5	4015	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	607:e98331f1d6b5	4016	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4017	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4018
vcoubard	607:e98331f1d6b5	4019	/* Bit 1 : Enable PPI channel 1. */
vcoubard	607:e98331f1d6b5	4020	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	607:e98331f1d6b5	4021	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	607:e98331f1d6b5	4022	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4023	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4024
vcoubard	607:e98331f1d6b5	4025	/* Bit 0 : Enable PPI channel 0. */
vcoubard	607:e98331f1d6b5	4026	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	607:e98331f1d6b5	4027	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	607:e98331f1d6b5	4028	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4029	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4030
vcoubard	607:e98331f1d6b5	4031	/* Register: PPI_CHENSET */
vcoubard	607:e98331f1d6b5	4032	/* Description: Channel enable set. */
vcoubard	607:e98331f1d6b5	4033
vcoubard	607:e98331f1d6b5	4034	/* Bit 31 : Enable PPI channel 31. */
vcoubard	607:e98331f1d6b5	4035	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	607:e98331f1d6b5	4036	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	607:e98331f1d6b5	4037	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4038	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4039	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4040
vcoubard	607:e98331f1d6b5	4041	/* Bit 30 : Enable PPI channel 30. */
vcoubard	607:e98331f1d6b5	4042	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	607:e98331f1d6b5	4043	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	607:e98331f1d6b5	4044	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4045	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4046	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4047
vcoubard	607:e98331f1d6b5	4048	/* Bit 29 : Enable PPI channel 29. */
vcoubard	607:e98331f1d6b5	4049	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	607:e98331f1d6b5	4050	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	607:e98331f1d6b5	4051	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4052	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4053	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4054
vcoubard	607:e98331f1d6b5	4055	/* Bit 28 : Enable PPI channel 28. */
vcoubard	607:e98331f1d6b5	4056	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	607:e98331f1d6b5	4057	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	607:e98331f1d6b5	4058	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4059	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4060	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4061
vcoubard	607:e98331f1d6b5	4062	/* Bit 27 : Enable PPI channel 27. */
vcoubard	607:e98331f1d6b5	4063	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	607:e98331f1d6b5	4064	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	607:e98331f1d6b5	4065	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4066	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4067	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4068
vcoubard	607:e98331f1d6b5	4069	/* Bit 26 : Enable PPI channel 26. */
vcoubard	607:e98331f1d6b5	4070	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	607:e98331f1d6b5	4071	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	607:e98331f1d6b5	4072	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4073	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4074	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4075
vcoubard	607:e98331f1d6b5	4076	/* Bit 25 : Enable PPI channel 25. */
vcoubard	607:e98331f1d6b5	4077	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	607:e98331f1d6b5	4078	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	607:e98331f1d6b5	4079	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4080	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4081	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4082
vcoubard	607:e98331f1d6b5	4083	/* Bit 24 : Enable PPI channel 24. */
vcoubard	607:e98331f1d6b5	4084	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	607:e98331f1d6b5	4085	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	607:e98331f1d6b5	4086	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4087	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4088	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4089
vcoubard	607:e98331f1d6b5	4090	/* Bit 23 : Enable PPI channel 23. */
vcoubard	607:e98331f1d6b5	4091	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	607:e98331f1d6b5	4092	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	607:e98331f1d6b5	4093	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4094	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4095	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4096
vcoubard	607:e98331f1d6b5	4097	/* Bit 22 : Enable PPI channel 22. */
vcoubard	607:e98331f1d6b5	4098	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	607:e98331f1d6b5	4099	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	607:e98331f1d6b5	4100	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4101	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4102	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4103
vcoubard	607:e98331f1d6b5	4104	/* Bit 21 : Enable PPI channel 21. */
vcoubard	607:e98331f1d6b5	4105	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	607:e98331f1d6b5	4106	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	607:e98331f1d6b5	4107	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4108	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4109	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4110
vcoubard	607:e98331f1d6b5	4111	/* Bit 20 : Enable PPI channel 20. */
vcoubard	607:e98331f1d6b5	4112	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	607:e98331f1d6b5	4113	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	607:e98331f1d6b5	4114	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4115	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4116	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4117
vcoubard	607:e98331f1d6b5	4118	/* Bit 15 : Enable PPI channel 15. */
vcoubard	607:e98331f1d6b5	4119	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	607:e98331f1d6b5	4120	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	607:e98331f1d6b5	4121	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4122	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4123	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4124
vcoubard	607:e98331f1d6b5	4125	/* Bit 14 : Enable PPI channel 14. */
vcoubard	607:e98331f1d6b5	4126	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	607:e98331f1d6b5	4127	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	607:e98331f1d6b5	4128	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4129	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4130	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4131
vcoubard	607:e98331f1d6b5	4132	/* Bit 13 : Enable PPI channel 13. */
vcoubard	607:e98331f1d6b5	4133	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	607:e98331f1d6b5	4134	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	607:e98331f1d6b5	4135	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4136	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4137	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4138
vcoubard	607:e98331f1d6b5	4139	/* Bit 12 : Enable PPI channel 12. */
vcoubard	607:e98331f1d6b5	4140	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	607:e98331f1d6b5	4141	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	607:e98331f1d6b5	4142	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4143	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4144	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4145
vcoubard	607:e98331f1d6b5	4146	/* Bit 11 : Enable PPI channel 11. */
vcoubard	607:e98331f1d6b5	4147	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	607:e98331f1d6b5	4148	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	607:e98331f1d6b5	4149	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4150	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4151	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4152
vcoubard	607:e98331f1d6b5	4153	/* Bit 10 : Enable PPI channel 10. */
vcoubard	607:e98331f1d6b5	4154	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	607:e98331f1d6b5	4155	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	607:e98331f1d6b5	4156	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4157	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4158	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4159
vcoubard	607:e98331f1d6b5	4160	/* Bit 9 : Enable PPI channel 9. */
vcoubard	607:e98331f1d6b5	4161	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	607:e98331f1d6b5	4162	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	607:e98331f1d6b5	4163	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4164	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4165	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4166
vcoubard	607:e98331f1d6b5	4167	/* Bit 8 : Enable PPI channel 8. */
vcoubard	607:e98331f1d6b5	4168	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	607:e98331f1d6b5	4169	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	607:e98331f1d6b5	4170	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4171	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4172	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4173
vcoubard	607:e98331f1d6b5	4174	/* Bit 7 : Enable PPI channel 7. */
vcoubard	607:e98331f1d6b5	4175	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	607:e98331f1d6b5	4176	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	607:e98331f1d6b5	4177	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4178	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4179	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4180
vcoubard	607:e98331f1d6b5	4181	/* Bit 6 : Enable PPI channel 6. */
vcoubard	607:e98331f1d6b5	4182	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	607:e98331f1d6b5	4183	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	607:e98331f1d6b5	4184	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4185	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4186	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4187
vcoubard	607:e98331f1d6b5	4188	/* Bit 5 : Enable PPI channel 5. */
vcoubard	607:e98331f1d6b5	4189	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	607:e98331f1d6b5	4190	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	607:e98331f1d6b5	4191	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4192	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4193	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4194
vcoubard	607:e98331f1d6b5	4195	/* Bit 4 : Enable PPI channel 4. */
vcoubard	607:e98331f1d6b5	4196	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	607:e98331f1d6b5	4197	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	607:e98331f1d6b5	4198	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4199	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4200	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4201
vcoubard	607:e98331f1d6b5	4202	/* Bit 3 : Enable PPI channel 3. */
vcoubard	607:e98331f1d6b5	4203	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	607:e98331f1d6b5	4204	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	607:e98331f1d6b5	4205	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4206	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4207	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4208
vcoubard	607:e98331f1d6b5	4209	/* Bit 2 : Enable PPI channel 2. */
vcoubard	607:e98331f1d6b5	4210	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	607:e98331f1d6b5	4211	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	607:e98331f1d6b5	4212	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4213	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4214	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4215
vcoubard	607:e98331f1d6b5	4216	/* Bit 1 : Enable PPI channel 1. */
vcoubard	607:e98331f1d6b5	4217	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	607:e98331f1d6b5	4218	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	607:e98331f1d6b5	4219	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4220	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4221	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4222
vcoubard	607:e98331f1d6b5	4223	/* Bit 0 : Enable PPI channel 0. */
vcoubard	607:e98331f1d6b5	4224	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	607:e98331f1d6b5	4225	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	607:e98331f1d6b5	4226	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4227	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4228	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
vcoubard	607:e98331f1d6b5	4229
vcoubard	607:e98331f1d6b5	4230	/* Register: PPI_CHENCLR */
vcoubard	607:e98331f1d6b5	4231	/* Description: Channel enable clear. */
vcoubard	607:e98331f1d6b5	4232
vcoubard	607:e98331f1d6b5	4233	/* Bit 31 : Disable PPI channel 31. */
vcoubard	607:e98331f1d6b5	4234	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	607:e98331f1d6b5	4235	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	607:e98331f1d6b5	4236	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4237	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4238	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4239
vcoubard	607:e98331f1d6b5	4240	/* Bit 30 : Disable PPI channel 30. */
vcoubard	607:e98331f1d6b5	4241	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	607:e98331f1d6b5	4242	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	607:e98331f1d6b5	4243	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4244	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4245	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4246
vcoubard	607:e98331f1d6b5	4247	/* Bit 29 : Disable PPI channel 29. */
vcoubard	607:e98331f1d6b5	4248	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	607:e98331f1d6b5	4249	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	607:e98331f1d6b5	4250	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4251	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4252	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4253
vcoubard	607:e98331f1d6b5	4254	/* Bit 28 : Disable PPI channel 28. */
vcoubard	607:e98331f1d6b5	4255	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	607:e98331f1d6b5	4256	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	607:e98331f1d6b5	4257	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4258	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4259	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4260
vcoubard	607:e98331f1d6b5	4261	/* Bit 27 : Disable PPI channel 27. */
vcoubard	607:e98331f1d6b5	4262	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	607:e98331f1d6b5	4263	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	607:e98331f1d6b5	4264	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4265	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4266	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4267
vcoubard	607:e98331f1d6b5	4268	/* Bit 26 : Disable PPI channel 26. */
vcoubard	607:e98331f1d6b5	4269	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	607:e98331f1d6b5	4270	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	607:e98331f1d6b5	4271	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4272	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4273	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4274
vcoubard	607:e98331f1d6b5	4275	/* Bit 25 : Disable PPI channel 25. */
vcoubard	607:e98331f1d6b5	4276	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	607:e98331f1d6b5	4277	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	607:e98331f1d6b5	4278	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4279	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4280	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4281
vcoubard	607:e98331f1d6b5	4282	/* Bit 24 : Disable PPI channel 24. */
vcoubard	607:e98331f1d6b5	4283	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	607:e98331f1d6b5	4284	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	607:e98331f1d6b5	4285	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4286	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4287	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4288
vcoubard	607:e98331f1d6b5	4289	/* Bit 23 : Disable PPI channel 23. */
vcoubard	607:e98331f1d6b5	4290	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	607:e98331f1d6b5	4291	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	607:e98331f1d6b5	4292	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4293	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4294	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4295
vcoubard	607:e98331f1d6b5	4296	/* Bit 22 : Disable PPI channel 22. */
vcoubard	607:e98331f1d6b5	4297	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	607:e98331f1d6b5	4298	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	607:e98331f1d6b5	4299	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4300	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4301	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4302
vcoubard	607:e98331f1d6b5	4303	/* Bit 21 : Disable PPI channel 21. */
vcoubard	607:e98331f1d6b5	4304	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	607:e98331f1d6b5	4305	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	607:e98331f1d6b5	4306	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4307	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4308	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4309
vcoubard	607:e98331f1d6b5	4310	/* Bit 20 : Disable PPI channel 20. */
vcoubard	607:e98331f1d6b5	4311	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	607:e98331f1d6b5	4312	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	607:e98331f1d6b5	4313	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4314	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4315	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4316
vcoubard	607:e98331f1d6b5	4317	/* Bit 15 : Disable PPI channel 15. */
vcoubard	607:e98331f1d6b5	4318	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	607:e98331f1d6b5	4319	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	607:e98331f1d6b5	4320	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4321	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4322	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4323
vcoubard	607:e98331f1d6b5	4324	/* Bit 14 : Disable PPI channel 14. */
vcoubard	607:e98331f1d6b5	4325	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	607:e98331f1d6b5	4326	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	607:e98331f1d6b5	4327	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4328	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4329	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4330
vcoubard	607:e98331f1d6b5	4331	/* Bit 13 : Disable PPI channel 13. */
vcoubard	607:e98331f1d6b5	4332	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	607:e98331f1d6b5	4333	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	607:e98331f1d6b5	4334	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4335	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4336	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4337
vcoubard	607:e98331f1d6b5	4338	/* Bit 12 : Disable PPI channel 12. */
vcoubard	607:e98331f1d6b5	4339	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	607:e98331f1d6b5	4340	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	607:e98331f1d6b5	4341	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4342	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4343	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4344
vcoubard	607:e98331f1d6b5	4345	/* Bit 11 : Disable PPI channel 11. */
vcoubard	607:e98331f1d6b5	4346	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	607:e98331f1d6b5	4347	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	607:e98331f1d6b5	4348	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4349	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4350	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4351
vcoubard	607:e98331f1d6b5	4352	/* Bit 10 : Disable PPI channel 10. */
vcoubard	607:e98331f1d6b5	4353	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	607:e98331f1d6b5	4354	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	607:e98331f1d6b5	4355	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4356	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4357	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4358
vcoubard	607:e98331f1d6b5	4359	/* Bit 9 : Disable PPI channel 9. */
vcoubard	607:e98331f1d6b5	4360	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	607:e98331f1d6b5	4361	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	607:e98331f1d6b5	4362	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4363	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4364	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4365
vcoubard	607:e98331f1d6b5	4366	/* Bit 8 : Disable PPI channel 8. */
vcoubard	607:e98331f1d6b5	4367	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	607:e98331f1d6b5	4368	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	607:e98331f1d6b5	4369	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4370	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4371	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4372
vcoubard	607:e98331f1d6b5	4373	/* Bit 7 : Disable PPI channel 7. */
vcoubard	607:e98331f1d6b5	4374	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	607:e98331f1d6b5	4375	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	607:e98331f1d6b5	4376	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4377	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4378	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4379
vcoubard	607:e98331f1d6b5	4380	/* Bit 6 : Disable PPI channel 6. */
vcoubard	607:e98331f1d6b5	4381	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	607:e98331f1d6b5	4382	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	607:e98331f1d6b5	4383	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4384	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4385	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4386
vcoubard	607:e98331f1d6b5	4387	/* Bit 5 : Disable PPI channel 5. */
vcoubard	607:e98331f1d6b5	4388	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	607:e98331f1d6b5	4389	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	607:e98331f1d6b5	4390	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4391	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4392	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4393
vcoubard	607:e98331f1d6b5	4394	/* Bit 4 : Disable PPI channel 4. */
vcoubard	607:e98331f1d6b5	4395	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	607:e98331f1d6b5	4396	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	607:e98331f1d6b5	4397	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4398	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4399	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4400
vcoubard	607:e98331f1d6b5	4401	/* Bit 3 : Disable PPI channel 3. */
vcoubard	607:e98331f1d6b5	4402	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	607:e98331f1d6b5	4403	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	607:e98331f1d6b5	4404	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4405	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4406	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4407
vcoubard	607:e98331f1d6b5	4408	/* Bit 2 : Disable PPI channel 2. */
vcoubard	607:e98331f1d6b5	4409	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	607:e98331f1d6b5	4410	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	607:e98331f1d6b5	4411	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4412	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4413	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4414
vcoubard	607:e98331f1d6b5	4415	/* Bit 1 : Disable PPI channel 1. */
vcoubard	607:e98331f1d6b5	4416	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	607:e98331f1d6b5	4417	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	607:e98331f1d6b5	4418	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4419	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4420	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4421
vcoubard	607:e98331f1d6b5	4422	/* Bit 0 : Disable PPI channel 0. */
vcoubard	607:e98331f1d6b5	4423	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	607:e98331f1d6b5	4424	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	607:e98331f1d6b5	4425	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	607:e98331f1d6b5	4426	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	607:e98331f1d6b5	4427	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
vcoubard	607:e98331f1d6b5	4428
vcoubard	607:e98331f1d6b5	4429	/* Register: PPI_CHG */
vcoubard	607:e98331f1d6b5	4430	/* Description: Channel group configuration. */
vcoubard	607:e98331f1d6b5	4431
vcoubard	607:e98331f1d6b5	4432	/* Bit 31 : Include CH31 in channel group. */
vcoubard	607:e98331f1d6b5	4433	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	607:e98331f1d6b5	4434	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	607:e98331f1d6b5	4435	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4436	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4437
vcoubard	607:e98331f1d6b5	4438	/* Bit 30 : Include CH30 in channel group. */
vcoubard	607:e98331f1d6b5	4439	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	607:e98331f1d6b5	4440	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	607:e98331f1d6b5	4441	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4442	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4443
vcoubard	607:e98331f1d6b5	4444	/* Bit 29 : Include CH29 in channel group. */
vcoubard	607:e98331f1d6b5	4445	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	607:e98331f1d6b5	4446	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	607:e98331f1d6b5	4447	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4448	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4449
vcoubard	607:e98331f1d6b5	4450	/* Bit 28 : Include CH28 in channel group. */
vcoubard	607:e98331f1d6b5	4451	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	607:e98331f1d6b5	4452	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	607:e98331f1d6b5	4453	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4454	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4455
vcoubard	607:e98331f1d6b5	4456	/* Bit 27 : Include CH27 in channel group. */
vcoubard	607:e98331f1d6b5	4457	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	607:e98331f1d6b5	4458	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	607:e98331f1d6b5	4459	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4460	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4461
vcoubard	607:e98331f1d6b5	4462	/* Bit 26 : Include CH26 in channel group. */
vcoubard	607:e98331f1d6b5	4463	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	607:e98331f1d6b5	4464	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	607:e98331f1d6b5	4465	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4466	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4467
vcoubard	607:e98331f1d6b5	4468	/* Bit 25 : Include CH25 in channel group. */
vcoubard	607:e98331f1d6b5	4469	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	607:e98331f1d6b5	4470	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	607:e98331f1d6b5	4471	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4472	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4473
vcoubard	607:e98331f1d6b5	4474	/* Bit 24 : Include CH24 in channel group. */
vcoubard	607:e98331f1d6b5	4475	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	607:e98331f1d6b5	4476	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	607:e98331f1d6b5	4477	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4478	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4479
vcoubard	607:e98331f1d6b5	4480	/* Bit 23 : Include CH23 in channel group. */
vcoubard	607:e98331f1d6b5	4481	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	607:e98331f1d6b5	4482	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	607:e98331f1d6b5	4483	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4484	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4485
vcoubard	607:e98331f1d6b5	4486	/* Bit 22 : Include CH22 in channel group. */
vcoubard	607:e98331f1d6b5	4487	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	607:e98331f1d6b5	4488	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	607:e98331f1d6b5	4489	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4490	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4491
vcoubard	607:e98331f1d6b5	4492	/* Bit 21 : Include CH21 in channel group. */
vcoubard	607:e98331f1d6b5	4493	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	607:e98331f1d6b5	4494	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	607:e98331f1d6b5	4495	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4496	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4497
vcoubard	607:e98331f1d6b5	4498	/* Bit 20 : Include CH20 in channel group. */
vcoubard	607:e98331f1d6b5	4499	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	607:e98331f1d6b5	4500	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	607:e98331f1d6b5	4501	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4502	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4503
vcoubard	607:e98331f1d6b5	4504	/* Bit 15 : Include CH15 in channel group. */
vcoubard	607:e98331f1d6b5	4505	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	607:e98331f1d6b5	4506	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	607:e98331f1d6b5	4507	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4508	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4509
vcoubard	607:e98331f1d6b5	4510	/* Bit 14 : Include CH14 in channel group. */
vcoubard	607:e98331f1d6b5	4511	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	607:e98331f1d6b5	4512	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	607:e98331f1d6b5	4513	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4514	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4515
vcoubard	607:e98331f1d6b5	4516	/* Bit 13 : Include CH13 in channel group. */
vcoubard	607:e98331f1d6b5	4517	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	607:e98331f1d6b5	4518	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	607:e98331f1d6b5	4519	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4520	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4521
vcoubard	607:e98331f1d6b5	4522	/* Bit 12 : Include CH12 in channel group. */
vcoubard	607:e98331f1d6b5	4523	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	607:e98331f1d6b5	4524	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	607:e98331f1d6b5	4525	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4526	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4527
vcoubard	607:e98331f1d6b5	4528	/* Bit 11 : Include CH11 in channel group. */
vcoubard	607:e98331f1d6b5	4529	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	607:e98331f1d6b5	4530	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	607:e98331f1d6b5	4531	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4532	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4533
vcoubard	607:e98331f1d6b5	4534	/* Bit 10 : Include CH10 in channel group. */
vcoubard	607:e98331f1d6b5	4535	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	607:e98331f1d6b5	4536	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	607:e98331f1d6b5	4537	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4538	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4539
vcoubard	607:e98331f1d6b5	4540	/* Bit 9 : Include CH9 in channel group. */
vcoubard	607:e98331f1d6b5	4541	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	607:e98331f1d6b5	4542	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	607:e98331f1d6b5	4543	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4544	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4545
vcoubard	607:e98331f1d6b5	4546	/* Bit 8 : Include CH8 in channel group. */
vcoubard	607:e98331f1d6b5	4547	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	607:e98331f1d6b5	4548	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	607:e98331f1d6b5	4549	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4550	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4551
vcoubard	607:e98331f1d6b5	4552	/* Bit 7 : Include CH7 in channel group. */
vcoubard	607:e98331f1d6b5	4553	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	607:e98331f1d6b5	4554	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	607:e98331f1d6b5	4555	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4556	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4557
vcoubard	607:e98331f1d6b5	4558	/* Bit 6 : Include CH6 in channel group. */
vcoubard	607:e98331f1d6b5	4559	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	607:e98331f1d6b5	4560	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	607:e98331f1d6b5	4561	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4562	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4563
vcoubard	607:e98331f1d6b5	4564	/* Bit 5 : Include CH5 in channel group. */
vcoubard	607:e98331f1d6b5	4565	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	607:e98331f1d6b5	4566	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	607:e98331f1d6b5	4567	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4568	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4569
vcoubard	607:e98331f1d6b5	4570	/* Bit 4 : Include CH4 in channel group. */
vcoubard	607:e98331f1d6b5	4571	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	607:e98331f1d6b5	4572	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	607:e98331f1d6b5	4573	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4574	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4575
vcoubard	607:e98331f1d6b5	4576	/* Bit 3 : Include CH3 in channel group. */
vcoubard	607:e98331f1d6b5	4577	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	607:e98331f1d6b5	4578	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	607:e98331f1d6b5	4579	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4580	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4581
vcoubard	607:e98331f1d6b5	4582	/* Bit 2 : Include CH2 in channel group. */
vcoubard	607:e98331f1d6b5	4583	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	607:e98331f1d6b5	4584	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	607:e98331f1d6b5	4585	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4586	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4587
vcoubard	607:e98331f1d6b5	4588	/* Bit 1 : Include CH1 in channel group. */
vcoubard	607:e98331f1d6b5	4589	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	607:e98331f1d6b5	4590	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	607:e98331f1d6b5	4591	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4592	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4593
vcoubard	607:e98331f1d6b5	4594	/* Bit 0 : Include CH0 in channel group. */
vcoubard	607:e98331f1d6b5	4595	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	607:e98331f1d6b5	4596	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	607:e98331f1d6b5	4597	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
vcoubard	607:e98331f1d6b5	4598	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
vcoubard	607:e98331f1d6b5	4599
vcoubard	607:e98331f1d6b5	4600
vcoubard	607:e98331f1d6b5	4601	/* Peripheral: QDEC */
vcoubard	607:e98331f1d6b5	4602	/* Description: Rotary decoder. */
vcoubard	607:e98331f1d6b5	4603
vcoubard	607:e98331f1d6b5	4604	/* Register: QDEC_SHORTS */
vcoubard	607:e98331f1d6b5	4605	/* Description: Shortcuts for the QDEC. */
vcoubard	607:e98331f1d6b5	4606
vcoubard	607:e98331f1d6b5	4607	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
vcoubard	607:e98331f1d6b5	4608	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
vcoubard	607:e98331f1d6b5	4609	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
vcoubard	607:e98331f1d6b5	4610	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4611	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4612
vcoubard	607:e98331f1d6b5	4613	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
vcoubard	607:e98331f1d6b5	4614	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
vcoubard	607:e98331f1d6b5	4615	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
vcoubard	607:e98331f1d6b5	4616	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4617	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4618
vcoubard	607:e98331f1d6b5	4619	/* Register: QDEC_INTENSET */
vcoubard	607:e98331f1d6b5	4620	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	4621
vcoubard	607:e98331f1d6b5	4622	/* Bit 2 : Enable interrupt on ACCOF event. */
vcoubard	607:e98331f1d6b5	4623	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
vcoubard	607:e98331f1d6b5	4624	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
vcoubard	607:e98331f1d6b5	4625	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4626	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4627	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4628
vcoubard	607:e98331f1d6b5	4629	/* Bit 1 : Enable interrupt on REPORTRDY event. */
vcoubard	607:e98331f1d6b5	4630	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
vcoubard	607:e98331f1d6b5	4631	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
vcoubard	607:e98331f1d6b5	4632	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4633	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4634	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4635
vcoubard	607:e98331f1d6b5	4636	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
vcoubard	607:e98331f1d6b5	4637	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
vcoubard	607:e98331f1d6b5	4638	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
vcoubard	607:e98331f1d6b5	4639	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4640	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4641	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4642
vcoubard	607:e98331f1d6b5	4643	/* Register: QDEC_INTENCLR */
vcoubard	607:e98331f1d6b5	4644	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	4645
vcoubard	607:e98331f1d6b5	4646	/* Bit 2 : Disable interrupt on ACCOF event. */
vcoubard	607:e98331f1d6b5	4647	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
vcoubard	607:e98331f1d6b5	4648	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
vcoubard	607:e98331f1d6b5	4649	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4650	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4651	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4652
vcoubard	607:e98331f1d6b5	4653	/* Bit 1 : Disable interrupt on REPORTRDY event. */
vcoubard	607:e98331f1d6b5	4654	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
vcoubard	607:e98331f1d6b5	4655	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
vcoubard	607:e98331f1d6b5	4656	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4657	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4658	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4659
vcoubard	607:e98331f1d6b5	4660	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
vcoubard	607:e98331f1d6b5	4661	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
vcoubard	607:e98331f1d6b5	4662	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
vcoubard	607:e98331f1d6b5	4663	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4664	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4665	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4666
vcoubard	607:e98331f1d6b5	4667	/* Register: QDEC_ENABLE */
vcoubard	607:e98331f1d6b5	4668	/* Description: Enable the QDEC. */
vcoubard	607:e98331f1d6b5	4669
vcoubard	607:e98331f1d6b5	4670	/* Bit 0 : Enable or disable QDEC. */
vcoubard	607:e98331f1d6b5	4671	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	4672	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	4673	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
vcoubard	607:e98331f1d6b5	4674	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
vcoubard	607:e98331f1d6b5	4675
vcoubard	607:e98331f1d6b5	4676	/* Register: QDEC_LEDPOL */
vcoubard	607:e98331f1d6b5	4677	/* Description: LED output pin polarity. */
vcoubard	607:e98331f1d6b5	4678
vcoubard	607:e98331f1d6b5	4679	/* Bit 0 : LED output pin polarity. */
vcoubard	607:e98331f1d6b5	4680	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
vcoubard	607:e98331f1d6b5	4681	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
vcoubard	607:e98331f1d6b5	4682	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
vcoubard	607:e98331f1d6b5	4683	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
vcoubard	607:e98331f1d6b5	4684
vcoubard	607:e98331f1d6b5	4685	/* Register: QDEC_SAMPLEPER */
vcoubard	607:e98331f1d6b5	4686	/* Description: Sample period. */
vcoubard	607:e98331f1d6b5	4687
vcoubard	607:e98331f1d6b5	4688	/* Bits 2..0 : Sample period. */
vcoubard	607:e98331f1d6b5	4689	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
vcoubard	607:e98331f1d6b5	4690	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
vcoubard	607:e98331f1d6b5	4691	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
vcoubard	607:e98331f1d6b5	4692	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
vcoubard	607:e98331f1d6b5	4693	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
vcoubard	607:e98331f1d6b5	4694	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
vcoubard	607:e98331f1d6b5	4695	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
vcoubard	607:e98331f1d6b5	4696	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
vcoubard	607:e98331f1d6b5	4697	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
vcoubard	607:e98331f1d6b5	4698	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
vcoubard	607:e98331f1d6b5	4699
vcoubard	607:e98331f1d6b5	4700	/* Register: QDEC_SAMPLE */
vcoubard	607:e98331f1d6b5	4701	/* Description: Motion sample value. */
vcoubard	607:e98331f1d6b5	4702
vcoubard	607:e98331f1d6b5	4703	/* Bits 31..0 : Last sample taken in compliment to 2. */
vcoubard	607:e98331f1d6b5	4704	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
vcoubard	607:e98331f1d6b5	4705	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
vcoubard	607:e98331f1d6b5	4706
vcoubard	607:e98331f1d6b5	4707	/* Register: QDEC_REPORTPER */
vcoubard	607:e98331f1d6b5	4708	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
vcoubard	607:e98331f1d6b5	4709
vcoubard	607:e98331f1d6b5	4710	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
vcoubard	607:e98331f1d6b5	4711	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
vcoubard	607:e98331f1d6b5	4712	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
vcoubard	607:e98331f1d6b5	4713	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
vcoubard	607:e98331f1d6b5	4714	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
vcoubard	607:e98331f1d6b5	4715	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
vcoubard	607:e98331f1d6b5	4716	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
vcoubard	607:e98331f1d6b5	4717	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
vcoubard	607:e98331f1d6b5	4718	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
vcoubard	607:e98331f1d6b5	4719	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
vcoubard	607:e98331f1d6b5	4720	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
vcoubard	607:e98331f1d6b5	4721
vcoubard	607:e98331f1d6b5	4722	/* Register: QDEC_DBFEN */
vcoubard	607:e98331f1d6b5	4723	/* Description: Enable debouncer input filters. */
vcoubard	607:e98331f1d6b5	4724
vcoubard	607:e98331f1d6b5	4725	/* Bit 0 : Enable debounce input filters. */
vcoubard	607:e98331f1d6b5	4726	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
vcoubard	607:e98331f1d6b5	4727	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
vcoubard	607:e98331f1d6b5	4728	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
vcoubard	607:e98331f1d6b5	4729	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
vcoubard	607:e98331f1d6b5	4730
vcoubard	607:e98331f1d6b5	4731	/* Register: QDEC_LEDPRE */
vcoubard	607:e98331f1d6b5	4732	/* Description: Time LED is switched ON before the sample. */
vcoubard	607:e98331f1d6b5	4733
vcoubard	607:e98331f1d6b5	4734	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
vcoubard	607:e98331f1d6b5	4735	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
vcoubard	607:e98331f1d6b5	4736	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
vcoubard	607:e98331f1d6b5	4737
vcoubard	607:e98331f1d6b5	4738	/* Register: QDEC_ACCDBL */
vcoubard	607:e98331f1d6b5	4739	/* Description: Accumulated double (error) transitions register. */
vcoubard	607:e98331f1d6b5	4740
vcoubard	607:e98331f1d6b5	4741	/* Bits 3..0 : Accumulated double (error) transitions. */
vcoubard	607:e98331f1d6b5	4742	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
vcoubard	607:e98331f1d6b5	4743	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
vcoubard	607:e98331f1d6b5	4744
vcoubard	607:e98331f1d6b5	4745	/* Register: QDEC_ACCDBLREAD */
vcoubard	607:e98331f1d6b5	4746	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
vcoubard	607:e98331f1d6b5	4747
vcoubard	607:e98331f1d6b5	4748	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
vcoubard	607:e98331f1d6b5	4749	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
vcoubard	607:e98331f1d6b5	4750	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
vcoubard	607:e98331f1d6b5	4751
vcoubard	607:e98331f1d6b5	4752	/* Register: QDEC_POWER */
vcoubard	607:e98331f1d6b5	4753	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	4754
vcoubard	607:e98331f1d6b5	4755	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	4756	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	4757	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	4758	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	4759	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	4760
vcoubard	607:e98331f1d6b5	4761
vcoubard	607:e98331f1d6b5	4762	/* Peripheral: RADIO */
vcoubard	607:e98331f1d6b5	4763	/* Description: The radio. */
vcoubard	607:e98331f1d6b5	4764
vcoubard	607:e98331f1d6b5	4765	/* Register: RADIO_SHORTS */
vcoubard	607:e98331f1d6b5	4766	/* Description: Shortcuts for the radio. */
vcoubard	607:e98331f1d6b5	4767
vcoubard	607:e98331f1d6b5	4768	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
vcoubard	607:e98331f1d6b5	4769	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
vcoubard	607:e98331f1d6b5	4770	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
vcoubard	607:e98331f1d6b5	4771	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4772	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4773
vcoubard	607:e98331f1d6b5	4774	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
vcoubard	607:e98331f1d6b5	4775	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
vcoubard	607:e98331f1d6b5	4776	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
vcoubard	607:e98331f1d6b5	4777	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4778	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4779
vcoubard	607:e98331f1d6b5	4780	/* Bit 5 : Shortcut between END event and START task. */
vcoubard	607:e98331f1d6b5	4781	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
vcoubard	607:e98331f1d6b5	4782	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
vcoubard	607:e98331f1d6b5	4783	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4784	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4785
vcoubard	607:e98331f1d6b5	4786	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
vcoubard	607:e98331f1d6b5	4787	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
vcoubard	607:e98331f1d6b5	4788	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
vcoubard	607:e98331f1d6b5	4789	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4790	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4791
vcoubard	607:e98331f1d6b5	4792	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
vcoubard	607:e98331f1d6b5	4793	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
vcoubard	607:e98331f1d6b5	4794	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
vcoubard	607:e98331f1d6b5	4795	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4796	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4797
vcoubard	607:e98331f1d6b5	4798	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
vcoubard	607:e98331f1d6b5	4799	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
vcoubard	607:e98331f1d6b5	4800	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
vcoubard	607:e98331f1d6b5	4801	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4802	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4803
vcoubard	607:e98331f1d6b5	4804	/* Bit 1 : Shortcut between END event and DISABLE task. */
vcoubard	607:e98331f1d6b5	4805	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
vcoubard	607:e98331f1d6b5	4806	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
vcoubard	607:e98331f1d6b5	4807	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4808	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4809
vcoubard	607:e98331f1d6b5	4810	/* Bit 0 : Shortcut between READY event and START task. */
vcoubard	607:e98331f1d6b5	4811	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
vcoubard	607:e98331f1d6b5	4812	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
vcoubard	607:e98331f1d6b5	4813	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	4814	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	4815
vcoubard	607:e98331f1d6b5	4816	/* Register: RADIO_INTENSET */
vcoubard	607:e98331f1d6b5	4817	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	4818
vcoubard	607:e98331f1d6b5	4819	/* Bit 10 : Enable interrupt on BCMATCH event. */
vcoubard	607:e98331f1d6b5	4820	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
vcoubard	607:e98331f1d6b5	4821	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
vcoubard	607:e98331f1d6b5	4822	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4823	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4824	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4825
vcoubard	607:e98331f1d6b5	4826	/* Bit 7 : Enable interrupt on RSSIEND event. */
vcoubard	607:e98331f1d6b5	4827	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
vcoubard	607:e98331f1d6b5	4828	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
vcoubard	607:e98331f1d6b5	4829	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4830	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4831	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4832
vcoubard	607:e98331f1d6b5	4833	/* Bit 6 : Enable interrupt on DEVMISS event. */
vcoubard	607:e98331f1d6b5	4834	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
vcoubard	607:e98331f1d6b5	4835	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
vcoubard	607:e98331f1d6b5	4836	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4837	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4838	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4839
vcoubard	607:e98331f1d6b5	4840	/* Bit 5 : Enable interrupt on DEVMATCH event. */
vcoubard	607:e98331f1d6b5	4841	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
vcoubard	607:e98331f1d6b5	4842	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
vcoubard	607:e98331f1d6b5	4843	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4844	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4845	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4846
vcoubard	607:e98331f1d6b5	4847	/* Bit 4 : Enable interrupt on DISABLED event. */
vcoubard	607:e98331f1d6b5	4848	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
vcoubard	607:e98331f1d6b5	4849	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
vcoubard	607:e98331f1d6b5	4850	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4851	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4852	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4853
vcoubard	607:e98331f1d6b5	4854	/* Bit 3 : Enable interrupt on END event. */
vcoubard	607:e98331f1d6b5	4855	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	4856	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	4857	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4858	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4859	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4860
vcoubard	607:e98331f1d6b5	4861	/* Bit 2 : Enable interrupt on PAYLOAD event. */
vcoubard	607:e98331f1d6b5	4862	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
vcoubard	607:e98331f1d6b5	4863	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
vcoubard	607:e98331f1d6b5	4864	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4865	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4866	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4867
vcoubard	607:e98331f1d6b5	4868	/* Bit 1 : Enable interrupt on ADDRESS event. */
vcoubard	607:e98331f1d6b5	4869	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
vcoubard	607:e98331f1d6b5	4870	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	607:e98331f1d6b5	4871	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4872	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4873	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4874
vcoubard	607:e98331f1d6b5	4875	/* Bit 0 : Enable interrupt on READY event. */
vcoubard	607:e98331f1d6b5	4876	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	607:e98331f1d6b5	4877	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	607:e98331f1d6b5	4878	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4879	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4880	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	4881
vcoubard	607:e98331f1d6b5	4882	/* Register: RADIO_INTENCLR */
vcoubard	607:e98331f1d6b5	4883	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	4884
vcoubard	607:e98331f1d6b5	4885	/* Bit 10 : Disable interrupt on BCMATCH event. */
vcoubard	607:e98331f1d6b5	4886	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
vcoubard	607:e98331f1d6b5	4887	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
vcoubard	607:e98331f1d6b5	4888	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4889	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4890	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4891
vcoubard	607:e98331f1d6b5	4892	/* Bit 7 : Disable interrupt on RSSIEND event. */
vcoubard	607:e98331f1d6b5	4893	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
vcoubard	607:e98331f1d6b5	4894	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
vcoubard	607:e98331f1d6b5	4895	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4896	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4897	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4898
vcoubard	607:e98331f1d6b5	4899	/* Bit 6 : Disable interrupt on DEVMISS event. */
vcoubard	607:e98331f1d6b5	4900	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
vcoubard	607:e98331f1d6b5	4901	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
vcoubard	607:e98331f1d6b5	4902	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4903	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4904	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4905
vcoubard	607:e98331f1d6b5	4906	/* Bit 5 : Disable interrupt on DEVMATCH event. */
vcoubard	607:e98331f1d6b5	4907	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
vcoubard	607:e98331f1d6b5	4908	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
vcoubard	607:e98331f1d6b5	4909	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4910	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4911	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4912
vcoubard	607:e98331f1d6b5	4913	/* Bit 4 : Disable interrupt on DISABLED event. */
vcoubard	607:e98331f1d6b5	4914	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
vcoubard	607:e98331f1d6b5	4915	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
vcoubard	607:e98331f1d6b5	4916	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4917	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4918	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4919
vcoubard	607:e98331f1d6b5	4920	/* Bit 3 : Disable interrupt on END event. */
vcoubard	607:e98331f1d6b5	4921	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	4922	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	4923	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4924	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4925	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4926
vcoubard	607:e98331f1d6b5	4927	/* Bit 2 : Disable interrupt on PAYLOAD event. */
vcoubard	607:e98331f1d6b5	4928	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
vcoubard	607:e98331f1d6b5	4929	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
vcoubard	607:e98331f1d6b5	4930	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4931	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4932	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4933
vcoubard	607:e98331f1d6b5	4934	/* Bit 1 : Disable interrupt on ADDRESS event. */
vcoubard	607:e98331f1d6b5	4935	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
vcoubard	607:e98331f1d6b5	4936	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	607:e98331f1d6b5	4937	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4938	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4939	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4940
vcoubard	607:e98331f1d6b5	4941	/* Bit 0 : Disable interrupt on READY event. */
vcoubard	607:e98331f1d6b5	4942	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	607:e98331f1d6b5	4943	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	607:e98331f1d6b5	4944	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	4945	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	4946	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	4947
vcoubard	607:e98331f1d6b5	4948	/* Register: RADIO_CRCSTATUS */
vcoubard	607:e98331f1d6b5	4949	/* Description: CRC status of received packet. */
vcoubard	607:e98331f1d6b5	4950
vcoubard	607:e98331f1d6b5	4951	/* Bit 0 : CRC status of received packet. */
vcoubard	607:e98331f1d6b5	4952	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
vcoubard	607:e98331f1d6b5	4953	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
vcoubard	607:e98331f1d6b5	4954	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
vcoubard	607:e98331f1d6b5	4955	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
vcoubard	607:e98331f1d6b5	4956
vcoubard	607:e98331f1d6b5	4957	/* Register: RADIO_RXMATCH */
vcoubard	607:e98331f1d6b5	4958	/* Description: Received address. */
vcoubard	607:e98331f1d6b5	4959
vcoubard	607:e98331f1d6b5	4960	/* Bits 2..0 : Logical address in which previous packet was received. */
vcoubard	607:e98331f1d6b5	4961	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
vcoubard	607:e98331f1d6b5	4962	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
vcoubard	607:e98331f1d6b5	4963
vcoubard	607:e98331f1d6b5	4964	/* Register: RADIO_RXCRC */
vcoubard	607:e98331f1d6b5	4965	/* Description: Received CRC. */
vcoubard	607:e98331f1d6b5	4966
vcoubard	607:e98331f1d6b5	4967	/* Bits 23..0 : CRC field of previously received packet. */
vcoubard	607:e98331f1d6b5	4968	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
vcoubard	607:e98331f1d6b5	4969	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
vcoubard	607:e98331f1d6b5	4970
vcoubard	607:e98331f1d6b5	4971	/* Register: RADIO_DAI */
vcoubard	607:e98331f1d6b5	4972	/* Description: Device address match index. */
vcoubard	607:e98331f1d6b5	4973
vcoubard	607:e98331f1d6b5	4974	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
vcoubard	607:e98331f1d6b5	4975	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
vcoubard	607:e98331f1d6b5	4976	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
vcoubard	607:e98331f1d6b5	4977
vcoubard	607:e98331f1d6b5	4978	/* Register: RADIO_FREQUENCY */
vcoubard	607:e98331f1d6b5	4979	/* Description: Frequency. */
vcoubard	607:e98331f1d6b5	4980
vcoubard	607:e98331f1d6b5	4981	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
vcoubard	607:e98331f1d6b5	4982	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	4983	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	4984
vcoubard	607:e98331f1d6b5	4985	/* Register: RADIO_TXPOWER */
vcoubard	607:e98331f1d6b5	4986	/* Description: Output power. */
vcoubard	607:e98331f1d6b5	4987
vcoubard	607:e98331f1d6b5	4988	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
vcoubard	607:e98331f1d6b5	4989	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
vcoubard	607:e98331f1d6b5	4990	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
vcoubard	607:e98331f1d6b5	4991	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
vcoubard	607:e98331f1d6b5	4992	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
vcoubard	607:e98331f1d6b5	4993	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
vcoubard	607:e98331f1d6b5	4994	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
vcoubard	607:e98331f1d6b5	4995	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
vcoubard	607:e98331f1d6b5	4996	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
vcoubard	607:e98331f1d6b5	4997	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
vcoubard	607:e98331f1d6b5	4998	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
vcoubard	607:e98331f1d6b5	4999
vcoubard	607:e98331f1d6b5	5000	/* Register: RADIO_MODE */
vcoubard	607:e98331f1d6b5	5001	/* Description: Data rate and modulation. */
vcoubard	607:e98331f1d6b5	5002
vcoubard	607:e98331f1d6b5	5003	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
vcoubard	607:e98331f1d6b5	5004	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	607:e98331f1d6b5	5005	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	607:e98331f1d6b5	5006	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
vcoubard	607:e98331f1d6b5	5007	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
vcoubard	607:e98331f1d6b5	5008	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
vcoubard	607:e98331f1d6b5	5009	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
vcoubard	607:e98331f1d6b5	5010
vcoubard	607:e98331f1d6b5	5011	/* Register: RADIO_PCNF0 */
vcoubard	607:e98331f1d6b5	5012	/* Description: Packet configuration 0. */
vcoubard	607:e98331f1d6b5	5013
vcoubard	607:e98331f1d6b5	5014	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5015	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
vcoubard	607:e98331f1d6b5	5016	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
vcoubard	607:e98331f1d6b5	5017
vcoubard	607:e98331f1d6b5	5018	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5019	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
vcoubard	607:e98331f1d6b5	5020	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
vcoubard	607:e98331f1d6b5	5021
vcoubard	607:e98331f1d6b5	5022	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5023	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
vcoubard	607:e98331f1d6b5	5024	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
vcoubard	607:e98331f1d6b5	5025
vcoubard	607:e98331f1d6b5	5026	/* Register: RADIO_PCNF1 */
vcoubard	607:e98331f1d6b5	5027	/* Description: Packet configuration 1. */
vcoubard	607:e98331f1d6b5	5028
vcoubard	607:e98331f1d6b5	5029	/* Bit 25 : Packet whitening enable. */
vcoubard	607:e98331f1d6b5	5030	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
vcoubard	607:e98331f1d6b5	5031	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
vcoubard	607:e98331f1d6b5	5032	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
vcoubard	607:e98331f1d6b5	5033	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
vcoubard	607:e98331f1d6b5	5034
vcoubard	607:e98331f1d6b5	5035	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5036	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
vcoubard	607:e98331f1d6b5	5037	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
vcoubard	607:e98331f1d6b5	5038	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
vcoubard	607:e98331f1d6b5	5039	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
vcoubard	607:e98331f1d6b5	5040
vcoubard	607:e98331f1d6b5	5041	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5042	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
vcoubard	607:e98331f1d6b5	5043	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
vcoubard	607:e98331f1d6b5	5044
vcoubard	607:e98331f1d6b5	5045	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5046	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
vcoubard	607:e98331f1d6b5	5047	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
vcoubard	607:e98331f1d6b5	5048
vcoubard	607:e98331f1d6b5	5049	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
vcoubard	607:e98331f1d6b5	5050	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
vcoubard	607:e98331f1d6b5	5051	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
vcoubard	607:e98331f1d6b5	5052
vcoubard	607:e98331f1d6b5	5053	/* Register: RADIO_PREFIX0 */
vcoubard	607:e98331f1d6b5	5054	/* Description: Prefixes bytes for logical addresses 0 to 3. */
vcoubard	607:e98331f1d6b5	5055
vcoubard	607:e98331f1d6b5	5056	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5057	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
vcoubard	607:e98331f1d6b5	5058	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
vcoubard	607:e98331f1d6b5	5059
vcoubard	607:e98331f1d6b5	5060	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5061	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
vcoubard	607:e98331f1d6b5	5062	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
vcoubard	607:e98331f1d6b5	5063
vcoubard	607:e98331f1d6b5	5064	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5065	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
vcoubard	607:e98331f1d6b5	5066	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
vcoubard	607:e98331f1d6b5	5067
vcoubard	607:e98331f1d6b5	5068	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5069	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
vcoubard	607:e98331f1d6b5	5070	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
vcoubard	607:e98331f1d6b5	5071
vcoubard	607:e98331f1d6b5	5072	/* Register: RADIO_PREFIX1 */
vcoubard	607:e98331f1d6b5	5073	/* Description: Prefixes bytes for logical addresses 4 to 7. */
vcoubard	607:e98331f1d6b5	5074
vcoubard	607:e98331f1d6b5	5075	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5076	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
vcoubard	607:e98331f1d6b5	5077	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
vcoubard	607:e98331f1d6b5	5078
vcoubard	607:e98331f1d6b5	5079	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5080	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
vcoubard	607:e98331f1d6b5	5081	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
vcoubard	607:e98331f1d6b5	5082
vcoubard	607:e98331f1d6b5	5083	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5084	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
vcoubard	607:e98331f1d6b5	5085	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
vcoubard	607:e98331f1d6b5	5086
vcoubard	607:e98331f1d6b5	5087	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5088	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
vcoubard	607:e98331f1d6b5	5089	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
vcoubard	607:e98331f1d6b5	5090
vcoubard	607:e98331f1d6b5	5091	/* Register: RADIO_TXADDRESS */
vcoubard	607:e98331f1d6b5	5092	/* Description: Transmit address select. */
vcoubard	607:e98331f1d6b5	5093
vcoubard	607:e98331f1d6b5	5094	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5095	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
vcoubard	607:e98331f1d6b5	5096	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
vcoubard	607:e98331f1d6b5	5097
vcoubard	607:e98331f1d6b5	5098	/* Register: RADIO_RXADDRESSES */
vcoubard	607:e98331f1d6b5	5099	/* Description: Receive address select. */
vcoubard	607:e98331f1d6b5	5100
vcoubard	607:e98331f1d6b5	5101	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5102	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
vcoubard	607:e98331f1d6b5	5103	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
vcoubard	607:e98331f1d6b5	5104	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5105	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5106
vcoubard	607:e98331f1d6b5	5107	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5108	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
vcoubard	607:e98331f1d6b5	5109	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
vcoubard	607:e98331f1d6b5	5110	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5111	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5112
vcoubard	607:e98331f1d6b5	5113	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5114	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
vcoubard	607:e98331f1d6b5	5115	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
vcoubard	607:e98331f1d6b5	5116	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5117	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5118
vcoubard	607:e98331f1d6b5	5119	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5120	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
vcoubard	607:e98331f1d6b5	5121	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
vcoubard	607:e98331f1d6b5	5122	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5123	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5124
vcoubard	607:e98331f1d6b5	5125	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5126	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
vcoubard	607:e98331f1d6b5	5127	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
vcoubard	607:e98331f1d6b5	5128	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5129	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5130
vcoubard	607:e98331f1d6b5	5131	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5132	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
vcoubard	607:e98331f1d6b5	5133	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
vcoubard	607:e98331f1d6b5	5134	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5135	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5136
vcoubard	607:e98331f1d6b5	5137	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5138	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
vcoubard	607:e98331f1d6b5	5139	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
vcoubard	607:e98331f1d6b5	5140	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5141	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5142
vcoubard	607:e98331f1d6b5	5143	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5144	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
vcoubard	607:e98331f1d6b5	5145	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
vcoubard	607:e98331f1d6b5	5146	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
vcoubard	607:e98331f1d6b5	5147	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
vcoubard	607:e98331f1d6b5	5148
vcoubard	607:e98331f1d6b5	5149	/* Register: RADIO_CRCCNF */
vcoubard	607:e98331f1d6b5	5150	/* Description: CRC configuration. */
vcoubard	607:e98331f1d6b5	5151
vcoubard	607:e98331f1d6b5	5152	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5153	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
vcoubard	607:e98331f1d6b5	5154	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
vcoubard	607:e98331f1d6b5	5155	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
vcoubard	607:e98331f1d6b5	5156	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
vcoubard	607:e98331f1d6b5	5157
vcoubard	607:e98331f1d6b5	5158	/* Bits 1..0 : CRC length. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5159	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
vcoubard	607:e98331f1d6b5	5160	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
vcoubard	607:e98331f1d6b5	5161	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
vcoubard	607:e98331f1d6b5	5162	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
vcoubard	607:e98331f1d6b5	5163	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
vcoubard	607:e98331f1d6b5	5164	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
vcoubard	607:e98331f1d6b5	5165
vcoubard	607:e98331f1d6b5	5166	/* Register: RADIO_CRCPOLY */
vcoubard	607:e98331f1d6b5	5167	/* Description: CRC polynomial. */
vcoubard	607:e98331f1d6b5	5168
vcoubard	607:e98331f1d6b5	5169	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5170	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
vcoubard	607:e98331f1d6b5	5171	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
vcoubard	607:e98331f1d6b5	5172
vcoubard	607:e98331f1d6b5	5173	/* Register: RADIO_CRCINIT */
vcoubard	607:e98331f1d6b5	5174	/* Description: CRC initial value. */
vcoubard	607:e98331f1d6b5	5175
vcoubard	607:e98331f1d6b5	5176	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
vcoubard	607:e98331f1d6b5	5177	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
vcoubard	607:e98331f1d6b5	5178	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
vcoubard	607:e98331f1d6b5	5179
vcoubard	607:e98331f1d6b5	5180	/* Register: RADIO_TEST */
vcoubard	607:e98331f1d6b5	5181	/* Description: Test features enable register. */
vcoubard	607:e98331f1d6b5	5182
vcoubard	607:e98331f1d6b5	5183	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
vcoubard	607:e98331f1d6b5	5184	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
vcoubard	607:e98331f1d6b5	5185	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
vcoubard	607:e98331f1d6b5	5186	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
vcoubard	607:e98331f1d6b5	5187	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
vcoubard	607:e98331f1d6b5	5188
vcoubard	607:e98331f1d6b5	5189	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
vcoubard	607:e98331f1d6b5	5190	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
vcoubard	607:e98331f1d6b5	5191	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
vcoubard	607:e98331f1d6b5	5192	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
vcoubard	607:e98331f1d6b5	5193	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
vcoubard	607:e98331f1d6b5	5194
vcoubard	607:e98331f1d6b5	5195	/* Register: RADIO_TIFS */
vcoubard	607:e98331f1d6b5	5196	/* Description: Inter Frame Spacing in microseconds. */
vcoubard	607:e98331f1d6b5	5197
vcoubard	607:e98331f1d6b5	5198	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
vcoubard	607:e98331f1d6b5	5199	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
vcoubard	607:e98331f1d6b5	5200	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
vcoubard	607:e98331f1d6b5	5201
vcoubard	607:e98331f1d6b5	5202	/* Register: RADIO_RSSISAMPLE */
vcoubard	607:e98331f1d6b5	5203	/* Description: RSSI sample. */
vcoubard	607:e98331f1d6b5	5204
vcoubard	607:e98331f1d6b5	5205	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
vcoubard	607:e98331f1d6b5	5206	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
vcoubard	607:e98331f1d6b5	5207	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
vcoubard	607:e98331f1d6b5	5208
vcoubard	607:e98331f1d6b5	5209	/* Register: RADIO_STATE */
vcoubard	607:e98331f1d6b5	5210	/* Description: Current radio state. */
vcoubard	607:e98331f1d6b5	5211
vcoubard	607:e98331f1d6b5	5212	/* Bits 3..0 : Current radio state. */
vcoubard	607:e98331f1d6b5	5213	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
vcoubard	607:e98331f1d6b5	5214	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	607:e98331f1d6b5	5215	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
vcoubard	607:e98331f1d6b5	5216	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
vcoubard	607:e98331f1d6b5	5217	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
vcoubard	607:e98331f1d6b5	5218	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
vcoubard	607:e98331f1d6b5	5219	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
vcoubard	607:e98331f1d6b5	5220	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
vcoubard	607:e98331f1d6b5	5221	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
vcoubard	607:e98331f1d6b5	5222	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
vcoubard	607:e98331f1d6b5	5223	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
vcoubard	607:e98331f1d6b5	5224
vcoubard	607:e98331f1d6b5	5225	/* Register: RADIO_DATAWHITEIV */
vcoubard	607:e98331f1d6b5	5226	/* Description: Data whitening initial value. */
vcoubard	607:e98331f1d6b5	5227
vcoubard	607:e98331f1d6b5	5228	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
vcoubard	607:e98331f1d6b5	5229	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
vcoubard	607:e98331f1d6b5	5230	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
vcoubard	607:e98331f1d6b5	5231
vcoubard	607:e98331f1d6b5	5232	/* Register: RADIO_DAP */
vcoubard	607:e98331f1d6b5	5233	/* Description: Device address prefix. */
vcoubard	607:e98331f1d6b5	5234
vcoubard	607:e98331f1d6b5	5235	/* Bits 15..0 : Device address prefix. */
vcoubard	607:e98331f1d6b5	5236	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
vcoubard	607:e98331f1d6b5	5237	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
vcoubard	607:e98331f1d6b5	5238
vcoubard	607:e98331f1d6b5	5239	/* Register: RADIO_DACNF */
vcoubard	607:e98331f1d6b5	5240	/* Description: Device address match configuration. */
vcoubard	607:e98331f1d6b5	5241
vcoubard	607:e98331f1d6b5	5242	/* Bit 15 : TxAdd for device address 7. */
vcoubard	607:e98331f1d6b5	5243	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
vcoubard	607:e98331f1d6b5	5244	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
vcoubard	607:e98331f1d6b5	5245
vcoubard	607:e98331f1d6b5	5246	/* Bit 14 : TxAdd for device address 6. */
vcoubard	607:e98331f1d6b5	5247	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
vcoubard	607:e98331f1d6b5	5248	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
vcoubard	607:e98331f1d6b5	5249
vcoubard	607:e98331f1d6b5	5250	/* Bit 13 : TxAdd for device address 5. */
vcoubard	607:e98331f1d6b5	5251	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
vcoubard	607:e98331f1d6b5	5252	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
vcoubard	607:e98331f1d6b5	5253
vcoubard	607:e98331f1d6b5	5254	/* Bit 12 : TxAdd for device address 4. */
vcoubard	607:e98331f1d6b5	5255	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
vcoubard	607:e98331f1d6b5	5256	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
vcoubard	607:e98331f1d6b5	5257
vcoubard	607:e98331f1d6b5	5258	/* Bit 11 : TxAdd for device address 3. */
vcoubard	607:e98331f1d6b5	5259	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
vcoubard	607:e98331f1d6b5	5260	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
vcoubard	607:e98331f1d6b5	5261
vcoubard	607:e98331f1d6b5	5262	/* Bit 10 : TxAdd for device address 2. */
vcoubard	607:e98331f1d6b5	5263	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
vcoubard	607:e98331f1d6b5	5264	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
vcoubard	607:e98331f1d6b5	5265
vcoubard	607:e98331f1d6b5	5266	/* Bit 9 : TxAdd for device address 1. */
vcoubard	607:e98331f1d6b5	5267	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
vcoubard	607:e98331f1d6b5	5268	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
vcoubard	607:e98331f1d6b5	5269
vcoubard	607:e98331f1d6b5	5270	/* Bit 8 : TxAdd for device address 0. */
vcoubard	607:e98331f1d6b5	5271	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
vcoubard	607:e98331f1d6b5	5272	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
vcoubard	607:e98331f1d6b5	5273
vcoubard	607:e98331f1d6b5	5274	/* Bit 7 : Enable or disable device address matching using device address 7. */
vcoubard	607:e98331f1d6b5	5275	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
vcoubard	607:e98331f1d6b5	5276	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
vcoubard	607:e98331f1d6b5	5277	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5278	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5279
vcoubard	607:e98331f1d6b5	5280	/* Bit 6 : Enable or disable device address matching using device address 6. */
vcoubard	607:e98331f1d6b5	5281	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
vcoubard	607:e98331f1d6b5	5282	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
vcoubard	607:e98331f1d6b5	5283	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5284	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5285
vcoubard	607:e98331f1d6b5	5286	/* Bit 5 : Enable or disable device address matching using device address 5. */
vcoubard	607:e98331f1d6b5	5287	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
vcoubard	607:e98331f1d6b5	5288	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
vcoubard	607:e98331f1d6b5	5289	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5290	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5291
vcoubard	607:e98331f1d6b5	5292	/* Bit 4 : Enable or disable device address matching using device address 4. */
vcoubard	607:e98331f1d6b5	5293	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
vcoubard	607:e98331f1d6b5	5294	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
vcoubard	607:e98331f1d6b5	5295	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5296	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5297
vcoubard	607:e98331f1d6b5	5298	/* Bit 3 : Enable or disable device address matching using device address 3. */
vcoubard	607:e98331f1d6b5	5299	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
vcoubard	607:e98331f1d6b5	5300	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
vcoubard	607:e98331f1d6b5	5301	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5302	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5303
vcoubard	607:e98331f1d6b5	5304	/* Bit 2 : Enable or disable device address matching using device address 2. */
vcoubard	607:e98331f1d6b5	5305	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
vcoubard	607:e98331f1d6b5	5306	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
vcoubard	607:e98331f1d6b5	5307	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5308	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5309
vcoubard	607:e98331f1d6b5	5310	/* Bit 1 : Enable or disable device address matching using device address 1. */
vcoubard	607:e98331f1d6b5	5311	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
vcoubard	607:e98331f1d6b5	5312	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
vcoubard	607:e98331f1d6b5	5313	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5314	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5315
vcoubard	607:e98331f1d6b5	5316	/* Bit 0 : Enable or disable device address matching using device address 0. */
vcoubard	607:e98331f1d6b5	5317	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
vcoubard	607:e98331f1d6b5	5318	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
vcoubard	607:e98331f1d6b5	5319	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	5320	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	5321
vcoubard	607:e98331f1d6b5	5322	/* Register: RADIO_OVERRIDE0 */
vcoubard	607:e98331f1d6b5	5323	/* Description: Trim value override register 0. */
vcoubard	607:e98331f1d6b5	5324
vcoubard	607:e98331f1d6b5	5325	/* Bits 31..0 : Trim value override 0. */
vcoubard	607:e98331f1d6b5	5326	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
vcoubard	607:e98331f1d6b5	5327	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
vcoubard	607:e98331f1d6b5	5328
vcoubard	607:e98331f1d6b5	5329	/* Register: RADIO_OVERRIDE1 */
vcoubard	607:e98331f1d6b5	5330	/* Description: Trim value override register 1. */
vcoubard	607:e98331f1d6b5	5331
vcoubard	607:e98331f1d6b5	5332	/* Bits 31..0 : Trim value override 1. */
vcoubard	607:e98331f1d6b5	5333	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
vcoubard	607:e98331f1d6b5	5334	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
vcoubard	607:e98331f1d6b5	5335
vcoubard	607:e98331f1d6b5	5336	/* Register: RADIO_OVERRIDE2 */
vcoubard	607:e98331f1d6b5	5337	/* Description: Trim value override register 2. */
vcoubard	607:e98331f1d6b5	5338
vcoubard	607:e98331f1d6b5	5339	/* Bits 31..0 : Trim value override 2. */
vcoubard	607:e98331f1d6b5	5340	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
vcoubard	607:e98331f1d6b5	5341	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
vcoubard	607:e98331f1d6b5	5342
vcoubard	607:e98331f1d6b5	5343	/* Register: RADIO_OVERRIDE3 */
vcoubard	607:e98331f1d6b5	5344	/* Description: Trim value override register 3. */
vcoubard	607:e98331f1d6b5	5345
vcoubard	607:e98331f1d6b5	5346	/* Bits 31..0 : Trim value override 3. */
vcoubard	607:e98331f1d6b5	5347	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
vcoubard	607:e98331f1d6b5	5348	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
vcoubard	607:e98331f1d6b5	5349
vcoubard	607:e98331f1d6b5	5350	/* Register: RADIO_OVERRIDE4 */
vcoubard	607:e98331f1d6b5	5351	/* Description: Trim value override register 4. */
vcoubard	607:e98331f1d6b5	5352
vcoubard	607:e98331f1d6b5	5353	/* Bit 31 : Enable or disable override of default trim values. */
vcoubard	607:e98331f1d6b5	5354	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	5355	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	5356	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
vcoubard	607:e98331f1d6b5	5357	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
vcoubard	607:e98331f1d6b5	5358
vcoubard	607:e98331f1d6b5	5359	/* Bits 27..0 : Trim value override 4. */
vcoubard	607:e98331f1d6b5	5360	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
vcoubard	607:e98331f1d6b5	5361	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
vcoubard	607:e98331f1d6b5	5362
vcoubard	607:e98331f1d6b5	5363	/* Register: RADIO_POWER */
vcoubard	607:e98331f1d6b5	5364	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	5365
vcoubard	607:e98331f1d6b5	5366	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	5367	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	5368	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	5369	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	5370	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	5371
vcoubard	607:e98331f1d6b5	5372
vcoubard	607:e98331f1d6b5	5373	/* Peripheral: RNG */
vcoubard	607:e98331f1d6b5	5374	/* Description: Random Number Generator. */
vcoubard	607:e98331f1d6b5	5375
vcoubard	607:e98331f1d6b5	5376	/* Register: RNG_SHORTS */
vcoubard	607:e98331f1d6b5	5377	/* Description: Shortcuts for the RNG. */
vcoubard	607:e98331f1d6b5	5378
vcoubard	607:e98331f1d6b5	5379	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
vcoubard	607:e98331f1d6b5	5380	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
vcoubard	607:e98331f1d6b5	5381	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
vcoubard	607:e98331f1d6b5	5382	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	5383	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	5384
vcoubard	607:e98331f1d6b5	5385	/* Register: RNG_INTENSET */
vcoubard	607:e98331f1d6b5	5386	/* Description: Interrupt enable set register */
vcoubard	607:e98331f1d6b5	5387
vcoubard	607:e98331f1d6b5	5388	/* Bit 0 : Enable interrupt on VALRDY event. */
vcoubard	607:e98331f1d6b5	5389	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
vcoubard	607:e98331f1d6b5	5390	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
vcoubard	607:e98331f1d6b5	5391	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5392	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5393	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5394
vcoubard	607:e98331f1d6b5	5395	/* Register: RNG_INTENCLR */
vcoubard	607:e98331f1d6b5	5396	/* Description: Interrupt enable clear register */
vcoubard	607:e98331f1d6b5	5397
vcoubard	607:e98331f1d6b5	5398	/* Bit 0 : Disable interrupt on VALRDY event. */
vcoubard	607:e98331f1d6b5	5399	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
vcoubard	607:e98331f1d6b5	5400	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
vcoubard	607:e98331f1d6b5	5401	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5402	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5403	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5404
vcoubard	607:e98331f1d6b5	5405	/* Register: RNG_CONFIG */
vcoubard	607:e98331f1d6b5	5406	/* Description: Configuration register. */
vcoubard	607:e98331f1d6b5	5407
vcoubard	607:e98331f1d6b5	5408	/* Bit 0 : Digital error correction enable. */
vcoubard	607:e98331f1d6b5	5409	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
vcoubard	607:e98331f1d6b5	5410	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
vcoubard	607:e98331f1d6b5	5411	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
vcoubard	607:e98331f1d6b5	5412	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
vcoubard	607:e98331f1d6b5	5413
vcoubard	607:e98331f1d6b5	5414	/* Register: RNG_VALUE */
vcoubard	607:e98331f1d6b5	5415	/* Description: RNG random number. */
vcoubard	607:e98331f1d6b5	5416
vcoubard	607:e98331f1d6b5	5417	/* Bits 7..0 : Generated random number. */
vcoubard	607:e98331f1d6b5	5418	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
vcoubard	607:e98331f1d6b5	5419	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
vcoubard	607:e98331f1d6b5	5420
vcoubard	607:e98331f1d6b5	5421	/* Register: RNG_POWER */
vcoubard	607:e98331f1d6b5	5422	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	5423
vcoubard	607:e98331f1d6b5	5424	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	5425	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	5426	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	5427	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	5428	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	5429
vcoubard	607:e98331f1d6b5	5430
vcoubard	607:e98331f1d6b5	5431	/* Peripheral: RTC */
vcoubard	607:e98331f1d6b5	5432	/* Description: Real time counter 0. */
vcoubard	607:e98331f1d6b5	5433
vcoubard	607:e98331f1d6b5	5434	/* Register: RTC_INTENSET */
vcoubard	607:e98331f1d6b5	5435	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	5436
vcoubard	607:e98331f1d6b5	5437	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
vcoubard	607:e98331f1d6b5	5438	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5439	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5440	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5441	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5442	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5443
vcoubard	607:e98331f1d6b5	5444	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
vcoubard	607:e98331f1d6b5	5445	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5446	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5447	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5448	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5449	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5450
vcoubard	607:e98331f1d6b5	5451	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
vcoubard	607:e98331f1d6b5	5452	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5453	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5454	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5455	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5456	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5457
vcoubard	607:e98331f1d6b5	5458	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
vcoubard	607:e98331f1d6b5	5459	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5460	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5461	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5462	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5463	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5464
vcoubard	607:e98331f1d6b5	5465	/* Bit 1 : Enable interrupt on OVRFLW event. */
vcoubard	607:e98331f1d6b5	5466	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5467	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5468	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5469	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5470	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5471
vcoubard	607:e98331f1d6b5	5472	/* Bit 0 : Enable interrupt on TICK event. */
vcoubard	607:e98331f1d6b5	5473	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	607:e98331f1d6b5	5474	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	607:e98331f1d6b5	5475	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5476	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5477	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5478
vcoubard	607:e98331f1d6b5	5479	/* Register: RTC_INTENCLR */
vcoubard	607:e98331f1d6b5	5480	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	5481
vcoubard	607:e98331f1d6b5	5482	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
vcoubard	607:e98331f1d6b5	5483	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5484	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5485	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5486	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5487	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5488
vcoubard	607:e98331f1d6b5	5489	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
vcoubard	607:e98331f1d6b5	5490	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5491	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5492	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5493	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5494	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5495
vcoubard	607:e98331f1d6b5	5496	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
vcoubard	607:e98331f1d6b5	5497	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5498	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5499	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5500	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5501	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5502
vcoubard	607:e98331f1d6b5	5503	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
vcoubard	607:e98331f1d6b5	5504	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5505	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5506	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5507	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5508	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5509
vcoubard	607:e98331f1d6b5	5510	/* Bit 1 : Disable interrupt on OVRFLW event. */
vcoubard	607:e98331f1d6b5	5511	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5512	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5513	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5514	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5515	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5516
vcoubard	607:e98331f1d6b5	5517	/* Bit 0 : Disable interrupt on TICK event. */
vcoubard	607:e98331f1d6b5	5518	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	607:e98331f1d6b5	5519	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	607:e98331f1d6b5	5520	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5521	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5522	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5523
vcoubard	607:e98331f1d6b5	5524	/* Register: RTC_EVTEN */
vcoubard	607:e98331f1d6b5	5525	/* Description: Configures event enable routing to PPI for each RTC event. */
vcoubard	607:e98331f1d6b5	5526
vcoubard	607:e98331f1d6b5	5527	/* Bit 19 : COMPARE[3] event enable. */
vcoubard	607:e98331f1d6b5	5528	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5529	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5530	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5531	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5532
vcoubard	607:e98331f1d6b5	5533	/* Bit 18 : COMPARE[2] event enable. */
vcoubard	607:e98331f1d6b5	5534	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5535	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5536	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5537	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5538
vcoubard	607:e98331f1d6b5	5539	/* Bit 17 : COMPARE[1] event enable. */
vcoubard	607:e98331f1d6b5	5540	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5541	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5542	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5543	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5544
vcoubard	607:e98331f1d6b5	5545	/* Bit 16 : COMPARE[0] event enable. */
vcoubard	607:e98331f1d6b5	5546	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5547	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5548	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5549	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5550
vcoubard	607:e98331f1d6b5	5551	/* Bit 1 : OVRFLW event enable. */
vcoubard	607:e98331f1d6b5	5552	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5553	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5554	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5555	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5556
vcoubard	607:e98331f1d6b5	5557	/* Bit 0 : TICK event enable. */
vcoubard	607:e98331f1d6b5	5558	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	607:e98331f1d6b5	5559	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	607:e98331f1d6b5	5560	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5561	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5562
vcoubard	607:e98331f1d6b5	5563	/* Register: RTC_EVTENSET */
vcoubard	607:e98331f1d6b5	5564	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
vcoubard	607:e98331f1d6b5	5565
vcoubard	607:e98331f1d6b5	5566	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
vcoubard	607:e98331f1d6b5	5567	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5568	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5569	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5570	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5571	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
vcoubard	607:e98331f1d6b5	5572
vcoubard	607:e98331f1d6b5	5573	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
vcoubard	607:e98331f1d6b5	5574	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5575	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5576	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5577	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5578	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
vcoubard	607:e98331f1d6b5	5579
vcoubard	607:e98331f1d6b5	5580	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
vcoubard	607:e98331f1d6b5	5581	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5582	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5583	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5584	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5585	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
vcoubard	607:e98331f1d6b5	5586
vcoubard	607:e98331f1d6b5	5587	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
vcoubard	607:e98331f1d6b5	5588	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5589	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5590	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5591	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5592	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
vcoubard	607:e98331f1d6b5	5593
vcoubard	607:e98331f1d6b5	5594	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
vcoubard	607:e98331f1d6b5	5595	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5596	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5597	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5598	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5599	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
vcoubard	607:e98331f1d6b5	5600
vcoubard	607:e98331f1d6b5	5601	/* Bit 0 : Enable routing to PPI of TICK event. */
vcoubard	607:e98331f1d6b5	5602	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	607:e98331f1d6b5	5603	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	607:e98331f1d6b5	5604	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5605	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5606	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
vcoubard	607:e98331f1d6b5	5607
vcoubard	607:e98331f1d6b5	5608	/* Register: RTC_EVTENCLR */
vcoubard	607:e98331f1d6b5	5609	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
vcoubard	607:e98331f1d6b5	5610
vcoubard	607:e98331f1d6b5	5611	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
vcoubard	607:e98331f1d6b5	5612	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5613	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	5614	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5615	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5616	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
vcoubard	607:e98331f1d6b5	5617
vcoubard	607:e98331f1d6b5	5618	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
vcoubard	607:e98331f1d6b5	5619	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5620	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	5621	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5622	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5623	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
vcoubard	607:e98331f1d6b5	5624
vcoubard	607:e98331f1d6b5	5625	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
vcoubard	607:e98331f1d6b5	5626	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5627	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	5628	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5629	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5630	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
vcoubard	607:e98331f1d6b5	5631
vcoubard	607:e98331f1d6b5	5632	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
vcoubard	607:e98331f1d6b5	5633	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5634	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	5635	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5636	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5637	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
vcoubard	607:e98331f1d6b5	5638
vcoubard	607:e98331f1d6b5	5639	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
vcoubard	607:e98331f1d6b5	5640	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5641	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	607:e98331f1d6b5	5642	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5643	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5644	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
vcoubard	607:e98331f1d6b5	5645
vcoubard	607:e98331f1d6b5	5646	/* Bit 0 : Disable routing to PPI of TICK event. */
vcoubard	607:e98331f1d6b5	5647	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	607:e98331f1d6b5	5648	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	607:e98331f1d6b5	5649	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	607:e98331f1d6b5	5650	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	607:e98331f1d6b5	5651	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
vcoubard	607:e98331f1d6b5	5652
vcoubard	607:e98331f1d6b5	5653	/* Register: RTC_COUNTER */
vcoubard	607:e98331f1d6b5	5654	/* Description: Current COUNTER value. */
vcoubard	607:e98331f1d6b5	5655
vcoubard	607:e98331f1d6b5	5656	/* Bits 23..0 : Counter value. */
vcoubard	607:e98331f1d6b5	5657	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
vcoubard	607:e98331f1d6b5	5658	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
vcoubard	607:e98331f1d6b5	5659
vcoubard	607:e98331f1d6b5	5660	/* Register: RTC_PRESCALER */
vcoubard	607:e98331f1d6b5	5661	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
vcoubard	607:e98331f1d6b5	5662
vcoubard	607:e98331f1d6b5	5663	/* Bits 11..0 : RTC PRESCALER value. */
vcoubard	607:e98331f1d6b5	5664	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
vcoubard	607:e98331f1d6b5	5665	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
vcoubard	607:e98331f1d6b5	5666
vcoubard	607:e98331f1d6b5	5667	/* Register: RTC_CC */
vcoubard	607:e98331f1d6b5	5668	/* Description: Capture/compare registers. */
vcoubard	607:e98331f1d6b5	5669
vcoubard	607:e98331f1d6b5	5670	/* Bits 23..0 : Compare value. */
vcoubard	607:e98331f1d6b5	5671	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
vcoubard	607:e98331f1d6b5	5672	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
vcoubard	607:e98331f1d6b5	5673
vcoubard	607:e98331f1d6b5	5674	/* Register: RTC_POWER */
vcoubard	607:e98331f1d6b5	5675	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	5676
vcoubard	607:e98331f1d6b5	5677	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	5678	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	5679	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	5680	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	5681	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	5682
vcoubard	607:e98331f1d6b5	5683
vcoubard	607:e98331f1d6b5	5684	/* Peripheral: SPI */
vcoubard	607:e98331f1d6b5	5685	/* Description: SPI master 0. */
vcoubard	607:e98331f1d6b5	5686
vcoubard	607:e98331f1d6b5	5687	/* Register: SPI_INTENSET */
vcoubard	607:e98331f1d6b5	5688	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	5689
vcoubard	607:e98331f1d6b5	5690	/* Bit 2 : Enable interrupt on READY event. */
vcoubard	607:e98331f1d6b5	5691	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
vcoubard	607:e98331f1d6b5	5692	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	607:e98331f1d6b5	5693	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5694	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5695	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5696
vcoubard	607:e98331f1d6b5	5697	/* Register: SPI_INTENCLR */
vcoubard	607:e98331f1d6b5	5698	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	5699
vcoubard	607:e98331f1d6b5	5700	/* Bit 2 : Disable interrupt on READY event. */
vcoubard	607:e98331f1d6b5	5701	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
vcoubard	607:e98331f1d6b5	5702	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	607:e98331f1d6b5	5703	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5704	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5705	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5706
vcoubard	607:e98331f1d6b5	5707	/* Register: SPI_ENABLE */
vcoubard	607:e98331f1d6b5	5708	/* Description: Enable SPI. */
vcoubard	607:e98331f1d6b5	5709
vcoubard	607:e98331f1d6b5	5710	/* Bits 2..0 : Enable or disable SPI. */
vcoubard	607:e98331f1d6b5	5711	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	5712	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	5713	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
vcoubard	607:e98331f1d6b5	5714	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
vcoubard	607:e98331f1d6b5	5715
vcoubard	607:e98331f1d6b5	5716	/* Register: SPI_RXD */
vcoubard	607:e98331f1d6b5	5717	/* Description: RX data. */
vcoubard	607:e98331f1d6b5	5718
vcoubard	607:e98331f1d6b5	5719	/* Bits 7..0 : RX data from last transfer. */
vcoubard	607:e98331f1d6b5	5720	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	607:e98331f1d6b5	5721	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	607:e98331f1d6b5	5722
vcoubard	607:e98331f1d6b5	5723	/* Register: SPI_TXD */
vcoubard	607:e98331f1d6b5	5724	/* Description: TX data. */
vcoubard	607:e98331f1d6b5	5725
vcoubard	607:e98331f1d6b5	5726	/* Bits 7..0 : TX data for next transfer. */
vcoubard	607:e98331f1d6b5	5727	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	607:e98331f1d6b5	5728	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	607:e98331f1d6b5	5729
vcoubard	607:e98331f1d6b5	5730	/* Register: SPI_FREQUENCY */
vcoubard	607:e98331f1d6b5	5731	/* Description: SPI frequency */
vcoubard	607:e98331f1d6b5	5732
vcoubard	607:e98331f1d6b5	5733	/* Bits 31..0 : SPI data rate. */
vcoubard	607:e98331f1d6b5	5734	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	5735	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	5736	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
vcoubard	607:e98331f1d6b5	5737	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
vcoubard	607:e98331f1d6b5	5738	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
vcoubard	607:e98331f1d6b5	5739	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
vcoubard	607:e98331f1d6b5	5740	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
vcoubard	607:e98331f1d6b5	5741	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
vcoubard	607:e98331f1d6b5	5742	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
vcoubard	607:e98331f1d6b5	5743
vcoubard	607:e98331f1d6b5	5744	/* Register: SPI_CONFIG */
vcoubard	607:e98331f1d6b5	5745	/* Description: Configuration register. */
vcoubard	607:e98331f1d6b5	5746
vcoubard	607:e98331f1d6b5	5747	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	607:e98331f1d6b5	5748	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	607:e98331f1d6b5	5749	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	607:e98331f1d6b5	5750	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	607:e98331f1d6b5	5751	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	607:e98331f1d6b5	5752
vcoubard	607:e98331f1d6b5	5753	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	607:e98331f1d6b5	5754	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	607:e98331f1d6b5	5755	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	607:e98331f1d6b5	5756	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	607:e98331f1d6b5	5757	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	607:e98331f1d6b5	5758
vcoubard	607:e98331f1d6b5	5759	/* Bit 0 : Bit order. */
vcoubard	607:e98331f1d6b5	5760	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	607:e98331f1d6b5	5761	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	607:e98331f1d6b5	5762	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	607:e98331f1d6b5	5763	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	607:e98331f1d6b5	5764
vcoubard	607:e98331f1d6b5	5765	/* Register: SPI_POWER */
vcoubard	607:e98331f1d6b5	5766	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	5767
vcoubard	607:e98331f1d6b5	5768	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	5769	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	5770	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	5771	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	5772	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	5773
vcoubard	607:e98331f1d6b5	5774
vcoubard	607:e98331f1d6b5	5775	/* Peripheral: SPIM */
vcoubard	607:e98331f1d6b5	5776	/* Description: SPI master with easyDMA 1. */
vcoubard	607:e98331f1d6b5	5777
vcoubard	607:e98331f1d6b5	5778	/* Register: SPIM_INTENSET */
vcoubard	607:e98331f1d6b5	5779	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	5780
vcoubard	607:e98331f1d6b5	5781	/* Bit 19 : Enable interrupt on STARTED event. */
vcoubard	607:e98331f1d6b5	5782	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
vcoubard	607:e98331f1d6b5	5783	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
vcoubard	607:e98331f1d6b5	5784	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5785	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5786	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5787
vcoubard	607:e98331f1d6b5	5788	/* Bit 8 : Enable interrupt on ENDTX event. */
vcoubard	607:e98331f1d6b5	5789	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
vcoubard	607:e98331f1d6b5	5790	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
vcoubard	607:e98331f1d6b5	5791	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5792	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5793	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5794
vcoubard	607:e98331f1d6b5	5795	/* Bit 4 : Enable interrupt on ENDRX event. */
vcoubard	607:e98331f1d6b5	5796	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	607:e98331f1d6b5	5797	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	607:e98331f1d6b5	5798	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5799	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5800	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5801
vcoubard	607:e98331f1d6b5	5802	/* Bit 1 : Enable interrupt on STOPPED event. */
vcoubard	607:e98331f1d6b5	5803	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	607:e98331f1d6b5	5804	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	607:e98331f1d6b5	5805	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5806	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5807	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5808
vcoubard	607:e98331f1d6b5	5809	/* Register: SPIM_INTENCLR */
vcoubard	607:e98331f1d6b5	5810	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	5811
vcoubard	607:e98331f1d6b5	5812	/* Bit 19 : Disable interrupt on STARTED event. */
vcoubard	607:e98331f1d6b5	5813	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
vcoubard	607:e98331f1d6b5	5814	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
vcoubard	607:e98331f1d6b5	5815	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5816	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5817	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5818
vcoubard	607:e98331f1d6b5	5819	/* Bit 8 : Disable interrupt on ENDTX event. */
vcoubard	607:e98331f1d6b5	5820	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
vcoubard	607:e98331f1d6b5	5821	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
vcoubard	607:e98331f1d6b5	5822	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5823	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5824	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5825
vcoubard	607:e98331f1d6b5	5826	/* Bit 4 : Disable interrupt on ENDRX event. */
vcoubard	607:e98331f1d6b5	5827	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	607:e98331f1d6b5	5828	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	607:e98331f1d6b5	5829	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5830	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5831	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5832
vcoubard	607:e98331f1d6b5	5833	/* Bit 1 : Disable interrupt on STOPPED event. */
vcoubard	607:e98331f1d6b5	5834	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	607:e98331f1d6b5	5835	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	607:e98331f1d6b5	5836	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5837	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5838	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5839
vcoubard	607:e98331f1d6b5	5840	/* Register: SPIM_ENABLE */
vcoubard	607:e98331f1d6b5	5841	/* Description: Enable SPIM. */
vcoubard	607:e98331f1d6b5	5842
vcoubard	607:e98331f1d6b5	5843	/* Bits 3..0 : Enable or disable SPIM. */
vcoubard	607:e98331f1d6b5	5844	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	5845	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	5846	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
vcoubard	607:e98331f1d6b5	5847	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
vcoubard	607:e98331f1d6b5	5848
vcoubard	607:e98331f1d6b5	5849	/* Register: SPIM_FREQUENCY */
vcoubard	607:e98331f1d6b5	5850	/* Description: SPI frequency. */
vcoubard	607:e98331f1d6b5	5851
vcoubard	607:e98331f1d6b5	5852	/* Bits 31..0 : SPI master data rate. */
vcoubard	607:e98331f1d6b5	5853	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	5854	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	5855	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
vcoubard	607:e98331f1d6b5	5856	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
vcoubard	607:e98331f1d6b5	5857	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
vcoubard	607:e98331f1d6b5	5858	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
vcoubard	607:e98331f1d6b5	5859	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
vcoubard	607:e98331f1d6b5	5860	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
vcoubard	607:e98331f1d6b5	5861	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
vcoubard	607:e98331f1d6b5	5862
vcoubard	607:e98331f1d6b5	5863	/* Register: SPIM_RXD_PTR */
vcoubard	607:e98331f1d6b5	5864	/* Description: Data pointer. */
vcoubard	607:e98331f1d6b5	5865
vcoubard	607:e98331f1d6b5	5866	/* Bits 31..0 : Data pointer. */
vcoubard	607:e98331f1d6b5	5867	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
vcoubard	607:e98331f1d6b5	5868	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
vcoubard	607:e98331f1d6b5	5869
vcoubard	607:e98331f1d6b5	5870	/* Register: SPIM_RXD_MAXCNT */
vcoubard	607:e98331f1d6b5	5871	/* Description: Maximum number of buffer bytes to receive. */
vcoubard	607:e98331f1d6b5	5872
vcoubard	607:e98331f1d6b5	5873	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
vcoubard	607:e98331f1d6b5	5874	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
vcoubard	607:e98331f1d6b5	5875	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
vcoubard	607:e98331f1d6b5	5876
vcoubard	607:e98331f1d6b5	5877	/* Register: SPIM_RXD_AMOUNT */
vcoubard	607:e98331f1d6b5	5878	/* Description: Number of bytes received in the last transaction. */
vcoubard	607:e98331f1d6b5	5879
vcoubard	607:e98331f1d6b5	5880	/* Bits 7..0 : Number of bytes received in the last transaction. */
vcoubard	607:e98331f1d6b5	5881	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
vcoubard	607:e98331f1d6b5	5882	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
vcoubard	607:e98331f1d6b5	5883
vcoubard	607:e98331f1d6b5	5884	/* Register: SPIM_TXD_PTR */
vcoubard	607:e98331f1d6b5	5885	/* Description: Data pointer. */
vcoubard	607:e98331f1d6b5	5886
vcoubard	607:e98331f1d6b5	5887	/* Bits 31..0 : Data pointer. */
vcoubard	607:e98331f1d6b5	5888	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
vcoubard	607:e98331f1d6b5	5889	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
vcoubard	607:e98331f1d6b5	5890
vcoubard	607:e98331f1d6b5	5891	/* Register: SPIM_TXD_MAXCNT */
vcoubard	607:e98331f1d6b5	5892	/* Description: Maximum number of buffer bytes to send. */
vcoubard	607:e98331f1d6b5	5893
vcoubard	607:e98331f1d6b5	5894	/* Bits 7..0 : Maximum number of buffer bytes to send. */
vcoubard	607:e98331f1d6b5	5895	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
vcoubard	607:e98331f1d6b5	5896	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
vcoubard	607:e98331f1d6b5	5897
vcoubard	607:e98331f1d6b5	5898	/* Register: SPIM_TXD_AMOUNT */
vcoubard	607:e98331f1d6b5	5899	/* Description: Number of bytes sent in the last transaction. */
vcoubard	607:e98331f1d6b5	5900
vcoubard	607:e98331f1d6b5	5901	/* Bits 7..0 : Number of bytes sent in the last transaction. */
vcoubard	607:e98331f1d6b5	5902	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
vcoubard	607:e98331f1d6b5	5903	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
vcoubard	607:e98331f1d6b5	5904
vcoubard	607:e98331f1d6b5	5905	/* Register: SPIM_CONFIG */
vcoubard	607:e98331f1d6b5	5906	/* Description: Configuration register. */
vcoubard	607:e98331f1d6b5	5907
vcoubard	607:e98331f1d6b5	5908	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	607:e98331f1d6b5	5909	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	607:e98331f1d6b5	5910	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	607:e98331f1d6b5	5911	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	607:e98331f1d6b5	5912	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	607:e98331f1d6b5	5913
vcoubard	607:e98331f1d6b5	5914	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	607:e98331f1d6b5	5915	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	607:e98331f1d6b5	5916	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	607:e98331f1d6b5	5917	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	607:e98331f1d6b5	5918	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	607:e98331f1d6b5	5919
vcoubard	607:e98331f1d6b5	5920	/* Bit 0 : Bit order. */
vcoubard	607:e98331f1d6b5	5921	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	607:e98331f1d6b5	5922	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	607:e98331f1d6b5	5923	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	607:e98331f1d6b5	5924	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	607:e98331f1d6b5	5925
vcoubard	607:e98331f1d6b5	5926	/* Register: SPIM_ORC */
vcoubard	607:e98331f1d6b5	5927	/* Description: Over-read character. */
vcoubard	607:e98331f1d6b5	5928
vcoubard	607:e98331f1d6b5	5929	/* Bits 7..0 : Over-read character. */
vcoubard	607:e98331f1d6b5	5930	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
vcoubard	607:e98331f1d6b5	5931	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
vcoubard	607:e98331f1d6b5	5932
vcoubard	607:e98331f1d6b5	5933	/* Register: SPIM_POWER */
vcoubard	607:e98331f1d6b5	5934	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	5935
vcoubard	607:e98331f1d6b5	5936	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	5937	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	5938	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	5939	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	5940	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	5941
vcoubard	607:e98331f1d6b5	5942
vcoubard	607:e98331f1d6b5	5943	/* Peripheral: SPIS */
vcoubard	607:e98331f1d6b5	5944	/* Description: SPI slave 1. */
vcoubard	607:e98331f1d6b5	5945
vcoubard	607:e98331f1d6b5	5946	/* Register: SPIS_SHORTS */
vcoubard	607:e98331f1d6b5	5947	/* Description: Shortcuts for SPIS. */
vcoubard	607:e98331f1d6b5	5948
vcoubard	607:e98331f1d6b5	5949	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
vcoubard	607:e98331f1d6b5	5950	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
vcoubard	607:e98331f1d6b5	5951	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
vcoubard	607:e98331f1d6b5	5952	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	5953	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	5954
vcoubard	607:e98331f1d6b5	5955	/* Register: SPIS_INTENSET */
vcoubard	607:e98331f1d6b5	5956	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	5957
vcoubard	607:e98331f1d6b5	5958	/* Bit 10 : Enable interrupt on ACQUIRED event. */
vcoubard	607:e98331f1d6b5	5959	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
vcoubard	607:e98331f1d6b5	5960	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
vcoubard	607:e98331f1d6b5	5961	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5962	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5963	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5964
vcoubard	607:e98331f1d6b5	5965	/* Bit 4 : enable interrupt on ENDRX event. */
vcoubard	607:e98331f1d6b5	5966	#define SPIS_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	607:e98331f1d6b5	5967	#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	607:e98331f1d6b5	5968	#define SPIS_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5969	#define SPIS_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5970	#define SPIS_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5971
vcoubard	607:e98331f1d6b5	5972	/* Bit 1 : Enable interrupt on END event. */
vcoubard	607:e98331f1d6b5	5973	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	5974	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	5975	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5976	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5977	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	5978
vcoubard	607:e98331f1d6b5	5979	/* Register: SPIS_INTENCLR */
vcoubard	607:e98331f1d6b5	5980	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	5981
vcoubard	607:e98331f1d6b5	5982	/* Bit 10 : Disable interrupt on ACQUIRED event. */
vcoubard	607:e98331f1d6b5	5983	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
vcoubard	607:e98331f1d6b5	5984	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
vcoubard	607:e98331f1d6b5	5985	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5986	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5987	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5988
vcoubard	607:e98331f1d6b5	5989	/* Bit 4 : Disable interrupt on ENDRX event. */
vcoubard	607:e98331f1d6b5	5990	#define SPIS_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	607:e98331f1d6b5	5991	#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	607:e98331f1d6b5	5992	#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	5993	#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	5994	#define SPIS_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	5995
vcoubard	607:e98331f1d6b5	5996	/* Bit 1 : Disable interrupt on END event. */
vcoubard	607:e98331f1d6b5	5997	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
vcoubard	607:e98331f1d6b5	5998	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	607:e98331f1d6b5	5999	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6000	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6001	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6002
vcoubard	607:e98331f1d6b5	6003	/* Register: SPIS_SEMSTAT */
vcoubard	607:e98331f1d6b5	6004	/* Description: Semaphore status. */
vcoubard	607:e98331f1d6b5	6005
vcoubard	607:e98331f1d6b5	6006	/* Bits 1..0 : Semaphore status. */
vcoubard	607:e98331f1d6b5	6007	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
vcoubard	607:e98331f1d6b5	6008	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
vcoubard	607:e98331f1d6b5	6009	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
vcoubard	607:e98331f1d6b5	6010	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
vcoubard	607:e98331f1d6b5	6011	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
vcoubard	607:e98331f1d6b5	6012	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
vcoubard	607:e98331f1d6b5	6013
vcoubard	607:e98331f1d6b5	6014	/* Register: SPIS_STATUS */
vcoubard	607:e98331f1d6b5	6015	/* Description: Status from last transaction. */
vcoubard	607:e98331f1d6b5	6016
vcoubard	607:e98331f1d6b5	6017	/* Bit 1 : RX buffer overflow detected, and prevented. */
vcoubard	607:e98331f1d6b5	6018	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
vcoubard	607:e98331f1d6b5	6019	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
vcoubard	607:e98331f1d6b5	6020	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6021	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6022	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
vcoubard	607:e98331f1d6b5	6023
vcoubard	607:e98331f1d6b5	6024	/* Bit 0 : TX buffer overread detected, and prevented. */
vcoubard	607:e98331f1d6b5	6025	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
vcoubard	607:e98331f1d6b5	6026	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
vcoubard	607:e98331f1d6b5	6027	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6028	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6029	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
vcoubard	607:e98331f1d6b5	6030
vcoubard	607:e98331f1d6b5	6031	/* Register: SPIS_ENABLE */
vcoubard	607:e98331f1d6b5	6032	/* Description: Enable SPIS. */
vcoubard	607:e98331f1d6b5	6033
vcoubard	607:e98331f1d6b5	6034	/* Bits 2..0 : Enable or disable SPIS. */
vcoubard	607:e98331f1d6b5	6035	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	6036	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	6037	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
vcoubard	607:e98331f1d6b5	6038	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
vcoubard	607:e98331f1d6b5	6039
vcoubard	607:e98331f1d6b5	6040	/* Register: SPIS_MAXRX */
vcoubard	607:e98331f1d6b5	6041	/* Description: Maximum number of bytes in the receive buffer. */
vcoubard	607:e98331f1d6b5	6042
vcoubard	607:e98331f1d6b5	6043	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
vcoubard	607:e98331f1d6b5	6044	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
vcoubard	607:e98331f1d6b5	6045	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
vcoubard	607:e98331f1d6b5	6046
vcoubard	607:e98331f1d6b5	6047	/* Register: SPIS_AMOUNTRX */
vcoubard	607:e98331f1d6b5	6048	/* Description: Number of bytes received in last granted transaction. */
vcoubard	607:e98331f1d6b5	6049
vcoubard	607:e98331f1d6b5	6050	/* Bits 7..0 : Number of bytes received in last granted transaction. */
vcoubard	607:e98331f1d6b5	6051	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
vcoubard	607:e98331f1d6b5	6052	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
vcoubard	607:e98331f1d6b5	6053
vcoubard	607:e98331f1d6b5	6054	/* Register: SPIS_MAXTX */
vcoubard	607:e98331f1d6b5	6055	/* Description: Maximum number of bytes in the transmit buffer. */
vcoubard	607:e98331f1d6b5	6056
vcoubard	607:e98331f1d6b5	6057	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
vcoubard	607:e98331f1d6b5	6058	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
vcoubard	607:e98331f1d6b5	6059	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
vcoubard	607:e98331f1d6b5	6060
vcoubard	607:e98331f1d6b5	6061	/* Register: SPIS_AMOUNTTX */
vcoubard	607:e98331f1d6b5	6062	/* Description: Number of bytes transmitted in last granted transaction. */
vcoubard	607:e98331f1d6b5	6063
vcoubard	607:e98331f1d6b5	6064	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
vcoubard	607:e98331f1d6b5	6065	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
vcoubard	607:e98331f1d6b5	6066	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
vcoubard	607:e98331f1d6b5	6067
vcoubard	607:e98331f1d6b5	6068	/* Register: SPIS_CONFIG */
vcoubard	607:e98331f1d6b5	6069	/* Description: Configuration register. */
vcoubard	607:e98331f1d6b5	6070
vcoubard	607:e98331f1d6b5	6071	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	607:e98331f1d6b5	6072	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	607:e98331f1d6b5	6073	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	607:e98331f1d6b5	6074	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	607:e98331f1d6b5	6075	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	607:e98331f1d6b5	6076
vcoubard	607:e98331f1d6b5	6077	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	607:e98331f1d6b5	6078	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	607:e98331f1d6b5	6079	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	607:e98331f1d6b5	6080	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	607:e98331f1d6b5	6081	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	607:e98331f1d6b5	6082
vcoubard	607:e98331f1d6b5	6083	/* Bit 0 : Bit order. */
vcoubard	607:e98331f1d6b5	6084	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	607:e98331f1d6b5	6085	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	607:e98331f1d6b5	6086	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	607:e98331f1d6b5	6087	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	607:e98331f1d6b5	6088
vcoubard	607:e98331f1d6b5	6089	/* Register: SPIS_DEF */
vcoubard	607:e98331f1d6b5	6090	/* Description: Default character. */
vcoubard	607:e98331f1d6b5	6091
vcoubard	607:e98331f1d6b5	6092	/* Bits 7..0 : Default character. */
vcoubard	607:e98331f1d6b5	6093	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
vcoubard	607:e98331f1d6b5	6094	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
vcoubard	607:e98331f1d6b5	6095
vcoubard	607:e98331f1d6b5	6096	/* Register: SPIS_ORC */
vcoubard	607:e98331f1d6b5	6097	/* Description: Over-read character. */
vcoubard	607:e98331f1d6b5	6098
vcoubard	607:e98331f1d6b5	6099	/* Bits 7..0 : Over-read character. */
vcoubard	607:e98331f1d6b5	6100	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
vcoubard	607:e98331f1d6b5	6101	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
vcoubard	607:e98331f1d6b5	6102
vcoubard	607:e98331f1d6b5	6103	/* Register: SPIS_POWER */
vcoubard	607:e98331f1d6b5	6104	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	6105
vcoubard	607:e98331f1d6b5	6106	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	6107	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	6108	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	6109	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	6110	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	6111
vcoubard	607:e98331f1d6b5	6112
vcoubard	607:e98331f1d6b5	6113	/* Peripheral: TEMP */
vcoubard	607:e98331f1d6b5	6114	/* Description: Temperature Sensor. */
vcoubard	607:e98331f1d6b5	6115
vcoubard	607:e98331f1d6b5	6116	/* Register: TEMP_INTENSET */
vcoubard	607:e98331f1d6b5	6117	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	6118
vcoubard	607:e98331f1d6b5	6119	/* Bit 0 : Enable interrupt on DATARDY event. */
vcoubard	607:e98331f1d6b5	6120	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
vcoubard	607:e98331f1d6b5	6121	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
vcoubard	607:e98331f1d6b5	6122	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6123	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6124	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6125
vcoubard	607:e98331f1d6b5	6126	/* Register: TEMP_INTENCLR */
vcoubard	607:e98331f1d6b5	6127	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	6128
vcoubard	607:e98331f1d6b5	6129	/* Bit 0 : Disable interrupt on DATARDY event. */
vcoubard	607:e98331f1d6b5	6130	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
vcoubard	607:e98331f1d6b5	6131	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
vcoubard	607:e98331f1d6b5	6132	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6133	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6134	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6135
vcoubard	607:e98331f1d6b5	6136	/* Register: TEMP_POWER */
vcoubard	607:e98331f1d6b5	6137	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	6138
vcoubard	607:e98331f1d6b5	6139	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	6140	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	6141	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	6142	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	6143	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	6144
vcoubard	607:e98331f1d6b5	6145
vcoubard	607:e98331f1d6b5	6146	/* Peripheral: TIMER */
vcoubard	607:e98331f1d6b5	6147	/* Description: Timer 0. */
vcoubard	607:e98331f1d6b5	6148
vcoubard	607:e98331f1d6b5	6149	/* Register: TIMER_SHORTS */
vcoubard	607:e98331f1d6b5	6150	/* Description: Shortcuts for Timer. */
vcoubard	607:e98331f1d6b5	6151
vcoubard	607:e98331f1d6b5	6152	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
vcoubard	607:e98331f1d6b5	6153	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
vcoubard	607:e98331f1d6b5	6154	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
vcoubard	607:e98331f1d6b5	6155	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6156	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6157
vcoubard	607:e98331f1d6b5	6158	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
vcoubard	607:e98331f1d6b5	6159	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
vcoubard	607:e98331f1d6b5	6160	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
vcoubard	607:e98331f1d6b5	6161	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6162	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6163
vcoubard	607:e98331f1d6b5	6164	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
vcoubard	607:e98331f1d6b5	6165	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
vcoubard	607:e98331f1d6b5	6166	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
vcoubard	607:e98331f1d6b5	6167	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6168	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6169
vcoubard	607:e98331f1d6b5	6170	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
vcoubard	607:e98331f1d6b5	6171	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
vcoubard	607:e98331f1d6b5	6172	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
vcoubard	607:e98331f1d6b5	6173	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6174	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6175
vcoubard	607:e98331f1d6b5	6176	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
vcoubard	607:e98331f1d6b5	6177	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
vcoubard	607:e98331f1d6b5	6178	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
vcoubard	607:e98331f1d6b5	6179	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6180	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6181
vcoubard	607:e98331f1d6b5	6182	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
vcoubard	607:e98331f1d6b5	6183	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
vcoubard	607:e98331f1d6b5	6184	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
vcoubard	607:e98331f1d6b5	6185	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6186	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6187
vcoubard	607:e98331f1d6b5	6188	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
vcoubard	607:e98331f1d6b5	6189	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
vcoubard	607:e98331f1d6b5	6190	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
vcoubard	607:e98331f1d6b5	6191	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6192	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6193
vcoubard	607:e98331f1d6b5	6194	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
vcoubard	607:e98331f1d6b5	6195	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
vcoubard	607:e98331f1d6b5	6196	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
vcoubard	607:e98331f1d6b5	6197	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6198	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6199
vcoubard	607:e98331f1d6b5	6200	/* Register: TIMER_INTENSET */
vcoubard	607:e98331f1d6b5	6201	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	6202
vcoubard	607:e98331f1d6b5	6203	/* Bit 19 : Enable interrupt on COMPARE[3] */
vcoubard	607:e98331f1d6b5	6204	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	6205	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	6206	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6207	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6208	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6209
vcoubard	607:e98331f1d6b5	6210	/* Bit 18 : Enable interrupt on COMPARE[2] */
vcoubard	607:e98331f1d6b5	6211	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	6212	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	6213	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6214	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6215	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6216
vcoubard	607:e98331f1d6b5	6217	/* Bit 17 : Enable interrupt on COMPARE[1] */
vcoubard	607:e98331f1d6b5	6218	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	6219	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	6220	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6221	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6222	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6223
vcoubard	607:e98331f1d6b5	6224	/* Bit 16 : Enable interrupt on COMPARE[0] */
vcoubard	607:e98331f1d6b5	6225	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	6226	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	6227	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6228	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6229	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6230
vcoubard	607:e98331f1d6b5	6231	/* Register: TIMER_INTENCLR */
vcoubard	607:e98331f1d6b5	6232	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	6233
vcoubard	607:e98331f1d6b5	6234	/* Bit 19 : Disable interrupt on COMPARE[3] */
vcoubard	607:e98331f1d6b5	6235	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	6236	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	607:e98331f1d6b5	6237	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6238	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6239	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6240
vcoubard	607:e98331f1d6b5	6241	/* Bit 18 : Disable interrupt on COMPARE[2] */
vcoubard	607:e98331f1d6b5	6242	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	6243	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	607:e98331f1d6b5	6244	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6245	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6246	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6247
vcoubard	607:e98331f1d6b5	6248	/* Bit 17 : Disable interrupt on COMPARE[1] */
vcoubard	607:e98331f1d6b5	6249	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	6250	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	607:e98331f1d6b5	6251	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6252	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6253	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6254
vcoubard	607:e98331f1d6b5	6255	/* Bit 16 : Disable interrupt on COMPARE[0] */
vcoubard	607:e98331f1d6b5	6256	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	6257	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	607:e98331f1d6b5	6258	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6259	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6260	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6261
vcoubard	607:e98331f1d6b5	6262	/* Register: TIMER_MODE */
vcoubard	607:e98331f1d6b5	6263	/* Description: Timer Mode selection. */
vcoubard	607:e98331f1d6b5	6264
vcoubard	607:e98331f1d6b5	6265	/* Bit 0 : Select Normal or Counter mode. */
vcoubard	607:e98331f1d6b5	6266	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	607:e98331f1d6b5	6267	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	607:e98331f1d6b5	6268	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
vcoubard	607:e98331f1d6b5	6269	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
vcoubard	607:e98331f1d6b5	6270
vcoubard	607:e98331f1d6b5	6271	/* Register: TIMER_BITMODE */
vcoubard	607:e98331f1d6b5	6272	/* Description: Sets timer behaviour. */
vcoubard	607:e98331f1d6b5	6273
vcoubard	607:e98331f1d6b5	6274	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
vcoubard	607:e98331f1d6b5	6275	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
vcoubard	607:e98331f1d6b5	6276	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
vcoubard	607:e98331f1d6b5	6277	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
vcoubard	607:e98331f1d6b5	6278	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
vcoubard	607:e98331f1d6b5	6279	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
vcoubard	607:e98331f1d6b5	6280	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
vcoubard	607:e98331f1d6b5	6281
vcoubard	607:e98331f1d6b5	6282	/* Register: TIMER_PRESCALER */
vcoubard	607:e98331f1d6b5	6283	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
vcoubard	607:e98331f1d6b5	6284
vcoubard	607:e98331f1d6b5	6285	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
vcoubard	607:e98331f1d6b5	6286	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
vcoubard	607:e98331f1d6b5	6287	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
vcoubard	607:e98331f1d6b5	6288
vcoubard	607:e98331f1d6b5	6289	/* Register: TIMER_POWER */
vcoubard	607:e98331f1d6b5	6290	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	6291
vcoubard	607:e98331f1d6b5	6292	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	6293	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	6294	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	6295	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	6296	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	6297
vcoubard	607:e98331f1d6b5	6298
vcoubard	607:e98331f1d6b5	6299	/* Peripheral: TWI */
vcoubard	607:e98331f1d6b5	6300	/* Description: Two-wire interface master 0. */
vcoubard	607:e98331f1d6b5	6301
vcoubard	607:e98331f1d6b5	6302	/* Register: TWI_SHORTS */
vcoubard	607:e98331f1d6b5	6303	/* Description: Shortcuts for TWI. */
vcoubard	607:e98331f1d6b5	6304
vcoubard	607:e98331f1d6b5	6305	/* Bit 1 : Shortcut between BB event and the STOP task. */
vcoubard	607:e98331f1d6b5	6306	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
vcoubard	607:e98331f1d6b5	6307	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
vcoubard	607:e98331f1d6b5	6308	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6309	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6310
vcoubard	607:e98331f1d6b5	6311	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
vcoubard	607:e98331f1d6b5	6312	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
vcoubard	607:e98331f1d6b5	6313	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
vcoubard	607:e98331f1d6b5	6314	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6315	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6316
vcoubard	607:e98331f1d6b5	6317	/* Register: TWI_INTENSET */
vcoubard	607:e98331f1d6b5	6318	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	6319
vcoubard	607:e98331f1d6b5	6320	/* Bit 18 : Enable interrupt on SUSPENDED event. */
vcoubard	607:e98331f1d6b5	6321	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
vcoubard	607:e98331f1d6b5	6322	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
vcoubard	607:e98331f1d6b5	6323	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6324	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6325	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6326
vcoubard	607:e98331f1d6b5	6327	/* Bit 14 : Enable interrupt on BB event. */
vcoubard	607:e98331f1d6b5	6328	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
vcoubard	607:e98331f1d6b5	6329	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
vcoubard	607:e98331f1d6b5	6330	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6331	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6332	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6333
vcoubard	607:e98331f1d6b5	6334	/* Bit 9 : Enable interrupt on ERROR event. */
vcoubard	607:e98331f1d6b5	6335	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	607:e98331f1d6b5	6336	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	607:e98331f1d6b5	6337	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6338	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6339	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6340
vcoubard	607:e98331f1d6b5	6341	/* Bit 7 : Enable interrupt on TXDSENT event. */
vcoubard	607:e98331f1d6b5	6342	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
vcoubard	607:e98331f1d6b5	6343	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
vcoubard	607:e98331f1d6b5	6344	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6345	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6346	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6347
vcoubard	607:e98331f1d6b5	6348	/* Bit 2 : Enable interrupt on READY event. */
vcoubard	607:e98331f1d6b5	6349	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
vcoubard	607:e98331f1d6b5	6350	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
vcoubard	607:e98331f1d6b5	6351	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6352	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6353	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6354
vcoubard	607:e98331f1d6b5	6355	/* Bit 1 : Enable interrupt on STOPPED event. */
vcoubard	607:e98331f1d6b5	6356	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	607:e98331f1d6b5	6357	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	607:e98331f1d6b5	6358	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6359	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6360	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6361
vcoubard	607:e98331f1d6b5	6362	/* Register: TWI_INTENCLR */
vcoubard	607:e98331f1d6b5	6363	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	6364
vcoubard	607:e98331f1d6b5	6365	/* Bit 18 : Disable interrupt on SUSPENDED event. */
vcoubard	607:e98331f1d6b5	6366	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
vcoubard	607:e98331f1d6b5	6367	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
vcoubard	607:e98331f1d6b5	6368	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6369	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6370	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6371
vcoubard	607:e98331f1d6b5	6372	/* Bit 14 : Disable interrupt on BB event. */
vcoubard	607:e98331f1d6b5	6373	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
vcoubard	607:e98331f1d6b5	6374	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
vcoubard	607:e98331f1d6b5	6375	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6376	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6377	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6378
vcoubard	607:e98331f1d6b5	6379	/* Bit 9 : Disable interrupt on ERROR event. */
vcoubard	607:e98331f1d6b5	6380	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	607:e98331f1d6b5	6381	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	607:e98331f1d6b5	6382	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6383	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6384	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6385
vcoubard	607:e98331f1d6b5	6386	/* Bit 7 : Disable interrupt on TXDSENT event. */
vcoubard	607:e98331f1d6b5	6387	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
vcoubard	607:e98331f1d6b5	6388	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
vcoubard	607:e98331f1d6b5	6389	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6390	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6391	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6392
vcoubard	607:e98331f1d6b5	6393	/* Bit 2 : Disable interrupt on RXDREADY event. */
vcoubard	607:e98331f1d6b5	6394	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
vcoubard	607:e98331f1d6b5	6395	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
vcoubard	607:e98331f1d6b5	6396	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6397	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6398	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6399
vcoubard	607:e98331f1d6b5	6400	/* Bit 1 : Disable interrupt on STOPPED event. */
vcoubard	607:e98331f1d6b5	6401	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	607:e98331f1d6b5	6402	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	607:e98331f1d6b5	6403	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6404	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6405	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6406
vcoubard	607:e98331f1d6b5	6407	/* Register: TWI_ERRORSRC */
vcoubard	607:e98331f1d6b5	6408	/* Description: Two-wire error source. Write error field to 1 to clear error. */
vcoubard	607:e98331f1d6b5	6409
vcoubard	607:e98331f1d6b5	6410	/* Bit 2 : NACK received after sending a data byte. */
vcoubard	607:e98331f1d6b5	6411	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
vcoubard	607:e98331f1d6b5	6412	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
vcoubard	607:e98331f1d6b5	6413	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6414	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6415	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
vcoubard	607:e98331f1d6b5	6416
vcoubard	607:e98331f1d6b5	6417	/* Bit 1 : NACK received after sending the address. */
vcoubard	607:e98331f1d6b5	6418	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
vcoubard	607:e98331f1d6b5	6419	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
vcoubard	607:e98331f1d6b5	6420	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6421	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6422	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
vcoubard	607:e98331f1d6b5	6423
vcoubard	607:e98331f1d6b5	6424	/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
vcoubard	607:e98331f1d6b5	6425	#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
vcoubard	607:e98331f1d6b5	6426	#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
vcoubard	607:e98331f1d6b5	6427	#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6428	#define TWI_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6429	#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
vcoubard	607:e98331f1d6b5	6430
vcoubard	607:e98331f1d6b5	6431	/* Register: TWI_ENABLE */
vcoubard	607:e98331f1d6b5	6432	/* Description: Enable two-wire master. */
vcoubard	607:e98331f1d6b5	6433
vcoubard	607:e98331f1d6b5	6434	/* Bits 2..0 : Enable or disable W2M */
vcoubard	607:e98331f1d6b5	6435	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	6436	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	6437	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	6438	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	6439
vcoubard	607:e98331f1d6b5	6440	/* Register: TWI_RXD */
vcoubard	607:e98331f1d6b5	6441	/* Description: RX data register. */
vcoubard	607:e98331f1d6b5	6442
vcoubard	607:e98331f1d6b5	6443	/* Bits 7..0 : RX data from last transfer. */
vcoubard	607:e98331f1d6b5	6444	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	607:e98331f1d6b5	6445	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	607:e98331f1d6b5	6446
vcoubard	607:e98331f1d6b5	6447	/* Register: TWI_TXD */
vcoubard	607:e98331f1d6b5	6448	/* Description: TX data register. */
vcoubard	607:e98331f1d6b5	6449
vcoubard	607:e98331f1d6b5	6450	/* Bits 7..0 : TX data for next transfer. */
vcoubard	607:e98331f1d6b5	6451	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	607:e98331f1d6b5	6452	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	607:e98331f1d6b5	6453
vcoubard	607:e98331f1d6b5	6454	/* Register: TWI_FREQUENCY */
vcoubard	607:e98331f1d6b5	6455	/* Description: Two-wire frequency. */
vcoubard	607:e98331f1d6b5	6456
vcoubard	607:e98331f1d6b5	6457	/* Bits 31..0 : Two-wire master clock frequency. */
vcoubard	607:e98331f1d6b5	6458	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	6459	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	607:e98331f1d6b5	6460	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
vcoubard	607:e98331f1d6b5	6461	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
vcoubard	607:e98331f1d6b5	6462	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
vcoubard	607:e98331f1d6b5	6463
vcoubard	607:e98331f1d6b5	6464	/* Register: TWI_ADDRESS */
vcoubard	607:e98331f1d6b5	6465	/* Description: Address used in the two-wire transfer. */
vcoubard	607:e98331f1d6b5	6466
vcoubard	607:e98331f1d6b5	6467	/* Bits 6..0 : Two-wire address. */
vcoubard	607:e98331f1d6b5	6468	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
vcoubard	607:e98331f1d6b5	6469	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	607:e98331f1d6b5	6470
vcoubard	607:e98331f1d6b5	6471	/* Register: TWI_POWER */
vcoubard	607:e98331f1d6b5	6472	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	6473
vcoubard	607:e98331f1d6b5	6474	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	6475	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	6476	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	6477	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	6478	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	6479
vcoubard	607:e98331f1d6b5	6480
vcoubard	607:e98331f1d6b5	6481	/* Peripheral: UART */
vcoubard	607:e98331f1d6b5	6482	/* Description: Universal Asynchronous Receiver/Transmitter. */
vcoubard	607:e98331f1d6b5	6483
vcoubard	607:e98331f1d6b5	6484	/* Register: UART_SHORTS */
vcoubard	607:e98331f1d6b5	6485	/* Description: Shortcuts for UART. */
vcoubard	607:e98331f1d6b5	6486
vcoubard	607:e98331f1d6b5	6487	/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
vcoubard	607:e98331f1d6b5	6488	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
vcoubard	607:e98331f1d6b5	6489	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
vcoubard	607:e98331f1d6b5	6490	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6491	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6492
vcoubard	607:e98331f1d6b5	6493	/* Bit 3 : Shortcut between CTS event and STARTRX task. */
vcoubard	607:e98331f1d6b5	6494	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
vcoubard	607:e98331f1d6b5	6495	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
vcoubard	607:e98331f1d6b5	6496	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	607:e98331f1d6b5	6497	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	607:e98331f1d6b5	6498
vcoubard	607:e98331f1d6b5	6499	/* Register: UART_INTENSET */
vcoubard	607:e98331f1d6b5	6500	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	6501
vcoubard	607:e98331f1d6b5	6502	/* Bit 17 : Enable interrupt on RXTO event. */
vcoubard	607:e98331f1d6b5	6503	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
vcoubard	607:e98331f1d6b5	6504	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
vcoubard	607:e98331f1d6b5	6505	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6506	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6507	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6508
vcoubard	607:e98331f1d6b5	6509	/* Bit 9 : Enable interrupt on ERROR event. */
vcoubard	607:e98331f1d6b5	6510	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	607:e98331f1d6b5	6511	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	607:e98331f1d6b5	6512	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6513	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6514	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6515
vcoubard	607:e98331f1d6b5	6516	/* Bit 7 : Enable interrupt on TXRDY event. */
vcoubard	607:e98331f1d6b5	6517	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
vcoubard	607:e98331f1d6b5	6518	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
vcoubard	607:e98331f1d6b5	6519	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6520	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6521	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6522
vcoubard	607:e98331f1d6b5	6523	/* Bit 2 : Enable interrupt on RXRDY event. */
vcoubard	607:e98331f1d6b5	6524	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
vcoubard	607:e98331f1d6b5	6525	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
vcoubard	607:e98331f1d6b5	6526	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6527	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6528	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6529
vcoubard	607:e98331f1d6b5	6530	/* Bit 1 : Enable interrupt on NCTS event. */
vcoubard	607:e98331f1d6b5	6531	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
vcoubard	607:e98331f1d6b5	6532	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
vcoubard	607:e98331f1d6b5	6533	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6534	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6535	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6536
vcoubard	607:e98331f1d6b5	6537	/* Bit 0 : Enable interrupt on CTS event. */
vcoubard	607:e98331f1d6b5	6538	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
vcoubard	607:e98331f1d6b5	6539	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
vcoubard	607:e98331f1d6b5	6540	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6541	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6542	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6543
vcoubard	607:e98331f1d6b5	6544	/* Register: UART_INTENCLR */
vcoubard	607:e98331f1d6b5	6545	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	6546
vcoubard	607:e98331f1d6b5	6547	/* Bit 17 : Disable interrupt on RXTO event. */
vcoubard	607:e98331f1d6b5	6548	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
vcoubard	607:e98331f1d6b5	6549	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
vcoubard	607:e98331f1d6b5	6550	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6551	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6552	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6553
vcoubard	607:e98331f1d6b5	6554	/* Bit 9 : Disable interrupt on ERROR event. */
vcoubard	607:e98331f1d6b5	6555	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	607:e98331f1d6b5	6556	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	607:e98331f1d6b5	6557	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6558	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6559	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6560
vcoubard	607:e98331f1d6b5	6561	/* Bit 7 : Disable interrupt on TXRDY event. */
vcoubard	607:e98331f1d6b5	6562	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
vcoubard	607:e98331f1d6b5	6563	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
vcoubard	607:e98331f1d6b5	6564	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6565	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6566	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6567
vcoubard	607:e98331f1d6b5	6568	/* Bit 2 : Disable interrupt on RXRDY event. */
vcoubard	607:e98331f1d6b5	6569	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
vcoubard	607:e98331f1d6b5	6570	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
vcoubard	607:e98331f1d6b5	6571	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6572	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6573	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6574
vcoubard	607:e98331f1d6b5	6575	/* Bit 1 : Disable interrupt on NCTS event. */
vcoubard	607:e98331f1d6b5	6576	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
vcoubard	607:e98331f1d6b5	6577	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
vcoubard	607:e98331f1d6b5	6578	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6579	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6580	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6581
vcoubard	607:e98331f1d6b5	6582	/* Bit 0 : Disable interrupt on CTS event. */
vcoubard	607:e98331f1d6b5	6583	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
vcoubard	607:e98331f1d6b5	6584	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
vcoubard	607:e98331f1d6b5	6585	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6586	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6587	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6588
vcoubard	607:e98331f1d6b5	6589	/* Register: UART_ERRORSRC */
vcoubard	607:e98331f1d6b5	6590	/* Description: Error source. Write error field to 1 to clear error. */
vcoubard	607:e98331f1d6b5	6591
vcoubard	607:e98331f1d6b5	6592	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
vcoubard	607:e98331f1d6b5	6593	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
vcoubard	607:e98331f1d6b5	6594	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
vcoubard	607:e98331f1d6b5	6595	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6596	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6597	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
vcoubard	607:e98331f1d6b5	6598
vcoubard	607:e98331f1d6b5	6599	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
vcoubard	607:e98331f1d6b5	6600	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
vcoubard	607:e98331f1d6b5	6601	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
vcoubard	607:e98331f1d6b5	6602	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6603	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6604	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
vcoubard	607:e98331f1d6b5	6605
vcoubard	607:e98331f1d6b5	6606	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
vcoubard	607:e98331f1d6b5	6607	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
vcoubard	607:e98331f1d6b5	6608	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
vcoubard	607:e98331f1d6b5	6609	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6610	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6611	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
vcoubard	607:e98331f1d6b5	6612
vcoubard	607:e98331f1d6b5	6613	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
vcoubard	607:e98331f1d6b5	6614	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
vcoubard	607:e98331f1d6b5	6615	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
vcoubard	607:e98331f1d6b5	6616	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
vcoubard	607:e98331f1d6b5	6617	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
vcoubard	607:e98331f1d6b5	6618	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
vcoubard	607:e98331f1d6b5	6619
vcoubard	607:e98331f1d6b5	6620	/* Register: UART_ENABLE */
vcoubard	607:e98331f1d6b5	6621	/* Description: Enable UART and acquire IOs. */
vcoubard	607:e98331f1d6b5	6622
vcoubard	607:e98331f1d6b5	6623	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
vcoubard	607:e98331f1d6b5	6624	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	607:e98331f1d6b5	6625	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	607:e98331f1d6b5	6626	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
vcoubard	607:e98331f1d6b5	6627	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
vcoubard	607:e98331f1d6b5	6628
vcoubard	607:e98331f1d6b5	6629	/* Register: UART_RXD */
vcoubard	607:e98331f1d6b5	6630	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
vcoubard	607:e98331f1d6b5	6631
vcoubard	607:e98331f1d6b5	6632	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
vcoubard	607:e98331f1d6b5	6633	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	607:e98331f1d6b5	6634	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	607:e98331f1d6b5	6635
vcoubard	607:e98331f1d6b5	6636	/* Register: UART_TXD */
vcoubard	607:e98331f1d6b5	6637	/* Description: TXD register. */
vcoubard	607:e98331f1d6b5	6638
vcoubard	607:e98331f1d6b5	6639	/* Bits 7..0 : TX data for transfer. */
vcoubard	607:e98331f1d6b5	6640	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	607:e98331f1d6b5	6641	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	607:e98331f1d6b5	6642
vcoubard	607:e98331f1d6b5	6643	/* Register: UART_BAUDRATE */
vcoubard	607:e98331f1d6b5	6644	/* Description: UART Baudrate. */
vcoubard	607:e98331f1d6b5	6645
vcoubard	607:e98331f1d6b5	6646	/* Bits 31..0 : UART baudrate. */
vcoubard	607:e98331f1d6b5	6647	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
vcoubard	607:e98331f1d6b5	6648	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
vcoubard	607:e98331f1d6b5	6649	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
vcoubard	607:e98331f1d6b5	6650	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
vcoubard	607:e98331f1d6b5	6651	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
vcoubard	607:e98331f1d6b5	6652	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
vcoubard	607:e98331f1d6b5	6653	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
vcoubard	607:e98331f1d6b5	6654	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
vcoubard	607:e98331f1d6b5	6655	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
vcoubard	607:e98331f1d6b5	6656	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
vcoubard	607:e98331f1d6b5	6657	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
vcoubard	607:e98331f1d6b5	6658	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
vcoubard	607:e98331f1d6b5	6659	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
vcoubard	607:e98331f1d6b5	6660	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
vcoubard	607:e98331f1d6b5	6661	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
vcoubard	607:e98331f1d6b5	6662	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
vcoubard	607:e98331f1d6b5	6663	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /!< 921600 baud. /
vcoubard	607:e98331f1d6b5	6664	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
vcoubard	607:e98331f1d6b5	6665
vcoubard	607:e98331f1d6b5	6666	/* Register: UART_CONFIG */
vcoubard	607:e98331f1d6b5	6667	/* Description: Configuration of parity and hardware flow control register. */
vcoubard	607:e98331f1d6b5	6668
vcoubard	607:e98331f1d6b5	6669	/* Bits 3..1 : Include parity bit. */
vcoubard	607:e98331f1d6b5	6670	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
vcoubard	607:e98331f1d6b5	6671	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
vcoubard	607:e98331f1d6b5	6672	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
vcoubard	607:e98331f1d6b5	6673	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
vcoubard	607:e98331f1d6b5	6674
vcoubard	607:e98331f1d6b5	6675	/* Bit 0 : Hardware flow control. */
vcoubard	607:e98331f1d6b5	6676	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
vcoubard	607:e98331f1d6b5	6677	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
vcoubard	607:e98331f1d6b5	6678	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
vcoubard	607:e98331f1d6b5	6679	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
vcoubard	607:e98331f1d6b5	6680
vcoubard	607:e98331f1d6b5	6681	/* Register: UART_POWER */
vcoubard	607:e98331f1d6b5	6682	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	6683
vcoubard	607:e98331f1d6b5	6684	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	6685	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	6686	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	6687	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	6688	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	6689
vcoubard	607:e98331f1d6b5	6690
vcoubard	607:e98331f1d6b5	6691	/* Peripheral: UICR */
vcoubard	607:e98331f1d6b5	6692	/* Description: User Information Configuration. */
vcoubard	607:e98331f1d6b5	6693
vcoubard	607:e98331f1d6b5	6694	/* Register: UICR_RBPCONF */
vcoubard	607:e98331f1d6b5	6695	/* Description: Readback protection configuration. */
vcoubard	607:e98331f1d6b5	6696
vcoubard	607:e98331f1d6b5	6697	/* Bits 15..8 : Readback protect all code in the device. */
vcoubard	607:e98331f1d6b5	6698	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
vcoubard	607:e98331f1d6b5	6699	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
vcoubard	607:e98331f1d6b5	6700	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	6701	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	6702
vcoubard	607:e98331f1d6b5	6703	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
vcoubard	607:e98331f1d6b5	6704	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
vcoubard	607:e98331f1d6b5	6705	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
vcoubard	607:e98331f1d6b5	6706	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
vcoubard	607:e98331f1d6b5	6707	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
vcoubard	607:e98331f1d6b5	6708
vcoubard	607:e98331f1d6b5	6709	/* Register: UICR_XTALFREQ */
vcoubard	607:e98331f1d6b5	6710	/* Description: Reset value for CLOCK XTALFREQ register. */
vcoubard	607:e98331f1d6b5	6711
vcoubard	607:e98331f1d6b5	6712	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
vcoubard	607:e98331f1d6b5	6713	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
vcoubard	607:e98331f1d6b5	6714	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
vcoubard	607:e98331f1d6b5	6715	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
vcoubard	607:e98331f1d6b5	6716	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
vcoubard	607:e98331f1d6b5	6717
vcoubard	607:e98331f1d6b5	6718	/* Register: UICR_FWID */
vcoubard	607:e98331f1d6b5	6719	/* Description: Firmware ID. */
vcoubard	607:e98331f1d6b5	6720
vcoubard	607:e98331f1d6b5	6721	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
vcoubard	607:e98331f1d6b5	6722	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
vcoubard	607:e98331f1d6b5	6723	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
vcoubard	607:e98331f1d6b5	6724
vcoubard	607:e98331f1d6b5	6725
vcoubard	607:e98331f1d6b5	6726	/* Peripheral: WDT */
vcoubard	607:e98331f1d6b5	6727	/* Description: Watchdog Timer. */
vcoubard	607:e98331f1d6b5	6728
vcoubard	607:e98331f1d6b5	6729	/* Register: WDT_INTENSET */
vcoubard	607:e98331f1d6b5	6730	/* Description: Interrupt enable set register. */
vcoubard	607:e98331f1d6b5	6731
vcoubard	607:e98331f1d6b5	6732	/* Bit 0 : Enable interrupt on TIMEOUT event. */
vcoubard	607:e98331f1d6b5	6733	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
vcoubard	607:e98331f1d6b5	6734	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
vcoubard	607:e98331f1d6b5	6735	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6736	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6737	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	607:e98331f1d6b5	6738
vcoubard	607:e98331f1d6b5	6739	/* Register: WDT_INTENCLR */
vcoubard	607:e98331f1d6b5	6740	/* Description: Interrupt enable clear register. */
vcoubard	607:e98331f1d6b5	6741
vcoubard	607:e98331f1d6b5	6742	/* Bit 0 : Disable interrupt on TIMEOUT event. */
vcoubard	607:e98331f1d6b5	6743	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
vcoubard	607:e98331f1d6b5	6744	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
vcoubard	607:e98331f1d6b5	6745	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	607:e98331f1d6b5	6746	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	607:e98331f1d6b5	6747	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	607:e98331f1d6b5	6748
vcoubard	607:e98331f1d6b5	6749	/* Register: WDT_RUNSTATUS */
vcoubard	607:e98331f1d6b5	6750	/* Description: Watchdog running status. */
vcoubard	607:e98331f1d6b5	6751
vcoubard	607:e98331f1d6b5	6752	/* Bit 0 : Watchdog running status. */
vcoubard	607:e98331f1d6b5	6753	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
vcoubard	607:e98331f1d6b5	6754	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
vcoubard	607:e98331f1d6b5	6755	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
vcoubard	607:e98331f1d6b5	6756	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
vcoubard	607:e98331f1d6b5	6757
vcoubard	607:e98331f1d6b5	6758	/* Register: WDT_REQSTATUS */
vcoubard	607:e98331f1d6b5	6759	/* Description: Request status. */
vcoubard	607:e98331f1d6b5	6760
vcoubard	607:e98331f1d6b5	6761	/* Bit 7 : Request status for RR[7]. */
vcoubard	607:e98331f1d6b5	6762	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
vcoubard	607:e98331f1d6b5	6763	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
vcoubard	607:e98331f1d6b5	6764	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6765	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6766
vcoubard	607:e98331f1d6b5	6767	/* Bit 6 : Request status for RR[6]. */
vcoubard	607:e98331f1d6b5	6768	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
vcoubard	607:e98331f1d6b5	6769	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
vcoubard	607:e98331f1d6b5	6770	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6771	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6772
vcoubard	607:e98331f1d6b5	6773	/* Bit 5 : Request status for RR[5]. */
vcoubard	607:e98331f1d6b5	6774	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
vcoubard	607:e98331f1d6b5	6775	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
vcoubard	607:e98331f1d6b5	6776	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6777	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6778
vcoubard	607:e98331f1d6b5	6779	/* Bit 4 : Request status for RR[4]. */
vcoubard	607:e98331f1d6b5	6780	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
vcoubard	607:e98331f1d6b5	6781	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
vcoubard	607:e98331f1d6b5	6782	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6783	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6784
vcoubard	607:e98331f1d6b5	6785	/* Bit 3 : Request status for RR[3]. */
vcoubard	607:e98331f1d6b5	6786	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
vcoubard	607:e98331f1d6b5	6787	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
vcoubard	607:e98331f1d6b5	6788	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6789	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6790
vcoubard	607:e98331f1d6b5	6791	/* Bit 2 : Request status for RR[2]. */
vcoubard	607:e98331f1d6b5	6792	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
vcoubard	607:e98331f1d6b5	6793	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
vcoubard	607:e98331f1d6b5	6794	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6795	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6796
vcoubard	607:e98331f1d6b5	6797	/* Bit 1 : Request status for RR[1]. */
vcoubard	607:e98331f1d6b5	6798	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
vcoubard	607:e98331f1d6b5	6799	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
vcoubard	607:e98331f1d6b5	6800	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6801	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6802
vcoubard	607:e98331f1d6b5	6803	/* Bit 0 : Request status for RR[0]. */
vcoubard	607:e98331f1d6b5	6804	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
vcoubard	607:e98331f1d6b5	6805	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
vcoubard	607:e98331f1d6b5	6806	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
vcoubard	607:e98331f1d6b5	6807	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
vcoubard	607:e98331f1d6b5	6808
vcoubard	607:e98331f1d6b5	6809	/* Register: WDT_RREN */
vcoubard	607:e98331f1d6b5	6810	/* Description: Reload request enable. */
vcoubard	607:e98331f1d6b5	6811
vcoubard	607:e98331f1d6b5	6812	/* Bit 7 : Enable or disable RR[7] register. */
vcoubard	607:e98331f1d6b5	6813	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
vcoubard	607:e98331f1d6b5	6814	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
vcoubard	607:e98331f1d6b5	6815	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
vcoubard	607:e98331f1d6b5	6816	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
vcoubard	607:e98331f1d6b5	6817
vcoubard	607:e98331f1d6b5	6818	/* Bit 6 : Enable or disable RR[6] register. */
vcoubard	607:e98331f1d6b5	6819	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
vcoubard	607:e98331f1d6b5	6820	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
vcoubard	607:e98331f1d6b5	6821	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
vcoubard	607:e98331f1d6b5	6822	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
vcoubard	607:e98331f1d6b5	6823
vcoubard	607:e98331f1d6b5	6824	/* Bit 5 : Enable or disable RR[5] register. */
vcoubard	607:e98331f1d6b5	6825	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
vcoubard	607:e98331f1d6b5	6826	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
vcoubard	607:e98331f1d6b5	6827	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
vcoubard	607:e98331f1d6b5	6828	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
vcoubard	607:e98331f1d6b5	6829
vcoubard	607:e98331f1d6b5	6830	/* Bit 4 : Enable or disable RR[4] register. */
vcoubard	607:e98331f1d6b5	6831	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
vcoubard	607:e98331f1d6b5	6832	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
vcoubard	607:e98331f1d6b5	6833	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
vcoubard	607:e98331f1d6b5	6834	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
vcoubard	607:e98331f1d6b5	6835
vcoubard	607:e98331f1d6b5	6836	/* Bit 3 : Enable or disable RR[3] register. */
vcoubard	607:e98331f1d6b5	6837	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
vcoubard	607:e98331f1d6b5	6838	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
vcoubard	607:e98331f1d6b5	6839	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
vcoubard	607:e98331f1d6b5	6840	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
vcoubard	607:e98331f1d6b5	6841
vcoubard	607:e98331f1d6b5	6842	/* Bit 2 : Enable or disable RR[2] register. */
vcoubard	607:e98331f1d6b5	6843	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
vcoubard	607:e98331f1d6b5	6844	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
vcoubard	607:e98331f1d6b5	6845	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
vcoubard	607:e98331f1d6b5	6846	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
vcoubard	607:e98331f1d6b5	6847
vcoubard	607:e98331f1d6b5	6848	/* Bit 1 : Enable or disable RR[1] register. */
vcoubard	607:e98331f1d6b5	6849	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
vcoubard	607:e98331f1d6b5	6850	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
vcoubard	607:e98331f1d6b5	6851	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
vcoubard	607:e98331f1d6b5	6852	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
vcoubard	607:e98331f1d6b5	6853
vcoubard	607:e98331f1d6b5	6854	/* Bit 0 : Enable or disable RR[0] register. */
vcoubard	607:e98331f1d6b5	6855	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
vcoubard	607:e98331f1d6b5	6856	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
vcoubard	607:e98331f1d6b5	6857	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
vcoubard	607:e98331f1d6b5	6858	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
vcoubard	607:e98331f1d6b5	6859
vcoubard	607:e98331f1d6b5	6860	/* Register: WDT_CONFIG */
vcoubard	607:e98331f1d6b5	6861	/* Description: Configuration register. */
vcoubard	607:e98331f1d6b5	6862
vcoubard	607:e98331f1d6b5	6863	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
vcoubard	607:e98331f1d6b5	6864	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
vcoubard	607:e98331f1d6b5	6865	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
vcoubard	607:e98331f1d6b5	6866	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
vcoubard	607:e98331f1d6b5	6867	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
vcoubard	607:e98331f1d6b5	6868
vcoubard	607:e98331f1d6b5	6869	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
vcoubard	607:e98331f1d6b5	6870	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
vcoubard	607:e98331f1d6b5	6871	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
vcoubard	607:e98331f1d6b5	6872	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
vcoubard	607:e98331f1d6b5	6873	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
vcoubard	607:e98331f1d6b5	6874
vcoubard	607:e98331f1d6b5	6875	/* Register: WDT_RR */
vcoubard	607:e98331f1d6b5	6876	/* Description: Reload requests registers. */
vcoubard	607:e98331f1d6b5	6877
vcoubard	607:e98331f1d6b5	6878	/* Bits 31..0 : Reload register. */
vcoubard	607:e98331f1d6b5	6879	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
vcoubard	607:e98331f1d6b5	6880	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
vcoubard	607:e98331f1d6b5	6881	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
vcoubard	607:e98331f1d6b5	6882
vcoubard	607:e98331f1d6b5	6883	/* Register: WDT_POWER */
vcoubard	607:e98331f1d6b5	6884	/* Description: Peripheral power control. */
vcoubard	607:e98331f1d6b5	6885
vcoubard	607:e98331f1d6b5	6886	/* Bit 0 : Peripheral power control. */
vcoubard	607:e98331f1d6b5	6887	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	607:e98331f1d6b5	6888	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	607:e98331f1d6b5	6889	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	607:e98331f1d6b5	6890	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	607:e98331f1d6b5	6891
vcoubard	607:e98331f1d6b5	6892
vcoubard	607:e98331f1d6b5	6893	/lint --flb "Leave library region" /
vcoubard	607:e98331f1d6b5	6894	#endif

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Created:	26 Feb 2017
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