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targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h@15:a81a8d6c1dfe, 2015-11-04 (annotated)

Committer:
mbed_official
Date:
Wed Nov 04 16:30:11 2015 +0000
Revision:
15:a81a8d6c1dfe
Synchronized with git revision 46af745ef4405614c3fa49abbd9a706a362ea514



Full URL: https://github.com/mbedmicro/mbed/commit/46af745ef4405614c3fa49abbd9a706a362ea514/



Renamed TARGET_SAM_CortexM0+ to TARGET_SAM_CortexM0P for compatiblity with online compiler

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 15:a81a8d6c1dfe 1 /**
mbed_official 15:a81a8d6c1dfe 2 * \file
mbed_official 15:a81a8d6c1dfe 3 *
mbed_official 15:a81a8d6c1dfe 4 * \brief Instance description for RTC
mbed_official 15:a81a8d6c1dfe 5 *
mbed_official 15:a81a8d6c1dfe 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
mbed_official 15:a81a8d6c1dfe 7 *
mbed_official 15:a81a8d6c1dfe 8 * \asf_license_start
mbed_official 15:a81a8d6c1dfe 9 *
mbed_official 15:a81a8d6c1dfe 10 * \page License
mbed_official 15:a81a8d6c1dfe 11 *
mbed_official 15:a81a8d6c1dfe 12 * Redistribution and use in source and binary forms, with or without
mbed_official 15:a81a8d6c1dfe 13 * modification, are permitted provided that the following conditions are met:
mbed_official 15:a81a8d6c1dfe 14 *
mbed_official 15:a81a8d6c1dfe 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 15:a81a8d6c1dfe 16 * this list of conditions and the following disclaimer.
mbed_official 15:a81a8d6c1dfe 17 *
mbed_official 15:a81a8d6c1dfe 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 15:a81a8d6c1dfe 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 15:a81a8d6c1dfe 20 * and/or other materials provided with the distribution.
mbed_official 15:a81a8d6c1dfe 21 *
mbed_official 15:a81a8d6c1dfe 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 15:a81a8d6c1dfe 23 * from this software without specific prior written permission.
mbed_official 15:a81a8d6c1dfe 24 *
mbed_official 15:a81a8d6c1dfe 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 15:a81a8d6c1dfe 26 * Atmel microcontroller product.
mbed_official 15:a81a8d6c1dfe 27 *
mbed_official 15:a81a8d6c1dfe 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 15:a81a8d6c1dfe 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 15:a81a8d6c1dfe 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 15:a81a8d6c1dfe 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 15:a81a8d6c1dfe 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 15:a81a8d6c1dfe 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 15:a81a8d6c1dfe 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 15:a81a8d6c1dfe 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 15:a81a8d6c1dfe 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 15:a81a8d6c1dfe 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 15:a81a8d6c1dfe 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 15:a81a8d6c1dfe 39 *
mbed_official 15:a81a8d6c1dfe 40 * \asf_license_stop
mbed_official 15:a81a8d6c1dfe 41 *
mbed_official 15:a81a8d6c1dfe 42 */
mbed_official 15:a81a8d6c1dfe 43
mbed_official 15:a81a8d6c1dfe 44 #ifndef _SAMR21_RTC_INSTANCE_
mbed_official 15:a81a8d6c1dfe 45 #define _SAMR21_RTC_INSTANCE_
mbed_official 15:a81a8d6c1dfe 46
mbed_official 15:a81a8d6c1dfe 47 /* ========== Register definition for RTC peripheral ========== */
mbed_official 15:a81a8d6c1dfe 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 49 #define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */
mbed_official 15:a81a8d6c1dfe 50 #define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */
mbed_official 15:a81a8d6c1dfe 51 #define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */
mbed_official 15:a81a8d6c1dfe 52 #define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */
mbed_official 15:a81a8d6c1dfe 53 #define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */
mbed_official 15:a81a8d6c1dfe 54 #define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
mbed_official 15:a81a8d6c1dfe 55 #define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 56 #define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 57 #define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 58 #define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
mbed_official 15:a81a8d6c1dfe 59 #define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
mbed_official 15:a81a8d6c1dfe 60 #define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */
mbed_official 15:a81a8d6c1dfe 61 #define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
mbed_official 15:a81a8d6c1dfe 62 #define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 63 #define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 64 #define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 65 #define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
mbed_official 15:a81a8d6c1dfe 66 #define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
mbed_official 15:a81a8d6c1dfe 67 #define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
mbed_official 15:a81a8d6c1dfe 68 #define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
mbed_official 15:a81a8d6c1dfe 69 #define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */
mbed_official 15:a81a8d6c1dfe 70 #define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
mbed_official 15:a81a8d6c1dfe 71 #define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 72 #define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 73 #define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 74 #define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
mbed_official 15:a81a8d6c1dfe 75 #define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
mbed_official 15:a81a8d6c1dfe 76 #define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
mbed_official 15:a81a8d6c1dfe 77 #else
mbed_official 15:a81a8d6c1dfe 78 #define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
mbed_official 15:a81a8d6c1dfe 79 #define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
mbed_official 15:a81a8d6c1dfe 80 #define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
mbed_official 15:a81a8d6c1dfe 81 #define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
mbed_official 15:a81a8d6c1dfe 82 #define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
mbed_official 15:a81a8d6c1dfe 83 #define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
mbed_official 15:a81a8d6c1dfe 84 #define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 85 #define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 86 #define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 87 #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
mbed_official 15:a81a8d6c1dfe 88 #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
mbed_official 15:a81a8d6c1dfe 89 #define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
mbed_official 15:a81a8d6c1dfe 90 #define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
mbed_official 15:a81a8d6c1dfe 91 #define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 92 #define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 93 #define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 94 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
mbed_official 15:a81a8d6c1dfe 95 #define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
mbed_official 15:a81a8d6c1dfe 96 #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
mbed_official 15:a81a8d6c1dfe 97 #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
mbed_official 15:a81a8d6c1dfe 98 #define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
mbed_official 15:a81a8d6c1dfe 99 #define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
mbed_official 15:a81a8d6c1dfe 100 #define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 101 #define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 102 #define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 103 #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
mbed_official 15:a81a8d6c1dfe 104 #define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
mbed_official 15:a81a8d6c1dfe 105 #define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
mbed_official 15:a81a8d6c1dfe 106 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 107
mbed_official 15:a81a8d6c1dfe 108 /* ========== Instance parameters for RTC peripheral ========== */
mbed_official 15:a81a8d6c1dfe 109 #define RTC_ALARM_NUM 1 // Number of Alarms
mbed_official 15:a81a8d6c1dfe 110 #define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
mbed_official 15:a81a8d6c1dfe 111 #define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
mbed_official 15:a81a8d6c1dfe 112 #define RTC_GCLK_ID 4 // Index of Generic Clock
mbed_official 15:a81a8d6c1dfe 113 #define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete)
mbed_official 15:a81a8d6c1dfe 114 #define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete)
mbed_official 15:a81a8d6c1dfe 115 #define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete)
mbed_official 15:a81a8d6c1dfe 116
mbed_official 15:a81a8d6c1dfe 117 #endif /* _SAMR21_RTC_INSTANCE_ */