Fawwaz Nadzmy / mbed-dev

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targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h@15:a81a8d6c1dfe, 2015-11-04 (annotated)

Committer:
mbed_official
Date:
Wed Nov 04 16:30:11 2015 +0000
Revision:
15:a81a8d6c1dfe
Synchronized with git revision 46af745ef4405614c3fa49abbd9a706a362ea514



Full URL: https://github.com/mbedmicro/mbed/commit/46af745ef4405614c3fa49abbd9a706a362ea514/



Renamed TARGET_SAM_CortexM0+ to TARGET_SAM_CortexM0P for compatiblity with online compiler

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 15:a81a8d6c1dfe 1 /**
mbed_official 15:a81a8d6c1dfe 2 * \file
mbed_official 15:a81a8d6c1dfe 3 *
mbed_official 15:a81a8d6c1dfe 4 * \brief Component description for DMAC
mbed_official 15:a81a8d6c1dfe 5 *
mbed_official 15:a81a8d6c1dfe 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
mbed_official 15:a81a8d6c1dfe 7 *
mbed_official 15:a81a8d6c1dfe 8 * \asf_license_start
mbed_official 15:a81a8d6c1dfe 9 *
mbed_official 15:a81a8d6c1dfe 10 * \page License
mbed_official 15:a81a8d6c1dfe 11 *
mbed_official 15:a81a8d6c1dfe 12 * Redistribution and use in source and binary forms, with or without
mbed_official 15:a81a8d6c1dfe 13 * modification, are permitted provided that the following conditions are met:
mbed_official 15:a81a8d6c1dfe 14 *
mbed_official 15:a81a8d6c1dfe 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 15:a81a8d6c1dfe 16 * this list of conditions and the following disclaimer.
mbed_official 15:a81a8d6c1dfe 17 *
mbed_official 15:a81a8d6c1dfe 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 15:a81a8d6c1dfe 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 15:a81a8d6c1dfe 20 * and/or other materials provided with the distribution.
mbed_official 15:a81a8d6c1dfe 21 *
mbed_official 15:a81a8d6c1dfe 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 15:a81a8d6c1dfe 23 * from this software without specific prior written permission.
mbed_official 15:a81a8d6c1dfe 24 *
mbed_official 15:a81a8d6c1dfe 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 15:a81a8d6c1dfe 26 * Atmel microcontroller product.
mbed_official 15:a81a8d6c1dfe 27 *
mbed_official 15:a81a8d6c1dfe 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 15:a81a8d6c1dfe 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 15:a81a8d6c1dfe 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 15:a81a8d6c1dfe 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 15:a81a8d6c1dfe 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 15:a81a8d6c1dfe 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 15:a81a8d6c1dfe 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 15:a81a8d6c1dfe 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 15:a81a8d6c1dfe 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 15:a81a8d6c1dfe 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 15:a81a8d6c1dfe 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 15:a81a8d6c1dfe 39 *
mbed_official 15:a81a8d6c1dfe 40 * \asf_license_stop
mbed_official 15:a81a8d6c1dfe 41 *
mbed_official 15:a81a8d6c1dfe 42 */
mbed_official 15:a81a8d6c1dfe 43 /*
mbed_official 15:a81a8d6c1dfe 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 15:a81a8d6c1dfe 45 */
mbed_official 15:a81a8d6c1dfe 46
mbed_official 15:a81a8d6c1dfe 47 #ifndef _SAMD21_DMAC_COMPONENT_
mbed_official 15:a81a8d6c1dfe 48 #define _SAMD21_DMAC_COMPONENT_
mbed_official 15:a81a8d6c1dfe 49
mbed_official 15:a81a8d6c1dfe 50 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 51 /** SOFTWARE API DEFINITION FOR DMAC */
mbed_official 15:a81a8d6c1dfe 52 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 53 /** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
mbed_official 15:a81a8d6c1dfe 54 /*@{*/
mbed_official 15:a81a8d6c1dfe 55
mbed_official 15:a81a8d6c1dfe 56 #define DMAC_U2223
mbed_official 15:a81a8d6c1dfe 57 #define REV_DMAC 0x110
mbed_official 15:a81a8d6c1dfe 58
mbed_official 15:a81a8d6c1dfe 59 /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
mbed_official 15:a81a8d6c1dfe 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 61 typedef union {
mbed_official 15:a81a8d6c1dfe 62 struct {
mbed_official 15:a81a8d6c1dfe 63 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 64 uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
mbed_official 15:a81a8d6c1dfe 65 uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
mbed_official 15:a81a8d6c1dfe 66 uint16_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 67 uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
mbed_official 15:a81a8d6c1dfe 68 uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
mbed_official 15:a81a8d6c1dfe 69 uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
mbed_official 15:a81a8d6c1dfe 70 uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
mbed_official 15:a81a8d6c1dfe 71 uint16_t :4; /*!< bit: 12..15 Reserved */
mbed_official 15:a81a8d6c1dfe 72 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 73 struct {
mbed_official 15:a81a8d6c1dfe 74 uint16_t :8; /*!< bit: 0.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 75 uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
mbed_official 15:a81a8d6c1dfe 76 uint16_t :4; /*!< bit: 12..15 Reserved */
mbed_official 15:a81a8d6c1dfe 77 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 78 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 79 } DMAC_CTRL_Type;
mbed_official 15:a81a8d6c1dfe 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 81
mbed_official 15:a81a8d6c1dfe 82 #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
mbed_official 15:a81a8d6c1dfe 83 #define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */
mbed_official 15:a81a8d6c1dfe 84
mbed_official 15:a81a8d6c1dfe 85 #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
mbed_official 15:a81a8d6c1dfe 86 #define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 87 #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
mbed_official 15:a81a8d6c1dfe 88 #define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 89 #define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
mbed_official 15:a81a8d6c1dfe 90 #define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 91 #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
mbed_official 15:a81a8d6c1dfe 92 #define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
mbed_official 15:a81a8d6c1dfe 93 #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
mbed_official 15:a81a8d6c1dfe 94 #define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
mbed_official 15:a81a8d6c1dfe 95 #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
mbed_official 15:a81a8d6c1dfe 96 #define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
mbed_official 15:a81a8d6c1dfe 97 #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
mbed_official 15:a81a8d6c1dfe 98 #define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
mbed_official 15:a81a8d6c1dfe 99 #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
mbed_official 15:a81a8d6c1dfe 100 #define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos)
mbed_official 15:a81a8d6c1dfe 101 #define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)))
mbed_official 15:a81a8d6c1dfe 102 #define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 103
mbed_official 15:a81a8d6c1dfe 104 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
mbed_official 15:a81a8d6c1dfe 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 106 typedef union {
mbed_official 15:a81a8d6c1dfe 107 struct {
mbed_official 15:a81a8d6c1dfe 108 uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
mbed_official 15:a81a8d6c1dfe 109 uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
mbed_official 15:a81a8d6c1dfe 110 uint16_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 111 uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
mbed_official 15:a81a8d6c1dfe 112 uint16_t :2; /*!< bit: 14..15 Reserved */
mbed_official 15:a81a8d6c1dfe 113 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 114 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 115 } DMAC_CRCCTRL_Type;
mbed_official 15:a81a8d6c1dfe 116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 117
mbed_official 15:a81a8d6c1dfe 118 #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
mbed_official 15:a81a8d6c1dfe 119 #define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
mbed_official 15:a81a8d6c1dfe 120
mbed_official 15:a81a8d6c1dfe 121 #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
mbed_official 15:a81a8d6c1dfe 122 #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 123 #define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)))
mbed_official 15:a81a8d6c1dfe 124 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) Byte bus access */
mbed_official 15:a81a8d6c1dfe 125 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) Half-word bus access */
mbed_official 15:a81a8d6c1dfe 126 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) Word bus access */
mbed_official 15:a81a8d6c1dfe 127 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 128 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 129 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 130 #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
mbed_official 15:a81a8d6c1dfe 131 #define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
mbed_official 15:a81a8d6c1dfe 132 #define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)))
mbed_official 15:a81a8d6c1dfe 133 #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
mbed_official 15:a81a8d6c1dfe 134 #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
mbed_official 15:a81a8d6c1dfe 135 #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
mbed_official 15:a81a8d6c1dfe 136 #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
mbed_official 15:a81a8d6c1dfe 137 #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
mbed_official 15:a81a8d6c1dfe 138 #define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
mbed_official 15:a81a8d6c1dfe 139 #define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)))
mbed_official 15:a81a8d6c1dfe 140 #define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */
mbed_official 15:a81a8d6c1dfe 141 #define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */
mbed_official 15:a81a8d6c1dfe 142 #define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
mbed_official 15:a81a8d6c1dfe 143 #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
mbed_official 15:a81a8d6c1dfe 144 #define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 145
mbed_official 15:a81a8d6c1dfe 146 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
mbed_official 15:a81a8d6c1dfe 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 148 typedef union {
mbed_official 15:a81a8d6c1dfe 149 struct {
mbed_official 15:a81a8d6c1dfe 150 uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
mbed_official 15:a81a8d6c1dfe 151 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 152 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 153 } DMAC_CRCDATAIN_Type;
mbed_official 15:a81a8d6c1dfe 154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 155
mbed_official 15:a81a8d6c1dfe 156 #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
mbed_official 15:a81a8d6c1dfe 157 #define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
mbed_official 15:a81a8d6c1dfe 158
mbed_official 15:a81a8d6c1dfe 159 #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
mbed_official 15:a81a8d6c1dfe 160 #define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
mbed_official 15:a81a8d6c1dfe 161 #define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)))
mbed_official 15:a81a8d6c1dfe 162 #define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
mbed_official 15:a81a8d6c1dfe 163
mbed_official 15:a81a8d6c1dfe 164 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
mbed_official 15:a81a8d6c1dfe 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 166 typedef union {
mbed_official 15:a81a8d6c1dfe 167 struct {
mbed_official 15:a81a8d6c1dfe 168 uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
mbed_official 15:a81a8d6c1dfe 169 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 170 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 171 } DMAC_CRCCHKSUM_Type;
mbed_official 15:a81a8d6c1dfe 172 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 173
mbed_official 15:a81a8d6c1dfe 174 #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
mbed_official 15:a81a8d6c1dfe 175 #define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
mbed_official 15:a81a8d6c1dfe 176
mbed_official 15:a81a8d6c1dfe 177 #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
mbed_official 15:a81a8d6c1dfe 178 #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
mbed_official 15:a81a8d6c1dfe 179 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)))
mbed_official 15:a81a8d6c1dfe 180 #define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
mbed_official 15:a81a8d6c1dfe 181
mbed_official 15:a81a8d6c1dfe 182 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
mbed_official 15:a81a8d6c1dfe 183 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 184 typedef union {
mbed_official 15:a81a8d6c1dfe 185 struct {
mbed_official 15:a81a8d6c1dfe 186 uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
mbed_official 15:a81a8d6c1dfe 187 uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
mbed_official 15:a81a8d6c1dfe 188 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 189 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 190 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 191 } DMAC_CRCSTATUS_Type;
mbed_official 15:a81a8d6c1dfe 192 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 193
mbed_official 15:a81a8d6c1dfe 194 #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
mbed_official 15:a81a8d6c1dfe 195 #define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
mbed_official 15:a81a8d6c1dfe 196
mbed_official 15:a81a8d6c1dfe 197 #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
mbed_official 15:a81a8d6c1dfe 198 #define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
mbed_official 15:a81a8d6c1dfe 199 #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
mbed_official 15:a81a8d6c1dfe 200 #define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
mbed_official 15:a81a8d6c1dfe 201 #define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 202
mbed_official 15:a81a8d6c1dfe 203 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
mbed_official 15:a81a8d6c1dfe 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 205 typedef union {
mbed_official 15:a81a8d6c1dfe 206 struct {
mbed_official 15:a81a8d6c1dfe 207 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
mbed_official 15:a81a8d6c1dfe 208 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 209 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 210 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 211 } DMAC_DBGCTRL_Type;
mbed_official 15:a81a8d6c1dfe 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 213
mbed_official 15:a81a8d6c1dfe 214 #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
mbed_official 15:a81a8d6c1dfe 215 #define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
mbed_official 15:a81a8d6c1dfe 216
mbed_official 15:a81a8d6c1dfe 217 #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
mbed_official 15:a81a8d6c1dfe 218 #define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
mbed_official 15:a81a8d6c1dfe 219 #define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 220
mbed_official 15:a81a8d6c1dfe 221 /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
mbed_official 15:a81a8d6c1dfe 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 223 typedef union {
mbed_official 15:a81a8d6c1dfe 224 struct {
mbed_official 15:a81a8d6c1dfe 225 uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
mbed_official 15:a81a8d6c1dfe 226 uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
mbed_official 15:a81a8d6c1dfe 227 uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
mbed_official 15:a81a8d6c1dfe 228 uint8_t :2; /*!< bit: 6.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 229 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 230 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 231 } DMAC_QOSCTRL_Type;
mbed_official 15:a81a8d6c1dfe 232 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 233
mbed_official 15:a81a8d6c1dfe 234 #define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */
mbed_official 15:a81a8d6c1dfe 235 #define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
mbed_official 15:a81a8d6c1dfe 236
mbed_official 15:a81a8d6c1dfe 237 #define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
mbed_official 15:a81a8d6c1dfe 238 #define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
mbed_official 15:a81a8d6c1dfe 239 #define DMAC_QOSCTRL_WRBQOS(value) ((DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)))
mbed_official 15:a81a8d6c1dfe 240 #define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
mbed_official 15:a81a8d6c1dfe 241 #define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
mbed_official 15:a81a8d6c1dfe 242 #define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
mbed_official 15:a81a8d6c1dfe 243 #define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
mbed_official 15:a81a8d6c1dfe 244 #define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
mbed_official 15:a81a8d6c1dfe 245 #define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos)
mbed_official 15:a81a8d6c1dfe 246 #define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
mbed_official 15:a81a8d6c1dfe 247 #define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
mbed_official 15:a81a8d6c1dfe 248 #define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
mbed_official 15:a81a8d6c1dfe 249 #define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
mbed_official 15:a81a8d6c1dfe 250 #define DMAC_QOSCTRL_FQOS(value) ((DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)))
mbed_official 15:a81a8d6c1dfe 251 #define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
mbed_official 15:a81a8d6c1dfe 252 #define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
mbed_official 15:a81a8d6c1dfe 253 #define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
mbed_official 15:a81a8d6c1dfe 254 #define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
mbed_official 15:a81a8d6c1dfe 255 #define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
mbed_official 15:a81a8d6c1dfe 256 #define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos)
mbed_official 15:a81a8d6c1dfe 257 #define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos)
mbed_official 15:a81a8d6c1dfe 258 #define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
mbed_official 15:a81a8d6c1dfe 259 #define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
mbed_official 15:a81a8d6c1dfe 260 #define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
mbed_official 15:a81a8d6c1dfe 261 #define DMAC_QOSCTRL_DQOS(value) ((DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)))
mbed_official 15:a81a8d6c1dfe 262 #define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
mbed_official 15:a81a8d6c1dfe 263 #define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
mbed_official 15:a81a8d6c1dfe 264 #define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
mbed_official 15:a81a8d6c1dfe 265 #define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
mbed_official 15:a81a8d6c1dfe 266 #define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
mbed_official 15:a81a8d6c1dfe 267 #define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos)
mbed_official 15:a81a8d6c1dfe 268 #define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos)
mbed_official 15:a81a8d6c1dfe 269 #define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos)
mbed_official 15:a81a8d6c1dfe 270 #define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 271
mbed_official 15:a81a8d6c1dfe 272 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
mbed_official 15:a81a8d6c1dfe 273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 274 typedef union {
mbed_official 15:a81a8d6c1dfe 275 struct {
mbed_official 15:a81a8d6c1dfe 276 uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
mbed_official 15:a81a8d6c1dfe 277 uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
mbed_official 15:a81a8d6c1dfe 278 uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
mbed_official 15:a81a8d6c1dfe 279 uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
mbed_official 15:a81a8d6c1dfe 280 uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
mbed_official 15:a81a8d6c1dfe 281 uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
mbed_official 15:a81a8d6c1dfe 282 uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
mbed_official 15:a81a8d6c1dfe 283 uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
mbed_official 15:a81a8d6c1dfe 284 uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
mbed_official 15:a81a8d6c1dfe 285 uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
mbed_official 15:a81a8d6c1dfe 286 uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
mbed_official 15:a81a8d6c1dfe 287 uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
mbed_official 15:a81a8d6c1dfe 288 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 289 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 290 struct {
mbed_official 15:a81a8d6c1dfe 291 uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
mbed_official 15:a81a8d6c1dfe 292 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 293 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 294 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 295 } DMAC_SWTRIGCTRL_Type;
mbed_official 15:a81a8d6c1dfe 296 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 297
mbed_official 15:a81a8d6c1dfe 298 #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
mbed_official 15:a81a8d6c1dfe 299 #define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
mbed_official 15:a81a8d6c1dfe 300
mbed_official 15:a81a8d6c1dfe 301 #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
mbed_official 15:a81a8d6c1dfe 302 #define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
mbed_official 15:a81a8d6c1dfe 303 #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
mbed_official 15:a81a8d6c1dfe 304 #define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
mbed_official 15:a81a8d6c1dfe 305 #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
mbed_official 15:a81a8d6c1dfe 306 #define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
mbed_official 15:a81a8d6c1dfe 307 #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
mbed_official 15:a81a8d6c1dfe 308 #define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
mbed_official 15:a81a8d6c1dfe 309 #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
mbed_official 15:a81a8d6c1dfe 310 #define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
mbed_official 15:a81a8d6c1dfe 311 #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
mbed_official 15:a81a8d6c1dfe 312 #define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
mbed_official 15:a81a8d6c1dfe 313 #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
mbed_official 15:a81a8d6c1dfe 314 #define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
mbed_official 15:a81a8d6c1dfe 315 #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
mbed_official 15:a81a8d6c1dfe 316 #define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
mbed_official 15:a81a8d6c1dfe 317 #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
mbed_official 15:a81a8d6c1dfe 318 #define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
mbed_official 15:a81a8d6c1dfe 319 #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
mbed_official 15:a81a8d6c1dfe 320 #define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
mbed_official 15:a81a8d6c1dfe 321 #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
mbed_official 15:a81a8d6c1dfe 322 #define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
mbed_official 15:a81a8d6c1dfe 323 #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
mbed_official 15:a81a8d6c1dfe 324 #define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
mbed_official 15:a81a8d6c1dfe 325 #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
mbed_official 15:a81a8d6c1dfe 326 #define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
mbed_official 15:a81a8d6c1dfe 327 #define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)))
mbed_official 15:a81a8d6c1dfe 328 #define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 329
mbed_official 15:a81a8d6c1dfe 330 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
mbed_official 15:a81a8d6c1dfe 331 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 332 typedef union {
mbed_official 15:a81a8d6c1dfe 333 struct {
mbed_official 15:a81a8d6c1dfe 334 uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 335 uint32_t :3; /*!< bit: 4.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 336 uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 337 uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 338 uint32_t :3; /*!< bit: 12..14 Reserved */
mbed_official 15:a81a8d6c1dfe 339 uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 340 uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 341 uint32_t :3; /*!< bit: 20..22 Reserved */
mbed_official 15:a81a8d6c1dfe 342 uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 343 uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 344 uint32_t :3; /*!< bit: 28..30 Reserved */
mbed_official 15:a81a8d6c1dfe 345 uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 346 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 347 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 348 } DMAC_PRICTRL0_Type;
mbed_official 15:a81a8d6c1dfe 349 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 350
mbed_official 15:a81a8d6c1dfe 351 #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
mbed_official 15:a81a8d6c1dfe 352 #define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
mbed_official 15:a81a8d6c1dfe 353
mbed_official 15:a81a8d6c1dfe 354 #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 355 #define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
mbed_official 15:a81a8d6c1dfe 356 #define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)))
mbed_official 15:a81a8d6c1dfe 357 #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 358 #define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
mbed_official 15:a81a8d6c1dfe 359 #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 360 #define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
mbed_official 15:a81a8d6c1dfe 361 #define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)))
mbed_official 15:a81a8d6c1dfe 362 #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 363 #define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
mbed_official 15:a81a8d6c1dfe 364 #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 365 #define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
mbed_official 15:a81a8d6c1dfe 366 #define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)))
mbed_official 15:a81a8d6c1dfe 367 #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 368 #define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
mbed_official 15:a81a8d6c1dfe 369 #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
mbed_official 15:a81a8d6c1dfe 370 #define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
mbed_official 15:a81a8d6c1dfe 371 #define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)))
mbed_official 15:a81a8d6c1dfe 372 #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
mbed_official 15:a81a8d6c1dfe 373 #define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
mbed_official 15:a81a8d6c1dfe 374 #define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
mbed_official 15:a81a8d6c1dfe 375
mbed_official 15:a81a8d6c1dfe 376 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
mbed_official 15:a81a8d6c1dfe 377 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 378 typedef union {
mbed_official 15:a81a8d6c1dfe 379 struct {
mbed_official 15:a81a8d6c1dfe 380 uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
mbed_official 15:a81a8d6c1dfe 381 uint16_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 382 uint16_t TERR:1; /*!< bit: 8 Transfer Error */
mbed_official 15:a81a8d6c1dfe 383 uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
mbed_official 15:a81a8d6c1dfe 384 uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
mbed_official 15:a81a8d6c1dfe 385 uint16_t :2; /*!< bit: 11..12 Reserved */
mbed_official 15:a81a8d6c1dfe 386 uint16_t FERR:1; /*!< bit: 13 Fetch Error */
mbed_official 15:a81a8d6c1dfe 387 uint16_t BUSY:1; /*!< bit: 14 Busy */
mbed_official 15:a81a8d6c1dfe 388 uint16_t PEND:1; /*!< bit: 15 Pending */
mbed_official 15:a81a8d6c1dfe 389 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 390 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 391 } DMAC_INTPEND_Type;
mbed_official 15:a81a8d6c1dfe 392 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 393
mbed_official 15:a81a8d6c1dfe 394 #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
mbed_official 15:a81a8d6c1dfe 395 #define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
mbed_official 15:a81a8d6c1dfe 396
mbed_official 15:a81a8d6c1dfe 397 #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
mbed_official 15:a81a8d6c1dfe 398 #define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos)
mbed_official 15:a81a8d6c1dfe 399 #define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)))
mbed_official 15:a81a8d6c1dfe 400 #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
mbed_official 15:a81a8d6c1dfe 401 #define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos)
mbed_official 15:a81a8d6c1dfe 402 #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
mbed_official 15:a81a8d6c1dfe 403 #define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos)
mbed_official 15:a81a8d6c1dfe 404 #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
mbed_official 15:a81a8d6c1dfe 405 #define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos)
mbed_official 15:a81a8d6c1dfe 406 #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
mbed_official 15:a81a8d6c1dfe 407 #define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos)
mbed_official 15:a81a8d6c1dfe 408 #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
mbed_official 15:a81a8d6c1dfe 409 #define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos)
mbed_official 15:a81a8d6c1dfe 410 #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
mbed_official 15:a81a8d6c1dfe 411 #define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos)
mbed_official 15:a81a8d6c1dfe 412 #define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */
mbed_official 15:a81a8d6c1dfe 413
mbed_official 15:a81a8d6c1dfe 414 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
mbed_official 15:a81a8d6c1dfe 415 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 416 typedef union {
mbed_official 15:a81a8d6c1dfe 417 struct {
mbed_official 15:a81a8d6c1dfe 418 uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 419 uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 420 uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 421 uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 422 uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 423 uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 424 uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 425 uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 426 uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 427 uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 428 uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 429 uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 430 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 431 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 432 struct {
mbed_official 15:a81a8d6c1dfe 433 uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 434 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 435 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 436 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 437 } DMAC_INTSTATUS_Type;
mbed_official 15:a81a8d6c1dfe 438 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 439
mbed_official 15:a81a8d6c1dfe 440 #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
mbed_official 15:a81a8d6c1dfe 441 #define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
mbed_official 15:a81a8d6c1dfe 442
mbed_official 15:a81a8d6c1dfe 443 #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 444 #define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
mbed_official 15:a81a8d6c1dfe 445 #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 446 #define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
mbed_official 15:a81a8d6c1dfe 447 #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 448 #define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
mbed_official 15:a81a8d6c1dfe 449 #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 450 #define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
mbed_official 15:a81a8d6c1dfe 451 #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 452 #define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
mbed_official 15:a81a8d6c1dfe 453 #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 454 #define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
mbed_official 15:a81a8d6c1dfe 455 #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 456 #define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
mbed_official 15:a81a8d6c1dfe 457 #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 458 #define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
mbed_official 15:a81a8d6c1dfe 459 #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 460 #define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
mbed_official 15:a81a8d6c1dfe 461 #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 462 #define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
mbed_official 15:a81a8d6c1dfe 463 #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 464 #define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
mbed_official 15:a81a8d6c1dfe 465 #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 466 #define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
mbed_official 15:a81a8d6c1dfe 467 #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
mbed_official 15:a81a8d6c1dfe 468 #define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
mbed_official 15:a81a8d6c1dfe 469 #define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)))
mbed_official 15:a81a8d6c1dfe 470 #define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 471
mbed_official 15:a81a8d6c1dfe 472 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
mbed_official 15:a81a8d6c1dfe 473 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 474 typedef union {
mbed_official 15:a81a8d6c1dfe 475 struct {
mbed_official 15:a81a8d6c1dfe 476 uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
mbed_official 15:a81a8d6c1dfe 477 uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
mbed_official 15:a81a8d6c1dfe 478 uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
mbed_official 15:a81a8d6c1dfe 479 uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
mbed_official 15:a81a8d6c1dfe 480 uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
mbed_official 15:a81a8d6c1dfe 481 uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
mbed_official 15:a81a8d6c1dfe 482 uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
mbed_official 15:a81a8d6c1dfe 483 uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
mbed_official 15:a81a8d6c1dfe 484 uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
mbed_official 15:a81a8d6c1dfe 485 uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
mbed_official 15:a81a8d6c1dfe 486 uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
mbed_official 15:a81a8d6c1dfe 487 uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
mbed_official 15:a81a8d6c1dfe 488 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 489 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 490 struct {
mbed_official 15:a81a8d6c1dfe 491 uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
mbed_official 15:a81a8d6c1dfe 492 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 493 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 494 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 495 } DMAC_BUSYCH_Type;
mbed_official 15:a81a8d6c1dfe 496 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 497
mbed_official 15:a81a8d6c1dfe 498 #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
mbed_official 15:a81a8d6c1dfe 499 #define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
mbed_official 15:a81a8d6c1dfe 500
mbed_official 15:a81a8d6c1dfe 501 #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
mbed_official 15:a81a8d6c1dfe 502 #define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
mbed_official 15:a81a8d6c1dfe 503 #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
mbed_official 15:a81a8d6c1dfe 504 #define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
mbed_official 15:a81a8d6c1dfe 505 #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
mbed_official 15:a81a8d6c1dfe 506 #define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
mbed_official 15:a81a8d6c1dfe 507 #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
mbed_official 15:a81a8d6c1dfe 508 #define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
mbed_official 15:a81a8d6c1dfe 509 #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
mbed_official 15:a81a8d6c1dfe 510 #define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
mbed_official 15:a81a8d6c1dfe 511 #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
mbed_official 15:a81a8d6c1dfe 512 #define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
mbed_official 15:a81a8d6c1dfe 513 #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
mbed_official 15:a81a8d6c1dfe 514 #define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
mbed_official 15:a81a8d6c1dfe 515 #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
mbed_official 15:a81a8d6c1dfe 516 #define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
mbed_official 15:a81a8d6c1dfe 517 #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
mbed_official 15:a81a8d6c1dfe 518 #define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
mbed_official 15:a81a8d6c1dfe 519 #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
mbed_official 15:a81a8d6c1dfe 520 #define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
mbed_official 15:a81a8d6c1dfe 521 #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
mbed_official 15:a81a8d6c1dfe 522 #define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
mbed_official 15:a81a8d6c1dfe 523 #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
mbed_official 15:a81a8d6c1dfe 524 #define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
mbed_official 15:a81a8d6c1dfe 525 #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
mbed_official 15:a81a8d6c1dfe 526 #define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
mbed_official 15:a81a8d6c1dfe 527 #define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)))
mbed_official 15:a81a8d6c1dfe 528 #define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
mbed_official 15:a81a8d6c1dfe 529
mbed_official 15:a81a8d6c1dfe 530 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
mbed_official 15:a81a8d6c1dfe 531 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 532 typedef union {
mbed_official 15:a81a8d6c1dfe 533 struct {
mbed_official 15:a81a8d6c1dfe 534 uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
mbed_official 15:a81a8d6c1dfe 535 uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
mbed_official 15:a81a8d6c1dfe 536 uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
mbed_official 15:a81a8d6c1dfe 537 uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
mbed_official 15:a81a8d6c1dfe 538 uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
mbed_official 15:a81a8d6c1dfe 539 uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
mbed_official 15:a81a8d6c1dfe 540 uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
mbed_official 15:a81a8d6c1dfe 541 uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
mbed_official 15:a81a8d6c1dfe 542 uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
mbed_official 15:a81a8d6c1dfe 543 uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
mbed_official 15:a81a8d6c1dfe 544 uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
mbed_official 15:a81a8d6c1dfe 545 uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
mbed_official 15:a81a8d6c1dfe 546 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 547 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 548 struct {
mbed_official 15:a81a8d6c1dfe 549 uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
mbed_official 15:a81a8d6c1dfe 550 uint32_t :20; /*!< bit: 12..31 Reserved */
mbed_official 15:a81a8d6c1dfe 551 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 552 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 553 } DMAC_PENDCH_Type;
mbed_official 15:a81a8d6c1dfe 554 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 555
mbed_official 15:a81a8d6c1dfe 556 #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
mbed_official 15:a81a8d6c1dfe 557 #define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
mbed_official 15:a81a8d6c1dfe 558
mbed_official 15:a81a8d6c1dfe 559 #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
mbed_official 15:a81a8d6c1dfe 560 #define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
mbed_official 15:a81a8d6c1dfe 561 #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
mbed_official 15:a81a8d6c1dfe 562 #define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
mbed_official 15:a81a8d6c1dfe 563 #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
mbed_official 15:a81a8d6c1dfe 564 #define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
mbed_official 15:a81a8d6c1dfe 565 #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
mbed_official 15:a81a8d6c1dfe 566 #define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
mbed_official 15:a81a8d6c1dfe 567 #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
mbed_official 15:a81a8d6c1dfe 568 #define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
mbed_official 15:a81a8d6c1dfe 569 #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
mbed_official 15:a81a8d6c1dfe 570 #define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
mbed_official 15:a81a8d6c1dfe 571 #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
mbed_official 15:a81a8d6c1dfe 572 #define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
mbed_official 15:a81a8d6c1dfe 573 #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
mbed_official 15:a81a8d6c1dfe 574 #define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
mbed_official 15:a81a8d6c1dfe 575 #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
mbed_official 15:a81a8d6c1dfe 576 #define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
mbed_official 15:a81a8d6c1dfe 577 #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
mbed_official 15:a81a8d6c1dfe 578 #define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
mbed_official 15:a81a8d6c1dfe 579 #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
mbed_official 15:a81a8d6c1dfe 580 #define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
mbed_official 15:a81a8d6c1dfe 581 #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
mbed_official 15:a81a8d6c1dfe 582 #define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
mbed_official 15:a81a8d6c1dfe 583 #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
mbed_official 15:a81a8d6c1dfe 584 #define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
mbed_official 15:a81a8d6c1dfe 585 #define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)))
mbed_official 15:a81a8d6c1dfe 586 #define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
mbed_official 15:a81a8d6c1dfe 587
mbed_official 15:a81a8d6c1dfe 588 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
mbed_official 15:a81a8d6c1dfe 589 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 590 typedef union {
mbed_official 15:a81a8d6c1dfe 591 struct {
mbed_official 15:a81a8d6c1dfe 592 uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 593 uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 594 uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 595 uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 596 uint32_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 597 uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
mbed_official 15:a81a8d6c1dfe 598 uint32_t :2; /*!< bit: 13..14 Reserved */
mbed_official 15:a81a8d6c1dfe 599 uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
mbed_official 15:a81a8d6c1dfe 600 uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
mbed_official 15:a81a8d6c1dfe 601 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 602 struct {
mbed_official 15:a81a8d6c1dfe 603 uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 604 uint32_t :28; /*!< bit: 4..31 Reserved */
mbed_official 15:a81a8d6c1dfe 605 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 606 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 607 } DMAC_ACTIVE_Type;
mbed_official 15:a81a8d6c1dfe 608 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 609
mbed_official 15:a81a8d6c1dfe 610 #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
mbed_official 15:a81a8d6c1dfe 611 #define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
mbed_official 15:a81a8d6c1dfe 612
mbed_official 15:a81a8d6c1dfe 613 #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 614 #define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
mbed_official 15:a81a8d6c1dfe 615 #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 616 #define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
mbed_official 15:a81a8d6c1dfe 617 #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 618 #define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
mbed_official 15:a81a8d6c1dfe 619 #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 620 #define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
mbed_official 15:a81a8d6c1dfe 621 #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
mbed_official 15:a81a8d6c1dfe 622 #define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos)
mbed_official 15:a81a8d6c1dfe 623 #define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)))
mbed_official 15:a81a8d6c1dfe 624 #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
mbed_official 15:a81a8d6c1dfe 625 #define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos)
mbed_official 15:a81a8d6c1dfe 626 #define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)))
mbed_official 15:a81a8d6c1dfe 627 #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
mbed_official 15:a81a8d6c1dfe 628 #define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
mbed_official 15:a81a8d6c1dfe 629 #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
mbed_official 15:a81a8d6c1dfe 630 #define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
mbed_official 15:a81a8d6c1dfe 631 #define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)))
mbed_official 15:a81a8d6c1dfe 632 #define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
mbed_official 15:a81a8d6c1dfe 633
mbed_official 15:a81a8d6c1dfe 634 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
mbed_official 15:a81a8d6c1dfe 635 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 636 typedef union {
mbed_official 15:a81a8d6c1dfe 637 struct {
mbed_official 15:a81a8d6c1dfe 638 uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
mbed_official 15:a81a8d6c1dfe 639 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 640 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 641 } DMAC_BASEADDR_Type;
mbed_official 15:a81a8d6c1dfe 642 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 643
mbed_official 15:a81a8d6c1dfe 644 #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
mbed_official 15:a81a8d6c1dfe 645 #define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
mbed_official 15:a81a8d6c1dfe 646
mbed_official 15:a81a8d6c1dfe 647 #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
mbed_official 15:a81a8d6c1dfe 648 #define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
mbed_official 15:a81a8d6c1dfe 649 #define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 650 #define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 651
mbed_official 15:a81a8d6c1dfe 652 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
mbed_official 15:a81a8d6c1dfe 653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 654 typedef union {
mbed_official 15:a81a8d6c1dfe 655 struct {
mbed_official 15:a81a8d6c1dfe 656 uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
mbed_official 15:a81a8d6c1dfe 657 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 658 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 659 } DMAC_WRBADDR_Type;
mbed_official 15:a81a8d6c1dfe 660 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 661
mbed_official 15:a81a8d6c1dfe 662 #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
mbed_official 15:a81a8d6c1dfe 663 #define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
mbed_official 15:a81a8d6c1dfe 664
mbed_official 15:a81a8d6c1dfe 665 #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
mbed_official 15:a81a8d6c1dfe 666 #define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
mbed_official 15:a81a8d6c1dfe 667 #define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 668 #define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 669
mbed_official 15:a81a8d6c1dfe 670 /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
mbed_official 15:a81a8d6c1dfe 671 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 672 typedef union {
mbed_official 15:a81a8d6c1dfe 673 struct {
mbed_official 15:a81a8d6c1dfe 674 uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
mbed_official 15:a81a8d6c1dfe 675 uint8_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 676 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 677 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 678 } DMAC_CHID_Type;
mbed_official 15:a81a8d6c1dfe 679 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 680
mbed_official 15:a81a8d6c1dfe 681 #define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
mbed_official 15:a81a8d6c1dfe 682 #define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */
mbed_official 15:a81a8d6c1dfe 683
mbed_official 15:a81a8d6c1dfe 684 #define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
mbed_official 15:a81a8d6c1dfe 685 #define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos)
mbed_official 15:a81a8d6c1dfe 686 #define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)))
mbed_official 15:a81a8d6c1dfe 687 #define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */
mbed_official 15:a81a8d6c1dfe 688
mbed_official 15:a81a8d6c1dfe 689 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
mbed_official 15:a81a8d6c1dfe 690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 691 typedef union {
mbed_official 15:a81a8d6c1dfe 692 struct {
mbed_official 15:a81a8d6c1dfe 693 uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
mbed_official 15:a81a8d6c1dfe 694 uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
mbed_official 15:a81a8d6c1dfe 695 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 696 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 697 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 698 } DMAC_CHCTRLA_Type;
mbed_official 15:a81a8d6c1dfe 699 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 700
mbed_official 15:a81a8d6c1dfe 701 #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
mbed_official 15:a81a8d6c1dfe 702 #define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
mbed_official 15:a81a8d6c1dfe 703
mbed_official 15:a81a8d6c1dfe 704 #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
mbed_official 15:a81a8d6c1dfe 705 #define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 706 #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
mbed_official 15:a81a8d6c1dfe 707 #define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 708 #define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */
mbed_official 15:a81a8d6c1dfe 709
mbed_official 15:a81a8d6c1dfe 710 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
mbed_official 15:a81a8d6c1dfe 711 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 712 typedef union {
mbed_official 15:a81a8d6c1dfe 713 struct {
mbed_official 15:a81a8d6c1dfe 714 uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
mbed_official 15:a81a8d6c1dfe 715 uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
mbed_official 15:a81a8d6c1dfe 716 uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
mbed_official 15:a81a8d6c1dfe 717 uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
mbed_official 15:a81a8d6c1dfe 718 uint32_t :1; /*!< bit: 7 Reserved */
mbed_official 15:a81a8d6c1dfe 719 uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
mbed_official 15:a81a8d6c1dfe 720 uint32_t :8; /*!< bit: 14..21 Reserved */
mbed_official 15:a81a8d6c1dfe 721 uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
mbed_official 15:a81a8d6c1dfe 722 uint32_t CMD:2; /*!< bit: 24..25 Software Command */
mbed_official 15:a81a8d6c1dfe 723 uint32_t :6; /*!< bit: 26..31 Reserved */
mbed_official 15:a81a8d6c1dfe 724 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 725 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 726 } DMAC_CHCTRLB_Type;
mbed_official 15:a81a8d6c1dfe 727 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 728
mbed_official 15:a81a8d6c1dfe 729 #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
mbed_official 15:a81a8d6c1dfe 730 #define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
mbed_official 15:a81a8d6c1dfe 731
mbed_official 15:a81a8d6c1dfe 732 #define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
mbed_official 15:a81a8d6c1dfe 733 #define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 734 #define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)))
mbed_official 15:a81a8d6c1dfe 735 #define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
mbed_official 15:a81a8d6c1dfe 736 #define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
mbed_official 15:a81a8d6c1dfe 737 #define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
mbed_official 15:a81a8d6c1dfe 738 #define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
mbed_official 15:a81a8d6c1dfe 739 #define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
mbed_official 15:a81a8d6c1dfe 740 #define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
mbed_official 15:a81a8d6c1dfe 741 #define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
mbed_official 15:a81a8d6c1dfe 742 #define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 743 #define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 744 #define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 745 #define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 746 #define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 747 #define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 748 #define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
mbed_official 15:a81a8d6c1dfe 749 #define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
mbed_official 15:a81a8d6c1dfe 750 #define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
mbed_official 15:a81a8d6c1dfe 751 #define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
mbed_official 15:a81a8d6c1dfe 752 #define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
mbed_official 15:a81a8d6c1dfe 753 #define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
mbed_official 15:a81a8d6c1dfe 754 #define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos)
mbed_official 15:a81a8d6c1dfe 755 #define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)))
mbed_official 15:a81a8d6c1dfe 756 #define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
mbed_official 15:a81a8d6c1dfe 757 #define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
mbed_official 15:a81a8d6c1dfe 758 #define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
mbed_official 15:a81a8d6c1dfe 759 #define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
mbed_official 15:a81a8d6c1dfe 760 #define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
mbed_official 15:a81a8d6c1dfe 761 #define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
mbed_official 15:a81a8d6c1dfe 762 #define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
mbed_official 15:a81a8d6c1dfe 763 #define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
mbed_official 15:a81a8d6c1dfe 764 #define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
mbed_official 15:a81a8d6c1dfe 765 #define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
mbed_official 15:a81a8d6c1dfe 766 #define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)))
mbed_official 15:a81a8d6c1dfe 767 #define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
mbed_official 15:a81a8d6c1dfe 768 #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
mbed_official 15:a81a8d6c1dfe 769 #define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
mbed_official 15:a81a8d6c1dfe 770 #define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
mbed_official 15:a81a8d6c1dfe 771 #define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)))
mbed_official 15:a81a8d6c1dfe 772 #define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
mbed_official 15:a81a8d6c1dfe 773 #define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
mbed_official 15:a81a8d6c1dfe 774 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
mbed_official 15:a81a8d6c1dfe 775 #define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
mbed_official 15:a81a8d6c1dfe 776 #define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
mbed_official 15:a81a8d6c1dfe 777 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
mbed_official 15:a81a8d6c1dfe 778 #define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
mbed_official 15:a81a8d6c1dfe 779 #define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos)
mbed_official 15:a81a8d6c1dfe 780 #define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)))
mbed_official 15:a81a8d6c1dfe 781 #define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
mbed_official 15:a81a8d6c1dfe 782 #define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
mbed_official 15:a81a8d6c1dfe 783 #define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
mbed_official 15:a81a8d6c1dfe 784 #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
mbed_official 15:a81a8d6c1dfe 785 #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
mbed_official 15:a81a8d6c1dfe 786 #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
mbed_official 15:a81a8d6c1dfe 787 #define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
mbed_official 15:a81a8d6c1dfe 788
mbed_official 15:a81a8d6c1dfe 789 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 790 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 791 typedef union {
mbed_official 15:a81a8d6c1dfe 792 struct {
mbed_official 15:a81a8d6c1dfe 793 uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 794 uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 795 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 796 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 797 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 798 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 799 } DMAC_CHINTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 800 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 801
mbed_official 15:a81a8d6c1dfe 802 #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 803 #define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 804
mbed_official 15:a81a8d6c1dfe 805 #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 806 #define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
mbed_official 15:a81a8d6c1dfe 807 #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 808 #define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
mbed_official 15:a81a8d6c1dfe 809 #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 810 #define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
mbed_official 15:a81a8d6c1dfe 811 #define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 812
mbed_official 15:a81a8d6c1dfe 813 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 814 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 815 typedef union {
mbed_official 15:a81a8d6c1dfe 816 struct {
mbed_official 15:a81a8d6c1dfe 817 uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 818 uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 819 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 820 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 821 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 822 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 823 } DMAC_CHINTENSET_Type;
mbed_official 15:a81a8d6c1dfe 824 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 825
mbed_official 15:a81a8d6c1dfe 826 #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 827 #define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 828
mbed_official 15:a81a8d6c1dfe 829 #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 830 #define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos)
mbed_official 15:a81a8d6c1dfe 831 #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 832 #define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
mbed_official 15:a81a8d6c1dfe 833 #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 834 #define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
mbed_official 15:a81a8d6c1dfe 835 #define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 836
mbed_official 15:a81a8d6c1dfe 837 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 838 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 839 typedef union {
mbed_official 15:a81a8d6c1dfe 840 struct {
mbed_official 15:a81a8d6c1dfe 841 uint8_t TERR:1; /*!< bit: 0 Transfer Error */
mbed_official 15:a81a8d6c1dfe 842 uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
mbed_official 15:a81a8d6c1dfe 843 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
mbed_official 15:a81a8d6c1dfe 844 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 845 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 846 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 847 } DMAC_CHINTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 848 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 849
mbed_official 15:a81a8d6c1dfe 850 #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 851 #define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 852
mbed_official 15:a81a8d6c1dfe 853 #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Transfer Error */
mbed_official 15:a81a8d6c1dfe 854 #define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
mbed_official 15:a81a8d6c1dfe 855 #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
mbed_official 15:a81a8d6c1dfe 856 #define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
mbed_official 15:a81a8d6c1dfe 857 #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
mbed_official 15:a81a8d6c1dfe 858 #define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
mbed_official 15:a81a8d6c1dfe 859 #define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 860
mbed_official 15:a81a8d6c1dfe 861 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
mbed_official 15:a81a8d6c1dfe 862 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 863 typedef union {
mbed_official 15:a81a8d6c1dfe 864 struct {
mbed_official 15:a81a8d6c1dfe 865 uint8_t PEND:1; /*!< bit: 0 Channel Pending */
mbed_official 15:a81a8d6c1dfe 866 uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
mbed_official 15:a81a8d6c1dfe 867 uint8_t FERR:1; /*!< bit: 2 Fetch Error */
mbed_official 15:a81a8d6c1dfe 868 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 869 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 870 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 871 } DMAC_CHSTATUS_Type;
mbed_official 15:a81a8d6c1dfe 872 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 873
mbed_official 15:a81a8d6c1dfe 874 #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
mbed_official 15:a81a8d6c1dfe 875 #define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
mbed_official 15:a81a8d6c1dfe 876
mbed_official 15:a81a8d6c1dfe 877 #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
mbed_official 15:a81a8d6c1dfe 878 #define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos)
mbed_official 15:a81a8d6c1dfe 879 #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
mbed_official 15:a81a8d6c1dfe 880 #define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
mbed_official 15:a81a8d6c1dfe 881 #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Fetch Error */
mbed_official 15:a81a8d6c1dfe 882 #define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos)
mbed_official 15:a81a8d6c1dfe 883 #define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 884
mbed_official 15:a81a8d6c1dfe 885 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
mbed_official 15:a81a8d6c1dfe 886 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 887 typedef union {
mbed_official 15:a81a8d6c1dfe 888 struct {
mbed_official 15:a81a8d6c1dfe 889 uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
mbed_official 15:a81a8d6c1dfe 890 uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
mbed_official 15:a81a8d6c1dfe 891 uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
mbed_official 15:a81a8d6c1dfe 892 uint16_t :3; /*!< bit: 5.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 893 uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
mbed_official 15:a81a8d6c1dfe 894 uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
mbed_official 15:a81a8d6c1dfe 895 uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
mbed_official 15:a81a8d6c1dfe 896 uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
mbed_official 15:a81a8d6c1dfe 897 uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
mbed_official 15:a81a8d6c1dfe 898 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 899 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 900 } DMAC_BTCTRL_Type;
mbed_official 15:a81a8d6c1dfe 901 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 902
mbed_official 15:a81a8d6c1dfe 903 #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
mbed_official 15:a81a8d6c1dfe 904
mbed_official 15:a81a8d6c1dfe 905 #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
mbed_official 15:a81a8d6c1dfe 906 #define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos)
mbed_official 15:a81a8d6c1dfe 907 #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
mbed_official 15:a81a8d6c1dfe 908 #define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
mbed_official 15:a81a8d6c1dfe 909 #define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)))
mbed_official 15:a81a8d6c1dfe 910 #define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */
mbed_official 15:a81a8d6c1dfe 911 #define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
mbed_official 15:a81a8d6c1dfe 912 #define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
mbed_official 15:a81a8d6c1dfe 913 #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
mbed_official 15:a81a8d6c1dfe 914 #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
mbed_official 15:a81a8d6c1dfe 915 #define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
mbed_official 15:a81a8d6c1dfe 916 #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
mbed_official 15:a81a8d6c1dfe 917 #define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
mbed_official 15:a81a8d6c1dfe 918 #define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)))
mbed_official 15:a81a8d6c1dfe 919 #define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) No action */
mbed_official 15:a81a8d6c1dfe 920 #define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
mbed_official 15:a81a8d6c1dfe 921 #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
mbed_official 15:a81a8d6c1dfe 922 #define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
mbed_official 15:a81a8d6c1dfe 923 #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
mbed_official 15:a81a8d6c1dfe 924 #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
mbed_official 15:a81a8d6c1dfe 925 #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
mbed_official 15:a81a8d6c1dfe 926 #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
mbed_official 15:a81a8d6c1dfe 927 #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
mbed_official 15:a81a8d6c1dfe 928 #define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 929 #define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)))
mbed_official 15:a81a8d6c1dfe 930 #define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit access */
mbed_official 15:a81a8d6c1dfe 931 #define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit access */
mbed_official 15:a81a8d6c1dfe 932 #define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit access */
mbed_official 15:a81a8d6c1dfe 933 #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 934 #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 935 #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 936 #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
mbed_official 15:a81a8d6c1dfe 937 #define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
mbed_official 15:a81a8d6c1dfe 938 #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
mbed_official 15:a81a8d6c1dfe 939 #define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
mbed_official 15:a81a8d6c1dfe 940 #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
mbed_official 15:a81a8d6c1dfe 941 #define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
mbed_official 15:a81a8d6c1dfe 942 #define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
mbed_official 15:a81a8d6c1dfe 943 #define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
mbed_official 15:a81a8d6c1dfe 944 #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
mbed_official 15:a81a8d6c1dfe 945 #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
mbed_official 15:a81a8d6c1dfe 946 #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
mbed_official 15:a81a8d6c1dfe 947 #define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 948 #define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)))
mbed_official 15:a81a8d6c1dfe 949 #define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 1 */
mbed_official 15:a81a8d6c1dfe 950 #define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 2 */
mbed_official 15:a81a8d6c1dfe 951 #define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 4 */
mbed_official 15:a81a8d6c1dfe 952 #define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 8 */
mbed_official 15:a81a8d6c1dfe 953 #define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 16 */
mbed_official 15:a81a8d6c1dfe 954 #define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 32 */
mbed_official 15:a81a8d6c1dfe 955 #define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 64 */
mbed_official 15:a81a8d6c1dfe 956 #define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 128 */
mbed_official 15:a81a8d6c1dfe 957 #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 958 #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 959 #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 960 #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 961 #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 962 #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 963 #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 964 #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 965 #define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 966
mbed_official 15:a81a8d6c1dfe 967 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
mbed_official 15:a81a8d6c1dfe 968 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 969 typedef union {
mbed_official 15:a81a8d6c1dfe 970 struct {
mbed_official 15:a81a8d6c1dfe 971 uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
mbed_official 15:a81a8d6c1dfe 972 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 973 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 974 } DMAC_BTCNT_Type;
mbed_official 15:a81a8d6c1dfe 975 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 976
mbed_official 15:a81a8d6c1dfe 977 #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
mbed_official 15:a81a8d6c1dfe 978
mbed_official 15:a81a8d6c1dfe 979 #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
mbed_official 15:a81a8d6c1dfe 980 #define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
mbed_official 15:a81a8d6c1dfe 981 #define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)))
mbed_official 15:a81a8d6c1dfe 982 #define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */
mbed_official 15:a81a8d6c1dfe 983
mbed_official 15:a81a8d6c1dfe 984 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
mbed_official 15:a81a8d6c1dfe 985 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 986 typedef union {
mbed_official 15:a81a8d6c1dfe 987 struct {
mbed_official 15:a81a8d6c1dfe 988 uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
mbed_official 15:a81a8d6c1dfe 989 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 990 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 991 } DMAC_SRCADDR_Type;
mbed_official 15:a81a8d6c1dfe 992 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 993
mbed_official 15:a81a8d6c1dfe 994 #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */
mbed_official 15:a81a8d6c1dfe 995
mbed_official 15:a81a8d6c1dfe 996 #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
mbed_official 15:a81a8d6c1dfe 997 #define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
mbed_official 15:a81a8d6c1dfe 998 #define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 999 #define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 1000
mbed_official 15:a81a8d6c1dfe 1001 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
mbed_official 15:a81a8d6c1dfe 1002 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1003 typedef union {
mbed_official 15:a81a8d6c1dfe 1004 struct {
mbed_official 15:a81a8d6c1dfe 1005 uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
mbed_official 15:a81a8d6c1dfe 1006 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1007 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1008 } DMAC_DSTADDR_Type;
mbed_official 15:a81a8d6c1dfe 1009 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1010
mbed_official 15:a81a8d6c1dfe 1011 #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */
mbed_official 15:a81a8d6c1dfe 1012
mbed_official 15:a81a8d6c1dfe 1013 #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
mbed_official 15:a81a8d6c1dfe 1014 #define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
mbed_official 15:a81a8d6c1dfe 1015 #define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 1016 #define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 1017
mbed_official 15:a81a8d6c1dfe 1018 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
mbed_official 15:a81a8d6c1dfe 1019 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1020 typedef union {
mbed_official 15:a81a8d6c1dfe 1021 struct {
mbed_official 15:a81a8d6c1dfe 1022 uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
mbed_official 15:a81a8d6c1dfe 1023 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1024 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1025 } DMAC_DESCADDR_Type;
mbed_official 15:a81a8d6c1dfe 1026 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1027
mbed_official 15:a81a8d6c1dfe 1028 #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
mbed_official 15:a81a8d6c1dfe 1029
mbed_official 15:a81a8d6c1dfe 1030 #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
mbed_official 15:a81a8d6c1dfe 1031 #define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
mbed_official 15:a81a8d6c1dfe 1032 #define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 1033 #define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 1034
mbed_official 15:a81a8d6c1dfe 1035 /** \brief DMAC APB hardware registers */
mbed_official 15:a81a8d6c1dfe 1036 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1037 typedef struct {
mbed_official 15:a81a8d6c1dfe 1038 __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
mbed_official 15:a81a8d6c1dfe 1039 __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
mbed_official 15:a81a8d6c1dfe 1040 __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
mbed_official 15:a81a8d6c1dfe 1041 __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
mbed_official 15:a81a8d6c1dfe 1042 __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
mbed_official 15:a81a8d6c1dfe 1043 __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
mbed_official 15:a81a8d6c1dfe 1044 __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
mbed_official 15:a81a8d6c1dfe 1045 RoReg8 Reserved1[0x1];
mbed_official 15:a81a8d6c1dfe 1046 __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
mbed_official 15:a81a8d6c1dfe 1047 __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
mbed_official 15:a81a8d6c1dfe 1048 RoReg8 Reserved2[0x8];
mbed_official 15:a81a8d6c1dfe 1049 __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
mbed_official 15:a81a8d6c1dfe 1050 RoReg8 Reserved3[0x2];
mbed_official 15:a81a8d6c1dfe 1051 __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
mbed_official 15:a81a8d6c1dfe 1052 __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
mbed_official 15:a81a8d6c1dfe 1053 __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
mbed_official 15:a81a8d6c1dfe 1054 __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
mbed_official 15:a81a8d6c1dfe 1055 __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
mbed_official 15:a81a8d6c1dfe 1056 __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
mbed_official 15:a81a8d6c1dfe 1057 RoReg8 Reserved4[0x3];
mbed_official 15:a81a8d6c1dfe 1058 __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
mbed_official 15:a81a8d6c1dfe 1059 __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
mbed_official 15:a81a8d6c1dfe 1060 RoReg8 Reserved5[0x3];
mbed_official 15:a81a8d6c1dfe 1061 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
mbed_official 15:a81a8d6c1dfe 1062 RoReg8 Reserved6[0x4];
mbed_official 15:a81a8d6c1dfe 1063 __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1064 __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1065 __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1066 __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
mbed_official 15:a81a8d6c1dfe 1067 } Dmac;
mbed_official 15:a81a8d6c1dfe 1068 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1069
mbed_official 15:a81a8d6c1dfe 1070 /** \brief DMAC Descriptor SRAM registers */
mbed_official 15:a81a8d6c1dfe 1071 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1072 typedef struct {
mbed_official 15:a81a8d6c1dfe 1073 __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
mbed_official 15:a81a8d6c1dfe 1074 __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
mbed_official 15:a81a8d6c1dfe 1075 __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
mbed_official 15:a81a8d6c1dfe 1076 __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
mbed_official 15:a81a8d6c1dfe 1077 __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
mbed_official 15:a81a8d6c1dfe 1078 } DmacDescriptor
mbed_official 15:a81a8d6c1dfe 1079 #ifdef __GNUC__
mbed_official 15:a81a8d6c1dfe 1080 __attribute__ ((aligned (8)))
mbed_official 15:a81a8d6c1dfe 1081 #endif
mbed_official 15:a81a8d6c1dfe 1082 ;
mbed_official 15:a81a8d6c1dfe 1083 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1084 #define SECTION_DMAC_DESCRIPTOR
mbed_official 15:a81a8d6c1dfe 1085
mbed_official 15:a81a8d6c1dfe 1086 /*@}*/
mbed_official 15:a81a8d6c1dfe 1087
mbed_official 15:a81a8d6c1dfe 1088 #endif /* _SAMD21_DMAC_COMPONENT_ */