Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
151:5eaa88a5bcc7 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * @file sleep.c
<> 149:156823d33999 4 * @brief Implementation of an sleep functionality
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 0.1 $
<> 149:156823d33999 8 * $Date: 01-21-2016 $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup sleep
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * Sleep implementation
<> 149:156823d33999 31 *
<> 149:156823d33999 32 */
<> 149:156823d33999 33 #if DEVICE_SLEEP
<> 149:156823d33999 34 #include "sleep.h"
<> 149:156823d33999 35 #include "sleep_api.h"
<> 149:156823d33999 36 #include "cmsis_nvic.h"
<> 149:156823d33999 37
<> 149:156823d33999 38 #define ENABLE (uint8_t)0x01
<> 149:156823d33999 39 #define DISABLE (uint8_t)0x00
<> 149:156823d33999 40 #define MAC_LUT_SIZE (uint8_t)96
<> 149:156823d33999 41
<> 149:156823d33999 42 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
<> 149:156823d33999 43 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
<> 149:156823d33999 44 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
<> 149:156823d33999 45 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
<> 149:156823d33999 46
<> 150:02e0a0aed4ec 47 void fncs36510_sleep(void)
<> 149:156823d33999 48 {
<> 149:156823d33999 49 /** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */
<> 149:156823d33999 50 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 149:156823d33999 51 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
<> 149:156823d33999 52
<> 149:156823d33999 53 /* Enter into sleep mode */
<> 149:156823d33999 54 __ISB();
<> 149:156823d33999 55 __WFI();
<> 149:156823d33999 56 }
<> 149:156823d33999 57
<> 150:02e0a0aed4ec 58 void fncs36510_deepsleep(void)
<> 149:156823d33999 59 {
<> 149:156823d33999 60 /** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */
<> 149:156823d33999 61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 149:156823d33999 62 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
<> 149:156823d33999 63
<> 149:156823d33999 64 /** Enter into deep sleep mode */
<> 149:156823d33999 65 __ISB();
<> 149:156823d33999 66 __WFI();
<> 149:156823d33999 67
<> 149:156823d33999 68 /** Wait for the external 32MHz to be power-ed up & running
<> 149:156823d33999 69 * Re-power down the 32MHz internal osc
<> 149:156823d33999 70 */
<> 149:156823d33999 71 while (!CLOCKREG->CSR.BITS.XTAL32M);
<> 149:156823d33999 72 PMUREG->CONTROL.BITS.INT32M = 1;
<> 149:156823d33999 73 }
<> 149:156823d33999 74
<> 150:02e0a0aed4ec 75 void fncs36510_coma(void)
<> 149:156823d33999 76 {
<> 149:156823d33999 77 /** Set SLEEPDEEP (SCR) and set COMA to select coma mode */
<> 149:156823d33999 78 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 149:156823d33999 79 PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
<> 149:156823d33999 80
<> 149:156823d33999 81 /* TODO Wait till MAC is idle */
<> 149:156823d33999 82 // while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
<> 149:156823d33999 83
<> 149:156823d33999 84 /* TODO Back up MAC_LUT *
<> 149:156823d33999 85 uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];
<> 149:156823d33999 86 fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */
<> 149:156823d33999 87
<> 149:156823d33999 88 /* Disable UART 1 & 2 FIFO during coma*/
<> 149:156823d33999 89 UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
<> 149:156823d33999 90 UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
<> 149:156823d33999 91
<> 149:156823d33999 92 /** Enter into coma mode */
<> 149:156823d33999 93 __ISB();
<> 149:156823d33999 94 __WFI();
<> 149:156823d33999 95
<> 149:156823d33999 96 /** Wait for the external 32MHz to be power-ed up & running
<> 149:156823d33999 97 * Re-power down the 32MHz internal osc
<> 149:156823d33999 98 */
<> 149:156823d33999 99 while (!CLOCKREG->CSR.BITS.XTAL32M);
<> 149:156823d33999 100 PMUREG->CONTROL.BITS.INT32M = 1;
<> 149:156823d33999 101
<> 149:156823d33999 102 /** Trim the oscillators */
<> 149:156823d33999 103 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 151:5eaa88a5bcc7 104 CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;
<> 149:156823d33999 105 }
<> 149:156823d33999 106 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 151:5eaa88a5bcc7 107 CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;
<> 149:156823d33999 108 }
<> 149:156823d33999 109
<> 149:156823d33999 110 /* Enable UART 1 & 2 FIFO */
<> 149:156823d33999 111 UART1REG->FCR.WORD |= FCR_FIFO_ENABLE;
<> 149:156823d33999 112 UART2REG->FCR.WORD |= FCR_FIFO_ENABLE;
<> 149:156823d33999 113
<> 149:156823d33999 114 /* TODO Restore MAC_LUT *
<> 149:156823d33999 115 fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */
<> 149:156823d33999 116 }
<> 149:156823d33999 117
<> 149:156823d33999 118 #endif /* DEVICE_SLEEP */