mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_spi.c@144:ef7eb2e8f9f7
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /****************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file spi.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @version V0.10 |
<> | 144:ef7eb2e8f9f7 | 4 | * $Revision: 15 $ |
<> | 144:ef7eb2e8f9f7 | 5 | * $Date: 14/09/30 1:10p $ |
<> | 144:ef7eb2e8f9f7 | 6 | * @brief NUC472/NUC442 SPI driver source file |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * @note |
<> | 144:ef7eb2e8f9f7 | 9 | * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 10 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 11 | #include "NUC472_442.h" |
<> | 144:ef7eb2e8f9f7 | 12 | |
<> | 144:ef7eb2e8f9f7 | 13 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
<> | 144:ef7eb2e8f9f7 | 14 | @{ |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | |
<> | 144:ef7eb2e8f9f7 | 17 | /** @addtogroup NUC472_442_SPI_Driver SPI Driver |
<> | 144:ef7eb2e8f9f7 | 18 | @{ |
<> | 144:ef7eb2e8f9f7 | 19 | */ |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | /** @addtogroup NUC472_442_SPI_EXPORTED_FUNCTIONS SPI Exported Functions |
<> | 144:ef7eb2e8f9f7 | 23 | @{ |
<> | 144:ef7eb2e8f9f7 | 24 | */ |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | /** |
<> | 144:ef7eb2e8f9f7 | 27 | * @brief This function make SPI module be ready to transfer. |
<> | 144:ef7eb2e8f9f7 | 28 | * By default, the SPI transfer sequence is MSB first and |
<> | 144:ef7eb2e8f9f7 | 29 | * the automatic slave select function is disabled. In |
<> | 144:ef7eb2e8f9f7 | 30 | * Slave mode, the u32BusClock must be NULL and the SPI clock |
<> | 144:ef7eb2e8f9f7 | 31 | * divider setting will be 0. |
<> | 144:ef7eb2e8f9f7 | 32 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 33 | * @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 34 | * - \ref SPI_SLAVE |
<> | 144:ef7eb2e8f9f7 | 35 | * - \ref SPI_MASTER |
<> | 144:ef7eb2e8f9f7 | 36 | * @param[in] u32SPIMode decides the transfer timing. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 37 | * - \ref SPI_MODE_0 |
<> | 144:ef7eb2e8f9f7 | 38 | * - \ref SPI_MODE_1 |
<> | 144:ef7eb2e8f9f7 | 39 | * - \ref SPI_MODE_2 |
<> | 144:ef7eb2e8f9f7 | 40 | * - \ref SPI_MODE_3 |
<> | 144:ef7eb2e8f9f7 | 41 | * @param[in] u32DataWidth decides the data width of a SPI transaction. |
<> | 144:ef7eb2e8f9f7 | 42 | * @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz. |
<> | 144:ef7eb2e8f9f7 | 43 | * @return Actual frequency of SPI peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 44 | */ |
<> | 144:ef7eb2e8f9f7 | 45 | uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) |
<> | 144:ef7eb2e8f9f7 | 46 | { |
<> | 144:ef7eb2e8f9f7 | 47 | if(u32DataWidth == 32) |
<> | 144:ef7eb2e8f9f7 | 48 | u32DataWidth = 0; |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode); |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | return ( SPI_SetBusClock(spi, u32BusClock) ); |
<> | 144:ef7eb2e8f9f7 | 53 | } |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | /** |
<> | 144:ef7eb2e8f9f7 | 56 | * @brief Reset SPI module and disable SPI peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 57 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 58 | * @return none |
<> | 144:ef7eb2e8f9f7 | 59 | */ |
<> | 144:ef7eb2e8f9f7 | 60 | void SPI_Close(SPI_T *spi) |
<> | 144:ef7eb2e8f9f7 | 61 | { |
<> | 144:ef7eb2e8f9f7 | 62 | /* Reset SPI */ |
<> | 144:ef7eb2e8f9f7 | 63 | if((uint32_t)spi == SPI0_BASE) { |
<> | 144:ef7eb2e8f9f7 | 64 | SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 65 | SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 66 | } else if((uint32_t)spi == SPI1_BASE) { |
<> | 144:ef7eb2e8f9f7 | 67 | SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 68 | SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 69 | } else if((uint32_t)spi == SPI2_BASE) { |
<> | 144:ef7eb2e8f9f7 | 70 | SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 71 | SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 72 | } else { |
<> | 144:ef7eb2e8f9f7 | 73 | SYS->IPRST1 |= SYS_IPRST1_SPI3RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 74 | SYS->IPRST1 &= ~SYS_IPRST1_SPI3RST_Msk; |
<> | 144:ef7eb2e8f9f7 | 75 | } |
<> | 144:ef7eb2e8f9f7 | 76 | } |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | /** |
<> | 144:ef7eb2e8f9f7 | 79 | * @brief Clear Rx FIFO buffer. |
<> | 144:ef7eb2e8f9f7 | 80 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 81 | * @return none |
<> | 144:ef7eb2e8f9f7 | 82 | */ |
<> | 144:ef7eb2e8f9f7 | 83 | void SPI_ClearRxFIFO(SPI_T *spi) |
<> | 144:ef7eb2e8f9f7 | 84 | { |
<> | 144:ef7eb2e8f9f7 | 85 | spi->FIFOCTL |= SPI_FIFOCTL_RXRST_Msk; |
<> | 144:ef7eb2e8f9f7 | 86 | } |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | /** |
<> | 144:ef7eb2e8f9f7 | 89 | * @brief Clear Tx FIFO buffer. |
<> | 144:ef7eb2e8f9f7 | 90 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 91 | * @return none |
<> | 144:ef7eb2e8f9f7 | 92 | */ |
<> | 144:ef7eb2e8f9f7 | 93 | void SPI_ClearTxFIFO(SPI_T *spi) |
<> | 144:ef7eb2e8f9f7 | 94 | { |
<> | 144:ef7eb2e8f9f7 | 95 | spi->FIFOCTL |= SPI_FIFOCTL_TXRST_Msk; |
<> | 144:ef7eb2e8f9f7 | 96 | } |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | /** |
<> | 144:ef7eb2e8f9f7 | 99 | * @brief Disable the automatic slave select function. |
<> | 144:ef7eb2e8f9f7 | 100 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 101 | * @return none |
<> | 144:ef7eb2e8f9f7 | 102 | */ |
<> | 144:ef7eb2e8f9f7 | 103 | void SPI_DisableAutoSS(SPI_T *spi) |
<> | 144:ef7eb2e8f9f7 | 104 | { |
<> | 144:ef7eb2e8f9f7 | 105 | spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk; |
<> | 144:ef7eb2e8f9f7 | 106 | } |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | /** |
<> | 144:ef7eb2e8f9f7 | 109 | * @brief Enable the automatic slave select function. Only available in Master mode. |
<> | 144:ef7eb2e8f9f7 | 110 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 111 | * @param[in] u32SSPinMask specifies slave select pins. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 112 | * - \ref SPI_SS0 |
<> | 144:ef7eb2e8f9f7 | 113 | * - \ref SPI_SS1 |
<> | 144:ef7eb2e8f9f7 | 114 | * @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 115 | * - \ref SPI_SS_ACTIVE_HIGH |
<> | 144:ef7eb2e8f9f7 | 116 | * - \ref SPI_SS_ACTIVE_LOW |
<> | 144:ef7eb2e8f9f7 | 117 | * @return none |
<> | 144:ef7eb2e8f9f7 | 118 | */ |
<> | 144:ef7eb2e8f9f7 | 119 | void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) |
<> | 144:ef7eb2e8f9f7 | 120 | { |
<> | 144:ef7eb2e8f9f7 | 121 | spi->SSCTL |= (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk; |
<> | 144:ef7eb2e8f9f7 | 122 | } |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | /** |
<> | 144:ef7eb2e8f9f7 | 125 | * @brief Set the SPI bus clock. Only available in Master mode. |
<> | 144:ef7eb2e8f9f7 | 126 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 127 | * @param[in] u32BusClock is the expected frequency of SPI bus clock. |
<> | 144:ef7eb2e8f9f7 | 128 | * @return Actual frequency of SPI peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 129 | */ |
<> | 144:ef7eb2e8f9f7 | 130 | uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) |
<> | 144:ef7eb2e8f9f7 | 131 | { |
<> | 144:ef7eb2e8f9f7 | 132 | uint32_t u32ClkSrc, u32Div = 0; |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | if(spi == SPI0) { |
<> | 144:ef7eb2e8f9f7 | 135 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 136 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 137 | else |
<> | 144:ef7eb2e8f9f7 | 138 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 139 | } else if(spi == SPI1) { |
<> | 144:ef7eb2e8f9f7 | 140 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 141 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 142 | else |
<> | 144:ef7eb2e8f9f7 | 143 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 144 | } else if(spi == SPI2) { |
<> | 144:ef7eb2e8f9f7 | 145 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 146 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 147 | else |
<> | 144:ef7eb2e8f9f7 | 148 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 149 | } else { |
<> | 144:ef7eb2e8f9f7 | 150 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 151 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 152 | else |
<> | 144:ef7eb2e8f9f7 | 153 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 154 | } |
<> | 144:ef7eb2e8f9f7 | 155 | |
<> | 144:ef7eb2e8f9f7 | 156 | |
<> | 144:ef7eb2e8f9f7 | 157 | if(u32BusClock != 0 ) { |
<> | 144:ef7eb2e8f9f7 | 158 | u32Div = (u32ClkSrc / u32BusClock) - 1; |
<> | 144:ef7eb2e8f9f7 | 159 | if(u32Div > SPI_CLKDIV_DIVIDER_Msk) |
<> | 144:ef7eb2e8f9f7 | 160 | u32Div = SPI_CLKDIV_DIVIDER_Msk; |
<> | 144:ef7eb2e8f9f7 | 161 | } |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div; |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | return ( u32ClkSrc / (u32Div+1) ); |
<> | 144:ef7eb2e8f9f7 | 166 | } |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | /** |
<> | 144:ef7eb2e8f9f7 | 169 | * @brief Set Tx FIFO threshold and Rx FIFO threshold configurations. |
<> | 144:ef7eb2e8f9f7 | 170 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 171 | * @param[in] u32TxThreshold decides the Tx FIFO threshold. |
<> | 144:ef7eb2e8f9f7 | 172 | * @param[in] u32RxThreshold decides the Rx FIFO threshold. |
<> | 144:ef7eb2e8f9f7 | 173 | * @return none |
<> | 144:ef7eb2e8f9f7 | 174 | */ |
<> | 144:ef7eb2e8f9f7 | 175 | void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) |
<> | 144:ef7eb2e8f9f7 | 176 | { |
<> | 144:ef7eb2e8f9f7 | 177 | spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) | |
<> | 144:ef7eb2e8f9f7 | 178 | (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | |
<> | 144:ef7eb2e8f9f7 | 179 | (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos)); |
<> | 144:ef7eb2e8f9f7 | 180 | } |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | /** |
<> | 144:ef7eb2e8f9f7 | 183 | * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. |
<> | 144:ef7eb2e8f9f7 | 184 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 185 | * @return Actual SPI bus clock frequency. |
<> | 144:ef7eb2e8f9f7 | 186 | */ |
<> | 144:ef7eb2e8f9f7 | 187 | uint32_t SPI_GetBusClock(SPI_T *spi) |
<> | 144:ef7eb2e8f9f7 | 188 | { |
<> | 144:ef7eb2e8f9f7 | 189 | uint32_t u32Div; |
<> | 144:ef7eb2e8f9f7 | 190 | uint32_t u32ClkSrc; |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | if(spi == SPI0) { |
<> | 144:ef7eb2e8f9f7 | 193 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 194 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 195 | else |
<> | 144:ef7eb2e8f9f7 | 196 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 197 | } else if(spi == SPI1) { |
<> | 144:ef7eb2e8f9f7 | 198 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 199 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 200 | else |
<> | 144:ef7eb2e8f9f7 | 201 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 202 | } else if(spi == SPI2) { |
<> | 144:ef7eb2e8f9f7 | 203 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 204 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 205 | else |
<> | 144:ef7eb2e8f9f7 | 206 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 207 | } else { |
<> | 144:ef7eb2e8f9f7 | 208 | if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK) |
<> | 144:ef7eb2e8f9f7 | 209 | u32ClkSrc = CLK_GetPCLKFreq(); |
<> | 144:ef7eb2e8f9f7 | 210 | else |
<> | 144:ef7eb2e8f9f7 | 211 | u32ClkSrc = CLK_GetPLLClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 212 | } |
<> | 144:ef7eb2e8f9f7 | 213 | |
<> | 144:ef7eb2e8f9f7 | 214 | u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk; |
<> | 144:ef7eb2e8f9f7 | 215 | return (u32ClkSrc / (u32Div + 1)); |
<> | 144:ef7eb2e8f9f7 | 216 | } |
<> | 144:ef7eb2e8f9f7 | 217 | |
<> | 144:ef7eb2e8f9f7 | 218 | /** |
<> | 144:ef7eb2e8f9f7 | 219 | * @brief Enable FIFO related interrupts specified by u32Mask parameter. |
<> | 144:ef7eb2e8f9f7 | 220 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 221 | * @param[in] u32Mask is the combination of all related interrupt enable bits. |
<> | 144:ef7eb2e8f9f7 | 222 | * Each bit corresponds to a interrupt bit. |
<> | 144:ef7eb2e8f9f7 | 223 | * This parameter decides which interrupts will be enabled. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 224 | * - \ref SPI_UNITIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 225 | * - \ref SPI_SSINAIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 226 | * - \ref SPI_SSACTIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 227 | * - \ref SPI_SLVURIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 228 | * - \ref SPI_SLVBEIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 229 | * - \ref SPI_SLVTOIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 230 | * - \ref SPI_FIFO_TXTHIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 231 | * - \ref SPI_FIFO_RXTHIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 232 | * - \ref SPI_FIFO_RXOVIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 233 | * - \ref SPI_FIFO_TXUFIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 234 | * - \ref SPI_FIFO_RXTOIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 235 | * @return none |
<> | 144:ef7eb2e8f9f7 | 236 | */ |
<> | 144:ef7eb2e8f9f7 | 237 | void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) |
<> | 144:ef7eb2e8f9f7 | 238 | { |
<> | 144:ef7eb2e8f9f7 | 239 | if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 240 | spi->CTL |= SPI_CTL_UNITIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 243 | spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 244 | |
<> | 144:ef7eb2e8f9f7 | 245 | if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 246 | spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 249 | spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 252 | spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 255 | spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 258 | spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 261 | spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 264 | spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 265 | |
<> | 144:ef7eb2e8f9f7 | 266 | if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 267 | spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 270 | spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 271 | } |
<> | 144:ef7eb2e8f9f7 | 272 | |
<> | 144:ef7eb2e8f9f7 | 273 | /** |
<> | 144:ef7eb2e8f9f7 | 274 | * @brief Disable FIFO related interrupts specified by u32Mask parameter. |
<> | 144:ef7eb2e8f9f7 | 275 | * @param[in] spi is the base address of SPI module. |
<> | 144:ef7eb2e8f9f7 | 276 | * @param[in] u32Mask is the combination of all related interrupt enable bits. |
<> | 144:ef7eb2e8f9f7 | 277 | * Each bit corresponds to a interrupt bit. |
<> | 144:ef7eb2e8f9f7 | 278 | * This parameter decides which interrupts will be enabled. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 279 | * - \ref SPI_UNITIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 280 | * - \ref SPI_SSINAIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 281 | * - \ref SPI_SSACTIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 282 | * - \ref SPI_SLVURIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 283 | * - \ref SPI_SLVBEIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 284 | * - \ref SPI_SLVTOIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 285 | * - \ref SPI_FIFO_TXTHIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 286 | * - \ref SPI_FIFO_RXTHIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 287 | * - \ref SPI_FIFO_RXOVIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 288 | * - \ref SPI_FIFO_TXUFIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 289 | * - \ref SPI_FIFO_RXTOIEN_MASK |
<> | 144:ef7eb2e8f9f7 | 290 | * @return none |
<> | 144:ef7eb2e8f9f7 | 291 | */ |
<> | 144:ef7eb2e8f9f7 | 292 | void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) |
<> | 144:ef7eb2e8f9f7 | 293 | { |
<> | 144:ef7eb2e8f9f7 | 294 | if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 295 | spi->CTL &= ~SPI_CTL_UNITIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 296 | |
<> | 144:ef7eb2e8f9f7 | 297 | if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 298 | spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 299 | |
<> | 144:ef7eb2e8f9f7 | 300 | if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 301 | spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 302 | |
<> | 144:ef7eb2e8f9f7 | 303 | if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 304 | spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 307 | spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 310 | spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 311 | |
<> | 144:ef7eb2e8f9f7 | 312 | if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 313 | spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 314 | |
<> | 144:ef7eb2e8f9f7 | 315 | if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 316 | spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 319 | spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 322 | spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 323 | |
<> | 144:ef7eb2e8f9f7 | 324 | if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 325 | spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 326 | } |
<> | 144:ef7eb2e8f9f7 | 327 | |
<> | 144:ef7eb2e8f9f7 | 328 | /*@}*/ /* end of group NUC472_442_SPI_EXPORTED_FUNCTIONS */ |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | /*@}*/ /* end of group NUC472_442_SPI_Driver */ |
<> | 144:ef7eb2e8f9f7 | 331 | |
<> | 144:ef7eb2e8f9f7 | 332 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ |