mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_gpio.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_gpio.c@144:ef7eb2e8f9f7
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file gpio.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @version V1.00 |
<> | 144:ef7eb2e8f9f7 | 4 | * $Revision: 9 $ |
<> | 144:ef7eb2e8f9f7 | 5 | * $Date: 14/10/06 11:47a $ |
<> | 144:ef7eb2e8f9f7 | 6 | * @brief NUC472/NUC442 GPIO driver source file |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * @note |
<> | 144:ef7eb2e8f9f7 | 9 | * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 10 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 11 | #include "NUC472_442.h" |
<> | 144:ef7eb2e8f9f7 | 12 | |
<> | 144:ef7eb2e8f9f7 | 13 | |
<> | 144:ef7eb2e8f9f7 | 14 | |
<> | 144:ef7eb2e8f9f7 | 15 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
<> | 144:ef7eb2e8f9f7 | 16 | @{ |
<> | 144:ef7eb2e8f9f7 | 17 | */ |
<> | 144:ef7eb2e8f9f7 | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | /** @addtogroup NUC472_442_GPIO_Driver GPIO Driver |
<> | 144:ef7eb2e8f9f7 | 20 | @{ |
<> | 144:ef7eb2e8f9f7 | 21 | */ |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | /** @addtogroup NUC472_442_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions |
<> | 144:ef7eb2e8f9f7 | 25 | @{ |
<> | 144:ef7eb2e8f9f7 | 26 | */ |
<> | 144:ef7eb2e8f9f7 | 27 | |
<> | 144:ef7eb2e8f9f7 | 28 | /** |
<> | 144:ef7eb2e8f9f7 | 29 | * @brief Set GPIO operation mode |
<> | 144:ef7eb2e8f9f7 | 30 | * |
<> | 144:ef7eb2e8f9f7 | 31 | * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI |
<> | 144:ef7eb2e8f9f7 | 32 | * @param[in] u32PinMask The single or multiple pins of specified GPIO port. |
<> | 144:ef7eb2e8f9f7 | 33 | * @param[in] u32Mode Operation mode. \ref GPIO_MODE_INPUT, \ref GPIO_MODE_OUTPUT, \ref GPIO_MODE_OPEN_DRAIN, \ref GPIO_MODE_QUASI |
<> | 144:ef7eb2e8f9f7 | 34 | * |
<> | 144:ef7eb2e8f9f7 | 35 | * @return None |
<> | 144:ef7eb2e8f9f7 | 36 | * |
<> | 144:ef7eb2e8f9f7 | 37 | * @details This function is used to set specified GPIO operation mode. |
<> | 144:ef7eb2e8f9f7 | 38 | */ |
<> | 144:ef7eb2e8f9f7 | 39 | void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode) |
<> | 144:ef7eb2e8f9f7 | 40 | { |
<> | 144:ef7eb2e8f9f7 | 41 | uint32_t i; |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | for (i=0; i<GPIO_PIN_MAX; i++) { |
<> | 144:ef7eb2e8f9f7 | 44 | if (u32PinMask & (1 << i)) { |
<> | 144:ef7eb2e8f9f7 | 45 | gpio->MODE = (gpio->MODE & ~(0x3 << (i << 1))) | (u32Mode << (i << 1)); |
<> | 144:ef7eb2e8f9f7 | 46 | } |
<> | 144:ef7eb2e8f9f7 | 47 | } |
<> | 144:ef7eb2e8f9f7 | 48 | } |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | /** |
<> | 144:ef7eb2e8f9f7 | 51 | * @brief Enable GPIO interrupt |
<> | 144:ef7eb2e8f9f7 | 52 | * |
<> | 144:ef7eb2e8f9f7 | 53 | * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI |
<> | 144:ef7eb2e8f9f7 | 54 | * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. |
<> | 144:ef7eb2e8f9f7 | 55 | * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n |
<> | 144:ef7eb2e8f9f7 | 56 | * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, GPIO_INT_LOW |
<> | 144:ef7eb2e8f9f7 | 57 | * |
<> | 144:ef7eb2e8f9f7 | 58 | * @return None |
<> | 144:ef7eb2e8f9f7 | 59 | * |
<> | 144:ef7eb2e8f9f7 | 60 | * @details This function is used to enable specified GPIO pin interrupt. |
<> | 144:ef7eb2e8f9f7 | 61 | */ |
<> | 144:ef7eb2e8f9f7 | 62 | void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs) |
<> | 144:ef7eb2e8f9f7 | 63 | { |
<> | 144:ef7eb2e8f9f7 | 64 | gpio->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); |
<> | 144:ef7eb2e8f9f7 | 65 | gpio->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); |
<> | 144:ef7eb2e8f9f7 | 66 | } |
<> | 144:ef7eb2e8f9f7 | 67 | |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | /** |
<> | 144:ef7eb2e8f9f7 | 70 | * @brief Disable GPIO interrupt |
<> | 144:ef7eb2e8f9f7 | 71 | * |
<> | 144:ef7eb2e8f9f7 | 72 | * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI |
<> | 144:ef7eb2e8f9f7 | 73 | * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. |
<> | 144:ef7eb2e8f9f7 | 74 | * |
<> | 144:ef7eb2e8f9f7 | 75 | * @return None |
<> | 144:ef7eb2e8f9f7 | 76 | * |
<> | 144:ef7eb2e8f9f7 | 77 | * @details This function is used to disable specified GPIO pin interrupt. |
<> | 144:ef7eb2e8f9f7 | 78 | */ |
<> | 144:ef7eb2e8f9f7 | 79 | void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin) |
<> | 144:ef7eb2e8f9f7 | 80 | { |
<> | 144:ef7eb2e8f9f7 | 81 | gpio->INTTYPE &= ~(1UL << u32Pin); |
<> | 144:ef7eb2e8f9f7 | 82 | gpio->INTEN &= ~((0x00010001UL) << u32Pin); |
<> | 144:ef7eb2e8f9f7 | 83 | } |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | /*@}*/ /* end of group NUC472_442_GPIO_EXPORTED_FUNCTIONS */ |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | /*@}*/ /* end of group NUC472_442_GPIO_Driver */ |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |