mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.h@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /**************************************************************************//** |
<> | 149:156823d33999 | 2 | * @file CLK.h |
<> | 149:156823d33999 | 3 | * @version V1.0 |
<> | 149:156823d33999 | 4 | * $Revision 1 $ |
<> | 149:156823d33999 | 5 | * $Date: 14/10/06 1:50p $ |
<> | 149:156823d33999 | 6 | * @brief NUC472/NUC442 CLK Header File |
<> | 149:156823d33999 | 7 | * |
<> | 149:156823d33999 | 8 | * @note |
<> | 149:156823d33999 | 9 | * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. |
<> | 149:156823d33999 | 10 | ******************************************************************************/ |
<> | 149:156823d33999 | 11 | #ifndef __CLK_H__ |
<> | 149:156823d33999 | 12 | #define __CLK_H__ |
<> | 149:156823d33999 | 13 | |
<> | 149:156823d33999 | 14 | #ifdef __cplusplus |
<> | 149:156823d33999 | 15 | extern "C" |
<> | 149:156823d33999 | 16 | { |
<> | 149:156823d33999 | 17 | #endif |
<> | 149:156823d33999 | 18 | |
<> | 149:156823d33999 | 19 | |
<> | 149:156823d33999 | 20 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
<> | 149:156823d33999 | 21 | @{ |
<> | 149:156823d33999 | 22 | */ |
<> | 149:156823d33999 | 23 | |
<> | 149:156823d33999 | 24 | /** @addtogroup NUC472_442_CLK_Driver CLK Driver |
<> | 149:156823d33999 | 25 | @{ |
<> | 149:156823d33999 | 26 | */ |
<> | 149:156823d33999 | 27 | |
<> | 149:156823d33999 | 28 | |
<> | 149:156823d33999 | 29 | /** @addtogroup NUC472_442_CLK_EXPORTED_CONSTANTS CLK Exported Constants |
<> | 149:156823d33999 | 30 | @{ |
<> | 149:156823d33999 | 31 | */ |
<> | 149:156823d33999 | 32 | |
<> | 149:156823d33999 | 33 | #define FREQ_50MHZ 50000000 |
<> | 149:156823d33999 | 34 | #define FREQ_24MHZ 24000000 |
<> | 149:156823d33999 | 35 | #define FREQ_22MHZ 22000000 |
<> | 149:156823d33999 | 36 | #define FREQ_32KHZ 32767 |
<> | 149:156823d33999 | 37 | #define FREQ_10KHZ 10000 |
<> | 149:156823d33999 | 38 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 39 | /* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */ |
<> | 149:156823d33999 | 40 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 41 | #define CLK_PLLCTL_PLLSRC_HIRC (0x1UL<<CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is internal RC clock. 4MHz < FIN < 24MHz \hideinitializer */ |
<> | 149:156823d33999 | 42 | #define CLK_PLLCTL_PLLSRC_HXT (0x0UL<<CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is external crystal. 4MHz < FIN < 24MHz \hideinitializer */ |
<> | 149:156823d33999 | 43 | |
<> | 149:156823d33999 | 44 | #define CLK_PLLCTL_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 15MHz \hideinitializer */ |
<> | 149:156823d33999 | 45 | #define CLK_PLLCTL_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 100MHz < FIN*NF/NR < 200MHz. (120MHz < FIN*NF/NR < 200MHz is preferred.) \hideinitializer */ |
<> | 149:156823d33999 | 46 | |
<> | 149:156823d33999 | 47 | #define CLK_PLLCTL_NO_1 (0x0UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 1 \hideinitializer */ |
<> | 149:156823d33999 | 48 | #define CLK_PLLCTL_NO_2 (0x1UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 2 \hideinitializer */ |
<> | 149:156823d33999 | 49 | #define CLK_PLLCTL_NO_4 (0x3UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 4 \hideinitializer */ |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | #if (__HXT == 12000000) |
<> | 149:156823d33999 | 52 | #define CLK_PLLCTL_FOR_I2S (0xA54) /*!< Predefined PLLCTL setting for 147428571.428571Hz PLL output with 12MHz XTAL \hideinitializer */ |
<> | 149:156823d33999 | 53 | #define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 28) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz XTAL \hideinitializer */ |
<> | 149:156823d33999 | 54 | #define CLK_PLLCTL_50MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 25) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50MHz PLL output with 12MHz XTAL \hideinitializer */ |
<> | 149:156823d33999 | 55 | #define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF(112) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz XTAL \hideinitializer */ |
<> | 149:156823d33999 | 56 | #define CLK_PLLCTL_36MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF( 84) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 36MHz PLL output with 12MHz XTAL \hideinitializer */ |
<> | 149:156823d33999 | 57 | #define CLK_PLLCTL_32MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(6) | CLK_PLLCTL_NF( 64) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 32MHz PLL output with 12MHz XTAL \hideinitializer */ |
<> | 149:156823d33999 | 58 | #define CLK_PLLCTL_24MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 16) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 24MHz PLL output with 12MHz XTAL \hideinitializer */ |
<> | 149:156823d33999 | 59 | #else |
<> | 149:156823d33999 | 60 | # error "The PLL pre-definitions are only valid when external crystal is 12MHz" |
<> | 149:156823d33999 | 61 | #endif |
<> | 149:156823d33999 | 62 | |
<> | 149:156823d33999 | 63 | #define CLK_PLLCTL_50MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF( 59) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50.1918MHz PLL output with 22.1184MHz IRC \hideinitializer */ |
<> | 149:156823d33999 | 64 | #define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48.064985MHz PLL output with 22.1184MHz IRC \hideinitializer */ |
<> | 149:156823d33999 | 65 | #define CLK_PLLCTL_36MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(12) | CLK_PLLCTL_NF( 78) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 35.9424MHz PLL output with 22.1184MHz IRC \hideinitializer */ |
<> | 149:156823d33999 | 66 | #define CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 9) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 31.9488MHz PLL output with 22.1184MHz IRC \hideinitializer */ |
<> | 149:156823d33999 | 67 | #define CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 3) | CLK_PLLCTL_NF( 13) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 23.9616MHz PLL output with 22.1184MHz IRC \hideinitializer */ |
<> | 149:156823d33999 | 68 | |
<> | 149:156823d33999 | 69 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 70 | /* PLL2CTL constant definitions. */ |
<> | 149:156823d33999 | 71 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 72 | #define CLK_PLL2CTL_USPLL(x) (((x)-1) << CLK_PLL2CTL_PLL2DIV_Pos) /*!< USBPLL clock frequency = (480 MHz) / 2 / (USB_N + 1). It could be 1~256, Max. PLL frequency :480MHz / 2 when XTL12M. \hideinitializer */ |
<> | 149:156823d33999 | 73 | #define CLK_PLL2CTL_USBPLL_DIS (0x00UL<<CLK_PLL2CTL_PLL2CKEN_Pos) /*!< USB PHY PLL (480MHz) Disable \hideinitializer */ |
<> | 149:156823d33999 | 74 | #define CLK_PLL2CTL_PLL2CKEN (0x01UL<<CLK_PLL2CTL_PLL2CKEN_Pos) /*!< USB PHY PLL (480MHz) Enable \hideinitializer */ |
<> | 149:156823d33999 | 75 | |
<> | 149:156823d33999 | 76 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 77 | /* CLKSEL0 constant definitions. (Write-protection) */ |
<> | 149:156823d33999 | 78 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 79 | #define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 80 | #define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 81 | #define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL output \hideinitializer */ |
<> | 149:156823d33999 | 82 | #define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 83 | #define CLK_CLKSEL0_HCLKSEL_USBPLL (0x04UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as USBPLL clock \hideinitializer */ |
<> | 149:156823d33999 | 84 | #define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 85 | |
<> | 149:156823d33999 | 86 | #define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 87 | #define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 88 | #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL/2 \hideinitializer */ |
<> | 149:156823d33999 | 89 | #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */ |
<> | 149:156823d33999 | 90 | #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock/2 \hideinitializer */ |
<> | 149:156823d33999 | 91 | |
<> | 149:156823d33999 | 92 | #define CLK_CLKSEL0_PCLKSEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */ |
<> | 149:156823d33999 | 93 | #define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */ |
<> | 149:156823d33999 | 94 | |
<> | 149:156823d33999 | 95 | #define CLK_CLKSEL0_USBHSEL_PLL2 (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */ |
<> | 149:156823d33999 | 96 | #define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 97 | |
<> | 149:156823d33999 | 98 | #define CLK_CLKSEL0_EMACSEL_PLL (0x01UL<<10) /*!< Setting clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 99 | |
<> | 149:156823d33999 | 100 | #define CLK_CLKSEL0_CAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 101 | #define CLK_CLKSEL0_CAPSEL_PLL2 (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */ |
<> | 149:156823d33999 | 102 | #define CLK_CLKSEL0_CAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */ |
<> | 149:156823d33999 | 103 | #define CLK_CLKSEL0_CAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 104 | |
<> | 149:156823d33999 | 105 | #define CLK_CLKSEL0_SDHSEL_HXT (0x00UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 106 | #define CLK_CLKSEL0_SDHSEL_PLL (0x01UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */ |
<> | 149:156823d33999 | 107 | #define CLK_CLKSEL0_SDHSEL_HCLK (0x02UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */ |
<> | 149:156823d33999 | 108 | #define CLK_CLKSEL0_SDHSEL_HIRC (0x03UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 109 | |
<> | 149:156823d33999 | 110 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 111 | /* CLKSEL1 constant definitions. */ |
<> | 149:156823d33999 | 112 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 113 | #define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 114 | #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 \hideinitializer */ |
<> | 149:156823d33999 | 115 | #define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 116 | |
<> | 149:156823d33999 | 117 | #define CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 118 | #define CLK_CLKSEL1_ADCSEL_PLL (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 119 | #define CLK_CLKSEL1_ADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 120 | #define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 121 | |
<> | 149:156823d33999 | 122 | #define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 123 | #define CLK_CLKSEL1_SPI0SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 124 | |
<> | 149:156823d33999 | 125 | #define CLK_CLKSEL1_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 126 | #define CLK_CLKSEL1_SPI1SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 127 | |
<> | 149:156823d33999 | 128 | #define CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 129 | #define CLK_CLKSEL1_SPI2SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 130 | |
<> | 149:156823d33999 | 131 | #define CLK_CLKSEL1_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 132 | #define CLK_CLKSEL1_SPI3SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 133 | |
<> | 149:156823d33999 | 134 | #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 135 | #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 136 | #define CLK_CLKSEL1_TMR0SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 137 | #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger \hideinitializer */ |
<> | 149:156823d33999 | 138 | #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 139 | #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 140 | |
<> | 149:156823d33999 | 141 | #define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 142 | #define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 143 | #define CLK_CLKSEL1_TMR1SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 144 | #define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger \hideinitializer */ |
<> | 149:156823d33999 | 145 | #define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 146 | #define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 147 | |
<> | 149:156823d33999 | 148 | #define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 149 | #define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 150 | #define CLK_CLKSEL1_TMR2SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 151 | #define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger \hideinitializer */ |
<> | 149:156823d33999 | 152 | #define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 153 | #define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 154 | |
<> | 149:156823d33999 | 155 | #define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 156 | #define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 157 | #define CLK_CLKSEL1_TMR3SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 158 | #define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger \hideinitializer */ |
<> | 149:156823d33999 | 159 | #define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 160 | #define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 161 | |
<> | 149:156823d33999 | 162 | #define CLK_CLKSEL1_UARTSEL_HXT (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 163 | #define CLK_CLKSEL1_UARTSEL_PLL (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external PLL \hideinitializer */ |
<> | 149:156823d33999 | 164 | #define CLK_CLKSEL1_UARTSEL_HIRC (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 165 | |
<> | 149:156823d33999 | 166 | #define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 167 | #define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 168 | #define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK \hideinitializer */ |
<> | 149:156823d33999 | 169 | #define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 170 | |
<> | 149:156823d33999 | 171 | #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting CLKO clock source as HCLK/2048 \hideinitializer */ |
<> | 149:156823d33999 | 172 | #define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting CLKO clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 173 | |
<> | 149:156823d33999 | 174 | |
<> | 149:156823d33999 | 175 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 176 | /* CLKSEL2 constant definitions. */ |
<> | 149:156823d33999 | 177 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 178 | #define CLK_CLKSEL2_PWM0CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 179 | #define CLK_CLKSEL2_PWM0CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 180 | #define CLK_CLKSEL2_PWM0CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 181 | #define CLK_CLKSEL2_PWM0CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 182 | #define CLK_CLKSEL2_PWM0CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 183 | |
<> | 149:156823d33999 | 184 | #define CLK_CLKSEL2_PWM0CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 185 | #define CLK_CLKSEL2_PWM0CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 186 | #define CLK_CLKSEL2_PWM0CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 187 | #define CLK_CLKSEL2_PWM0CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 188 | #define CLK_CLKSEL2_PWM0CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 189 | |
<> | 149:156823d33999 | 190 | #define CLK_CLKSEL2_PWM0CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 191 | #define CLK_CLKSEL2_PWM0CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 192 | #define CLK_CLKSEL2_PWM0CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 193 | #define CLK_CLKSEL2_PWM0CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 194 | #define CLK_CLKSEL2_PWM0CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 195 | |
<> | 149:156823d33999 | 196 | #define CLK_CLKSEL2_PWM1CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 197 | #define CLK_CLKSEL2_PWM1CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 198 | #define CLK_CLKSEL2_PWM1CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 199 | #define CLK_CLKSEL2_PWM1CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 200 | #define CLK_CLKSEL2_PWM1CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 201 | |
<> | 149:156823d33999 | 202 | #define CLK_CLKSEL2_PWM1CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 203 | #define CLK_CLKSEL2_PWM1CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 204 | #define CLK_CLKSEL2_PWM1CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 205 | #define CLK_CLKSEL2_PWM1CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 206 | #define CLK_CLKSEL2_PWM1CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 207 | |
<> | 149:156823d33999 | 208 | #define CLK_CLKSEL2_PWM1CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 209 | #define CLK_CLKSEL2_PWM1CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz \hideinitializer */ |
<> | 149:156823d33999 | 210 | #define CLK_CLKSEL2_PWM1CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 211 | #define CLK_CLKSEL2_PWM1CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 212 | #define CLK_CLKSEL2_PWM1CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 213 | |
<> | 149:156823d33999 | 214 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 215 | /* CLKSEL3 constant definitions. */ |
<> | 149:156823d33999 | 216 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 217 | #define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 218 | #define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 219 | #define CLK_CLKSEL3_SC0SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 220 | #define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 221 | |
<> | 149:156823d33999 | 222 | #define CLK_CLKSEL3_SC1SEL_HXT (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 223 | #define CLK_CLKSEL3_SC1SEL_PLL (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 224 | #define CLK_CLKSEL3_SC1SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 225 | #define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 226 | |
<> | 149:156823d33999 | 227 | #define CLK_CLKSEL3_SC2SEL_HXT (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 228 | #define CLK_CLKSEL3_SC2SEL_PLL (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 229 | #define CLK_CLKSEL3_SC2SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 230 | #define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 231 | |
<> | 149:156823d33999 | 232 | #define CLK_CLKSEL3_SC3SEL_HXT (0x0UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 233 | #define CLK_CLKSEL3_SC3SEL_PLL (0x1UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 234 | #define CLK_CLKSEL3_SC3SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 235 | #define CLK_CLKSEL3_SC3SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 236 | |
<> | 149:156823d33999 | 237 | #define CLK_CLKSEL3_SC4SEL_HXT (0x0UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 238 | #define CLK_CLKSEL3_SC4SEL_PLL (0x1UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 239 | #define CLK_CLKSEL3_SC4SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 240 | #define CLK_CLKSEL3_SC4SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 241 | |
<> | 149:156823d33999 | 242 | #define CLK_CLKSEL3_SC5SEL_HXT (0x0UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 243 | #define CLK_CLKSEL3_SC5SEL_PLL (0x1UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 244 | #define CLK_CLKSEL3_SC5SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 245 | #define CLK_CLKSEL3_SC5SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 246 | |
<> | 149:156823d33999 | 247 | #define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 248 | #define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 249 | #define CLK_CLKSEL3_I2S0SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 250 | #define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 251 | |
<> | 149:156823d33999 | 252 | #define CLK_CLKSEL3_I2S1SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as external XTAL \hideinitializer */ |
<> | 149:156823d33999 | 253 | #define CLK_CLKSEL3_I2S1SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as PLL \hideinitializer */ |
<> | 149:156823d33999 | 254 | #define CLK_CLKSEL3_I2S1SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as PCLK \hideinitializer */ |
<> | 149:156823d33999 | 255 | #define CLK_CLKSEL3_I2S1SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as internal 22.1184MHz RC clock \hideinitializer */ |
<> | 149:156823d33999 | 256 | |
<> | 149:156823d33999 | 257 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 258 | /* CLKDIV0 constant definitions. */ |
<> | 149:156823d33999 | 259 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 260 | #define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 \hideinitializer */ |
<> | 149:156823d33999 | 261 | #define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBHDIV_Pos) /*!< CLKDIV Setting for USB clock divider. It could be 1~16 \hideinitializer */ |
<> | 149:156823d33999 | 262 | #define CLK_CLKDIV0_UART(x) (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLKDIV Setting for UR clock divider. It could be 1~16 \hideinitializer */ |
<> | 149:156823d33999 | 263 | #define CLK_CLKDIV0_ADC(x) (((x)-1) << CLK_CLKDIV0_ADCDIV_Pos) /*!< CLKDIV Setting for ADC clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 264 | #define CLK_CLKDIV0_SDH(x) (((x)-1) << CLK_CLKDIV0_SDHDIV_Pos) /*!< CLKDIV Setting for SDIO clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 265 | |
<> | 149:156823d33999 | 266 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 267 | /* CLKDIV1 constant definitions. */ |
<> | 149:156823d33999 | 268 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 269 | #define CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV Setting for SC0 clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 270 | #define CLK_CLKDIV1_SC1(x) (((x)-1) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV Setting for SC1 clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 271 | #define CLK_CLKDIV1_SC2(x) (((x)-1) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV Setting for SC2 clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 272 | #define CLK_CLKDIV1_SC3(x) (((x)-1) << CLK_CLKDIV1_SC3DIV_Pos) /*!< CLKDIV Setting for SC3 clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 273 | |
<> | 149:156823d33999 | 274 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 275 | /* CLKDIV2 constant definitions. */ |
<> | 149:156823d33999 | 276 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 277 | #define CLK_CLKDIV2_SC4(x) (((x)-1) << CLK_CLKDIV2_SC4DIV_Pos) /*!< CLKDIV Setting for SC4 clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 278 | #define CLK_CLKDIV2_SC5(x) (((x)-1) << CLK_CLKDIV2_SC5DIV_Pos) /*!< CLKDIV Setting for SC5 clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 279 | |
<> | 149:156823d33999 | 280 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 281 | /* CLKDIV3 constant definitions. */ |
<> | 149:156823d33999 | 282 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 283 | #define CLK_CLKDIV3_CAP(x) (((x)-1) << CLK_CLKDIV3_ICAPDIV_Pos) /*!< CLKDIV Setting for CAP Engine clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 284 | #define CLK_CLKDIV3_VASENSOR(x) (((x)-1) << CLK_CLKDIV3_VASENSORDIV_Pos) /*!< CLKDIV Setting for Video Pixel clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 285 | #define CLK_CLKDIV3_EMAC(x) (((x)-1) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV Setting for EMAC_MDCLK clock divider. It could be 1~256 \hideinitializer */ |
<> | 149:156823d33999 | 286 | |
<> | 149:156823d33999 | 287 | |
<> | 149:156823d33999 | 288 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 289 | /* MODULE constant definitions. */ |
<> | 149:156823d33999 | 290 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 291 | #define MODULE_AHPBCLK(x) ((x >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 292 | #define MODULE_CLKSEL(x) ((x >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 293 | #define MODULE_CLKSEL_Msk(x) ((x >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 294 | #define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 295 | #define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 296 | #define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 297 | #define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 298 | #define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 299 | #define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index \hideinitializer */ |
<> | 149:156823d33999 | 300 | /*--------------------------------------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 301 | /* AHBCLK/APBCLK(2) | CLKSEL(2) | CLKSEL_Msk(3) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/ |
<> | 149:156823d33999 | 302 | /*--------------------------------------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 303 | #define PDMA_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_PDMACKEN_Pos) /*!< PDMA Module \hideinitializer */ |
<> | 149:156823d33999 | 304 | #define ISP_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos) /*!< ISP Module \hideinitializer */ |
<> | 149:156823d33999 | 305 | #define EBI_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBICKEN_Pos) /*!< EBI Module \hideinitializer */ |
<> | 149:156823d33999 | 306 | #define USBH_MODULE ((0UL<<30)|(0<<28)|(1<<25) |( 8<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_AHBCLK_USBHCKEN_Pos) /*!< USBH Module \hideinitializer */ |
<> | 149:156823d33999 | 307 | #define EMAC_MODULE ((0UL<<30)|(0<<28)|(1<<25) |(10<<20)|(3<<18)|(0xFF<<10) |(16<<5)|CLK_AHBCLK_EMACCKEN_Pos) /*!< EMAC Module \hideinitializer */ |
<> | 149:156823d33999 | 308 | #define SDH_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(20<<20)|(0<<18)|(0xFF<<10) |(24<<5)|CLK_AHBCLK_SDHCKEN_Pos) /*!< SDH Module \hideinitializer */ |
<> | 149:156823d33999 | 309 | #define CRC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRCCKEN_Pos) /*!< CRC Module \hideinitializer */ |
<> | 149:156823d33999 | 310 | #define CAP_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(16<<20)|(3<<18)|(0xFF<<10) |( 0<<5)|CLK_AHBCLK_ICAPCKEN_Pos) /*!< CAP Module \hideinitializer */ |
<> | 149:156823d33999 | 311 | #define SENCLK_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(3<<18)|(0xFF<<10) |( 8<<5)|CLK_AHBCLK_SENCLKCKEN_Pos) /*!< Sensor Clock Module \hideinitializer */ |
<> | 149:156823d33999 | 312 | #define USBD_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_USBDCKEN_Pos) /*!< USBD Module \hideinitializer */ |
<> | 149:156823d33999 | 313 | #define CRPT_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRPTCKEN_Pos) /*!< CRYPTO Module \hideinitializer */ |
<> | 149:156823d33999 | 314 | |
<> | 149:156823d33999 | 315 | #define WDT_MODULE ((1UL<<30)|(3<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Watchdog Timer Module \hideinitializer */ |
<> | 149:156823d33999 | 316 | #define WWDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(30<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Window Watchdog Timer Module \hideinitializer */ |
<> | 149:156823d33999 | 317 | #define RTC_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_RTCCKEN_Pos) /*!< RTC Module \hideinitializer */ |
<> | 149:156823d33999 | 318 | #define TMR0_MODULE ((1UL<<30)|(1<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR0CKEN_Pos) /*!< Timer0 Module \hideinitializer */ |
<> | 149:156823d33999 | 319 | #define TMR1_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR1CKEN_Pos) /*!< Timer1 Module \hideinitializer */ |
<> | 149:156823d33999 | 320 | #define TMR2_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR2CKEN_Pos) /*!< Timer2 Module \hideinitializer */ |
<> | 149:156823d33999 | 321 | #define TMR3_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR3CKEN_Pos) /*!< Timer3 Module \hideinitializer */ |
<> | 149:156823d33999 | 322 | #define CLKO_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(28<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLKO Module \hideinitializer */ |
<> | 149:156823d33999 | 323 | #define ACMP_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_ACMPCKEN_Pos) /*!< ACMP Module \hideinitializer */ |
<> | 149:156823d33999 | 324 | #define I2C0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C0CKEN_Pos) /*!< I2C0 Module \hideinitializer */ |
<> | 149:156823d33999 | 325 | #define I2C1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C1CKEN_Pos) /*!< I2C1 Module \hideinitializer */ |
<> | 149:156823d33999 | 326 | #define I2C2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C2CKEN_Pos) /*!< I2C2 Module \hideinitializer */ |
<> | 149:156823d33999 | 327 | #define I2C3_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C3CKEN_Pos) /*!< I2C3 Module \hideinitializer */ |
<> | 149:156823d33999 | 328 | #define SPI0_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI0CKEN_Pos) /*!< SPI0 Module \hideinitializer */ |
<> | 149:156823d33999 | 329 | #define SPI1_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 5<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI1CKEN_Pos) /*!< SPI1 Module \hideinitializer */ |
<> | 149:156823d33999 | 330 | #define SPI2_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI2CKEN_Pos) /*!< SPI2 Module \hideinitializer */ |
<> | 149:156823d33999 | 331 | #define SPI3_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 7<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI3CKEN_Pos) /*!< SPI3 Module \hideinitializer */ |
<> | 149:156823d33999 | 332 | #define UART0_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART0CKEN_Pos) /*!< UART0 Module \hideinitializer */ |
<> | 149:156823d33999 | 333 | #define UART1_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART1CKEN_Pos) /*!< UART1 Module \hideinitializer */ |
<> | 149:156823d33999 | 334 | #define UART2_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART2CKEN_Pos) /*!< UART2 Module \hideinitializer */ |
<> | 149:156823d33999 | 335 | #define UART3_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART3CKEN_Pos) /*!< UART3 Module \hideinitializer */ |
<> | 149:156823d33999 | 336 | #define UART4_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART4CKEN_Pos) /*!< UART4 Module \hideinitializer */ |
<> | 149:156823d33999 | 337 | #define UART5_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART5CKEN_Pos) /*!< UART5 Module \hideinitializer */ |
<> | 149:156823d33999 | 338 | #define CAN0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN0CKEN_Pos) /*!< CAN0 Module \hideinitializer */ |
<> | 149:156823d33999 | 339 | #define CAN1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN1CKEN_Pos) /*!< CAN1 Module \hideinitializer */ |
<> | 149:156823d33999 | 340 | #define OTG_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_OTGCKEN_Pos) /*!< OTG Module \hideinitializer */ |
<> | 149:156823d33999 | 341 | #define ADC_MODULE ((1UL<<30)|(1<<28)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK0_ADCCKEN_Pos) /*!< ADC Module \hideinitializer */ |
<> | 149:156823d33999 | 342 | #define I2S0_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S0CKEN_Pos) /*!< I2S0 Module \hideinitializer */ |
<> | 149:156823d33999 | 343 | #define I2S1_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S1CKEN_Pos) /*!< I2S1 Module \hideinitializer */ |
<> | 149:156823d33999 | 344 | #define PS2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_PS2CKEN_Pos) /*!< PS2 Module \hideinitializer */ |
<> | 149:156823d33999 | 345 | |
<> | 149:156823d33999 | 346 | #define SC0_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 0<<20)|(1<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC0CKEN_Pos) /*!< SmartCard0 Module \hideinitializer */ |
<> | 149:156823d33999 | 347 | #define SC1_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 2<<20)|(1<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC1CKEN_Pos) /*!< SmartCard1 Module \hideinitializer */ |
<> | 149:156823d33999 | 348 | #define SC2_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 4<<20)|(1<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK1_SC2CKEN_Pos) /*!< SmartCard2 Module \hideinitializer */ |
<> | 149:156823d33999 | 349 | #define SC3_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 6<<20)|(1<<18)|(0xFF<<10) |(24<<5)|CLK_APBCLK1_SC3CKEN_Pos) /*!< SmartCard3 Module \hideinitializer */ |
<> | 149:156823d33999 | 350 | #define SC4_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 8<<20)|(2<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC4CKEN_Pos) /*!< SmartCard4 Module \hideinitializer */ |
<> | 149:156823d33999 | 351 | #define SC5_MODULE ((2UL<<30)|(3<<28)|(3<<25) |(10<<20)|(2<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC5CKEN_Pos) /*!< SmartCard5 Module \hideinitializer */ |
<> | 149:156823d33999 | 352 | #define I2C4_MODULE ((2UL<<30)|(0<<28)|(0<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos) /*!< I2C4 Module */ |
<> | 149:156823d33999 | 353 | #define PWM0CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH01CKEN_Pos) /*!< PWM0CH01 Module \hideinitializer */ |
<> | 149:156823d33999 | 354 | #define PWM0CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH23CKEN_Pos) /*!< PWM0CH23 Module \hideinitializer */ |
<> | 149:156823d33999 | 355 | #define PWM0CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH45CKEN_Pos) /*!< PWM0CH45 Module \hideinitializer */ |
<> | 149:156823d33999 | 356 | #define PWM1CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH01CKEN_Pos) /*!< PWM1CH01 Module \hideinitializer */ |
<> | 149:156823d33999 | 357 | #define PWM1CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH23CKEN_Pos) /*!< PWM1CH23 Module \hideinitializer */ |
<> | 149:156823d33999 | 358 | #define PWM1CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH45CKEN_Pos) /*!< PWM1CH45 Module \hideinitializer */ |
<> | 149:156823d33999 | 359 | #define QEI0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI0CKEN_Pos) /*!< QEI0 Module \hideinitializer */ |
<> | 149:156823d33999 | 360 | #define QEI1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI1CKEN_Pos) /*!< QEI1 Module \hideinitializer */ |
<> | 149:156823d33999 | 361 | #define TAMPER_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_TAMPERCKEN_Pos) /*!< TAMPER Module \hideinitializer */ |
<> | 149:156823d33999 | 362 | #define ECAP0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP0CKEN_Pos) /*!< ECAP0 Module \hideinitializer */ |
<> | 149:156823d33999 | 363 | #define ECAP1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP1CKEN_Pos) /*!< ECAP1 Module \hideinitializer */ |
<> | 149:156823d33999 | 364 | #define EPWM0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM0CKEN_Pos) /*!< EPWM0 Module \hideinitializer */ |
<> | 149:156823d33999 | 365 | #define EPWM1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM1CKEN_Pos) /*!< EPWM1 Module \hideinitializer */ |
<> | 149:156823d33999 | 366 | #define OPA_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_OPACKEN_Pos) /*!< OPA Module \hideinitializer */ |
<> | 149:156823d33999 | 367 | #define EADC_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EADCCKEN_Pos) /*!< EADC Module \hideinitializer */ |
<> | 149:156823d33999 | 368 | |
<> | 149:156823d33999 | 369 | /*@}*/ /* end of group NUC472_442_CLK_EXPORTED_CONSTANTS */ |
<> | 149:156823d33999 | 370 | |
<> | 149:156823d33999 | 371 | |
<> | 149:156823d33999 | 372 | /** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions |
<> | 149:156823d33999 | 373 | @{ |
<> | 149:156823d33999 | 374 | */ |
<> | 149:156823d33999 | 375 | |
<> | 149:156823d33999 | 376 | void CLK_DisableCKO(void); |
<> | 149:156823d33999 | 377 | void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); |
<> | 149:156823d33999 | 378 | void CLK_PowerDown(void); |
<> | 149:156823d33999 | 379 | void CLK_Idle(void); |
<> | 149:156823d33999 | 380 | uint32_t CLK_GetHXTFreq(void); |
<> | 149:156823d33999 | 381 | uint32_t CLK_GetLXTFreq(void); |
<> | 149:156823d33999 | 382 | uint32_t CLK_GetHCLKFreq(void); |
<> | 149:156823d33999 | 383 | uint32_t CLK_GetPCLKFreq(void); |
<> | 149:156823d33999 | 384 | uint32_t CLK_GetCPUFreq(void); |
<> | 149:156823d33999 | 385 | uint32_t CLK_GetPLLClockFreq(void); |
<> | 149:156823d33999 | 386 | uint32_t CLK_SetCoreClock(uint32_t u32Hclk); |
<> | 149:156823d33999 | 387 | void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); |
<> | 149:156823d33999 | 388 | void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); |
<> | 149:156823d33999 | 389 | void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); |
<> | 149:156823d33999 | 390 | void CLK_EnableXtalRC(uint32_t u32ClkMask); |
<> | 149:156823d33999 | 391 | void CLK_DisableXtalRC(uint32_t u32ClkMask); |
<> | 149:156823d33999 | 392 | void CLK_EnableModuleClock(uint32_t u32ModuleIdx); |
<> | 149:156823d33999 | 393 | void CLK_DisableModuleClock(uint32_t u32ModuleIdx); |
<> | 149:156823d33999 | 394 | uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); |
<> | 149:156823d33999 | 395 | void CLK_DisablePLL(void); |
<> | 149:156823d33999 | 396 | void CLK_SysTickDelay(uint32_t us); |
<> | 149:156823d33999 | 397 | uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); |
<> | 149:156823d33999 | 398 | |
<> | 149:156823d33999 | 399 | /*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */ |
<> | 149:156823d33999 | 400 | |
<> | 149:156823d33999 | 401 | /*@}*/ /* end of group NUC472_442_CLK_Driver */ |
<> | 149:156823d33999 | 402 | |
<> | 149:156823d33999 | 403 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
<> | 149:156823d33999 | 404 | |
<> | 149:156823d33999 | 405 | #ifdef __cplusplus |
<> | 149:156823d33999 | 406 | } |
<> | 149:156823d33999 | 407 | #endif |
<> | 149:156823d33999 | 408 | |
<> | 149:156823d33999 | 409 | #endif //__CLK_H__ |
<> | 149:156823d33999 | 410 | |
<> | 149:156823d33999 | 411 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |