Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**************************************************************************//**
<> 149:156823d33999 2 * @file SYS.h
<> 149:156823d33999 3 * @version V3.0
<> 149:156823d33999 4 * $Revision 1 $
<> 149:156823d33999 5 * $Date: 15/08/11 10:26a $
<> 149:156823d33999 6 * @brief M451 Series SYS Header File
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 ******************************************************************************/
<> 149:156823d33999 11
<> 149:156823d33999 12 #ifndef __SYS_H__
<> 149:156823d33999 13 #define __SYS_H__
<> 149:156823d33999 14
<> 149:156823d33999 15 #ifdef __cplusplus
<> 149:156823d33999 16 extern "C"
<> 149:156823d33999 17 {
<> 149:156823d33999 18 #endif
<> 149:156823d33999 19
<> 149:156823d33999 20 /** @addtogroup Standard_Driver Standard Driver
<> 149:156823d33999 21 @{
<> 149:156823d33999 22 */
<> 149:156823d33999 23
<> 149:156823d33999 24 /** @addtogroup SYS_Driver SYS Driver
<> 149:156823d33999 25 @{
<> 149:156823d33999 26 */
<> 149:156823d33999 27
<> 149:156823d33999 28 /** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
<> 149:156823d33999 29 @{
<> 149:156823d33999 30 */
<> 149:156823d33999 31
<> 149:156823d33999 32
<> 149:156823d33999 33 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 34 /* Module Reset Control Resister constant definitions. */
<> 149:156823d33999 35 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 36 #define PDMA_RST ((0x0<<24) | SYS_IPRST0_PDMARST_Pos ) /*!< Reset PDMA */
<> 149:156823d33999 37 #define EBI_RST ((0x0<<24) | SYS_IPRST0_EBIRST_Pos ) /*!< Reset EBI */
<> 149:156823d33999 38 #define USBH_RST ((0x0<<24) | SYS_IPRST0_USBHRST_Pos ) /*!< Reset USBH */
<> 149:156823d33999 39 #define CRC_RST ((0x0<<24) | SYS_IPRST0_CRCRST_Pos ) /*!< Reset CRC */
<> 149:156823d33999 40
<> 149:156823d33999 41 #define GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos ) /*!< Reset GPIO */
<> 149:156823d33999 42 #define TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos ) /*!< Reset TMR0 */
<> 149:156823d33999 43 #define TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos ) /*!< Reset TMR1 */
<> 149:156823d33999 44 #define TMR2_RST ((0x4<<24) | SYS_IPRST1_TMR2RST_Pos ) /*!< Reset TMR2 */
<> 149:156823d33999 45 #define TMR3_RST ((0x4<<24) | SYS_IPRST1_TMR3RST_Pos ) /*!< Reset TMR3 */
<> 149:156823d33999 46 #define ACMP01_RST ((0x4<<24) | SYS_IPRST1_ACMP01RST_Pos ) /*!< Reset ACMP01 */
<> 149:156823d33999 47 #define I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos ) /*!< Reset I2C0 */
<> 149:156823d33999 48 #define I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos ) /*!< Reset I2C1 */
<> 149:156823d33999 49 #define SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos ) /*!< Reset SPI0 */
<> 149:156823d33999 50 #define SPI1_RST ((0x4<<24) | SYS_IPRST1_SPI1RST_Pos ) /*!< Reset SPI1 */
<> 149:156823d33999 51 #define SPI2_RST ((0x4<<24) | SYS_IPRST1_SPI2RST_Pos ) /*!< Reset SPI2 */
<> 149:156823d33999 52 #define UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos ) /*!< Reset UART0 */
<> 149:156823d33999 53 #define UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos ) /*!< Reset UART1 */
<> 149:156823d33999 54 #define UART2_RST ((0x4<<24) | SYS_IPRST1_UART2RST_Pos ) /*!< Reset UART2 */
<> 149:156823d33999 55 #define UART3_RST ((0x4<<24) | SYS_IPRST1_UART3RST_Pos ) /*!< Reset UART3 */
<> 149:156823d33999 56 #define CAN0_RST ((0x4<<24) | SYS_IPRST1_CAN0RST_Pos ) /*!< Reset CAN0 */
<> 149:156823d33999 57 #define OTG_RST ((0x4<<24) | SYS_IPRST1_OTGRST_Pos ) /*!< Reset OTG */
<> 149:156823d33999 58 #define USBD_RST ((0x4<<24) | SYS_IPRST1_USBDRST_Pos ) /*!< Reset USBD */
<> 149:156823d33999 59 #define EADC_RST ((0x4<<24) | SYS_IPRST1_EADCRST_Pos ) /*!< Reset EADC */
<> 149:156823d33999 60
<> 149:156823d33999 61 #define SC0_RST ((0x8<<24) | SYS_IPRST2_SC0RST_Pos ) /*!< Reset SC0 */
<> 149:156823d33999 62 #define DAC_RST ((0x8<<24) | SYS_IPRST2_DACRST_Pos ) /*!< Reset DAC */
<> 149:156823d33999 63 #define PWM0_RST ((0x8<<24) | SYS_IPRST2_PWM0RST_Pos ) /*!< Reset PWM0 */
<> 149:156823d33999 64 #define PWM1_RST ((0x8<<24) | SYS_IPRST2_PWM1RST_Pos ) /*!< Reset PWM1 */
<> 149:156823d33999 65 #define TK_RST ((0x8<<24) | SYS_IPRST2_TKRST_Pos ) /*!< Reset TK */
<> 149:156823d33999 66
<> 149:156823d33999 67
<> 149:156823d33999 68 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 69 /* Brown Out Detector Threshold Voltage Selection constant definitions. */
<> 149:156823d33999 70 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 71 #define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */
<> 149:156823d33999 72 #define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */
<> 149:156823d33999 73 #define SYS_BODCTL_BODVL_4_5V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 4.5V */
<> 149:156823d33999 74 #define SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.7V */
<> 149:156823d33999 75 #define SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.7V */
<> 149:156823d33999 76 #define SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
<> 149:156823d33999 77
<> 149:156823d33999 78
<> 149:156823d33999 79 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 80 /* VREFCTL constant definitions. (Write-Protection Register) */
<> 149:156823d33999 81 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 82 #define SYS_VREFCTL_VREF_2_56V (0x3UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 2.56V */
<> 149:156823d33999 83 #define SYS_VREFCTL_VREF_2_048V (0x7UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 2.048V */
<> 149:156823d33999 84 #define SYS_VREFCTL_VREF_3_072V (0xBUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 3.072V */
<> 149:156823d33999 85 #define SYS_VREFCTL_VREF_4_096V (0xFUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 4.096V */
<> 149:156823d33999 86
<> 149:156823d33999 87
<> 149:156823d33999 88 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 89 /* USBPHY constant definitions. (Write-Protection Register) */
<> 149:156823d33999 90 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 91 #define SYS_USBPHY_USBROLE_OTG_V33_EN (0x1UL<<SYS_USBPHY_LDO33EN_Pos) /*!< USB LDO33 Enabled */
<> 149:156823d33999 92 #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */
<> 149:156823d33999 93 #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */
<> 149:156823d33999 94 #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */
<> 149:156823d33999 95 #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */
<> 149:156823d33999 96
<> 149:156823d33999 97
<> 149:156823d33999 98 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 99 /* Multi-Function constant definitions. */
<> 149:156823d33999 100 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 101 /* How to use below #define?
<> 149:156823d33999 102 Example 1: If user want to set PA.0 as SC0_CLK in initial function,
<> 149:156823d33999 103 user can issue following command to achieve it.
<> 149:156823d33999 104
<> 149:156823d33999 105 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
<> 149:156823d33999 106
<> 149:156823d33999 107 */
<> 149:156823d33999 108 //PA0 MFP
<> 149:156823d33999 109 #define SYS_GPA_MFPL_PA0MFP_GPIO (0ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO*/
<> 149:156823d33999 110 #define SYS_GPA_MFPL_PA0MFP_UART1_nCTS (1ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nCTS*/
<> 149:156823d33999 111 #define SYS_GPA_MFPL_PA0MFP_UART1_TXD (3ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_TXD*/
<> 149:156823d33999 112 #define SYS_GPA_MFPL_PA0MFP_CAN0_RXD (4ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for CAN0_RXD*/
<> 149:156823d33999 113 #define SYS_GPA_MFPL_PA0MFP_SC0_CLK (5ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CLK*/
<> 149:156823d33999 114 #define SYS_GPA_MFPL_PA0MFP_PWM1_CH5 (6ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for PWM1_CH5*/
<> 149:156823d33999 115 #define SYS_GPA_MFPL_PA0MFP_EBI_AD0 (7ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for EBI_AD0*/
<> 149:156823d33999 116 #define SYS_GPA_MFPL_PA0MFP_INT0 (8ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for INT0*/
<> 149:156823d33999 117 #define SYS_GPA_MFPL_PA0MFP_SPI1_I2SMCLK (9ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI1_I2SMCLK*/
<> 149:156823d33999 118
<> 149:156823d33999 119 //PA1 MFP
<> 149:156823d33999 120 #define SYS_GPA_MFPL_PA1MFP_GPIO (0ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO*/
<> 149:156823d33999 121 #define SYS_GPA_MFPL_PA1MFP_UART1_nRTS (1ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nRTS*/
<> 149:156823d33999 122 #define SYS_GPA_MFPL_PA1MFP_UART1_RXD (3ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_RXD*/
<> 149:156823d33999 123 #define SYS_GPA_MFPL_PA1MFP_CAN0_TXD (4ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for CAN0_TXD*/
<> 149:156823d33999 124 #define SYS_GPA_MFPL_PA1MFP_SC0_DAT (5ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC0_DAT*/
<> 149:156823d33999 125 #define SYS_GPA_MFPL_PA1MFP_PWM1_CH4 (6ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for PWM1_CH4*/
<> 149:156823d33999 126 #define SYS_GPA_MFPL_PA1MFP_EBI_AD1 (7ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EBI_AD1*/
<> 149:156823d33999 127 #define SYS_GPA_MFPL_PA1MFP_STADC (10ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for STADC*/
<> 149:156823d33999 128
<> 149:156823d33999 129 //PA2 MFP
<> 149:156823d33999 130 #define SYS_GPA_MFPL_PA2MFP_GPIO (0ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO*/
<> 149:156823d33999 131 #define SYS_GPA_MFPL_PA2MFP_USB_VBUS_EN (1ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for USB_VBUS_EN*/
<> 149:156823d33999 132 #define SYS_GPA_MFPL_PA2MFP_UART0_TXD (2ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_TXD*/
<> 149:156823d33999 133 #define SYS_GPA_MFPL_PA2MFP_UART0_nCTS (3ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_nCTS*/
<> 149:156823d33999 134 #define SYS_GPA_MFPL_PA2MFP_I2C0_SDA (4ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C0_SDA*/
<> 149:156823d33999 135 #define SYS_GPA_MFPL_PA2MFP_SC0_RST (5ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC0_RST*/
<> 149:156823d33999 136 #define SYS_GPA_MFPL_PA2MFP_PWM1_CH3 (6ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for PWM1_CH3*/
<> 149:156823d33999 137 #define SYS_GPA_MFPL_PA2MFP_EBI_AD2 (7ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EBI_AD2*/
<> 149:156823d33999 138
<> 149:156823d33999 139 //PA3 MFP
<> 149:156823d33999 140 #define SYS_GPA_MFPL_PA3MFP_GPIO (0ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO*/
<> 149:156823d33999 141 #define SYS_GPA_MFPL_PA3MFP_USB_VBUS_ST (1ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for USB_VBUS_ST*/
<> 149:156823d33999 142 #define SYS_GPA_MFPL_PA3MFP_UART0_RXD (2ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_RXD*/
<> 149:156823d33999 143 #define SYS_GPA_MFPL_PA3MFP_UART0_nRTS (3ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_nRTS*/
<> 149:156823d33999 144 #define SYS_GPA_MFPL_PA3MFP_I2C0_SCL (4ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C0_SCL*/
<> 149:156823d33999 145 #define SYS_GPA_MFPL_PA3MFP_SC0_PWR (5ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC0_PWR*/
<> 149:156823d33999 146 #define SYS_GPA_MFPL_PA3MFP_PWM1_CH2 (6ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for PWM1_CH2*/
<> 149:156823d33999 147 #define SYS_GPA_MFPL_PA3MFP_EBI_AD3 (7ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EBI_AD3*/
<> 149:156823d33999 148
<> 149:156823d33999 149 //PA4 MFP
<> 149:156823d33999 150 #define SYS_GPA_MFPL_PA4MFP_GPIO (0ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO*/
<> 149:156823d33999 151 #define SYS_GPA_MFPL_PA4MFP_SPI1_SS (2ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI1_SS*/
<> 149:156823d33999 152 #define SYS_GPA_MFPL_PA4MFP_EBI_AD4 (7ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EBI_AD4*/
<> 149:156823d33999 153
<> 149:156823d33999 154 //PA5 MFP
<> 149:156823d33999 155 #define SYS_GPA_MFPL_PA5MFP_GPIO (0ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO*/
<> 149:156823d33999 156 #define SYS_GPA_MFPL_PA5MFP_SPI1_MOSI (2ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI1_MOSI*/
<> 149:156823d33999 157 #define SYS_GPA_MFPL_PA5MFP_T2_EXT (3ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for T2_EXT*/
<> 149:156823d33999 158 #define SYS_GPA_MFPL_PA5MFP_EBI_AD5 (7ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EBI_AD5*/
<> 149:156823d33999 159
<> 149:156823d33999 160 //PA6 MFP
<> 149:156823d33999 161 #define SYS_GPA_MFPL_PA6MFP_GPIO (0ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO*/
<> 149:156823d33999 162 #define SYS_GPA_MFPL_PA6MFP_SPI1_MISO (2ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SPI1_MISO*/
<> 149:156823d33999 163 #define SYS_GPA_MFPL_PA6MFP_T1_EXT (3ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for T1_EXT*/
<> 149:156823d33999 164 #define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (7ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6*/
<> 149:156823d33999 165
<> 149:156823d33999 166 //PA7 MFP
<> 149:156823d33999 167 #define SYS_GPA_MFPL_PA7MFP_GPIO (0ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO*/
<> 149:156823d33999 168 #define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (2ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI1_CLK*/
<> 149:156823d33999 169 #define SYS_GPA_MFPL_PA7MFP_T0_EXT (3ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for T0_EXT*/
<> 149:156823d33999 170 #define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (7ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7*/
<> 149:156823d33999 171
<> 149:156823d33999 172 //PA8 MFP
<> 149:156823d33999 173 #define SYS_GPA_MFPH_PA8MFP_GPIO (0ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO*/
<> 149:156823d33999 174 #define SYS_GPA_MFPH_PA8MFP_UART3_TXD (3ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART3_TXD*/
<> 149:156823d33999 175
<> 149:156823d33999 176 //PA9 MFP
<> 149:156823d33999 177 #define SYS_GPA_MFPH_PA9MFP_GPIO (0ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO*/
<> 149:156823d33999 178 #define SYS_GPA_MFPH_PA9MFP_UART3_RXD (3ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART3_RXD*/
<> 149:156823d33999 179
<> 149:156823d33999 180 //PA10 MFP
<> 149:156823d33999 181 #define SYS_GPA_MFPH_PA10MFP_GPIO (0ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for GPIO*/
<> 149:156823d33999 182 #define SYS_GPA_MFPH_PA10MFP_UART3_nCTS (3ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for UART3_nCTS*/
<> 149:156823d33999 183
<> 149:156823d33999 184 //PA11 MFP
<> 149:156823d33999 185 #define SYS_GPA_MFPH_PA11MFP_GPIO (0ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for GPIO*/
<> 149:156823d33999 186 #define SYS_GPA_MFPH_PA11MFP_UART3_nRTS (3ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for UART3_nRTS*/
<> 149:156823d33999 187
<> 149:156823d33999 188 //PA12 MFP
<> 149:156823d33999 189 #define SYS_GPA_MFPH_PA12MFP_GPIO (0ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for GPIO*/
<> 149:156823d33999 190 #define SYS_GPA_MFPH_PA12MFP_SPI1_I2SMCLK (2ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SPI1_I2SMCLK*/
<> 149:156823d33999 191 #define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (4ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for CAN0_TXD*/
<> 149:156823d33999 192
<> 149:156823d33999 193 //PA13 MFP
<> 149:156823d33999 194 #define SYS_GPA_MFPH_PA13MFP_GPIO (0ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for GPIO*/
<> 149:156823d33999 195 #define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (4ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for CAN0_RXD*/
<> 149:156823d33999 196
<> 149:156823d33999 197 //PA14 MFP
<> 149:156823d33999 198 #define SYS_GPA_MFPH_PA14MFP_GPIO (0ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for GPIO*/
<> 149:156823d33999 199 #define SYS_GPA_MFPH_PA14MFP_UART2_nCTS (3ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for UART2_nCTS*/
<> 149:156823d33999 200 #define SYS_GPA_MFPH_PA14MFP_I2C0_SMBAL (4ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for I2C0_SMBAL*/
<> 149:156823d33999 201
<> 149:156823d33999 202 //PA15 MFP
<> 149:156823d33999 203 #define SYS_GPA_MFPH_PA15MFP_GPIO (0ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for GPIO*/
<> 149:156823d33999 204 #define SYS_GPA_MFPH_PA15MFP_UART2_nRTS (3ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for UART2_nRTS*/
<> 149:156823d33999 205 #define SYS_GPA_MFPH_PA15MFP_I2C0_SMBSUS (4ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2C0_SMBSUS*/
<> 149:156823d33999 206
<> 149:156823d33999 207 //PB0 MFP
<> 149:156823d33999 208 #define SYS_GPB_MFPL_PB0MFP_GPIO (0ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO*/
<> 149:156823d33999 209 #define SYS_GPB_MFPL_PB0MFP_EADC_CH0 (1ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC_CH0*/
<> 149:156823d33999 210 #define SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1 (2ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_MOSI1*/
<> 149:156823d33999 211 #define SYS_GPB_MFPL_PB0MFP_UART2_RXD (3ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD*/
<> 149:156823d33999 212 #define SYS_GPB_MFPL_PB0MFP_T2 (4ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for T2*/
<> 149:156823d33999 213 #define SYS_GPB_MFPL_PB0MFP_DAC (5ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for DAC*/
<> 149:156823d33999 214 #define SYS_GPB_MFPL_PB0MFP_EBI_nWRL (7ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_nWRL*/
<> 149:156823d33999 215 #define SYS_GPB_MFPL_PB0MFP_INT1 (8ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for INT1*/
<> 149:156823d33999 216
<> 149:156823d33999 217 //PB1 MFP
<> 149:156823d33999 218 #define SYS_GPB_MFPL_PB1MFP_GPIO (0ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO*/
<> 149:156823d33999 219 #define SYS_GPB_MFPL_PB1MFP_EADC_CH1 (1ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EADC_CH1*/
<> 149:156823d33999 220 #define SYS_GPB_MFPL_PB1MFP_SPI0_MISO1 (2ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI0_MISO1*/
<> 149:156823d33999 221 #define SYS_GPB_MFPL_PB1MFP_UART2_TXD (3ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD*/
<> 149:156823d33999 222 #define SYS_GPB_MFPL_PB1MFP_T3 (4ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for T3*/
<> 149:156823d33999 223 #define SYS_GPB_MFPL_PB1MFP_SC0_RST (5ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SC0_RST*/
<> 149:156823d33999 224 #define SYS_GPB_MFPL_PB1MFP_PWM0_SYNC_OUT (6ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for PWM0_SYNC_OUT*/
<> 149:156823d33999 225 #define SYS_GPB_MFPL_PB1MFP_EBI_nWRH (7ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_nWRH*/
<> 149:156823d33999 226
<> 149:156823d33999 227 //PB2 MFP
<> 149:156823d33999 228 #define SYS_GPB_MFPL_PB2MFP_GPIO (0ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO*/
<> 149:156823d33999 229 #define SYS_GPB_MFPL_PB2MFP_EADC_CH2 (1ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EADC_CH2*/
<> 149:156823d33999 230 #define SYS_GPB_MFPL_PB2MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI0_CLK*/
<> 149:156823d33999 231 #define SYS_GPB_MFPL_PB2MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI1_CLK*/
<> 149:156823d33999 232 #define SYS_GPB_MFPL_PB2MFP_UART1_RXD (4ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD*/
<> 149:156823d33999 233 #define SYS_GPB_MFPL_PB2MFP_SC0_CD (5ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SC0_CD*/
<> 149:156823d33999 234 #define SYS_GPB_MFPL_PB2MFP_UART3_RXD (9ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART3_RXD*/
<> 149:156823d33999 235 #define SYS_GPB_MFPL_PB2MFP_T2_EXT (11ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for T2_EXT*/
<> 149:156823d33999 236
<> 149:156823d33999 237 //PB3
<> 149:156823d33999 238 #define SYS_GPB_MFPL_PB3MFP_GPIO (0ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO*/
<> 149:156823d33999 239 #define SYS_GPB_MFPL_PB3MFP_EADC_CH3 (1ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EADC_CH3*/
<> 149:156823d33999 240 #define SYS_GPB_MFPL_PB3MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI0_MISO0*/
<> 149:156823d33999 241 #define SYS_GPB_MFPL_PB3MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI1_MISO*/
<> 149:156823d33999 242 #define SYS_GPB_MFPL_PB3MFP_UART1_TXD (4ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD*/
<> 149:156823d33999 243 #define SYS_GPB_MFPL_PB3MFP_UART3_TXD (9ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART3_TXD*/
<> 149:156823d33999 244 #define SYS_GPB_MFPL_PB3MFP_T0_EXT (11ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for T0_EXT*/
<> 149:156823d33999 245
<> 149:156823d33999 246 //PB4
<> 149:156823d33999 247 #define SYS_GPB_MFPL_PB4MFP_GPIO (0ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO*/
<> 149:156823d33999 248 #define SYS_GPB_MFPL_PB4MFP_EADC_CH4 (1ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EADC_CH4*/
<> 149:156823d33999 249 #define SYS_GPB_MFPL_PB4MFP_SPI0_SS (2ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI0_SS*/
<> 149:156823d33999 250 #define SYS_GPB_MFPL_PB4MFP_SPI1_SS (3ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI1_SS*/
<> 149:156823d33999 251 #define SYS_GPB_MFPL_PB4MFP_UART1_nCTS (4ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART1_nCTS*/
<> 149:156823d33999 252 #define SYS_GPB_MFPL_PB4MFP_ACMP0_N (5ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP0_N*/
<> 149:156823d33999 253 #define SYS_GPB_MFPL_PB4MFP_EBI_AD7 (7ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_AD7*/
<> 149:156823d33999 254 #define SYS_GPB_MFPL_PB4MFP_UART2_TXD (9ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART2_TXD*/
<> 149:156823d33999 255 #define SYS_GPB_MFPL_PB4MFP_T1_EXT (11ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for T1_EXT*/
<> 149:156823d33999 256
<> 149:156823d33999 257 //PB5
<> 149:156823d33999 258 #define SYS_GPB_MFPL_PB5MFP_GPIO (0ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO*/
<> 149:156823d33999 259 #define SYS_GPB_MFPL_PB5MFP_EADC_CH13 (1ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EADC_CH13*/
<> 149:156823d33999 260 #define SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0 (2ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI0_MOSI0*/
<> 149:156823d33999 261 #define SYS_GPB_MFPL_PB5MFP_SPI1_MOSI (3ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI1_MOSI*/
<> 149:156823d33999 262 #define SYS_GPB_MFPL_PB5MFP_TK3 (4ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TK3*/
<> 149:156823d33999 263 #define SYS_GPB_MFPL_PB5MFP_ACMP0_P2 (5ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP0_P2*/
<> 149:156823d33999 264 #define SYS_GPB_MFPL_PB5MFP_EBI_AD6 (7ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_AD6*/
<> 149:156823d33999 265 #define SYS_GPB_MFPL_PB5MFP_UART2_RXD (9ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART2_RXD*/
<> 149:156823d33999 266
<> 149:156823d33999 267 //PB6
<> 149:156823d33999 268 #define SYS_GPB_MFPL_PB6MFP_GPIO (0ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO*/
<> 149:156823d33999 269 #define SYS_GPB_MFPL_PB6MFP_EADC_CH14 (1ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EADC_CH14*/
<> 149:156823d33999 270 #define SYS_GPB_MFPL_PB6MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI0_MISO0*/
<> 149:156823d33999 271 #define SYS_GPB_MFPL_PB6MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI1_MISO*/
<> 149:156823d33999 272 #define SYS_GPB_MFPL_PB6MFP_TK4 (4ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for TK4*/
<> 149:156823d33999 273 #define SYS_GPB_MFPL_PB6MFP_ACMP0_P1 (5ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP0_P1*/
<> 149:156823d33999 274 #define SYS_GPB_MFPL_PB6MFP_EBI_AD5 (7ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_AD5*/
<> 149:156823d33999 275
<> 149:156823d33999 276 //PB7
<> 149:156823d33999 277 #define SYS_GPB_MFPL_PB7MFP_GPIO (0ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO*/
<> 149:156823d33999 278 #define SYS_GPB_MFPL_PB7MFP_EADC_CH15 (1ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EADC_CH15*/
<> 149:156823d33999 279 #define SYS_GPB_MFPL_PB7MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI0_CLK*/
<> 149:156823d33999 280 #define SYS_GPB_MFPL_PB7MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI1_CLK*/
<> 149:156823d33999 281 #define SYS_GPB_MFPL_PB7MFP_TK5 (4ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for TK5*/
<> 149:156823d33999 282 #define SYS_GPB_MFPL_PB7MFP_ACMP0_P0 (5ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_P0*/
<> 149:156823d33999 283 #define SYS_GPB_MFPL_PB7MFP_EBI_AD4 (7ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_AD4*/
<> 149:156823d33999 284 #define SYS_GPB_MFPL_PB7MFP_STADC (10ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for STADC*/
<> 149:156823d33999 285
<> 149:156823d33999 286 //PB8
<> 149:156823d33999 287 #define SYS_GPB_MFPH_PB8MFP_GPIO (0ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO*/
<> 149:156823d33999 288 #define SYS_GPB_MFPH_PB8MFP_EADC_CH5 (1ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EADC_CH5*/
<> 149:156823d33999 289 #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (4ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS*/
<> 149:156823d33999 290 #define SYS_GPB_MFPH_PB8MFP_PWM0_CH2 (6ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for PWM0_CH2*/
<> 149:156823d33999 291
<> 149:156823d33999 292 //PB9
<> 149:156823d33999 293 #define SYS_GPB_MFPH_PB9MFP_GPIO (0ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO*/
<> 149:156823d33999 294 #define SYS_GPB_MFPH_PB9MFP_EADC_CH6 (1ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EADC_CH6*/
<> 149:156823d33999 295
<> 149:156823d33999 296 //PB10
<> 149:156823d33999 297 #define SYS_GPB_MFPH_PB10MFP_GPIO (0ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for GPIO*/
<> 149:156823d33999 298 #define SYS_GPB_MFPH_PB10MFP_EADC_CH7 (1ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for EADC_CH7*/
<> 149:156823d33999 299
<> 149:156823d33999 300 //PB11
<> 149:156823d33999 301 #define SYS_GPB_MFPH_PB11MFP_GPIO (0ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for GPIO*/
<> 149:156823d33999 302 #define SYS_GPB_MFPH_PB11MFP_EADC_CH8 (1ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for EADC_CH8*/
<> 149:156823d33999 303 #define SYS_GPB_MFPH_PB11MFP_TK0 (4ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for TK0*/
<> 149:156823d33999 304
<> 149:156823d33999 305 //PB12
<> 149:156823d33999 306 #define SYS_GPB_MFPH_PB12MFP_GPIO (0ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for GPIO*/
<> 149:156823d33999 307 #define SYS_GPB_MFPH_PB12MFP_EADC_CH9 (1ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for EADC_CH9*/
<> 149:156823d33999 308 #define SYS_GPB_MFPH_PB12MFP_TK1 (4ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for TK1*/
<> 149:156823d33999 309
<> 149:156823d33999 310 //PB13
<> 149:156823d33999 311 #define SYS_GPB_MFPH_PB13MFP_GPIO (0ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for GPIO*/
<> 149:156823d33999 312 #define SYS_GPB_MFPH_PB13MFP_EADC_CH10 (1ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EADC_CH10*/
<> 149:156823d33999 313
<> 149:156823d33999 314 //PB14
<> 149:156823d33999 315 #define SYS_GPB_MFPH_PB14MFP_GPIO (0ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for GPIO*/
<> 149:156823d33999 316 #define SYS_GPB_MFPH_PB14MFP_EADC_CH11 (1ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EADC_CH11*/
<> 149:156823d33999 317
<> 149:156823d33999 318 //PB15
<> 149:156823d33999 319 #define SYS_GPB_MFPH_PB15MFP_GPIO (0ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for GPIO*/
<> 149:156823d33999 320 #define SYS_GPB_MFPH_PB15MFP_EADC_CH12 (1ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EADC_CH12*/
<> 149:156823d33999 321 #define SYS_GPB_MFPH_PB15MFP_TK2 (4ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for TK2*/
<> 149:156823d33999 322 #define SYS_GPB_MFPH_PB15MFP_ACMP0_P3 (5ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for ACMP0_P3*/
<> 149:156823d33999 323 #define SYS_GPB_MFPH_PB15MFP_EBI_nCS1 (7ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EBI_nCS1*/
<> 149:156823d33999 324
<> 149:156823d33999 325 //PC0
<> 149:156823d33999 326 #define SYS_GPC_MFPL_PC0MFP_GPIO (0ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO*/
<> 149:156823d33999 327 #define SYS_GPC_MFPL_PC0MFP_SPI2_CLK (2ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI2_CLK*/
<> 149:156823d33999 328 #define SYS_GPC_MFPL_PC0MFP_UART2_nCTS (3ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_nCTS*/
<> 149:156823d33999 329 #define SYS_GPC_MFPL_PC0MFP_CAN0_TXD (4ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for CAN0_TXD*/
<> 149:156823d33999 330 #define SYS_GPC_MFPL_PC0MFP_PWM0_CH0 (6ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for PWM0_CH0*/
<> 149:156823d33999 331 #define SYS_GPC_MFPL_PC0MFP_EBI_AD8 (7ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD8*/
<> 149:156823d33999 332 #define SYS_GPC_MFPL_PC0MFP_INT2 (8ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for INT2*/
<> 149:156823d33999 333 #define SYS_GPC_MFPL_PC0MFP_UART3_TXD (9ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART3_TXD*/
<> 149:156823d33999 334 #define SYS_GPC_MFPL_PC0MFP_T3_EXT (11ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for T3_EXT*/
<> 149:156823d33999 335
<> 149:156823d33999 336 //PC1
<> 149:156823d33999 337 #define SYS_GPC_MFPL_PC1MFP_GPIO (0ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO*/
<> 149:156823d33999 338 #define SYS_GPC_MFPL_PC1MFP_CLKO (1ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CLKO*/
<> 149:156823d33999 339 #define SYS_GPC_MFPL_PC1MFP_STDAC (2ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for STDAC*/
<> 149:156823d33999 340 #define SYS_GPC_MFPL_PC1MFP_UART2_nRTS (3ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_nRTS*/
<> 149:156823d33999 341 #define SYS_GPC_MFPL_PC1MFP_CAN0_RXD (4ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CAN0_RXD*/
<> 149:156823d33999 342 #define SYS_GPC_MFPL_PC1MFP_PWM0_CH1 (6ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for PWM0_CH1*/
<> 149:156823d33999 343 #define SYS_GPC_MFPL_PC1MFP_EBI_AD9 (7ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD9*/
<> 149:156823d33999 344 #define SYS_GPC_MFPL_PC1MFP_UART3_RXD (9ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART3_RXD*/
<> 149:156823d33999 345
<> 149:156823d33999 346 //PC2
<> 149:156823d33999 347 #define SYS_GPC_MFPL_PC2MFP_GPIO (0ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO*/
<> 149:156823d33999 348 #define SYS_GPC_MFPL_PC2MFP_SPI2_SS (2ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI2_SS*/
<> 149:156823d33999 349 #define SYS_GPC_MFPL_PC2MFP_UART2_TXD (3ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_TXD*/
<> 149:156823d33999 350 #define SYS_GPC_MFPL_PC2MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for ACMP1_O*/
<> 149:156823d33999 351 #define SYS_GPC_MFPL_PC2MFP_PWM0_CH2 (6ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for PWM0_CH2*/
<> 149:156823d33999 352 #define SYS_GPC_MFPL_PC2MFP_EBI_AD10 (7ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD10*/
<> 149:156823d33999 353
<> 149:156823d33999 354 //PC3
<> 149:156823d33999 355 #define SYS_GPC_MFPL_PC3MFP_GPIO (0ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO*/
<> 149:156823d33999 356 #define SYS_GPC_MFPL_PC3MFP_SPI2_MOSI (2ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI2_MOSI*/
<> 149:156823d33999 357 #define SYS_GPC_MFPL_PC3MFP_UART2_RXD (3ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_RXD*/
<> 149:156823d33999 358 #define SYS_GPC_MFPL_PC3MFP_USB_VBUS_ST (4ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for USB_VBUS_ST*/
<> 149:156823d33999 359 #define SYS_GPC_MFPL_PC3MFP_PWM0_CH3 (6ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for PWM0_CH3*/
<> 149:156823d33999 360 #define SYS_GPC_MFPL_PC3MFP_EBI_AD11 (7ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD11*/
<> 149:156823d33999 361
<> 149:156823d33999 362 //PC4
<> 149:156823d33999 363 #define SYS_GPC_MFPL_PC4MFP_GPIO (0ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO*/
<> 149:156823d33999 364 #define SYS_GPC_MFPL_PC4MFP_SPI2_MISO (2ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI2_MISO*/
<> 149:156823d33999 365 #define SYS_GPC_MFPL_PC4MFP_I2C1_SCL (3ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SCL*/
<> 149:156823d33999 366 #define SYS_GPC_MFPL_PC4MFP_USB_VBUS_EN (4ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for USB_VBUS_EN*/
<> 149:156823d33999 367 #define SYS_GPC_MFPL_PC4MFP_PWM0_CH4 (6ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for PWM0_CH4*/
<> 149:156823d33999 368 #define SYS_GPC_MFPL_PC4MFP_EBI_AD12 (7ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD12*/
<> 149:156823d33999 369
<> 149:156823d33999 370 //PC5
<> 149:156823d33999 371 #define SYS_GPC_MFPL_PC5MFP_GPIO (0ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO*/
<> 149:156823d33999 372 #define SYS_GPC_MFPL_PC5MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for SPI2_I2SMCLK*/
<> 149:156823d33999 373 #define SYS_GPC_MFPL_PC5MFP_PWM0_CH5 (6ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for PWM0_CH5*/
<> 149:156823d33999 374 #define SYS_GPC_MFPL_PC5MFP_EBI_AD13 (7ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD13*/
<> 149:156823d33999 375
<> 149:156823d33999 376 //PC6
<> 149:156823d33999 377 #define SYS_GPC_MFPL_PC6MFP_GPIO (0ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO*/
<> 149:156823d33999 378 #define SYS_GPC_MFPL_PC6MFP_I2C1_SMBAL (3ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for I2C1_SMBAL*/
<> 149:156823d33999 379 #define SYS_GPC_MFPL_PC6MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for ACMP1_O*/
<> 149:156823d33999 380 #define SYS_GPC_MFPL_PC6MFP_PWM1_CH0 (6ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for PWM1_CH0*/
<> 149:156823d33999 381 #define SYS_GPC_MFPL_PC6MFP_EBI_AD14 (7ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD14*/
<> 149:156823d33999 382 #define SYS_GPC_MFPL_PC6MFP_UART0_TXD (9ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_TXD*/
<> 149:156823d33999 383
<> 149:156823d33999 384 //PC7
<> 149:156823d33999 385 #define SYS_GPC_MFPL_PC7MFP_GPIO (0ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO*/
<> 149:156823d33999 386 #define SYS_GPC_MFPL_PC7MFP_I2C1_SMBSUS (3ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for I2C1_SMBSUS*/
<> 149:156823d33999 387 #define SYS_GPC_MFPL_PC7MFP_PWM1_CH1 (6ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for PWM1_CH1*/
<> 149:156823d33999 388 #define SYS_GPC_MFPL_PC7MFP_EBI_AD15 (7ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD15*/
<> 149:156823d33999 389 #define SYS_GPC_MFPL_PC7MFP_UART0_RXD (9ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_RXD*/
<> 149:156823d33999 390
<> 149:156823d33999 391 //PC8
<> 149:156823d33999 392 #define SYS_GPC_MFPH_PC8MFP_GPIO (0ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for GPIO*/
<> 149:156823d33999 393 #define SYS_GPC_MFPH_PC8MFP_TK7 (4ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for TK7*/
<> 149:156823d33999 394
<> 149:156823d33999 395 //PC9
<> 149:156823d33999 396 #define SYS_GPC_MFPH_PC9MFP_GPIO (0ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO*/
<> 149:156823d33999 397 #define SYS_GPC_MFPH_PC9MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SPI2_I2SMCLK*/
<> 149:156823d33999 398 #define SYS_GPC_MFPH_PC9MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for PWM1_CH0*/
<> 149:156823d33999 399
<> 149:156823d33999 400 //PC10
<> 149:156823d33999 401 #define SYS_GPC_MFPH_PC10MFP_GPIO (0ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for GPIO*/
<> 149:156823d33999 402 #define SYS_GPC_MFPH_PC10MFP_SPI2_MOSI (2ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for SPI2_MOSI*/
<> 149:156823d33999 403 #define SYS_GPC_MFPH_PC10MFP_PWM1_CH1 (6ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for PWM1_CH1*/
<> 149:156823d33999 404
<> 149:156823d33999 405 //PC11
<> 149:156823d33999 406 #define SYS_GPC_MFPH_PC11MFP_GPIO (0ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for GPIO*/
<> 149:156823d33999 407 #define SYS_GPC_MFPH_PC11MFP_SPI2_MISO (2ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for SPI2_MISO*/
<> 149:156823d33999 408 #define SYS_GPC_MFPH_PC11MFP_PWM1_CH2 (6ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for PWM1_CH2*/
<> 149:156823d33999 409
<> 149:156823d33999 410 //PC12
<> 149:156823d33999 411 #define SYS_GPC_MFPH_PC12MFP_GPIO (0ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for GPIO*/
<> 149:156823d33999 412 #define SYS_GPC_MFPH_PC12MFP_SPI2_CLK (2ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SPI2_CLK*/
<> 149:156823d33999 413 #define SYS_GPC_MFPH_PC12MFP_PWM1_CH3 (6ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for PWM1_CH3*/
<> 149:156823d33999 414
<> 149:156823d33999 415 //PC13
<> 149:156823d33999 416 #define SYS_GPC_MFPH_PC13MFP_GPIO (0ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for GPIO*/
<> 149:156823d33999 417 #define SYS_GPC_MFPH_PC13MFP_SPI2_SS (2ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SPI2_SS*/
<> 149:156823d33999 418 #define SYS_GPC_MFPH_PC13MFP_PWM1_CH4 (6ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for PWM1_CH4*/
<> 149:156823d33999 419
<> 149:156823d33999 420 //PC14
<> 149:156823d33999 421 #define SYS_GPC_MFPH_PC14MFP_GPIO (0ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for GPIO*/
<> 149:156823d33999 422 #define SYS_GPC_MFPH_PC14MFP_PWM1_CH5 (6ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for PWM1_CH5*/
<> 149:156823d33999 423
<> 149:156823d33999 424 //PC15
<> 149:156823d33999 425 #define SYS_GPC_MFPH_PC15MFP_GPIO (0ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for GPIO*/
<> 149:156823d33999 426 #define SYS_GPC_MFPH_PC15MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for PWM1_CH0*/
<> 149:156823d33999 427
<> 149:156823d33999 428 //PD0
<> 149:156823d33999 429 #define SYS_GPD_MFPL_PD0MFP_GPIO (0ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO*/
<> 149:156823d33999 430 #define SYS_GPD_MFPL_PD0MFP_EADC_CH6 (1ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EADC_CH6*/
<> 149:156823d33999 431 #define SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK (2ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI1_I2SMCLK*/
<> 149:156823d33999 432 #define SYS_GPD_MFPL_PD0MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART0_RXD*/
<> 149:156823d33999 433 #define SYS_GPD_MFPL_PD0MFP_TK6 (4ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TK6*/
<> 149:156823d33999 434 #define SYS_GPD_MFPL_PD0MFP_ACMP1_N (5ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for ACMP1_N*/
<> 149:156823d33999 435 #define SYS_GPD_MFPL_PD0MFP_INT3 (8ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for INT3*/
<> 149:156823d33999 436 #define SYS_GPD_MFPL_PD0MFP_T3 (11ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for T3*/
<> 149:156823d33999 437
<> 149:156823d33999 438 //PD1
<> 149:156823d33999 439 #define SYS_GPD_MFPL_PD1MFP_GPIO (0ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO*/
<> 149:156823d33999 440 #define SYS_GPD_MFPL_PD1MFP_EADC_CH11 (1ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EADC_CH11*/
<> 149:156823d33999 441 #define SYS_GPD_MFPL_PD1MFP_PWM0_SYNC_IN (2ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for PWM0_SYNC_IN*/
<> 149:156823d33999 442 #define SYS_GPD_MFPL_PD1MFP_UART0_TXD (3ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART0_TXD*/
<> 149:156823d33999 443 #define SYS_GPD_MFPL_PD1MFP_TK10 (4ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for TK10*/
<> 149:156823d33999 444 #define SYS_GPD_MFPL_PD1MFP_ACMP1_P2 (5ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for ACMP1_P2*/
<> 149:156823d33999 445 #define SYS_GPD_MFPL_PD1MFP_T0 (6ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for T0*/
<> 149:156823d33999 446 #define SYS_GPD_MFPL_PD1MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_nRD*/
<> 149:156823d33999 447
<> 149:156823d33999 448 //PD2
<> 149:156823d33999 449 #define SYS_GPD_MFPL_PD2MFP_GPIO (0ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO*/
<> 149:156823d33999 450 #define SYS_GPD_MFPL_PD2MFP_STADC (1ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for STADC*/
<> 149:156823d33999 451 #define SYS_GPD_MFPL_PD2MFP_T0_EXT (3ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for T0_EXT*/
<> 149:156823d33999 452 #define SYS_GPD_MFPL_PD2MFP_TK11 (4ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for TK11*/
<> 149:156823d33999 453 #define SYS_GPD_MFPL_PD2MFP_ACMP1_P1 (5ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for ACMP1_P1*/
<> 149:156823d33999 454 #define SYS_GPD_MFPL_PD2MFP_PWM0_BRAKE0 (6ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for PWM0_BRAKE0*/
<> 149:156823d33999 455 #define SYS_GPD_MFPL_PD2MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_nWR*/
<> 149:156823d33999 456 #define SYS_GPD_MFPL_PD2MFP_INT0 (8ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for INT0*/
<> 149:156823d33999 457
<> 149:156823d33999 458 //PD3
<> 149:156823d33999 459 #define SYS_GPD_MFPL_PD3MFP_GPIO (0ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO*/
<> 149:156823d33999 460 #define SYS_GPD_MFPL_PD3MFP_T2 (1ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T2*/
<> 149:156823d33999 461 #define SYS_GPD_MFPL_PD3MFP_T1_EXT (3ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T1_EXT*/
<> 149:156823d33999 462 #define SYS_GPD_MFPL_PD3MFP_TK12 (4ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for TK12*/
<> 149:156823d33999 463 #define SYS_GPD_MFPL_PD3MFP_ACMP1_P0 (5ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for ACMP1_P0*/
<> 149:156823d33999 464 #define SYS_GPD_MFPL_PD3MFP_PWM0_BRAKE1 (6ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for PWM0_BRAKE1*/
<> 149:156823d33999 465 #define SYS_GPD_MFPL_PD3MFP_EBI_MCLK (7ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_MCLK*/
<> 149:156823d33999 466 #define SYS_GPD_MFPL_PD3MFP_INT1 (8ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for INT1*/
<> 149:156823d33999 467
<> 149:156823d33999 468 //PD4
<> 149:156823d33999 469 #define SYS_GPD_MFPL_PD4MFP_GPIO (0ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO*/
<> 149:156823d33999 470 #define SYS_GPD_MFPL_PD4MFP_SPI1_CLK (2ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SPI1_CLK*/
<> 149:156823d33999 471 #define SYS_GPD_MFPL_PD4MFP_I2C0_SDA (3ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C0_SDA*/
<> 149:156823d33999 472 #define SYS_GPD_MFPL_PD4MFP_TK13 (4ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for TK13*/
<> 149:156823d33999 473 #define SYS_GPD_MFPL_PD4MFP_PWM0_BRAKE0 (5ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for PWM0_BRAKE0*/
<> 149:156823d33999 474 #define SYS_GPD_MFPL_PD4MFP_T0 (6ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for T0*/
<> 149:156823d33999 475
<> 149:156823d33999 476 //PD5
<> 149:156823d33999 477 #define SYS_GPD_MFPL_PD5MFP_GPIO (0ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO*/
<> 149:156823d33999 478 #define SYS_GPD_MFPL_PD5MFP_CLKO (1ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for CLKO*/
<> 149:156823d33999 479 #define SYS_GPD_MFPL_PD5MFP_SPI1_MISO (2ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SPI1_MISO*/
<> 149:156823d33999 480 #define SYS_GPD_MFPL_PD5MFP_I2C0_SCL (3ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C0_SCL*/
<> 149:156823d33999 481 #define SYS_GPD_MFPL_PD5MFP_TK14 (4ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for TK14*/
<> 149:156823d33999 482 #define SYS_GPD_MFPL_PD5MFP_PWM0_BRAKE1 (5ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for PWM0_BRAKE1*/
<> 149:156823d33999 483 #define SYS_GPD_MFPL_PD5MFP_T1 (6ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for T1*/
<> 149:156823d33999 484
<> 149:156823d33999 485 //PD6
<> 149:156823d33999 486 #define SYS_GPD_MFPL_PD6MFP_GPIO (0ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO*/
<> 149:156823d33999 487 #define SYS_GPD_MFPL_PD6MFP_CLKO (1ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for CLKO*/
<> 149:156823d33999 488 #define SYS_GPD_MFPL_PD6MFP_SPI1_SS (2ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SPI1_SS*/
<> 149:156823d33999 489 #define SYS_GPD_MFPL_PD6MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART0_RXD*/
<> 149:156823d33999 490 #define SYS_GPD_MFPL_PD6MFP_TK16 (4ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for TK16*/
<> 149:156823d33999 491 #define SYS_GPD_MFPL_PD6MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for ACMP0_O*/
<> 149:156823d33999 492 #define SYS_GPD_MFPL_PD6MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for PWM0_CH5*/
<> 149:156823d33999 493 #define SYS_GPD_MFPL_PD6MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for EBI_nWR*/
<> 149:156823d33999 494
<> 149:156823d33999 495 //PD7
<> 149:156823d33999 496 #define SYS_GPD_MFPL_PD7MFP_GPIO (0ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO*/
<> 149:156823d33999 497 #define SYS_GPD_MFPL_PD7MFP_PWM0_SYNC_IN (3ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_SYNC_IN*/
<> 149:156823d33999 498 #define SYS_GPD_MFPL_PD7MFP_T1 (4ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for T1*/
<> 149:156823d33999 499 #define SYS_GPD_MFPL_PD7MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for ACMP0_O*/
<> 149:156823d33999 500 #define SYS_GPD_MFPL_PD7MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_CH5*/
<> 149:156823d33999 501 #define SYS_GPD_MFPL_PD7MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for EBI_nRD*/
<> 149:156823d33999 502
<> 149:156823d33999 503 //PD8
<> 149:156823d33999 504 #define SYS_GPD_MFPH_PD8MFP_GPIO (0ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO*/
<> 149:156823d33999 505 #define SYS_GPD_MFPH_PD8MFP_EADC_CH7 (1ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EADC_CH7*/
<> 149:156823d33999 506 #define SYS_GPD_MFPH_PD8MFP_TK8 (4ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for TK8*/
<> 149:156823d33999 507 #define SYS_GPD_MFPH_PD8MFP_EBI_nCS0 (7ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_nCS0*/
<> 149:156823d33999 508
<> 149:156823d33999 509 //PD9
<> 149:156823d33999 510 #define SYS_GPD_MFPH_PD9MFP_GPIO (0ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO*/
<> 149:156823d33999 511 #define SYS_GPD_MFPH_PD9MFP_EADC_CH10 (1ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EADC_CH10*/
<> 149:156823d33999 512 #define SYS_GPD_MFPH_PD9MFP_TK9 (4ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for TK9*/
<> 149:156823d33999 513 #define SYS_GPD_MFPH_PD9MFP_ACMP1_P3 (5ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for ACMP1_P3*/
<> 149:156823d33999 514 #define SYS_GPD_MFPH_PD9MFP_EBI_ALE (7ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_ALE*/
<> 149:156823d33999 515
<> 149:156823d33999 516 //PD10
<> 149:156823d33999 517 #define SYS_GPD_MFPH_PD10MFP_GPIO (0ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for GPIO*/
<> 149:156823d33999 518 #define SYS_GPD_MFPH_PD10MFP_T2 (4ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for T2*/
<> 149:156823d33999 519
<> 149:156823d33999 520 //PD11
<> 149:156823d33999 521 #define SYS_GPD_MFPH_PD11MFP_GPIO (0ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for GPIO*/
<> 149:156823d33999 522 #define SYS_GPD_MFPH_PD11MFP_T3 (4ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for T3*/
<> 149:156823d33999 523
<> 149:156823d33999 524 //PD12
<> 149:156823d33999 525 #define SYS_GPD_MFPH_PD12MFP_GPIO (0ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for GPIO*/
<> 149:156823d33999 526 #define SYS_GPD_MFPH_PD12MFP_SPI2_SS (2ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for SPI2_SS*/
<> 149:156823d33999 527 #define SYS_GPD_MFPH_PD12MFP_UART3_TXD (3ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for UART3_TXD*/
<> 149:156823d33999 528 #define SYS_GPD_MFPH_PD12MFP_PWM1_CH0 (6ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for PWM1_CH0*/
<> 149:156823d33999 529 #define SYS_GPD_MFPH_PD12MFP_EBI_ADR16 (7ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for EBI_ADR16*/
<> 149:156823d33999 530
<> 149:156823d33999 531 //PD13
<> 149:156823d33999 532 #define SYS_GPD_MFPH_PD13MFP_GPIO (0ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for GPIO*/
<> 149:156823d33999 533 #define SYS_GPD_MFPH_PD13MFP_SPI2_MOSI (2ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for SPI2_MOSI*/
<> 149:156823d33999 534 #define SYS_GPD_MFPH_PD13MFP_UART3_RXD (3ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for UART3_RXD*/
<> 149:156823d33999 535 #define SYS_GPD_MFPH_PD13MFP_PWM1_CH1 (6ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for PWM1_CH1*/
<> 149:156823d33999 536 #define SYS_GPD_MFPH_PD13MFP_EBI_ADR17 (7ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for EBI_ADR17*/
<> 149:156823d33999 537
<> 149:156823d33999 538 //PD14
<> 149:156823d33999 539 #define SYS_GPD_MFPH_PD14MFP_GPIO (0ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for GPIO*/
<> 149:156823d33999 540 #define SYS_GPD_MFPH_PD14MFP_SPI2_MISO (2ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for SPI2_MISO*/
<> 149:156823d33999 541 #define SYS_GPD_MFPH_PD14MFP_UART3_nCTS (3ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for UART3_nCTS*/
<> 149:156823d33999 542 #define SYS_GPD_MFPH_PD14MFP_PWM1_CH2 (6ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for PWM1_CH2*/
<> 149:156823d33999 543 #define SYS_GPD_MFPH_PD14MFP_EBI_ADR18 (7ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for EBI_ADR18*/
<> 149:156823d33999 544
<> 149:156823d33999 545 //PD15
<> 149:156823d33999 546 #define SYS_GPD_MFPH_PD15MFP_GPIO (0ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for GPIO*/
<> 149:156823d33999 547 #define SYS_GPD_MFPH_PD15MFP_SPI2_CLK (2ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for SPI2_CLK*/
<> 149:156823d33999 548 #define SYS_GPD_MFPH_PD15MFP_UART3_nRTS (3ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for UART3_nRTS*/
<> 149:156823d33999 549 #define SYS_GPD_MFPH_PD15MFP_PWM1_CH3 (6ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for PWM1_CH3*/
<> 149:156823d33999 550 #define SYS_GPD_MFPH_PD15MFP_EBI_ADR19 (7ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for EBI_ADR19*/
<> 149:156823d33999 551
<> 149:156823d33999 552 //PE0
<> 149:156823d33999 553 #define SYS_GPE_MFPL_PE0MFP_GPIO (0ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO*/
<> 149:156823d33999 554 #define SYS_GPE_MFPL_PE0MFP_SPI2_CLK (2ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SPI2_CLK*/
<> 149:156823d33999 555 #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA*/
<> 149:156823d33999 556 #define SYS_GPE_MFPL_PE0MFP_T2_EXT (4ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for T2_EXT*/
<> 149:156823d33999 557 #define SYS_GPE_MFPL_PE0MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SC0_CD*/
<> 149:156823d33999 558 #define SYS_GPE_MFPL_PE0MFP_PWM0_CH0 (6ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for PWM0_CH0*/
<> 149:156823d33999 559 #define SYS_GPE_MFPL_PE0MFP_EBI_nCS1 (7ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_nCS1*/
<> 149:156823d33999 560 #define SYS_GPE_MFPL_PE0MFP_INT4 (8ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for INT4*/
<> 149:156823d33999 561
<> 149:156823d33999 562 //PE1
<> 149:156823d33999 563 #define SYS_GPE_MFPL_PE1MFP_GPIO (0ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO*/
<> 149:156823d33999 564 #define SYS_GPE_MFPL_PE1MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for T3_EXT*/
<> 149:156823d33999 565 #define SYS_GPE_MFPL_PE1MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SC0_CD*/
<> 149:156823d33999 566 #define SYS_GPE_MFPL_PE1MFP_PWM0_CH1 (6ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for PWM0_CH1*/
<> 149:156823d33999 567
<> 149:156823d33999 568 //PE2
<> 149:156823d33999 569 #define SYS_GPE_MFPL_PE2MFP_GPIO (0ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO*/
<> 149:156823d33999 570 #define SYS_GPE_MFPL_PE2MFP_PWM1_CH1 (6ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for PWM1_CH1*/
<> 149:156823d33999 571
<> 149:156823d33999 572 //PE3
<> 149:156823d33999 573 #define SYS_GPE_MFPL_PE3MFP_GPIO (0ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO*/
<> 149:156823d33999 574 #define SYS_GPE_MFPL_PE3MFP_SPI1_MOSI (2ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI1_MOSI*/
<> 149:156823d33999 575 #define SYS_GPE_MFPL_PE3MFP_TK15 (4ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for TK15*/
<> 149:156823d33999 576 #define SYS_GPE_MFPL_PE3MFP_PWM0_CH3 (6ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for PWM0_CH3*/
<> 149:156823d33999 577
<> 149:156823d33999 578 //PE4
<> 149:156823d33999 579 #define SYS_GPE_MFPL_PE4MFP_GPIO (0ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO*/
<> 149:156823d33999 580 #define SYS_GPE_MFPL_PE4MFP_I2C1_SCL (3ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for I2C1_SCL*/
<> 149:156823d33999 581 #define SYS_GPE_MFPL_PE4MFP_SC0_PWR (5ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_PWR*/
<> 149:156823d33999 582 #define SYS_GPE_MFPL_PE4MFP_PWM1_BRAKE0 (6ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for PWM1_BRAKE0*/
<> 149:156823d33999 583 #define SYS_GPE_MFPL_PE4MFP_EBI_nCS0 (7ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nCS0*/
<> 149:156823d33999 584 #define SYS_GPE_MFPL_PE4MFP_INT0 (8ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for INT0*/
<> 149:156823d33999 585
<> 149:156823d33999 586 //PE5
<> 149:156823d33999 587 #define SYS_GPE_MFPL_PE5MFP_GPIO (0ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO*/
<> 149:156823d33999 588 #define SYS_GPE_MFPL_PE5MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for I2C1_SDA*/
<> 149:156823d33999 589 #define SYS_GPE_MFPL_PE5MFP_SC0_RST (5ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_RST*/
<> 149:156823d33999 590 #define SYS_GPE_MFPL_PE5MFP_PWM1_BRAKE1 (6ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for PWM1_BRAKE1*/
<> 149:156823d33999 591 #define SYS_GPE_MFPL_PE5MFP_EBI_ALE (7ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_ALE*/
<> 149:156823d33999 592 #define SYS_GPE_MFPL_PE5MFP_INT1 (8ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for INT1*/
<> 149:156823d33999 593
<> 149:156823d33999 594 //PE6
<> 149:156823d33999 595 #define SYS_GPE_MFPL_PE6MFP_GPIO (0ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO*/
<> 149:156823d33999 596 #define SYS_GPE_MFPL_PE6MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for T3_EXT*/
<> 149:156823d33999 597
<> 149:156823d33999 598 //PE7
<> 149:156823d33999 599 #define SYS_GPE_MFPL_PE7MFP_GPIO (0ul << SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO*/
<> 149:156823d33999 600
<> 149:156823d33999 601 //PE8
<> 149:156823d33999 602 #define SYS_GPE_MFPH_PE8MFP_GPIO (0ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO*/
<> 149:156823d33999 603 #define SYS_GPE_MFPH_PE8MFP_UART1_TXD (1ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART1_TXD*/
<> 149:156823d33999 604 #define SYS_GPE_MFPH_PE8MFP_SPI0_MISO1 (2ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SPI0_MISO1*/
<> 149:156823d33999 605 #define SYS_GPE_MFPH_PE8MFP_I2C1_SCL (4ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for I2C1_SCL*/
<> 149:156823d33999 606 #define SYS_GPE_MFPH_PE8MFP_SC0_PWR (5ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SC0_PWR*/
<> 149:156823d33999 607 #define SYS_GPE_MFPH_PE8MFP_CLKO (9ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for CLKO*/
<> 149:156823d33999 608 #define SYS_GPE_MFPH_PE8MFP_PWM0_BRAKE0 (10ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for PWM0_BRAKE0*/
<> 149:156823d33999 609 #define SYS_GPE_MFPH_PE8MFP_T1 (11ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for T1*/
<> 149:156823d33999 610
<> 149:156823d33999 611 //PE9
<> 149:156823d33999 612 #define SYS_GPE_MFPH_PE9MFP_GPIO (0ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO*/
<> 149:156823d33999 613 #define SYS_GPE_MFPH_PE9MFP_UART1_RXD (1ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART1_RXD*/
<> 149:156823d33999 614 #define SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1 (2ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI0_MOSI1*/
<> 149:156823d33999 615 #define SYS_GPE_MFPH_PE9MFP_I2C1_SDA (4ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for I2C1_SDA*/
<> 149:156823d33999 616 #define SYS_GPE_MFPH_PE9MFP_SC0_RST (5ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SC0_RST*/
<> 149:156823d33999 617 #define SYS_GPE_MFPH_PE9MFP_SPI1_I2SMCLK (9ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI1_I2SMCLK*/
<> 149:156823d33999 618 #define SYS_GPE_MFPH_PE9MFP_PWM1_BRAKE1 (10ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for PWM1_BRAKE1*/
<> 149:156823d33999 619 #define SYS_GPE_MFPH_PE9MFP_T2 (11ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for T2*/
<> 149:156823d33999 620
<> 149:156823d33999 621 //PE10
<> 149:156823d33999 622 #define SYS_GPE_MFPH_PE10MFP_GPIO (0ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for GPIO*/
<> 149:156823d33999 623 #define SYS_GPE_MFPH_PE10MFP_SPI1_MISO (1ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI1_MISO*/
<> 149:156823d33999 624 #define SYS_GPE_MFPH_PE10MFP_SPI0_MISO0 (2ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI0_MISO0*/
<> 149:156823d33999 625 #define SYS_GPE_MFPH_PE10MFP_UART1_nCTS (3ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART1_nCTS*/
<> 149:156823d33999 626 #define SYS_GPE_MFPH_PE10MFP_I2C0_SMBAL (4ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C0_SMBAL*/
<> 149:156823d33999 627 #define SYS_GPE_MFPH_PE10MFP_SC0_DAT (5ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SC0_DAT*/
<> 149:156823d33999 628 #define SYS_GPE_MFPH_PE10MFP_UART3_TXD (9ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART3_TXD*/
<> 149:156823d33999 629 #define SYS_GPE_MFPH_PE10MFP_I2C1_SCL (11ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C1_SCL*/
<> 149:156823d33999 630
<> 149:156823d33999 631 //PE11
<> 149:156823d33999 632 #define SYS_GPE_MFPH_PE11MFP_GPIO (0ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for GPIO*/
<> 149:156823d33999 633 #define SYS_GPE_MFPH_PE11MFP_SPI1_MOSI (1ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI1_MOSI*/
<> 149:156823d33999 634 #define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0 (2ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI0_MOSI0*/
<> 149:156823d33999 635 #define SYS_GPE_MFPH_PE11MFP_UART1_nRTS (3ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART1_nRTS*/
<> 149:156823d33999 636 #define SYS_GPE_MFPH_PE11MFP_I2C0_SMBSUS (4ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C0_SMBSUS*/
<> 149:156823d33999 637 #define SYS_GPE_MFPH_PE11MFP_SC0_CLK (5ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SC0_CLK*/
<> 149:156823d33999 638 #define SYS_GPE_MFPH_PE11MFP_UART3_RXD (9ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART3_RXD*/
<> 149:156823d33999 639 #define SYS_GPE_MFPH_PE11MFP_I2C1_SDA (11ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C1_SDA*/
<> 149:156823d33999 640
<> 149:156823d33999 641 //PE12
<> 149:156823d33999 642 #define SYS_GPE_MFPH_PE12MFP_GPIO (0ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for GPIO*/
<> 149:156823d33999 643 #define SYS_GPE_MFPH_PE12MFP_SPI1_SS (1ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI1_SS*/
<> 149:156823d33999 644 #define SYS_GPE_MFPH_PE12MFP_SPI0_SS (2ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI0_SS*/
<> 149:156823d33999 645 #define SYS_GPE_MFPH_PE12MFP_UART1_TXD (3ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for UART1_TXD*/
<> 149:156823d33999 646 #define SYS_GPE_MFPH_PE12MFP_I2C0_SCL (4ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for I2C0_SCL*/
<> 149:156823d33999 647
<> 149:156823d33999 648 //PE13
<> 149:156823d33999 649 #define SYS_GPE_MFPH_PE13MFP_GPIO (0ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for GPIO*/
<> 149:156823d33999 650 #define SYS_GPE_MFPH_PE13MFP_SPI1_CLK (1ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI1_CLK*/
<> 149:156823d33999 651 #define SYS_GPE_MFPH_PE13MFP_SPI0_CLK (2ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI0_CLK*/
<> 149:156823d33999 652 #define SYS_GPE_MFPH_PE13MFP_UART1_RXD (3ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for UART1_RXD*/
<> 149:156823d33999 653 #define SYS_GPE_MFPH_PE13MFP_I2C0_SDA (4ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for I2C0_SDA*/
<> 149:156823d33999 654
<> 149:156823d33999 655 //PE14
<> 149:156823d33999 656 #define SYS_GPE_MFPH_PE14MFP_GPIO (0ul << SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for GPIO*/
<> 149:156823d33999 657
<> 149:156823d33999 658 //PF0
<> 149:156823d33999 659 #define SYS_GPF_MFPL_PF0MFP_GPIO (0ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO*/
<> 149:156823d33999 660 #define SYS_GPF_MFPL_PF0MFP_X32_OUT (1ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for X32_OUT*/
<> 149:156823d33999 661 #define SYS_GPF_MFPL_PF0MFP_INT5 (8ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for INT5*/
<> 149:156823d33999 662
<> 149:156823d33999 663 //PF1
<> 149:156823d33999 664 #define SYS_GPF_MFPL_PF1MFP_GPIO (0ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO*/
<> 149:156823d33999 665 #define SYS_GPF_MFPL_PF1MFP_X32_IN (1ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for X32_IN*/
<> 149:156823d33999 666
<> 149:156823d33999 667 //PF2
<> 149:156823d33999 668 #define SYS_GPF_MFPL_PF2MFP_GPIO (0ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO*/
<> 149:156823d33999 669 #define SYS_GPF_MFPL_PF2MFP_TAMPER (1ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for TAMPER*/
<> 149:156823d33999 670
<> 149:156823d33999 671 //PF3
<> 149:156823d33999 672 #define SYS_GPF_MFPL_PF3MFP_GPIO (0ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO*/
<> 149:156823d33999 673 #define SYS_GPF_MFPL_PF3MFP_XT1_OUT (1ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_OUT*/
<> 149:156823d33999 674 #define SYS_GPF_MFPL_PF3MFP_I2C1_SCL (3ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C1_SCL*/
<> 149:156823d33999 675
<> 149:156823d33999 676 //PF4
<> 149:156823d33999 677 #define SYS_GPF_MFPL_PF4MFP_GPIO (0ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO*/
<> 149:156823d33999 678 #define SYS_GPF_MFPL_PF4MFP_XT1_IN (1ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for XT1_IN*/
<> 149:156823d33999 679 #define SYS_GPF_MFPL_PF4MFP_I2C1_SDA (3ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for I2C1_SDA*/
<> 149:156823d33999 680
<> 149:156823d33999 681 //PF5
<> 149:156823d33999 682 #define SYS_GPF_MFPL_PF5MFP_GPIO (0ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO*/
<> 149:156823d33999 683 #define SYS_GPF_MFPL_PF5MFP_ICE_CLK (1ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for ICE_CLK*/
<> 149:156823d33999 684
<> 149:156823d33999 685 //PF6
<> 149:156823d33999 686 #define SYS_GPF_MFPL_PF6MFP_GPIO (0ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO*/
<> 149:156823d33999 687 #define SYS_GPF_MFPL_PF6MFP_ICE_DAT (1ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for ICE_DAT*/
<> 149:156823d33999 688
<> 149:156823d33999 689 //PF7
<> 149:156823d33999 690 #define SYS_GPF_MFPL_PF7MFP_GPIO (0ul << SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO*/
<> 149:156823d33999 691
<> 149:156823d33999 692
<> 149:156823d33999 693 /*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
<> 149:156823d33999 694
<> 149:156823d33999 695
<> 149:156823d33999 696 /** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
<> 149:156823d33999 697 @{
<> 149:156823d33999 698 */
<> 149:156823d33999 699
<> 149:156823d33999 700
<> 149:156823d33999 701 /**
<> 149:156823d33999 702 * @brief Clear Brown-out detector interrupt flag
<> 149:156823d33999 703 * @param None
<> 149:156823d33999 704 * @return None
<> 149:156823d33999 705 * @details This macro clear Brown-out detector interrupt flag.
<> 149:156823d33999 706 */
<> 149:156823d33999 707 #define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
<> 149:156823d33999 708
<> 149:156823d33999 709 /**
<> 149:156823d33999 710 * @brief Set Brown-out detector function to normal mode
<> 149:156823d33999 711 * @param None
<> 149:156823d33999 712 * @return None
<> 149:156823d33999 713 * @details This macro set Brown-out detector to normal mode.
<> 149:156823d33999 714 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 715 */
<> 149:156823d33999 716 #define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
<> 149:156823d33999 717
<> 149:156823d33999 718 /**
<> 149:156823d33999 719 * @brief Disable Brown-out detector function
<> 149:156823d33999 720 * @param None
<> 149:156823d33999 721 * @return None
<> 149:156823d33999 722 * @details This macro disable Brown-out detector function.
<> 149:156823d33999 723 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 724 */
<> 149:156823d33999 725 #define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
<> 149:156823d33999 726
<> 149:156823d33999 727 /**
<> 149:156823d33999 728 * @brief Enable Brown-out detector function
<> 149:156823d33999 729 * @param None
<> 149:156823d33999 730 * @return None
<> 149:156823d33999 731 * @details This macro enable Brown-out detector function.
<> 149:156823d33999 732 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 733 */
<> 149:156823d33999 734 #define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
<> 149:156823d33999 735
<> 149:156823d33999 736 /**
<> 149:156823d33999 737 * @brief Get Brown-out detector interrupt flag
<> 149:156823d33999 738 * @param None
<> 149:156823d33999 739 * @retval 0 Brown-out detect interrupt flag is not set.
<> 149:156823d33999 740 * @retval >=1 Brown-out detect interrupt flag is set.
<> 149:156823d33999 741 * @details This macro get Brown-out detector interrupt flag.
<> 149:156823d33999 742 */
<> 149:156823d33999 743 #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
<> 149:156823d33999 744
<> 149:156823d33999 745 /**
<> 149:156823d33999 746 * @brief Get Brown-out detector status
<> 149:156823d33999 747 * @param None
<> 149:156823d33999 748 * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
<> 149:156823d33999 749 * @retval >=1 System voltage is lower than BOD threshold voltage setting.
<> 149:156823d33999 750 * @details This macro get Brown-out detector output status.
<> 149:156823d33999 751 * If the BOD function is disabled, this function always return 0.
<> 149:156823d33999 752 */
<> 149:156823d33999 753 #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
<> 149:156823d33999 754
<> 149:156823d33999 755 /**
<> 149:156823d33999 756 * @brief Enable Brown-out detector interrupt function
<> 149:156823d33999 757 * @param None
<> 149:156823d33999 758 * @return None
<> 149:156823d33999 759 * @details This macro enable Brown-out detector interrupt function.
<> 149:156823d33999 760 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 761 */
<> 149:156823d33999 762 #define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
<> 149:156823d33999 763
<> 149:156823d33999 764 /**
<> 149:156823d33999 765 * @brief Enable Brown-out detector reset function
<> 149:156823d33999 766 * @param None
<> 149:156823d33999 767 * @return None
<> 149:156823d33999 768 * @details This macro enable Brown-out detect reset function.
<> 149:156823d33999 769 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 770 */
<> 149:156823d33999 771 #define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
<> 149:156823d33999 772
<> 149:156823d33999 773 /**
<> 149:156823d33999 774 * @brief Set Brown-out detector function low power mode
<> 149:156823d33999 775 * @param None
<> 149:156823d33999 776 * @return None
<> 149:156823d33999 777 * @details This macro set Brown-out detector to low power mode.
<> 149:156823d33999 778 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 779 */
<> 149:156823d33999 780 #define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
<> 149:156823d33999 781
<> 149:156823d33999 782 /**
<> 149:156823d33999 783 * @brief Set Brown-out detector voltage level
<> 149:156823d33999 784 * @param[in] u32Level is Brown-out voltage level. Including :
<> 149:156823d33999 785 * - \ref SYS_BODCTL_BODVL_4_5V
<> 149:156823d33999 786 * - \ref SYS_BODCTL_BODVL_3_7V
<> 149:156823d33999 787 * - \ref SYS_BODCTL_BODVL_2_7V
<> 149:156823d33999 788 * - \ref SYS_BODCTL_BODVL_2_2V
<> 149:156823d33999 789 * @return None
<> 149:156823d33999 790 * @details This macro set Brown-out detector voltage level.
<> 149:156823d33999 791 * The write-protection function should be disabled before using this macro.
<> 149:156823d33999 792 */
<> 149:156823d33999 793 #define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
<> 149:156823d33999 794
<> 149:156823d33999 795 /**
<> 149:156823d33999 796 * @brief Get reset source is from Brown-out detector reset
<> 149:156823d33999 797 * @param None
<> 149:156823d33999 798 * @retval 0 Previous reset source is not from Brown-out detector reset
<> 149:156823d33999 799 * @retval >=1 Previous reset source is from Brown-out detector reset
<> 149:156823d33999 800 * @details This macro get previous reset source is from Brown-out detect reset or not.
<> 149:156823d33999 801 */
<> 149:156823d33999 802 #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
<> 149:156823d33999 803
<> 149:156823d33999 804 /**
<> 149:156823d33999 805 * @brief Get reset source is from CPU reset
<> 149:156823d33999 806 * @param None
<> 149:156823d33999 807 * @retval 0 Previous reset source is not from CPU reset
<> 149:156823d33999 808 * @retval >=1 Previous reset source is from CPU reset
<> 149:156823d33999 809 * @details This macro get previous reset source is from CPU reset.
<> 149:156823d33999 810 */
<> 149:156823d33999 811 #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
<> 149:156823d33999 812
<> 149:156823d33999 813 /**
<> 149:156823d33999 814 * @brief Get reset source is from LVR Reset
<> 149:156823d33999 815 * @param None
<> 149:156823d33999 816 * @retval 0 Previous reset source is not from Low-Voltage-Reset
<> 149:156823d33999 817 * @retval >=1 Previous reset source is from Low-Voltage-Reset
<> 149:156823d33999 818 * @details This macro get previous reset source is from Low-Voltage-Reset.
<> 149:156823d33999 819 */
<> 149:156823d33999 820 #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
<> 149:156823d33999 821
<> 149:156823d33999 822 /**
<> 149:156823d33999 823 * @brief Get reset source is from Power-on Reset
<> 149:156823d33999 824 * @param None
<> 149:156823d33999 825 * @retval 0 Previous reset source is not from Power-on Reset
<> 149:156823d33999 826 * @retval >=1 Previous reset source is from Power-on Reset
<> 149:156823d33999 827 * @details This macro get previous reset source is from Power-on Reset.
<> 149:156823d33999 828 */
<> 149:156823d33999 829 #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
<> 149:156823d33999 830
<> 149:156823d33999 831 /**
<> 149:156823d33999 832 * @brief Get reset source is from reset pin reset
<> 149:156823d33999 833 * @param None
<> 149:156823d33999 834 * @retval 0 Previous reset source is not from reset pin reset
<> 149:156823d33999 835 * @retval >=1 Previous reset source is from reset pin reset
<> 149:156823d33999 836 * @details This macro get previous reset source is from reset pin reset.
<> 149:156823d33999 837 */
<> 149:156823d33999 838 #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
<> 149:156823d33999 839
<> 149:156823d33999 840 /**
<> 149:156823d33999 841 * @brief Get reset source is from system reset
<> 149:156823d33999 842 * @param None
<> 149:156823d33999 843 * @retval 0 Previous reset source is not from system reset
<> 149:156823d33999 844 * @retval >=1 Previous reset source is from system reset
<> 149:156823d33999 845 * @details This macro get previous reset source is from system reset.
<> 149:156823d33999 846 */
<> 149:156823d33999 847 #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
<> 149:156823d33999 848
<> 149:156823d33999 849 /**
<> 149:156823d33999 850 * @brief Get reset source is from window watch dog reset
<> 149:156823d33999 851 * @param None
<> 149:156823d33999 852 * @retval 0 Previous reset source is not from window watch dog reset
<> 149:156823d33999 853 * @retval >=1 Previous reset source is from window watch dog reset
<> 149:156823d33999 854 * @details This macro get previous reset source is from window watch dog reset.
<> 149:156823d33999 855 */
<> 149:156823d33999 856 #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
<> 149:156823d33999 857
<> 149:156823d33999 858 /**
<> 149:156823d33999 859 * @brief Disable Low-Voltage-Reset function
<> 149:156823d33999 860 * @param None
<> 149:156823d33999 861 * @return None
<> 149:156823d33999 862 * @details This macro disable Low-Voltage-Reset function.
<> 149:156823d33999 863 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 864 */
<> 149:156823d33999 865 #define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
<> 149:156823d33999 866
<> 149:156823d33999 867 /**
<> 149:156823d33999 868 * @brief Enable Low-Voltage-Reset function
<> 149:156823d33999 869 * @param None
<> 149:156823d33999 870 * @return None
<> 149:156823d33999 871 * @details This macro enable Low-Voltage-Reset function.
<> 149:156823d33999 872 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 873 */
<> 149:156823d33999 874 #define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
<> 149:156823d33999 875
<> 149:156823d33999 876 /**
<> 149:156823d33999 877 * @brief Disable Power-on Reset function
<> 149:156823d33999 878 * @param None
<> 149:156823d33999 879 * @return None
<> 149:156823d33999 880 * @details This macro disable Power-on Reset function.
<> 149:156823d33999 881 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 882 */
<> 149:156823d33999 883 #define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
<> 149:156823d33999 884
<> 149:156823d33999 885 /**
<> 149:156823d33999 886 * @brief Enable Power-on Reset function
<> 149:156823d33999 887 * @param None
<> 149:156823d33999 888 * @return None
<> 149:156823d33999 889 * @details This macro enable Power-on Reset function.
<> 149:156823d33999 890 * The register write-protection function should be disabled before using this macro.
<> 149:156823d33999 891 */
<> 149:156823d33999 892 #define SYS_ENABLE_POR() (SYS->PORCTL = 0)
<> 149:156823d33999 893
<> 149:156823d33999 894 /**
<> 149:156823d33999 895 * @brief Clear reset source flag
<> 149:156823d33999 896 * @param[in] u32RstSrc is reset source. Including :
<> 149:156823d33999 897 * - \ref SYS_RSTSTS_PORF_Msk
<> 149:156823d33999 898 * - \ref SYS_RSTSTS_PINRF_Msk
<> 149:156823d33999 899 * - \ref SYS_RSTSTS_WDTRF_Msk
<> 149:156823d33999 900 * - \ref SYS_RSTSTS_LVRF_Msk
<> 149:156823d33999 901 * - \ref SYS_RSTSTS_BODRF_Msk
<> 149:156823d33999 902 * - \ref SYS_RSTSTS_SYSRF_Msk
<> 149:156823d33999 903 * - \ref SYS_RSTSTS_CPURF_Msk
<> 149:156823d33999 904 * - \ref SYS_RSTSTS_CPULKRF_Msk
<> 149:156823d33999 905 * @return None
<> 149:156823d33999 906 * @details This macro clear reset source flag.
<> 149:156823d33999 907 */
<> 149:156823d33999 908 #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
<> 149:156823d33999 909
<> 149:156823d33999 910
<> 149:156823d33999 911 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 912 /* static inline functions */
<> 149:156823d33999 913 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 914
<> 149:156823d33999 915
<> 149:156823d33999 916 /**
<> 149:156823d33999 917 * @brief Disable register write-protection function
<> 149:156823d33999 918 * @param None
<> 149:156823d33999 919 * @return None
<> 149:156823d33999 920 * @details This function disable register write-protection function.
<> 149:156823d33999 921 * To unlock the protected register to allow write access.
<> 149:156823d33999 922 */
<> 149:156823d33999 923 __STATIC_INLINE void SYS_UnlockReg(void)
<> 149:156823d33999 924 {
<> 149:156823d33999 925 do
<> 149:156823d33999 926 {
<> 149:156823d33999 927 SYS->REGLCTL = 0x59;
<> 149:156823d33999 928 SYS->REGLCTL = 0x16;
<> 149:156823d33999 929 SYS->REGLCTL = 0x88;
<> 149:156823d33999 930 }
<> 149:156823d33999 931 while(SYS->REGLCTL == 0);
<> 149:156823d33999 932 }
<> 149:156823d33999 933
<> 149:156823d33999 934 /**
<> 149:156823d33999 935 * @brief Enable register write-protection function
<> 149:156823d33999 936 * @param None
<> 149:156823d33999 937 * @return None
<> 149:156823d33999 938 * @details This function is used to enable register write-protection function.
<> 149:156823d33999 939 * To lock the protected register to forbid write access.
<> 149:156823d33999 940 */
<> 149:156823d33999 941 __STATIC_INLINE void SYS_LockReg(void)
<> 149:156823d33999 942 {
<> 149:156823d33999 943 SYS->REGLCTL = 0;
<> 149:156823d33999 944 }
<> 149:156823d33999 945
<> 149:156823d33999 946
<> 149:156823d33999 947 void SYS_ClearResetSrc(uint32_t u32Src);
<> 149:156823d33999 948 uint32_t SYS_GetBODStatus(void);
<> 149:156823d33999 949 uint32_t SYS_GetResetSrc(void);
<> 149:156823d33999 950 uint32_t SYS_IsRegLocked(void);
<> 149:156823d33999 951 uint32_t SYS_ReadPDID(void);
<> 149:156823d33999 952 void SYS_ResetChip(void);
<> 149:156823d33999 953 void SYS_ResetCPU(void);
<> 149:156823d33999 954 void SYS_ResetModule(uint32_t u32ModuleIndex);
<> 149:156823d33999 955 void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
<> 149:156823d33999 956 void SYS_DisableBOD(void);
<> 149:156823d33999 957
<> 149:156823d33999 958
<> 149:156823d33999 959 /*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
<> 149:156823d33999 960
<> 149:156823d33999 961 /*@}*/ /* end of group SYS_Driver */
<> 149:156823d33999 962
<> 149:156823d33999 963 /*@}*/ /* end of group Standard_Driver */
<> 149:156823d33999 964
<> 149:156823d33999 965
<> 149:156823d33999 966 #ifdef __cplusplus
<> 149:156823d33999 967 }
<> 149:156823d33999 968 #endif
<> 149:156823d33999 969
<> 149:156823d33999 970 #endif //__SYS_H__