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targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /**************************************************************************//** |
<> | 149:156823d33999 | 2 | * @file pdma.c |
<> | 149:156823d33999 | 3 | * @version V1.00 |
<> | 149:156823d33999 | 4 | * $Revision: 12 $ |
<> | 149:156823d33999 | 5 | * $Date: 15/08/11 10:26a $ |
<> | 149:156823d33999 | 6 | * @brief M451 series PDMA driver source file |
<> | 149:156823d33999 | 7 | * |
<> | 149:156823d33999 | 8 | * @note |
<> | 149:156823d33999 | 9 | * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved. |
<> | 149:156823d33999 | 10 | *****************************************************************************/ |
<> | 149:156823d33999 | 11 | #include "M451Series.h" |
<> | 149:156823d33999 | 12 | |
<> | 149:156823d33999 | 13 | |
<> | 149:156823d33999 | 14 | static uint8_t u32ChSelect[PDMA_CH_MAX]; |
<> | 149:156823d33999 | 15 | |
<> | 149:156823d33999 | 16 | /** @addtogroup Standard_Driver Standard Driver |
<> | 149:156823d33999 | 17 | @{ |
<> | 149:156823d33999 | 18 | */ |
<> | 149:156823d33999 | 19 | |
<> | 149:156823d33999 | 20 | /** @addtogroup PDMA_Driver PDMA Driver |
<> | 149:156823d33999 | 21 | @{ |
<> | 149:156823d33999 | 22 | */ |
<> | 149:156823d33999 | 23 | |
<> | 149:156823d33999 | 24 | |
<> | 149:156823d33999 | 25 | /** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions |
<> | 149:156823d33999 | 26 | @{ |
<> | 149:156823d33999 | 27 | */ |
<> | 149:156823d33999 | 28 | |
<> | 149:156823d33999 | 29 | /** |
<> | 149:156823d33999 | 30 | * @brief PDMA Open |
<> | 149:156823d33999 | 31 | * |
<> | 149:156823d33999 | 32 | * @param[in] u32Mask Channel enable bits. |
<> | 149:156823d33999 | 33 | * |
<> | 149:156823d33999 | 34 | * @return None |
<> | 149:156823d33999 | 35 | * |
<> | 149:156823d33999 | 36 | * @details This function enable the PDMA channels. |
<> | 149:156823d33999 | 37 | */ |
<> | 149:156823d33999 | 38 | void PDMA_Open(uint32_t u32Mask) |
<> | 149:156823d33999 | 39 | { |
<> | 149:156823d33999 | 40 | int volatile i; |
<> | 149:156823d33999 | 41 | |
<> | 149:156823d33999 | 42 | for(i = 0; i < PDMA_CH_MAX; i++) |
<> | 149:156823d33999 | 43 | { |
<> | 149:156823d33999 | 44 | PDMA->DSCT[i].CTL = 0; |
<> | 149:156823d33999 | 45 | u32ChSelect[i] = 0x1f; |
<> | 149:156823d33999 | 46 | } |
<> | 149:156823d33999 | 47 | |
<> | 149:156823d33999 | 48 | PDMA->CHCTL |= u32Mask; |
<> | 149:156823d33999 | 49 | } |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | /** |
<> | 149:156823d33999 | 52 | * @brief PDMA Close |
<> | 149:156823d33999 | 53 | * |
<> | 149:156823d33999 | 54 | * @param None |
<> | 149:156823d33999 | 55 | * |
<> | 149:156823d33999 | 56 | * @return None |
<> | 149:156823d33999 | 57 | * |
<> | 149:156823d33999 | 58 | * @details This function disable all PDMA channels. |
<> | 149:156823d33999 | 59 | */ |
<> | 149:156823d33999 | 60 | void PDMA_Close(void) |
<> | 149:156823d33999 | 61 | { |
<> | 149:156823d33999 | 62 | PDMA->CHCTL = 0; |
<> | 149:156823d33999 | 63 | } |
<> | 149:156823d33999 | 64 | |
<> | 149:156823d33999 | 65 | /** |
<> | 149:156823d33999 | 66 | * @brief Set PDMA Transfer Count |
<> | 149:156823d33999 | 67 | * |
<> | 149:156823d33999 | 68 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 69 | * @param[in] u32Width Data width. Valid values are |
<> | 149:156823d33999 | 70 | * - \ref PDMA_WIDTH_8 |
<> | 149:156823d33999 | 71 | * - \ref PDMA_WIDTH_16 |
<> | 149:156823d33999 | 72 | * - \ref PDMA_WIDTH_32 |
<> | 149:156823d33999 | 73 | * @param[in] u32TransCount Transfer count |
<> | 149:156823d33999 | 74 | * |
<> | 149:156823d33999 | 75 | * @return None |
<> | 149:156823d33999 | 76 | * |
<> | 149:156823d33999 | 77 | * @details This function set the selected channel data width and transfer count. |
<> | 149:156823d33999 | 78 | */ |
<> | 149:156823d33999 | 79 | void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) |
<> | 149:156823d33999 | 80 | { |
<> | 149:156823d33999 | 81 | PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); |
<> | 149:156823d33999 | 82 | PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1) << PDMA_DSCT_CTL_TXCNT_Pos)); |
<> | 149:156823d33999 | 83 | } |
<> | 149:156823d33999 | 84 | |
<> | 149:156823d33999 | 85 | /** |
<> | 149:156823d33999 | 86 | * @brief Set PDMA Transfer Address |
<> | 149:156823d33999 | 87 | * |
<> | 149:156823d33999 | 88 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 89 | * @param[in] u32SrcAddr Source address |
<> | 149:156823d33999 | 90 | * @param[in] u32SrcCtrl Source control attribute. Valid values are |
<> | 149:156823d33999 | 91 | * - \ref PDMA_SAR_INC |
<> | 149:156823d33999 | 92 | * - \ref PDMA_SAR_FIX |
<> | 149:156823d33999 | 93 | * @param[in] u32DstAddr destination address |
<> | 149:156823d33999 | 94 | * @param[in] u32DstCtrl destination control attribute. Valid values are |
<> | 149:156823d33999 | 95 | * - \ref PDMA_DAR_INC |
<> | 149:156823d33999 | 96 | * - \ref PDMA_DAR_FIX |
<> | 149:156823d33999 | 97 | * |
<> | 149:156823d33999 | 98 | * @return None |
<> | 149:156823d33999 | 99 | * |
<> | 149:156823d33999 | 100 | * @details This function set the selected channel source/destination address and attribute. |
<> | 149:156823d33999 | 101 | */ |
<> | 149:156823d33999 | 102 | void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) |
<> | 149:156823d33999 | 103 | { |
<> | 149:156823d33999 | 104 | PDMA->DSCT[u32Ch].SA = u32SrcAddr; |
<> | 149:156823d33999 | 105 | PDMA->DSCT[u32Ch].DA = u32DstAddr; |
<> | 149:156823d33999 | 106 | PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); |
<> | 149:156823d33999 | 107 | PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); |
<> | 149:156823d33999 | 108 | } |
<> | 149:156823d33999 | 109 | |
<> | 149:156823d33999 | 110 | /** |
<> | 149:156823d33999 | 111 | * @brief Set PDMA Transfer Mode |
<> | 149:156823d33999 | 112 | * |
<> | 149:156823d33999 | 113 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 114 | * @param[in] u32Peripheral The selected peripheral. Valid values are |
<> | 149:156823d33999 | 115 | * - \ref PDMA_SPI0_TX |
<> | 149:156823d33999 | 116 | * - \ref PDMA_SPI1_TX |
<> | 149:156823d33999 | 117 | * - \ref PDMA_SPI2_TX |
<> | 149:156823d33999 | 118 | * - \ref PDMA_UART0_TX |
<> | 149:156823d33999 | 119 | * - \ref PDMA_UART1_TX |
<> | 149:156823d33999 | 120 | * - \ref PDMA_UART2_TX |
<> | 149:156823d33999 | 121 | * - \ref PDMA_UART3_TX |
<> | 149:156823d33999 | 122 | * - \ref PDMA_DAC_TX |
<> | 149:156823d33999 | 123 | * - \ref PDMA_ADC_RX |
<> | 149:156823d33999 | 124 | * - \ref PDMA_PWM0_P1_RX |
<> | 149:156823d33999 | 125 | * - \ref PDMA_PWM0_P2_RX |
<> | 149:156823d33999 | 126 | * - \ref PDMA_PWM0_P3_RX |
<> | 149:156823d33999 | 127 | * - \ref PDMA_PWM1_P1_RX |
<> | 149:156823d33999 | 128 | * - \ref PDMA_PWM1_P2_RX |
<> | 149:156823d33999 | 129 | * - \ref PDMA_PWM1_P3_RX |
<> | 149:156823d33999 | 130 | * - \ref PDMA_SPI0_RX |
<> | 149:156823d33999 | 131 | * - \ref PDMA_SPI1_RX |
<> | 149:156823d33999 | 132 | * - \ref PDMA_SPI2_RX |
<> | 149:156823d33999 | 133 | * - \ref PDMA_UART0_RX |
<> | 149:156823d33999 | 134 | * - \ref PDMA_UART1_RX |
<> | 149:156823d33999 | 135 | * - \ref PDMA_UART2_RX |
<> | 149:156823d33999 | 136 | * - \ref PDMA_UART3_RX |
<> | 149:156823d33999 | 137 | * - \ref PDMA_MEM |
<> | 149:156823d33999 | 138 | * @param[in] u32ScatterEn Scatter-gather mode enable |
<> | 149:156823d33999 | 139 | * @param[in] u32DescAddr Scatter-gather descriptor address |
<> | 149:156823d33999 | 140 | * |
<> | 149:156823d33999 | 141 | * @return None |
<> | 149:156823d33999 | 142 | * |
<> | 149:156823d33999 | 143 | * @details This function set the selected channel transfer mode. Include peripheral setting. |
<> | 149:156823d33999 | 144 | */ |
<> | 149:156823d33999 | 145 | void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) |
<> | 149:156823d33999 | 146 | { |
<> | 149:156823d33999 | 147 | u32ChSelect[u32Ch] = u32Peripheral; |
<> | 149:156823d33999 | 148 | switch(u32Ch) |
<> | 149:156823d33999 | 149 | { |
<> | 149:156823d33999 | 150 | case 0: |
<> | 149:156823d33999 | 151 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; |
<> | 149:156823d33999 | 152 | break; |
<> | 149:156823d33999 | 153 | case 1: |
<> | 149:156823d33999 | 154 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); |
<> | 149:156823d33999 | 155 | break; |
<> | 149:156823d33999 | 156 | case 2: |
<> | 149:156823d33999 | 157 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); |
<> | 149:156823d33999 | 158 | break; |
<> | 149:156823d33999 | 159 | case 3: |
<> | 149:156823d33999 | 160 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); |
<> | 149:156823d33999 | 161 | break; |
<> | 149:156823d33999 | 162 | case 4: |
<> | 149:156823d33999 | 163 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; |
<> | 149:156823d33999 | 164 | break; |
<> | 149:156823d33999 | 165 | case 5: |
<> | 149:156823d33999 | 166 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); |
<> | 149:156823d33999 | 167 | break; |
<> | 149:156823d33999 | 168 | case 6: |
<> | 149:156823d33999 | 169 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); |
<> | 149:156823d33999 | 170 | break; |
<> | 149:156823d33999 | 171 | case 7: |
<> | 149:156823d33999 | 172 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); |
<> | 149:156823d33999 | 173 | break; |
<> | 149:156823d33999 | 174 | case 8: |
<> | 149:156823d33999 | 175 | PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral; |
<> | 149:156823d33999 | 176 | break; |
<> | 149:156823d33999 | 177 | case 9: |
<> | 149:156823d33999 | 178 | PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos); |
<> | 149:156823d33999 | 179 | break; |
<> | 149:156823d33999 | 180 | case 10: |
<> | 149:156823d33999 | 181 | PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos); |
<> | 149:156823d33999 | 182 | break; |
<> | 149:156823d33999 | 183 | case 11: |
<> | 149:156823d33999 | 184 | PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos); |
<> | 149:156823d33999 | 185 | break; |
<> | 149:156823d33999 | 186 | default: |
<> | 149:156823d33999 | 187 | ; |
<> | 149:156823d33999 | 188 | } |
<> | 149:156823d33999 | 189 | |
<> | 149:156823d33999 | 190 | if(u32ScatterEn) |
<> | 149:156823d33999 | 191 | { |
<> | 149:156823d33999 | 192 | PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; |
<> | 149:156823d33999 | 193 | PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA); |
<> | 149:156823d33999 | 194 | } |
<> | 149:156823d33999 | 195 | else |
<> | 149:156823d33999 | 196 | PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; |
<> | 149:156823d33999 | 197 | } |
<> | 149:156823d33999 | 198 | |
<> | 149:156823d33999 | 199 | /** |
<> | 149:156823d33999 | 200 | * @brief Set PDMA Burst Type and Size |
<> | 149:156823d33999 | 201 | * |
<> | 149:156823d33999 | 202 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 203 | * @param[in] u32BurstType Burst mode or single mode. Valid values are |
<> | 149:156823d33999 | 204 | * - \ref PDMA_REQ_SINGLE |
<> | 149:156823d33999 | 205 | * - \ref PDMA_REQ_BURST |
<> | 149:156823d33999 | 206 | * @param[in] u32BurstSize Set the size of burst mode. Valid values are |
<> | 149:156823d33999 | 207 | * - \ref PDMA_BURST_128 |
<> | 149:156823d33999 | 208 | * - \ref PDMA_BURST_64 |
<> | 149:156823d33999 | 209 | * - \ref PDMA_BURST_32 |
<> | 149:156823d33999 | 210 | * - \ref PDMA_BURST_16 |
<> | 149:156823d33999 | 211 | * - \ref PDMA_BURST_8 |
<> | 149:156823d33999 | 212 | * - \ref PDMA_BURST_4 |
<> | 149:156823d33999 | 213 | * - \ref PDMA_BURST_2 |
<> | 149:156823d33999 | 214 | * - \ref PDMA_BURST_1 |
<> | 149:156823d33999 | 215 | * |
<> | 149:156823d33999 | 216 | * @return None |
<> | 149:156823d33999 | 217 | * |
<> | 149:156823d33999 | 218 | * @details This function set the selected channel burst type and size. |
<> | 149:156823d33999 | 219 | */ |
<> | 149:156823d33999 | 220 | void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) |
<> | 149:156823d33999 | 221 | { |
<> | 149:156823d33999 | 222 | PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); |
<> | 149:156823d33999 | 223 | PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); |
<> | 149:156823d33999 | 224 | } |
<> | 149:156823d33999 | 225 | |
<> | 149:156823d33999 | 226 | /** |
<> | 149:156823d33999 | 227 | * @brief Enable timeout function |
<> | 149:156823d33999 | 228 | * |
<> | 149:156823d33999 | 229 | * @param[in] u32Mask Channel enable bits. |
<> | 149:156823d33999 | 230 | * |
<> | 149:156823d33999 | 231 | * @return None |
<> | 149:156823d33999 | 232 | * |
<> | 149:156823d33999 | 233 | * @details This function enable timeout function of the selected channel(s). |
<> | 149:156823d33999 | 234 | * @note This function is only supported in M45xD/M45xC. |
<> | 149:156823d33999 | 235 | */ |
<> | 149:156823d33999 | 236 | void PDMA_EnableTimeout(uint32_t u32Mask) |
<> | 149:156823d33999 | 237 | { |
<> | 149:156823d33999 | 238 | PDMA->TOUTEN |= u32Mask; |
<> | 149:156823d33999 | 239 | } |
<> | 149:156823d33999 | 240 | |
<> | 149:156823d33999 | 241 | /** |
<> | 149:156823d33999 | 242 | * @brief Disable timeout function |
<> | 149:156823d33999 | 243 | * |
<> | 149:156823d33999 | 244 | * @param[in] u32Mask Channel enable bits. |
<> | 149:156823d33999 | 245 | * |
<> | 149:156823d33999 | 246 | * @return None |
<> | 149:156823d33999 | 247 | * |
<> | 149:156823d33999 | 248 | * @details This function disable timeout function of the selected channel(s). |
<> | 149:156823d33999 | 249 | * @note This function is only supported in M45xD/M45xC. |
<> | 149:156823d33999 | 250 | */ |
<> | 149:156823d33999 | 251 | void PDMA_DisableTimeout(uint32_t u32Mask) |
<> | 149:156823d33999 | 252 | { |
<> | 149:156823d33999 | 253 | PDMA->TOUTEN &= ~u32Mask; |
<> | 149:156823d33999 | 254 | } |
<> | 149:156823d33999 | 255 | |
<> | 149:156823d33999 | 256 | /** |
<> | 149:156823d33999 | 257 | * @brief Set PDMA Timeout Count |
<> | 149:156823d33999 | 258 | * |
<> | 149:156823d33999 | 259 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 260 | * @param[in] u32OnOff Enable/disable time out function |
<> | 149:156823d33999 | 261 | * @param[in] u32TimeOutCnt Timeout count |
<> | 149:156823d33999 | 262 | * |
<> | 149:156823d33999 | 263 | * @return None |
<> | 149:156823d33999 | 264 | * |
<> | 149:156823d33999 | 265 | * @details This function set the timeout count. |
<> | 149:156823d33999 | 266 | * @note This function is only supported in M45xD/M45xC. |
<> | 149:156823d33999 | 267 | */ |
<> | 149:156823d33999 | 268 | void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) |
<> | 149:156823d33999 | 269 | { |
<> | 149:156823d33999 | 270 | switch(u32Ch) |
<> | 149:156823d33999 | 271 | { |
<> | 149:156823d33999 | 272 | case 0: |
<> | 149:156823d33999 | 273 | PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; |
<> | 149:156823d33999 | 274 | break; |
<> | 149:156823d33999 | 275 | case 1: |
<> | 149:156823d33999 | 276 | PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); |
<> | 149:156823d33999 | 277 | break; |
<> | 149:156823d33999 | 278 | case 2: |
<> | 149:156823d33999 | 279 | PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt; |
<> | 149:156823d33999 | 280 | break; |
<> | 149:156823d33999 | 281 | case 3: |
<> | 149:156823d33999 | 282 | PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos); |
<> | 149:156823d33999 | 283 | break; |
<> | 149:156823d33999 | 284 | case 4: |
<> | 149:156823d33999 | 285 | PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt; |
<> | 149:156823d33999 | 286 | break; |
<> | 149:156823d33999 | 287 | case 5: |
<> | 149:156823d33999 | 288 | PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos); |
<> | 149:156823d33999 | 289 | break; |
<> | 149:156823d33999 | 290 | case 6: |
<> | 149:156823d33999 | 291 | PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt; |
<> | 149:156823d33999 | 292 | break; |
<> | 149:156823d33999 | 293 | case 7: |
<> | 149:156823d33999 | 294 | PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos); |
<> | 149:156823d33999 | 295 | break; |
<> | 149:156823d33999 | 296 | |
<> | 149:156823d33999 | 297 | default: |
<> | 149:156823d33999 | 298 | ; |
<> | 149:156823d33999 | 299 | } |
<> | 149:156823d33999 | 300 | } |
<> | 149:156823d33999 | 301 | |
<> | 149:156823d33999 | 302 | /** |
<> | 149:156823d33999 | 303 | * @brief Trigger PDMA |
<> | 149:156823d33999 | 304 | * |
<> | 149:156823d33999 | 305 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 306 | * |
<> | 149:156823d33999 | 307 | * @return None |
<> | 149:156823d33999 | 308 | * |
<> | 149:156823d33999 | 309 | * @details This function trigger the selected channel. |
<> | 149:156823d33999 | 310 | */ |
<> | 149:156823d33999 | 311 | void PDMA_Trigger(uint32_t u32Ch) |
<> | 149:156823d33999 | 312 | { |
<> | 149:156823d33999 | 313 | if(u32ChSelect[u32Ch] == PDMA_MEM) |
<> | 149:156823d33999 | 314 | PDMA->SWREQ = (1 << u32Ch); |
<> | 149:156823d33999 | 315 | } |
<> | 149:156823d33999 | 316 | |
<> | 149:156823d33999 | 317 | /** |
<> | 149:156823d33999 | 318 | * @brief Enable Interrupt |
<> | 149:156823d33999 | 319 | * |
<> | 149:156823d33999 | 320 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 321 | * @param[in] u32Mask The Interrupt Type. Valid values are |
<> | 149:156823d33999 | 322 | * - \ref PDMA_INT_TRANS_DONE |
<> | 149:156823d33999 | 323 | * - \ref PDMA_INT_TEMPTY |
<> | 149:156823d33999 | 324 | * - \ref PDMA_INT_TIMEOUT |
<> | 149:156823d33999 | 325 | * |
<> | 149:156823d33999 | 326 | * @return None |
<> | 149:156823d33999 | 327 | * |
<> | 149:156823d33999 | 328 | * @details This function enable the selected channel interrupt. |
<> | 149:156823d33999 | 329 | * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC. |
<> | 149:156823d33999 | 330 | */ |
<> | 149:156823d33999 | 331 | void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask) |
<> | 149:156823d33999 | 332 | { |
<> | 149:156823d33999 | 333 | switch(u32Mask) |
<> | 149:156823d33999 | 334 | { |
<> | 149:156823d33999 | 335 | case PDMA_INT_TRANS_DONE: |
<> | 149:156823d33999 | 336 | PDMA->INTEN |= (1 << u32Ch); |
<> | 149:156823d33999 | 337 | break; |
<> | 149:156823d33999 | 338 | case PDMA_INT_TEMPTY: |
<> | 149:156823d33999 | 339 | PDMA->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; |
<> | 149:156823d33999 | 340 | break; |
<> | 149:156823d33999 | 341 | case PDMA_INT_TIMEOUT: |
<> | 149:156823d33999 | 342 | PDMA->TOUTIEN |= (1 << u32Ch); |
<> | 149:156823d33999 | 343 | break; |
<> | 149:156823d33999 | 344 | |
<> | 149:156823d33999 | 345 | default: |
<> | 149:156823d33999 | 346 | ; |
<> | 149:156823d33999 | 347 | } |
<> | 149:156823d33999 | 348 | } |
<> | 149:156823d33999 | 349 | |
<> | 149:156823d33999 | 350 | /** |
<> | 149:156823d33999 | 351 | * @brief Disable Interrupt |
<> | 149:156823d33999 | 352 | * |
<> | 149:156823d33999 | 353 | * @param[in] u32Ch The selected channel |
<> | 149:156823d33999 | 354 | * @param[in] u32Mask The Interrupt Type. Valid values are |
<> | 149:156823d33999 | 355 | * - \ref PDMA_INT_TRANS_DONE |
<> | 149:156823d33999 | 356 | * - \ref PDMA_INT_TEMPTY |
<> | 149:156823d33999 | 357 | * - \ref PDMA_INT_TIMEOUT |
<> | 149:156823d33999 | 358 | * |
<> | 149:156823d33999 | 359 | * @return None |
<> | 149:156823d33999 | 360 | * |
<> | 149:156823d33999 | 361 | * @details This function disable the selected channel interrupt. |
<> | 149:156823d33999 | 362 | * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC. |
<> | 149:156823d33999 | 363 | */ |
<> | 149:156823d33999 | 364 | void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask) |
<> | 149:156823d33999 | 365 | { |
<> | 149:156823d33999 | 366 | switch(u32Mask) |
<> | 149:156823d33999 | 367 | { |
<> | 149:156823d33999 | 368 | case PDMA_INT_TRANS_DONE: |
<> | 149:156823d33999 | 369 | PDMA->INTEN &= ~(1 << u32Ch); |
<> | 149:156823d33999 | 370 | break; |
<> | 149:156823d33999 | 371 | case PDMA_INT_TEMPTY: |
<> | 149:156823d33999 | 372 | PDMA->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; |
<> | 149:156823d33999 | 373 | break; |
<> | 149:156823d33999 | 374 | case PDMA_INT_TIMEOUT: |
<> | 149:156823d33999 | 375 | PDMA->TOUTIEN &= ~(1 << u32Ch); |
<> | 149:156823d33999 | 376 | break; |
<> | 149:156823d33999 | 377 | |
<> | 149:156823d33999 | 378 | default: |
<> | 149:156823d33999 | 379 | ; |
<> | 149:156823d33999 | 380 | } |
<> | 149:156823d33999 | 381 | } |
<> | 149:156823d33999 | 382 | |
<> | 149:156823d33999 | 383 | /*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ |
<> | 149:156823d33999 | 384 | |
<> | 149:156823d33999 | 385 | /*@}*/ /* end of group PDMA_Driver */ |
<> | 149:156823d33999 | 386 | |
<> | 149:156823d33999 | 387 | /*@}*/ /* end of group Standard_Driver */ |
<> | 149:156823d33999 | 388 | |
<> | 149:156823d33999 | 389 | /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/ |