Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

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targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_pdma.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file pdma.h
<> 144:ef7eb2e8f9f7 3 * @version V1.00
<> 144:ef7eb2e8f9f7 4 * $Revision: 8 $
<> 144:ef7eb2e8f9f7 5 * $Date: 14/06/05 5:16p $
<> 144:ef7eb2e8f9f7 6 * @brief NUC472/NUC442 PDMA driver header file
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *****************************************************************************/
<> 144:ef7eb2e8f9f7 11 #ifndef __PDMA_H__
<> 144:ef7eb2e8f9f7 12 #define __PDMA_H__
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 15 extern "C"
<> 144:ef7eb2e8f9f7 16 {
<> 144:ef7eb2e8f9f7 17 #endif
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
<> 144:ef7eb2e8f9f7 21 @{
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 /** @addtogroup NUC472_442_PDMA_Driver PDMA Driver
<> 144:ef7eb2e8f9f7 25 @{
<> 144:ef7eb2e8f9f7 26 */
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 /** @addtogroup NUC472_442_PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
<> 144:ef7eb2e8f9f7 29 @{
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31 #define PDMA_CH_MAX 16 /*!< Specify Maximum Channels of PDMA \hideinitializer */
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 34 /* operation Mode Constant Definitions */
<> 144:ef7eb2e8f9f7 35 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36 #define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
<> 144:ef7eb2e8f9f7 37 #define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
<> 144:ef7eb2e8f9f7 38 #define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 41 /* Data Width Constant Definitions */
<> 144:ef7eb2e8f9f7 42 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 43 #define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
<> 144:ef7eb2e8f9f7 44 #define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
<> 144:ef7eb2e8f9f7 45 #define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 /* Address Attribute Constant Definitions */
<> 144:ef7eb2e8f9f7 49 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 50 #define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
<> 144:ef7eb2e8f9f7 51 #define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
<> 144:ef7eb2e8f9f7 52 #define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
<> 144:ef7eb2e8f9f7 53 #define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /* Burst Mode Constant Definitions */
<> 144:ef7eb2e8f9f7 57 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 #define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
<> 144:ef7eb2e8f9f7 59 #define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 62 #define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 63 #define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 64 #define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 65 #define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 66 #define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 67 #define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 68 #define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 71 /* Peripheral Transfer Mode Constant Definitions */
<> 144:ef7eb2e8f9f7 72 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 73 #define PDMA_SPI0_TX 0x00000000UL /*!<DMA Connect to SPI0 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 74 #define PDMA_SPI1_TX 0x00000001UL /*!<DMA Connect to SPI1 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 75 #define PDMA_SPI2_TX 0x00000002UL /*!<DMA Connect to SPI2 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 76 #define PDMA_SPI3_TX 0x00000003UL /*!<DMA Connect to SPI3 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 77 #define PDMA_UART0_TX 0x00000004UL /*!<DMA Connect to UART0 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 78 #define PDMA_UART1_TX 0x00000005UL /*!<DMA Connect to UART1 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 79 #define PDMA_UART2_TX 0x00000006UL /*!<DMA Connect to UART2 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 80 #define PDMA_UART3_TX 0x00000007UL /*!<DMA Connect to UART3 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 81 #define PDMA_UART4_TX 0x00000008UL /*!<DMA Connect to UART4 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 82 #define PDMA_UART5_TX 0x00000009UL /*!<DMA Connect to UART5 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 83 #define PDMA_I2S0_TX 0x0000000BUL /*!<DMA Connect to I2S TX \hideinitializer */
<> 144:ef7eb2e8f9f7 84 #define PDMA_I2S1_TX 0x0000000CUL /*!<DMA Connect to I2S1 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 85 #define PDMA_SPI0_RX 0x0000000DUL /*!<DMA Connect to SPI0 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 86 #define PDMA_SPI1_RX 0x0000000EUL /*!<DMA Connect to SPI1 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 87 #define PDMA_SPI2_RX 0x0000000FUL /*!<DMA Connect to SPI2 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 88 #define PDMA_SPI3_RX 0x00000010UL /*!<DMA Connect to SPI3 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 89 #define PDMA_UART0_RX 0x00000011UL /*!<DMA Connect to UART0 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 90 #define PDMA_UART1_RX 0x00000012UL /*!<DMA Connect to UART1 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 91 #define PDMA_UART2_RX 0x00000013UL /*!<DMA Connect to UART2 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 92 #define PDMA_UART3_RX 0x00000014UL /*!<DMA Connect to UART3 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 93 #define PDMA_UART4_RX 0x00000015UL /*!<DMA Connect to UART4 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 94 #define PDMA_UART5_RX 0x00000016UL /*!<DMA Connect to UART5 RX \hideinitializer */
<> 144:ef7eb2e8f9f7 95 #define PDMA_ADC 0x00000018UL /*!<DMA Connect to ADC \hideinitializer */
<> 144:ef7eb2e8f9f7 96 #define PDMA_I2S0_RX 0x00000019UL /*!<DMA Connect to I2S TX \hideinitializer */
<> 144:ef7eb2e8f9f7 97 #define PDMA_I2S1_RX 0x0000001AUL /*!<DMA Connect to I2S1 TX \hideinitializer */
<> 144:ef7eb2e8f9f7 98 #define PDMA_MEM 0x0000001FUL /*!<DMA Connect to Memory \hideinitializer */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_CONSTANTS */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup NUC472_442_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
<> 144:ef7eb2e8f9f7 103 @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief Get PDMA Interrupt Status
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * @param[in] None
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * @return None
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * @details This macro gets the interrupt status.
<> 144:ef7eb2e8f9f7 114 * \hideinitializer
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 #define PDMA_GET_INT_STATUS() ((uint32_t)(PDMA->INTSTS))
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @brief Get Transfer Done Interrupt Status
<> 144:ef7eb2e8f9f7 120 *
<> 144:ef7eb2e8f9f7 121 * @param[in] None
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 * @return None
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 * @details Get the transfer done Interrupt status.
<> 144:ef7eb2e8f9f7 126 * \hideinitializer
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 #define PDMA_GET_TD_STS() ((uint32_t)(PDMA->TDSTS))
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /**
<> 144:ef7eb2e8f9f7 131 * @brief Clear Transfer Done Interrupt Status
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 * @param[in] u32Mask The channel mask
<> 144:ef7eb2e8f9f7 134 *
<> 144:ef7eb2e8f9f7 135 * @return None
<> 144:ef7eb2e8f9f7 136 *
<> 144:ef7eb2e8f9f7 137 * @details Clear the transfer done Interrupt status.
<> 144:ef7eb2e8f9f7 138 * \hideinitializer
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 #define PDMA_CLR_TD_FLAG(u32Mask) ((uint32_t)(PDMA->TDSTS = u32Mask))
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @brief Get Target Abort Interrupt Status
<> 144:ef7eb2e8f9f7 144 *
<> 144:ef7eb2e8f9f7 145 * @param[in] None
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 * @return None
<> 144:ef7eb2e8f9f7 148 *
<> 144:ef7eb2e8f9f7 149 * @details Get the target abort Interrupt status.
<> 144:ef7eb2e8f9f7 150 * \hideinitializer
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 #define PDMA_GET_ABORT_STS() ((uint32_t)(PDMA->ABTSTS))
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @brief Clear Target Abort Interrupt Status
<> 144:ef7eb2e8f9f7 156 *
<> 144:ef7eb2e8f9f7 157 * @param[in] u32Mask The channel mask
<> 144:ef7eb2e8f9f7 158 *
<> 144:ef7eb2e8f9f7 159 * @return None
<> 144:ef7eb2e8f9f7 160 *
<> 144:ef7eb2e8f9f7 161 * @details Clear the target abort Interrupt status.
<> 144:ef7eb2e8f9f7 162 * \hideinitializer
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define PDMA_CLR_ABORT_FLAG(u32Mask) ((uint32_t)(PDMA->ABTSTS = u32Mask))
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @brief Get Scatter-Gather Table Empty Interrupt Status
<> 144:ef7eb2e8f9f7 168 *
<> 144:ef7eb2e8f9f7 169 * @param[in] None
<> 144:ef7eb2e8f9f7 170 *
<> 144:ef7eb2e8f9f7 171 * @return None
<> 144:ef7eb2e8f9f7 172 *
<> 144:ef7eb2e8f9f7 173 * @details Get the scatter-gather table empty Interrupt status.
<> 144:ef7eb2e8f9f7 174 * \hideinitializer
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 #define PDMA_GET_EMPTY_STS() ((uint32_t)(PDMA->SCATSTS))
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @brief Clear Scatter-Gather Table Empty Interrupt Status
<> 144:ef7eb2e8f9f7 180 *
<> 144:ef7eb2e8f9f7 181 * @param[in] u32Mask The channel mask
<> 144:ef7eb2e8f9f7 182 *
<> 144:ef7eb2e8f9f7 183 * @return None
<> 144:ef7eb2e8f9f7 184 *
<> 144:ef7eb2e8f9f7 185 * @details Clear the scatter-gather table empty Interrupt status.
<> 144:ef7eb2e8f9f7 186 * \hideinitializer
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 #define PDMA_CLR_EMPTY_FLAG(u32Mask) ((uint32_t)(PDMA->SCATSTS = u32Mask))
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief Clear Timeout Interrupt Status
<> 144:ef7eb2e8f9f7 192 *
<> 144:ef7eb2e8f9f7 193 * @param[in] u32Ch The selected channel
<> 144:ef7eb2e8f9f7 194 *
<> 144:ef7eb2e8f9f7 195 * @return None
<> 144:ef7eb2e8f9f7 196 *
<> 144:ef7eb2e8f9f7 197 * @details Clear the selected channel timeout interrupt status.
<> 144:ef7eb2e8f9f7 198 * \hideinitializer
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 #define PDMA_CLR_TMOUT_FLAG(u32Ch) ((uint32_t)(PDMA->INTSTS = (1 << (u32Ch + 8))))
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @brief Check Channel Status
<> 144:ef7eb2e8f9f7 204 *
<> 144:ef7eb2e8f9f7 205 * @param[in] u32Ch The selected channel
<> 144:ef7eb2e8f9f7 206 *
<> 144:ef7eb2e8f9f7 207 * @return 0 = idle; 1 = busy
<> 144:ef7eb2e8f9f7 208 *
<> 144:ef7eb2e8f9f7 209 * @details Check the selected channel is busy or not.
<> 144:ef7eb2e8f9f7 210 * \hideinitializer
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 #define PDMA_IS_CH_BUSY(u32Ch) ((uint32_t)(PDMA->TRGSTS & (1 << u32Ch))? 1 : 0)
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @brief Set Source Address
<> 144:ef7eb2e8f9f7 216 *
<> 144:ef7eb2e8f9f7 217 * @param[in] u32Ch The selected channel
<> 144:ef7eb2e8f9f7 218 * @param[in] u32Addr The selected address
<> 144:ef7eb2e8f9f7 219 *
<> 144:ef7eb2e8f9f7 220 * @return None
<> 144:ef7eb2e8f9f7 221 *
<> 144:ef7eb2e8f9f7 222 * @details This macro set the selected channel source address.
<> 144:ef7eb2e8f9f7 223 * \hideinitializer
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225 #define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].ENDSA = u32Addr))
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @brief Set Destination Address
<> 144:ef7eb2e8f9f7 229 *
<> 144:ef7eb2e8f9f7 230 * @param[in] u32Ch The selected channel
<> 144:ef7eb2e8f9f7 231 * @param[in] u32Addr The selected address
<> 144:ef7eb2e8f9f7 232 *
<> 144:ef7eb2e8f9f7 233 * @return None
<> 144:ef7eb2e8f9f7 234 *
<> 144:ef7eb2e8f9f7 235 * @details This macro set the selected channel destination address.
<> 144:ef7eb2e8f9f7 236 * \hideinitializer
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 #define PDMA_SET_DST_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].ENDDA = u32Addr))
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief Set Transfer Count
<> 144:ef7eb2e8f9f7 242 *
<> 144:ef7eb2e8f9f7 243 * @param[in] u32Ch The selected channel
<> 144:ef7eb2e8f9f7 244 * @param[in] u32Count Transfer Count
<> 144:ef7eb2e8f9f7 245 *
<> 144:ef7eb2e8f9f7 246 * @return None
<> 144:ef7eb2e8f9f7 247 *
<> 144:ef7eb2e8f9f7 248 * @details This macro set the selected channel transfer count.
<> 144:ef7eb2e8f9f7 249 * \hideinitializer
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define PDMA_SET_TRANS_CNT(u32Ch, u32Count) ((uint32_t)(PDMA->DSCT[u32Ch].CTL=(PDMA->DSCT[u32Ch].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|((u32Count-1) << PDMA_DSCT_CTL_TXCNT_Pos))
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @brief Set Scatter-gather descriptor Address
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 * @param[in] u32Ch The selected channel
<> 144:ef7eb2e8f9f7 257 * @param[in] u32Addr The descriptor address
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 * @return None
<> 144:ef7eb2e8f9f7 260 *
<> 144:ef7eb2e8f9f7 261 * @details This macro set the selected channel scatter-gather descriptor address.
<> 144:ef7eb2e8f9f7 262 * \hideinitializer
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 #define PDMA_SET_SCATTER_DESC(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].NEXT = u32Addr - (PDMA->SCATBA)))
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @brief Stop the channel
<> 144:ef7eb2e8f9f7 268 *
<> 144:ef7eb2e8f9f7 269 * @param[in] u32Ch The selected channel
<> 144:ef7eb2e8f9f7 270 *
<> 144:ef7eb2e8f9f7 271 * @return None
<> 144:ef7eb2e8f9f7 272 *
<> 144:ef7eb2e8f9f7 273 * @details This macro stop the selected channel.
<> 144:ef7eb2e8f9f7 274 * \hideinitializer
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 #define PDMA_STOP(u32Ch) ((uint32_t)(PDMA->STOP = (1 << u32Ch)))
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 void PDMA_Open(uint32_t u32Mask);
<> 144:ef7eb2e8f9f7 281 void PDMA_Close(void);
<> 144:ef7eb2e8f9f7 282 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
<> 144:ef7eb2e8f9f7 283 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
<> 144:ef7eb2e8f9f7 284 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
<> 144:ef7eb2e8f9f7 285 void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
<> 144:ef7eb2e8f9f7 286 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
<> 144:ef7eb2e8f9f7 287 void PDMA_Trigger(uint32_t u32Ch);
<> 144:ef7eb2e8f9f7 288 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
<> 144:ef7eb2e8f9f7 289 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_FUNCTIONS */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /*@}*/ /* end of group NUC472_442_PDMA_Driver */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /*@}*/ /* end of group NUC472_442_Device_Driver */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 #endif
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 #endif //__PDMA_H__
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/