mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_pdma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file pdma.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @version V1.00 |
<> | 144:ef7eb2e8f9f7 | 4 | * $Revision: 7 $ |
<> | 144:ef7eb2e8f9f7 | 5 | * $Date: 14/05/29 1:13p $ |
<> | 144:ef7eb2e8f9f7 | 6 | * @brief NUC472/NUC442 PDMA driver source file |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * @note |
<> | 144:ef7eb2e8f9f7 | 9 | * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 10 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 11 | #include "NUC472_442.h" |
<> | 144:ef7eb2e8f9f7 | 12 | |
<> | 144:ef7eb2e8f9f7 | 13 | |
<> | 144:ef7eb2e8f9f7 | 14 | static uint8_t u32ChSelect[PDMA_CH_MAX]; |
<> | 144:ef7eb2e8f9f7 | 15 | |
<> | 144:ef7eb2e8f9f7 | 16 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
<> | 144:ef7eb2e8f9f7 | 17 | @{ |
<> | 144:ef7eb2e8f9f7 | 18 | */ |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | /** @addtogroup NUC472_442_PDMA_Driver PDMA Driver |
<> | 144:ef7eb2e8f9f7 | 21 | @{ |
<> | 144:ef7eb2e8f9f7 | 22 | */ |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | /** @addtogroup NUC472_442_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions |
<> | 144:ef7eb2e8f9f7 | 26 | @{ |
<> | 144:ef7eb2e8f9f7 | 27 | */ |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | /** |
<> | 144:ef7eb2e8f9f7 | 30 | * @brief PDMA Open |
<> | 144:ef7eb2e8f9f7 | 31 | * |
<> | 144:ef7eb2e8f9f7 | 32 | * @param[in] u32Mask Channel enable bits. |
<> | 144:ef7eb2e8f9f7 | 33 | * |
<> | 144:ef7eb2e8f9f7 | 34 | * @return None |
<> | 144:ef7eb2e8f9f7 | 35 | * |
<> | 144:ef7eb2e8f9f7 | 36 | * @details This function enable the PDMA channels. |
<> | 144:ef7eb2e8f9f7 | 37 | */ |
<> | 144:ef7eb2e8f9f7 | 38 | void PDMA_Open(uint32_t u32Mask) |
<> | 144:ef7eb2e8f9f7 | 39 | { |
<> | 144:ef7eb2e8f9f7 | 40 | int volatile i; |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | for (i=0; i<PDMA_CH_MAX; i++) { |
<> | 144:ef7eb2e8f9f7 | 43 | PDMA->DSCT[i].CTL = 0; |
<> | 144:ef7eb2e8f9f7 | 44 | u32ChSelect[i] = 0x1f; |
<> | 144:ef7eb2e8f9f7 | 45 | } |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | PDMA->CHCTL |= u32Mask; |
<> | 144:ef7eb2e8f9f7 | 48 | } |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | /** |
<> | 144:ef7eb2e8f9f7 | 51 | * @brief PDMA Close |
<> | 144:ef7eb2e8f9f7 | 52 | * |
<> | 144:ef7eb2e8f9f7 | 53 | * @param[in] None |
<> | 144:ef7eb2e8f9f7 | 54 | * |
<> | 144:ef7eb2e8f9f7 | 55 | * @return None |
<> | 144:ef7eb2e8f9f7 | 56 | * |
<> | 144:ef7eb2e8f9f7 | 57 | * @details This function disable all PDMA channels. |
<> | 144:ef7eb2e8f9f7 | 58 | */ |
<> | 144:ef7eb2e8f9f7 | 59 | void PDMA_Close(void) |
<> | 144:ef7eb2e8f9f7 | 60 | { |
<> | 144:ef7eb2e8f9f7 | 61 | PDMA->CHCTL = 0; |
<> | 144:ef7eb2e8f9f7 | 62 | } |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | /** |
<> | 144:ef7eb2e8f9f7 | 65 | * @brief Set PDMA Transfer Count |
<> | 144:ef7eb2e8f9f7 | 66 | * |
<> | 144:ef7eb2e8f9f7 | 67 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 68 | * @param[in] u32Width Data width. PDMA_WIDTH_8, PDMA_WIDTH_16, or PDMA_WIDTH_32 |
<> | 144:ef7eb2e8f9f7 | 69 | * @param[in] u32TransCount Transfer count |
<> | 144:ef7eb2e8f9f7 | 70 | * |
<> | 144:ef7eb2e8f9f7 | 71 | * @return None |
<> | 144:ef7eb2e8f9f7 | 72 | * |
<> | 144:ef7eb2e8f9f7 | 73 | * @details This function set the selected channel data width and transfer count. |
<> | 144:ef7eb2e8f9f7 | 74 | */ |
<> | 144:ef7eb2e8f9f7 | 75 | void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) |
<> | 144:ef7eb2e8f9f7 | 76 | { |
<> | 144:ef7eb2e8f9f7 | 77 | PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); |
<> | 144:ef7eb2e8f9f7 | 78 | PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount-1) << PDMA_DSCT_CTL_TXCNT_Pos)); |
<> | 144:ef7eb2e8f9f7 | 79 | } |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | /** |
<> | 144:ef7eb2e8f9f7 | 82 | * @brief Set PDMA Transfer Address |
<> | 144:ef7eb2e8f9f7 | 83 | * |
<> | 144:ef7eb2e8f9f7 | 84 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 85 | * @param[in] u32SrcAddr Source address |
<> | 144:ef7eb2e8f9f7 | 86 | * @param[in] u32SrcCtrl Source control attribute. PDMA_SAR_INC or PDMA_SAR_FIX |
<> | 144:ef7eb2e8f9f7 | 87 | * @param[in] u32DstAddr destination address |
<> | 144:ef7eb2e8f9f7 | 88 | * @param[in] u32DstCtrl destination control attribute. PDMA_DAR_INC or PDMA_DAR_FIX |
<> | 144:ef7eb2e8f9f7 | 89 | * |
<> | 144:ef7eb2e8f9f7 | 90 | * @return None |
<> | 144:ef7eb2e8f9f7 | 91 | * |
<> | 144:ef7eb2e8f9f7 | 92 | * @details This function set the selected channel source/destination address and attribute. |
<> | 144:ef7eb2e8f9f7 | 93 | */ |
<> | 144:ef7eb2e8f9f7 | 94 | void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) |
<> | 144:ef7eb2e8f9f7 | 95 | { |
<> | 144:ef7eb2e8f9f7 | 96 | PDMA->DSCT[u32Ch].ENDSA = u32SrcAddr; |
<> | 144:ef7eb2e8f9f7 | 97 | PDMA->DSCT[u32Ch].ENDDA = u32DstAddr; |
<> | 144:ef7eb2e8f9f7 | 98 | PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); |
<> | 144:ef7eb2e8f9f7 | 99 | PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); |
<> | 144:ef7eb2e8f9f7 | 100 | } |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | /** |
<> | 144:ef7eb2e8f9f7 | 103 | * @brief Set PDMA Transfer Mode |
<> | 144:ef7eb2e8f9f7 | 104 | * |
<> | 144:ef7eb2e8f9f7 | 105 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 106 | * @param[in] u32Peripheral The selected peripheral. PDMA_SPI0_TX, PDMA_UART0_TX, PDMA_I2S_TX,...PDMA_MEM |
<> | 144:ef7eb2e8f9f7 | 107 | * @param[in] u32ScatterEn Scatter-gather mode enable |
<> | 144:ef7eb2e8f9f7 | 108 | * @param[in] u32DescAddr Scatter-gather descriptor address |
<> | 144:ef7eb2e8f9f7 | 109 | * |
<> | 144:ef7eb2e8f9f7 | 110 | * @return None |
<> | 144:ef7eb2e8f9f7 | 111 | * |
<> | 144:ef7eb2e8f9f7 | 112 | * @details This function set the selected channel transfer mode. Include peripheral setting. |
<> | 144:ef7eb2e8f9f7 | 113 | */ |
<> | 144:ef7eb2e8f9f7 | 114 | void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) |
<> | 144:ef7eb2e8f9f7 | 115 | { |
<> | 144:ef7eb2e8f9f7 | 116 | u32ChSelect[u32Ch] = u32Peripheral; |
<> | 144:ef7eb2e8f9f7 | 117 | switch (u32Ch) { |
<> | 144:ef7eb2e8f9f7 | 118 | case 0: |
<> | 144:ef7eb2e8f9f7 | 119 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; |
<> | 144:ef7eb2e8f9f7 | 120 | break; |
<> | 144:ef7eb2e8f9f7 | 121 | case 1: |
<> | 144:ef7eb2e8f9f7 | 122 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); |
<> | 144:ef7eb2e8f9f7 | 123 | break; |
<> | 144:ef7eb2e8f9f7 | 124 | case 2: |
<> | 144:ef7eb2e8f9f7 | 125 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); |
<> | 144:ef7eb2e8f9f7 | 126 | break; |
<> | 144:ef7eb2e8f9f7 | 127 | case 3: |
<> | 144:ef7eb2e8f9f7 | 128 | PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); |
<> | 144:ef7eb2e8f9f7 | 129 | break; |
<> | 144:ef7eb2e8f9f7 | 130 | case 4: |
<> | 144:ef7eb2e8f9f7 | 131 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; |
<> | 144:ef7eb2e8f9f7 | 132 | break; |
<> | 144:ef7eb2e8f9f7 | 133 | case 5: |
<> | 144:ef7eb2e8f9f7 | 134 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); |
<> | 144:ef7eb2e8f9f7 | 135 | break; |
<> | 144:ef7eb2e8f9f7 | 136 | case 6: |
<> | 144:ef7eb2e8f9f7 | 137 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); |
<> | 144:ef7eb2e8f9f7 | 138 | break; |
<> | 144:ef7eb2e8f9f7 | 139 | case 7: |
<> | 144:ef7eb2e8f9f7 | 140 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); |
<> | 144:ef7eb2e8f9f7 | 141 | break; |
<> | 144:ef7eb2e8f9f7 | 142 | case 8: |
<> | 144:ef7eb2e8f9f7 | 143 | PDMA->REQSEL8_11 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral; |
<> | 144:ef7eb2e8f9f7 | 144 | break; |
<> | 144:ef7eb2e8f9f7 | 145 | case 9: |
<> | 144:ef7eb2e8f9f7 | 146 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos); |
<> | 144:ef7eb2e8f9f7 | 147 | break; |
<> | 144:ef7eb2e8f9f7 | 148 | case 10: |
<> | 144:ef7eb2e8f9f7 | 149 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos); |
<> | 144:ef7eb2e8f9f7 | 150 | break; |
<> | 144:ef7eb2e8f9f7 | 151 | case 11: |
<> | 144:ef7eb2e8f9f7 | 152 | PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos); |
<> | 144:ef7eb2e8f9f7 | 153 | break; |
<> | 144:ef7eb2e8f9f7 | 154 | case 12: |
<> | 144:ef7eb2e8f9f7 | 155 | PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral; |
<> | 144:ef7eb2e8f9f7 | 156 | break; |
<> | 144:ef7eb2e8f9f7 | 157 | case 13: |
<> | 144:ef7eb2e8f9f7 | 158 | PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos); |
<> | 144:ef7eb2e8f9f7 | 159 | break; |
<> | 144:ef7eb2e8f9f7 | 160 | case 14: |
<> | 144:ef7eb2e8f9f7 | 161 | PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos); |
<> | 144:ef7eb2e8f9f7 | 162 | break; |
<> | 144:ef7eb2e8f9f7 | 163 | case 15: |
<> | 144:ef7eb2e8f9f7 | 164 | PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos); |
<> | 144:ef7eb2e8f9f7 | 165 | break; |
<> | 144:ef7eb2e8f9f7 | 166 | default: |
<> | 144:ef7eb2e8f9f7 | 167 | ; |
<> | 144:ef7eb2e8f9f7 | 168 | } |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | if (u32ScatterEn) { |
<> | 144:ef7eb2e8f9f7 | 171 | PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; |
<> | 144:ef7eb2e8f9f7 | 172 | PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA); |
<> | 144:ef7eb2e8f9f7 | 173 | } else |
<> | 144:ef7eb2e8f9f7 | 174 | PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; |
<> | 144:ef7eb2e8f9f7 | 175 | } |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | /** |
<> | 144:ef7eb2e8f9f7 | 178 | * @brief Set PDMA Burst Type |
<> | 144:ef7eb2e8f9f7 | 179 | * |
<> | 144:ef7eb2e8f9f7 | 180 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 181 | * @param[in] u32BurstType Burst mode or single mode |
<> | 144:ef7eb2e8f9f7 | 182 | * @param[in] u32BurstSize Set the size of burst mode |
<> | 144:ef7eb2e8f9f7 | 183 | * |
<> | 144:ef7eb2e8f9f7 | 184 | * @return None |
<> | 144:ef7eb2e8f9f7 | 185 | * |
<> | 144:ef7eb2e8f9f7 | 186 | * @details This function set the selected channel burst type and size. |
<> | 144:ef7eb2e8f9f7 | 187 | */ |
<> | 144:ef7eb2e8f9f7 | 188 | void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) |
<> | 144:ef7eb2e8f9f7 | 189 | { |
<> | 144:ef7eb2e8f9f7 | 190 | PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); |
<> | 144:ef7eb2e8f9f7 | 191 | PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); |
<> | 144:ef7eb2e8f9f7 | 192 | } |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | /** |
<> | 144:ef7eb2e8f9f7 | 195 | * @brief Set PDMA TimeOut Count |
<> | 144:ef7eb2e8f9f7 | 196 | * |
<> | 144:ef7eb2e8f9f7 | 197 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 198 | * @param[in] u32OnOff Enable/disable time out function |
<> | 144:ef7eb2e8f9f7 | 199 | * @param[in] u32TimeOutCnt Timeout count |
<> | 144:ef7eb2e8f9f7 | 200 | * |
<> | 144:ef7eb2e8f9f7 | 201 | * @return None |
<> | 144:ef7eb2e8f9f7 | 202 | * |
<> | 144:ef7eb2e8f9f7 | 203 | * @details This function set the timeout count. |
<> | 144:ef7eb2e8f9f7 | 204 | */ |
<> | 144:ef7eb2e8f9f7 | 205 | void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) |
<> | 144:ef7eb2e8f9f7 | 206 | { |
<> | 144:ef7eb2e8f9f7 | 207 | switch(u32Ch) { |
<> | 144:ef7eb2e8f9f7 | 208 | case 0: |
<> | 144:ef7eb2e8f9f7 | 209 | PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 210 | break; |
<> | 144:ef7eb2e8f9f7 | 211 | case 1: |
<> | 144:ef7eb2e8f9f7 | 212 | PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); |
<> | 144:ef7eb2e8f9f7 | 213 | break; |
<> | 144:ef7eb2e8f9f7 | 214 | case 2: |
<> | 144:ef7eb2e8f9f7 | 215 | PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 216 | break; |
<> | 144:ef7eb2e8f9f7 | 217 | case 3: |
<> | 144:ef7eb2e8f9f7 | 218 | PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos); |
<> | 144:ef7eb2e8f9f7 | 219 | break; |
<> | 144:ef7eb2e8f9f7 | 220 | case 4: |
<> | 144:ef7eb2e8f9f7 | 221 | PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 222 | break; |
<> | 144:ef7eb2e8f9f7 | 223 | case 5: |
<> | 144:ef7eb2e8f9f7 | 224 | PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos); |
<> | 144:ef7eb2e8f9f7 | 225 | break; |
<> | 144:ef7eb2e8f9f7 | 226 | case 6: |
<> | 144:ef7eb2e8f9f7 | 227 | PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 228 | break; |
<> | 144:ef7eb2e8f9f7 | 229 | case 7: |
<> | 144:ef7eb2e8f9f7 | 230 | PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos); |
<> | 144:ef7eb2e8f9f7 | 231 | break; |
<> | 144:ef7eb2e8f9f7 | 232 | case 8: |
<> | 144:ef7eb2e8f9f7 | 233 | PDMA->TOC8_9 = (PDMA->TOC8_9 & ~PDMA_TOC8_9_TOC8_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 234 | break; |
<> | 144:ef7eb2e8f9f7 | 235 | case 9: |
<> | 144:ef7eb2e8f9f7 | 236 | PDMA->TOC8_9 = (PDMA->TOC8_9 & ~PDMA_TOC8_9_TOC9_Msk) | (u32TimeOutCnt << PDMA_TOC8_9_TOC9_Pos); |
<> | 144:ef7eb2e8f9f7 | 237 | break; |
<> | 144:ef7eb2e8f9f7 | 238 | case 10: |
<> | 144:ef7eb2e8f9f7 | 239 | PDMA->TOC10_11 = (PDMA->TOC10_11 & ~PDMA_TOC10_11_TOC10_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 240 | break; |
<> | 144:ef7eb2e8f9f7 | 241 | case 11: |
<> | 144:ef7eb2e8f9f7 | 242 | PDMA->TOC10_11 = (PDMA->TOC10_11 & ~PDMA_TOC10_11_TOC11_Msk) | (u32TimeOutCnt << PDMA_TOC10_11_TOC11_Pos); |
<> | 144:ef7eb2e8f9f7 | 243 | break; |
<> | 144:ef7eb2e8f9f7 | 244 | case 12: |
<> | 144:ef7eb2e8f9f7 | 245 | PDMA->TOC12_13 = (PDMA->TOC12_13 & ~PDMA_TOC12_13_TOC12_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 246 | break; |
<> | 144:ef7eb2e8f9f7 | 247 | case 13: |
<> | 144:ef7eb2e8f9f7 | 248 | PDMA->TOC12_13 = (PDMA->TOC12_13 & ~PDMA_TOC12_13_TOC13_Msk) | (u32TimeOutCnt << PDMA_TOC12_13_TOC13_Pos); |
<> | 144:ef7eb2e8f9f7 | 249 | break; |
<> | 144:ef7eb2e8f9f7 | 250 | case 14: |
<> | 144:ef7eb2e8f9f7 | 251 | PDMA->TOC14_15 = (PDMA->TOC14_15 & ~PDMA_TOC14_15_TOC14_Msk) | u32TimeOutCnt; |
<> | 144:ef7eb2e8f9f7 | 252 | break; |
<> | 144:ef7eb2e8f9f7 | 253 | case 15: |
<> | 144:ef7eb2e8f9f7 | 254 | PDMA->TOC14_15 = (PDMA->TOC14_15 & ~PDMA_TOC14_15_TOC15_Msk) | (u32TimeOutCnt << PDMA_TOC14_15_TOC15_Pos); |
<> | 144:ef7eb2e8f9f7 | 255 | break; |
<> | 144:ef7eb2e8f9f7 | 256 | default: |
<> | 144:ef7eb2e8f9f7 | 257 | ; |
<> | 144:ef7eb2e8f9f7 | 258 | } |
<> | 144:ef7eb2e8f9f7 | 259 | } |
<> | 144:ef7eb2e8f9f7 | 260 | |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | /** |
<> | 144:ef7eb2e8f9f7 | 263 | * @brief Trigger PDMA |
<> | 144:ef7eb2e8f9f7 | 264 | * |
<> | 144:ef7eb2e8f9f7 | 265 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 266 | * |
<> | 144:ef7eb2e8f9f7 | 267 | * @return None |
<> | 144:ef7eb2e8f9f7 | 268 | * |
<> | 144:ef7eb2e8f9f7 | 269 | * @details This function trigger the selected channel. |
<> | 144:ef7eb2e8f9f7 | 270 | */ |
<> | 144:ef7eb2e8f9f7 | 271 | void PDMA_Trigger(uint32_t u32Ch) |
<> | 144:ef7eb2e8f9f7 | 272 | { |
<> | 144:ef7eb2e8f9f7 | 273 | if (u32ChSelect[u32Ch] == PDMA_MEM) |
<> | 144:ef7eb2e8f9f7 | 274 | PDMA->SWREQ = (1 << u32Ch); |
<> | 144:ef7eb2e8f9f7 | 275 | } |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | /** |
<> | 144:ef7eb2e8f9f7 | 278 | * @brief Enable Interrupt |
<> | 144:ef7eb2e8f9f7 | 279 | * |
<> | 144:ef7eb2e8f9f7 | 280 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 281 | * @param[in] u32Mask The Interrupt Type |
<> | 144:ef7eb2e8f9f7 | 282 | * |
<> | 144:ef7eb2e8f9f7 | 283 | * @return None |
<> | 144:ef7eb2e8f9f7 | 284 | * |
<> | 144:ef7eb2e8f9f7 | 285 | * @details This function enable the selected channel interrupt. |
<> | 144:ef7eb2e8f9f7 | 286 | */ |
<> | 144:ef7eb2e8f9f7 | 287 | void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask) |
<> | 144:ef7eb2e8f9f7 | 288 | { |
<> | 144:ef7eb2e8f9f7 | 289 | PDMA->INTEN |= (1 << u32Ch); |
<> | 144:ef7eb2e8f9f7 | 290 | } |
<> | 144:ef7eb2e8f9f7 | 291 | |
<> | 144:ef7eb2e8f9f7 | 292 | /** |
<> | 144:ef7eb2e8f9f7 | 293 | * @brief Disable Interrupt |
<> | 144:ef7eb2e8f9f7 | 294 | * |
<> | 144:ef7eb2e8f9f7 | 295 | * @param[in] u32Ch The selected channel |
<> | 144:ef7eb2e8f9f7 | 296 | * @param[in] u32Mask The Interrupt Type |
<> | 144:ef7eb2e8f9f7 | 297 | * |
<> | 144:ef7eb2e8f9f7 | 298 | * @return None |
<> | 144:ef7eb2e8f9f7 | 299 | * |
<> | 144:ef7eb2e8f9f7 | 300 | * @details This function disable the selected channel interrupt. |
<> | 144:ef7eb2e8f9f7 | 301 | */ |
<> | 144:ef7eb2e8f9f7 | 302 | void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask) |
<> | 144:ef7eb2e8f9f7 | 303 | { |
<> | 144:ef7eb2e8f9f7 | 304 | PDMA->INTEN &= ~(1 << u32Ch); |
<> | 144:ef7eb2e8f9f7 | 305 | } |
<> | 144:ef7eb2e8f9f7 | 306 | |
<> | 144:ef7eb2e8f9f7 | 307 | /*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_FUNCTIONS */ |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | /*@}*/ /* end of group NUC472_442_PDMA_Driver */ |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
<> | 144:ef7eb2e8f9f7 | 312 | |
<> | 144:ef7eb2e8f9f7 | 313 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |