mbed library sources. Supersedes mbed-src.
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targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_adc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file adc.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @version V1.00 |
<> | 144:ef7eb2e8f9f7 | 4 | * $Revision: 13 $ |
<> | 144:ef7eb2e8f9f7 | 5 | * $Date: 14/05/29 1:13p $ |
<> | 144:ef7eb2e8f9f7 | 6 | * @brief NUC472/NUC442 ADC driver source file |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * @note |
<> | 144:ef7eb2e8f9f7 | 9 | * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 10 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 11 | #include "NUC472_442.h" |
<> | 144:ef7eb2e8f9f7 | 12 | |
<> | 144:ef7eb2e8f9f7 | 13 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
<> | 144:ef7eb2e8f9f7 | 14 | @{ |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | |
<> | 144:ef7eb2e8f9f7 | 17 | /** @addtogroup NUC472_442_ADC_Driver ADC Driver |
<> | 144:ef7eb2e8f9f7 | 18 | @{ |
<> | 144:ef7eb2e8f9f7 | 19 | */ |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | /** @addtogroup NUC472_442_ADC_EXPORTED_FUNCTIONS ADC Exported Functions |
<> | 144:ef7eb2e8f9f7 | 23 | @{ |
<> | 144:ef7eb2e8f9f7 | 24 | */ |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | /** |
<> | 144:ef7eb2e8f9f7 | 27 | * @brief This API configures ADC module to be ready for convert the input from selected channel |
<> | 144:ef7eb2e8f9f7 | 28 | * @param[in] adc Base address of ADC module |
<> | 144:ef7eb2e8f9f7 | 29 | * @param[in] u32InputMode Input mode (single-end/differential). Valid values are: |
<> | 144:ef7eb2e8f9f7 | 30 | * - \ref ADC_INPUT_MODE_SINGLE_END |
<> | 144:ef7eb2e8f9f7 | 31 | * - \ref ADC_INPUT_MODE_DIFFERENTIAL |
<> | 144:ef7eb2e8f9f7 | 32 | * @param[in] u32OpMode Operation mode (single/single cycle/continuous). Valid values are: |
<> | 144:ef7eb2e8f9f7 | 33 | * - \ref ADC_OPERATION_MODE_SINGLE |
<> | 144:ef7eb2e8f9f7 | 34 | * - \ref ADC_OPERATION_MODE_SINGLE_CYCLE |
<> | 144:ef7eb2e8f9f7 | 35 | * - \ref ADC_OPERATION_MODE_CONTINUOUS |
<> | 144:ef7eb2e8f9f7 | 36 | * @param[in] u32ChMask Channel enable bit. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 37 | * - \ref ADC_CH_0_MASK |
<> | 144:ef7eb2e8f9f7 | 38 | * - \ref ADC_CH_1_MASK |
<> | 144:ef7eb2e8f9f7 | 39 | * - \ref ADC_CH_2_MASK |
<> | 144:ef7eb2e8f9f7 | 40 | * - \ref ADC_CH_3_MASK |
<> | 144:ef7eb2e8f9f7 | 41 | * - \ref ADC_CH_4_MASK |
<> | 144:ef7eb2e8f9f7 | 42 | * - \ref ADC_CH_5_MASK |
<> | 144:ef7eb2e8f9f7 | 43 | * - \ref ADC_CH_6_MASK |
<> | 144:ef7eb2e8f9f7 | 44 | * - \ref ADC_CH_7_MASK |
<> | 144:ef7eb2e8f9f7 | 45 | * - \ref ADC_CH_8_MASK |
<> | 144:ef7eb2e8f9f7 | 46 | * - \ref ADC_CH_9_MASK |
<> | 144:ef7eb2e8f9f7 | 47 | * - \ref ADC_CH_10_MASK |
<> | 144:ef7eb2e8f9f7 | 48 | * - \ref ADC_CH_11_MASK |
<> | 144:ef7eb2e8f9f7 | 49 | * - \ref ADC_CH_TS_MASK |
<> | 144:ef7eb2e8f9f7 | 50 | * - \ref ADC_CH_BG_MASK |
<> | 144:ef7eb2e8f9f7 | 51 | * @return None |
<> | 144:ef7eb2e8f9f7 | 52 | * @note This API does not turn on ADC power nor does trigger ADC conversion |
<> | 144:ef7eb2e8f9f7 | 53 | */ |
<> | 144:ef7eb2e8f9f7 | 54 | void ADC_Open(ADC_T *adc, |
<> | 144:ef7eb2e8f9f7 | 55 | uint32_t u32InputMode, |
<> | 144:ef7eb2e8f9f7 | 56 | uint32_t u32OpMode, |
<> | 144:ef7eb2e8f9f7 | 57 | uint32_t u32ChMask) |
<> | 144:ef7eb2e8f9f7 | 58 | { |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 144:ef7eb2e8f9f7 | 60 | ADC->CTL |= u32InputMode; |
<> | 144:ef7eb2e8f9f7 | 61 | ADC->CTL |= u32OpMode; |
<> | 144:ef7eb2e8f9f7 | 62 | ADC->CHEN = (ADC->CHEN & ~(ADC_CHEN_CHEN_Msk | ADC_CHEN_ADBGEN_Msk | ADC_CHEN_ADTSEN_Msk)) | u32ChMask; |
<> | 144:ef7eb2e8f9f7 | 63 | return; |
<> | 144:ef7eb2e8f9f7 | 64 | } |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | /** |
<> | 144:ef7eb2e8f9f7 | 67 | * @brief Disable ADC module |
<> | 144:ef7eb2e8f9f7 | 68 | * @param[in] adc Base address of ADC module |
<> | 144:ef7eb2e8f9f7 | 69 | * @return None |
<> | 144:ef7eb2e8f9f7 | 70 | */ |
<> | 144:ef7eb2e8f9f7 | 71 | void ADC_Close(ADC_T *adc) |
<> | 144:ef7eb2e8f9f7 | 72 | { |
<> | 144:ef7eb2e8f9f7 | 73 | SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk; |
<> | 144:ef7eb2e8f9f7 | 74 | SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk; |
<> | 144:ef7eb2e8f9f7 | 75 | return; |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | } |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | /** |
<> | 144:ef7eb2e8f9f7 | 80 | * @brief Configure the hardware trigger condition and enable hardware trigger |
<> | 144:ef7eb2e8f9f7 | 81 | * @param[in] adc Base address of ADC module |
<> | 144:ef7eb2e8f9f7 | 82 | * @param[in] u32Source Decides the hardware trigger source. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 83 | * - \ref ADC_TRIGGER_BY_EXT_PIN |
<> | 144:ef7eb2e8f9f7 | 84 | * - \ref ADC_TRIGGER_BY_PWM |
<> | 144:ef7eb2e8f9f7 | 85 | * @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM |
<> | 144:ef7eb2e8f9f7 | 86 | * trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay |
<> | 144:ef7eb2e8f9f7 | 87 | * time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter |
<> | 144:ef7eb2e8f9f7 | 88 | * is used to set trigger condition. Valid values are: |
<> | 144:ef7eb2e8f9f7 | 89 | * - \ref ADC_LOW_LEVEL_TRIGGER |
<> | 144:ef7eb2e8f9f7 | 90 | * - \ref ADC_HIGH_LEVEL_TRIGGER |
<> | 144:ef7eb2e8f9f7 | 91 | * - \ref ADC_FALLING_EDGE_TRIGGER |
<> | 144:ef7eb2e8f9f7 | 92 | * - \ref ADC_RISING_EDGE_TRIGGER |
<> | 144:ef7eb2e8f9f7 | 93 | * @return None |
<> | 144:ef7eb2e8f9f7 | 94 | */ |
<> | 144:ef7eb2e8f9f7 | 95 | void ADC_EnableHWTrigger(ADC_T *adc, |
<> | 144:ef7eb2e8f9f7 | 96 | uint32_t u32Source, |
<> | 144:ef7eb2e8f9f7 | 97 | uint32_t u32Param) |
<> | 144:ef7eb2e8f9f7 | 98 | { |
<> | 144:ef7eb2e8f9f7 | 99 | ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk); |
<> | 144:ef7eb2e8f9f7 | 100 | if(u32Source == ADC_TRIGGER_BY_EXT_PIN) { |
<> | 144:ef7eb2e8f9f7 | 101 | ADC->CTL &= ~(ADC_CTL_HWTRGSEL_Msk | ADC_CTL_HWTRGCOND_Msk); |
<> | 144:ef7eb2e8f9f7 | 102 | ADC->CTL |= u32Source | u32Param | ADC_CTL_HWTRGEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 103 | } else { |
<> | 144:ef7eb2e8f9f7 | 104 | ADC->CTL &= ~(ADC_CTL_HWTRGSEL_Msk | ADC_CTL_PWMTRGDLY_Msk); |
<> | 144:ef7eb2e8f9f7 | 105 | ADC->CTL |= u32Source | (u32Param << ADC_CTL_PWMTRGDLY_Pos) | ADC_CTL_HWTRGEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 106 | } |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | return; |
<> | 144:ef7eb2e8f9f7 | 109 | } |
<> | 144:ef7eb2e8f9f7 | 110 | |
<> | 144:ef7eb2e8f9f7 | 111 | /** |
<> | 144:ef7eb2e8f9f7 | 112 | * @brief Disable hardware trigger ADC function. |
<> | 144:ef7eb2e8f9f7 | 113 | * @param[in] adc Base address of ADC module |
<> | 144:ef7eb2e8f9f7 | 114 | * @return None |
<> | 144:ef7eb2e8f9f7 | 115 | */ |
<> | 144:ef7eb2e8f9f7 | 116 | void ADC_DisableHWTrigger(ADC_T *adc) |
<> | 144:ef7eb2e8f9f7 | 117 | { |
<> | 144:ef7eb2e8f9f7 | 118 | ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk); |
<> | 144:ef7eb2e8f9f7 | 119 | return; |
<> | 144:ef7eb2e8f9f7 | 120 | } |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | /** |
<> | 144:ef7eb2e8f9f7 | 123 | * @brief Enable the interrupt(s) selected by u32Mask parameter. |
<> | 144:ef7eb2e8f9f7 | 124 | * @param[in] adc Base address of ADC module |
<> | 144:ef7eb2e8f9f7 | 125 | * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit |
<> | 144:ef7eb2e8f9f7 | 126 | * corresponds to a interrupt status. This parameter decides which |
<> | 144:ef7eb2e8f9f7 | 127 | * interrupts will be enabled. |
<> | 144:ef7eb2e8f9f7 | 128 | * - \ref ADC_ADF_INT |
<> | 144:ef7eb2e8f9f7 | 129 | * - \ref ADC_CMP0_INT |
<> | 144:ef7eb2e8f9f7 | 130 | * - \ref ADC_CMP1_INT |
<> | 144:ef7eb2e8f9f7 | 131 | * @return None |
<> | 144:ef7eb2e8f9f7 | 132 | */ |
<> | 144:ef7eb2e8f9f7 | 133 | void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask) |
<> | 144:ef7eb2e8f9f7 | 134 | { |
<> | 144:ef7eb2e8f9f7 | 135 | if(u32Mask & ADC_ADF_INT) |
<> | 144:ef7eb2e8f9f7 | 136 | ADC->CTL |= ADC_CTL_ADCIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 137 | if(u32Mask & ADC_CMP0_INT) |
<> | 144:ef7eb2e8f9f7 | 138 | ADC->CMP[0] |= ADC_CMP0_ADCMPIE_Msk; |
<> | 144:ef7eb2e8f9f7 | 139 | if(u32Mask & ADC_CMP1_INT) |
<> | 144:ef7eb2e8f9f7 | 140 | ADC->CMP[1] |= ADC_CMP1_ADCMPIE_Msk; |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | return; |
<> | 144:ef7eb2e8f9f7 | 143 | } |
<> | 144:ef7eb2e8f9f7 | 144 | |
<> | 144:ef7eb2e8f9f7 | 145 | /** |
<> | 144:ef7eb2e8f9f7 | 146 | * @brief Disable the interrupt(s) selected by u32Mask parameter. |
<> | 144:ef7eb2e8f9f7 | 147 | * @param[in] adc Base address of ADC module |
<> | 144:ef7eb2e8f9f7 | 148 | * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit |
<> | 144:ef7eb2e8f9f7 | 149 | * corresponds to a interrupt status. This parameter decides which |
<> | 144:ef7eb2e8f9f7 | 150 | * interrupts will be disabled. |
<> | 144:ef7eb2e8f9f7 | 151 | * - \ref ADC_ADF_INT |
<> | 144:ef7eb2e8f9f7 | 152 | * - \ref ADC_CMP0_INT |
<> | 144:ef7eb2e8f9f7 | 153 | * - \ref ADC_CMP1_INT |
<> | 144:ef7eb2e8f9f7 | 154 | * @return None |
<> | 144:ef7eb2e8f9f7 | 155 | */ |
<> | 144:ef7eb2e8f9f7 | 156 | void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask) |
<> | 144:ef7eb2e8f9f7 | 157 | { |
<> | 144:ef7eb2e8f9f7 | 158 | if(u32Mask & ADC_ADF_INT) |
<> | 144:ef7eb2e8f9f7 | 159 | ADC->CTL &= ~ADC_CTL_ADCIEN_Msk; |
<> | 144:ef7eb2e8f9f7 | 160 | if(u32Mask & ADC_CMP0_INT) |
<> | 144:ef7eb2e8f9f7 | 161 | ADC->CMP[0] &= ~ADC_CMP0_ADCMPIE_Msk; |
<> | 144:ef7eb2e8f9f7 | 162 | if(u32Mask & ADC_CMP1_INT) |
<> | 144:ef7eb2e8f9f7 | 163 | ADC->CMP[1] &= ~ADC_CMP1_ADCMPIE_Msk; |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | return; |
<> | 144:ef7eb2e8f9f7 | 166 | } |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | /*@}*/ /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */ |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | /*@}*/ /* end of group NUC472_442_ADC_Driver */ |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |