Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 // math.h required for floating point operations for baud rate calculation
bogdanm 0:9b334a45a8ff 17 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 18 #include <math.h>
bogdanm 0:9b334a45a8ff 19 #include <string.h>
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 #include "serial_api.h"
bogdanm 0:9b334a45a8ff 22 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 23 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 24 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #if DEVICE_SERIAL
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 /******************************************************************************
bogdanm 0:9b334a45a8ff 29 * INITIALIZATION
bogdanm 0:9b334a45a8ff 30 ******************************************************************************/
bogdanm 0:9b334a45a8ff 31 #define UART_NUM 3
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 static const SWM_Map SWM_UART_TX[] = {
bogdanm 0:9b334a45a8ff 34 {0, 0},
bogdanm 0:9b334a45a8ff 35 {1, 8},
bogdanm 0:9b334a45a8ff 36 {2, 16},
bogdanm 0:9b334a45a8ff 37 };
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 static const SWM_Map SWM_UART_RX[] = {
bogdanm 0:9b334a45a8ff 40 {0, 8},
bogdanm 0:9b334a45a8ff 41 {1, 16},
bogdanm 0:9b334a45a8ff 42 {2, 24},
bogdanm 0:9b334a45a8ff 43 };
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 static const SWM_Map SWM_UART_RTS[] = {
bogdanm 0:9b334a45a8ff 46 {0, 16},
bogdanm 0:9b334a45a8ff 47 {1, 24},
bogdanm 0:9b334a45a8ff 48 {3, 0},
bogdanm 0:9b334a45a8ff 49 };
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 static const SWM_Map SWM_UART_CTS[] = {
bogdanm 0:9b334a45a8ff 52 {0, 24},
bogdanm 0:9b334a45a8ff 53 {2, 0},
bogdanm 0:9b334a45a8ff 54 {3, 8}
bogdanm 0:9b334a45a8ff 55 };
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 // bit flags for used UARTs
bogdanm 0:9b334a45a8ff 58 static unsigned char uart_used = 0;
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 static int get_available_uart(void)
bogdanm 0:9b334a45a8ff 61 {
bogdanm 0:9b334a45a8ff 62 int i;
bogdanm 0:9b334a45a8ff 63 for (i=0; i<UART_NUM; i++) {
bogdanm 0:9b334a45a8ff 64 if ((uart_used & (1 << i)) == 0)
bogdanm 0:9b334a45a8ff 65 return i;
bogdanm 0:9b334a45a8ff 66 }
bogdanm 0:9b334a45a8ff 67 return -1;
bogdanm 0:9b334a45a8ff 68 }
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 #define UART_EN (0x01<<0)
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 #define CTS_DELTA (0x01<<5)
bogdanm 0:9b334a45a8ff 73 #define RXBRK (0x01<<10)
bogdanm 0:9b334a45a8ff 74 #define DELTA_RXBRK (0x01<<11)
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 #define RXRDY (0x01<<0)
bogdanm 0:9b334a45a8ff 77 #define TXRDY (0x01<<2)
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 #define RXRDYEN RXRDY
bogdanm 0:9b334a45a8ff 80 #define TXRDYEN TXRDY
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 #define TXBRKEN (0x01<<1)
bogdanm 0:9b334a45a8ff 83 #define CTSEN (0x01<<9)
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 static uint32_t UARTSysClk;
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 static uint32_t serial_irq_ids[UART_NUM] = {0};
bogdanm 0:9b334a45a8ff 88 static uart_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 int stdio_uart_inited = 0;
bogdanm 0:9b334a45a8ff 91 serial_t stdio_uart;
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 static int check_duplication(serial_t *obj, PinName tx, PinName rx)
bogdanm 0:9b334a45a8ff 94 {
bogdanm 0:9b334a45a8ff 95 if (uart_used == 0)
bogdanm 0:9b334a45a8ff 96 return 0;
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 const SWM_Map *swm;
bogdanm 0:9b334a45a8ff 99 uint32_t assigned_tx, assigned_rx;
bogdanm 0:9b334a45a8ff 100 int ch;
bogdanm 0:9b334a45a8ff 101 for (ch=0; ch<UART_NUM; ch++) {
bogdanm 0:9b334a45a8ff 102 // read assigned TX in the UART channel of switch matrix
bogdanm 0:9b334a45a8ff 103 swm = &SWM_UART_TX[ch];
bogdanm 0:9b334a45a8ff 104 assigned_tx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
bogdanm 0:9b334a45a8ff 105 assigned_tx = assigned_tx >> swm->offset;
bogdanm 0:9b334a45a8ff 106 // read assigned RX in the UART channel of switch matrix
bogdanm 0:9b334a45a8ff 107 swm = &SWM_UART_RX[ch];
bogdanm 0:9b334a45a8ff 108 assigned_rx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
bogdanm 0:9b334a45a8ff 109 assigned_rx = assigned_rx >> swm->offset;
bogdanm 0:9b334a45a8ff 110 if ((assigned_tx == (uint32_t)(tx >> PIN_SHIFT)) && (assigned_rx == (uint32_t)(rx >> PIN_SHIFT))) {
bogdanm 0:9b334a45a8ff 111 obj->index = ch;
bogdanm 0:9b334a45a8ff 112 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * ch));
bogdanm 0:9b334a45a8ff 113 return 1;
bogdanm 0:9b334a45a8ff 114 }
bogdanm 0:9b334a45a8ff 115 }
bogdanm 0:9b334a45a8ff 116 return 0;
bogdanm 0:9b334a45a8ff 117 }
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 void serial_init(serial_t *obj, PinName tx, PinName rx)
bogdanm 0:9b334a45a8ff 120 {
bogdanm 0:9b334a45a8ff 121 int is_stdio_uart = 0;
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 if (check_duplication(obj, tx, rx) == 1)
bogdanm 0:9b334a45a8ff 124 return;
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 int uart_n = get_available_uart();
bogdanm 0:9b334a45a8ff 127 if (uart_n == -1) {
bogdanm 0:9b334a45a8ff 128 error("No available UART");
bogdanm 0:9b334a45a8ff 129 }
bogdanm 0:9b334a45a8ff 130 obj->index = uart_n;
bogdanm 0:9b334a45a8ff 131 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n));
bogdanm 0:9b334a45a8ff 132 uart_used |= (1 << uart_n);
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 const SWM_Map *swm;
bogdanm 0:9b334a45a8ff 135 uint32_t regVal;
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 swm = &SWM_UART_TX[uart_n];
bogdanm 0:9b334a45a8ff 138 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
bogdanm 0:9b334a45a8ff 139 LPC_SWM->PINASSIGN[swm->n] = regVal | ((tx >> PIN_SHIFT) << swm->offset);
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 swm = &SWM_UART_RX[uart_n];
bogdanm 0:9b334a45a8ff 142 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
bogdanm 0:9b334a45a8ff 143 LPC_SWM->PINASSIGN[swm->n] = regVal | ((rx >> PIN_SHIFT) << swm->offset);
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 /* uart clock divided by 1 */
bogdanm 0:9b334a45a8ff 146 LPC_SYSCON->UARTCLKDIV = 1;
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /* disable uart interrupts */
bogdanm 0:9b334a45a8ff 149 NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /* Enable UART clock */
bogdanm 0:9b334a45a8ff 152 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /* Peripheral reset control to UART, a "1" bring it out of reset. */
bogdanm 0:9b334a45a8ff 155 LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
bogdanm 0:9b334a45a8ff 156 LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 // set default baud rate and format
bogdanm 0:9b334a45a8ff 161 serial_baud (obj, 9600);
bogdanm 0:9b334a45a8ff 162 serial_format(obj, 8, ParityNone, 1);
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /* Clear all status bits. */
bogdanm 0:9b334a45a8ff 165 obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /* enable uart interrupts */
bogdanm 0:9b334a45a8ff 168 NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* Enable UART */
bogdanm 0:9b334a45a8ff 171 obj->uart->CFG |= UART_EN;
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 if (is_stdio_uart) {
bogdanm 0:9b334a45a8ff 176 stdio_uart_inited = 1;
bogdanm 0:9b334a45a8ff 177 memcpy(&stdio_uart, obj, sizeof(serial_t));
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179 }
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 void serial_free(serial_t *obj)
bogdanm 0:9b334a45a8ff 182 {
bogdanm 0:9b334a45a8ff 183 uart_used &= ~(1 << obj->index);
bogdanm 0:9b334a45a8ff 184 serial_irq_ids[obj->index] = 0;
bogdanm 0:9b334a45a8ff 185 }
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 void serial_baud(serial_t *obj, int baudrate)
bogdanm 0:9b334a45a8ff 188 {
bogdanm 0:9b334a45a8ff 189 /* Integer divider:
bogdanm 0:9b334a45a8ff 190 BRG = UARTSysClk/(Baudrate * 16) - 1
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 Frational divider:
bogdanm 0:9b334a45a8ff 193 FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 where
bogdanm 0:9b334a45a8ff 196 FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
bogdanm 0:9b334a45a8ff 199 register is 0xFF.
bogdanm 0:9b334a45a8ff 200 (2) In ADD register value, depending on the value of UartSysClk,
bogdanm 0:9b334a45a8ff 201 baudrate, BRG register value, and SUB register value, be careful
bogdanm 0:9b334a45a8ff 202 about the order of multiplier and divider and make sure any
bogdanm 0:9b334a45a8ff 203 multiplier doesn't exceed 32-bit boundary and any divider doesn't get
bogdanm 0:9b334a45a8ff 204 down below one(integer 0).
bogdanm 0:9b334a45a8ff 205 (3) ADD should be always less than SUB.
bogdanm 0:9b334a45a8ff 206 */
bogdanm 0:9b334a45a8ff 207 obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 LPC_SYSCON->UARTFRGDIV = 0xFF;
bogdanm 0:9b334a45a8ff 210 LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
bogdanm 0:9b334a45a8ff 211 (baudrate * (obj->uart->BRG + 1))
bogdanm 0:9b334a45a8ff 212 ) - (LPC_SYSCON->UARTFRGDIV + 1);
bogdanm 0:9b334a45a8ff 213 }
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
bogdanm 0:9b334a45a8ff 216 {
bogdanm 0:9b334a45a8ff 217 // 0: 1 stop bits, 1: 2 stop bits
bogdanm 0:9b334a45a8ff 218 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
bogdanm 0:9b334a45a8ff 219 MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
bogdanm 0:9b334a45a8ff 220 MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
bogdanm 0:9b334a45a8ff 221 stop_bits -= 1;
bogdanm 0:9b334a45a8ff 222 data_bits -= 7;
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 int paritysel = 0;
bogdanm 0:9b334a45a8ff 225 switch (parity) {
bogdanm 0:9b334a45a8ff 226 case ParityNone: paritysel = 0; break;
bogdanm 0:9b334a45a8ff 227 case ParityEven: paritysel = 2; break;
bogdanm 0:9b334a45a8ff 228 case ParityOdd : paritysel = 3; break;
bogdanm 0:9b334a45a8ff 229 default:
bogdanm 0:9b334a45a8ff 230 break;
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 // First disable the the usart as described in documentation and then enable while updating CFG
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 // 24.6.1 USART Configuration register
bogdanm 0:9b334a45a8ff 236 // Remark: If software needs to change configuration values, the following sequence should
bogdanm 0:9b334a45a8ff 237 // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
bogdanm 0:9b334a45a8ff 238 // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
bogdanm 0:9b334a45a8ff 239 // Write the new configuration value, with the ENABLE bit set to 1.
bogdanm 0:9b334a45a8ff 240 obj->uart->CFG &= ~(1 << 0);
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 obj->uart->CFG = (1 << 0) // this will enable the usart
bogdanm 0:9b334a45a8ff 243 | (data_bits << 2)
bogdanm 0:9b334a45a8ff 244 | (paritysel << 4)
bogdanm 0:9b334a45a8ff 245 | (stop_bits << 6);
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /******************************************************************************
bogdanm 0:9b334a45a8ff 249 * INTERRUPTS HANDLING
bogdanm 0:9b334a45a8ff 250 ******************************************************************************/
bogdanm 0:9b334a45a8ff 251 static inline void uart_irq(SerialIrq irq_type, uint32_t index)
bogdanm 0:9b334a45a8ff 252 {
bogdanm 0:9b334a45a8ff 253 if (serial_irq_ids[index] != 0)
bogdanm 0:9b334a45a8ff 254 irq_handler(serial_irq_ids[index], irq_type);
bogdanm 0:9b334a45a8ff 255 }
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 void uart0_irq() {uart_irq((LPC_USART0->INTSTAT & RXRDY) ? RxIrq : TxIrq, 0);}
bogdanm 0:9b334a45a8ff 258 void uart1_irq() {uart_irq((LPC_USART1->INTSTAT & RXRDY) ? RxIrq : TxIrq, 1);}
bogdanm 0:9b334a45a8ff 259 void uart2_irq() {uart_irq((LPC_USART2->INTSTAT & RXRDY) ? RxIrq : TxIrq, 2);}
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 irq_handler = handler;
bogdanm 0:9b334a45a8ff 264 serial_irq_ids[obj->index] = id;
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 IRQn_Type irq_n = (IRQn_Type)0;
bogdanm 0:9b334a45a8ff 270 uint32_t vector = 0;
bogdanm 0:9b334a45a8ff 271 switch ((int)obj->uart) {
bogdanm 0:9b334a45a8ff 272 case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
bogdanm 0:9b334a45a8ff 273 case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
bogdanm 0:9b334a45a8ff 274 case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 if (enable) {
bogdanm 0:9b334a45a8ff 278 NVIC_DisableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 279 obj->uart->INTENSET |= (1 << ((irq == RxIrq) ? 0 : 2));
bogdanm 0:9b334a45a8ff 280 NVIC_SetVector(irq_n, vector);
bogdanm 0:9b334a45a8ff 281 NVIC_EnableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 282 } else { // disable
bogdanm 0:9b334a45a8ff 283 obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2));
bogdanm 0:9b334a45a8ff 284 if ( (obj->uart->INTENSET & (RXRDYEN | TXRDYEN)) == 0) {
bogdanm 0:9b334a45a8ff 285 NVIC_DisableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288 }
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /******************************************************************************
bogdanm 0:9b334a45a8ff 291 * READ/WRITE
bogdanm 0:9b334a45a8ff 292 ******************************************************************************/
bogdanm 0:9b334a45a8ff 293 int serial_getc(serial_t *obj)
bogdanm 0:9b334a45a8ff 294 {
bogdanm 0:9b334a45a8ff 295 while (!serial_readable(obj));
bogdanm 0:9b334a45a8ff 296 return obj->uart->RXDAT;
bogdanm 0:9b334a45a8ff 297 }
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 void serial_putc(serial_t *obj, int c)
bogdanm 0:9b334a45a8ff 300 {
bogdanm 0:9b334a45a8ff 301 while (!serial_writable(obj));
bogdanm 0:9b334a45a8ff 302 obj->uart->TXDAT = c;
bogdanm 0:9b334a45a8ff 303 }
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 int serial_readable(serial_t *obj)
bogdanm 0:9b334a45a8ff 306 {
bogdanm 0:9b334a45a8ff 307 return obj->uart->STAT & RXRDY;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 int serial_writable(serial_t *obj)
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 return obj->uart->STAT & TXRDY;
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 void serial_clear(serial_t *obj)
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 // [TODO]
bogdanm 0:9b334a45a8ff 318 }
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 void serial_pinout_tx(PinName tx)
bogdanm 0:9b334a45a8ff 321 {
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 }
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 void serial_break_set(serial_t *obj)
bogdanm 0:9b334a45a8ff 326 {
bogdanm 0:9b334a45a8ff 327 obj->uart->CTL |= TXBRKEN;
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 void serial_break_clear(serial_t *obj)
bogdanm 0:9b334a45a8ff 331 {
bogdanm 0:9b334a45a8ff 332 obj->uart->CTL &= ~TXBRKEN;
bogdanm 0:9b334a45a8ff 333 }
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
bogdanm 0:9b334a45a8ff 336 {
bogdanm 0:9b334a45a8ff 337 const SWM_Map *swm_rts, *swm_cts;
bogdanm 0:9b334a45a8ff 338 uint32_t regVal_rts, regVal_cts;
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 swm_rts = &SWM_UART_RTS[obj->index];
bogdanm 0:9b334a45a8ff 341 swm_cts = &SWM_UART_CTS[obj->index];
bogdanm 0:9b334a45a8ff 342 regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
bogdanm 0:9b334a45a8ff 343 regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 if (FlowControlNone == type) {
bogdanm 0:9b334a45a8ff 346 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
bogdanm 0:9b334a45a8ff 347 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
bogdanm 0:9b334a45a8ff 348 obj->uart->CFG &= ~CTSEN;
bogdanm 0:9b334a45a8ff 349 return;
bogdanm 0:9b334a45a8ff 350 }
bogdanm 0:9b334a45a8ff 351 if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
bogdanm 0:9b334a45a8ff 352 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | ((rxflow >> PIN_SHIFT) << swm_rts->offset);
bogdanm 0:9b334a45a8ff 353 if (FlowControlRTS == type) {
bogdanm 0:9b334a45a8ff 354 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
bogdanm 0:9b334a45a8ff 355 obj->uart->CFG &= ~CTSEN;
bogdanm 0:9b334a45a8ff 356 }
bogdanm 0:9b334a45a8ff 357 }
bogdanm 0:9b334a45a8ff 358 if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
bogdanm 0:9b334a45a8ff 359 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | ((txflow >> PIN_SHIFT) << swm_cts->offset);
bogdanm 0:9b334a45a8ff 360 obj->uart->CFG |= CTSEN;
bogdanm 0:9b334a45a8ff 361 if (FlowControlCTS == type) {
bogdanm 0:9b334a45a8ff 362 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 #endif