Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_def.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2015 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 * ----------------------------------------------------------------
bogdanm 0:9b334a45a8ff 16 * File: apspi.h
bogdanm 0:9b334a45a8ff 17 * Release: Version 2.0
bogdanm 0:9b334a45a8ff 18 * ----------------------------------------------------------------
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * SSP interface Support
bogdanm 0:9b334a45a8ff 21 * =====================
bogdanm 0:9b334a45a8ff 22 */
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 #define SSPCS_BASE (0x4002804C) // SSP chip select register
bogdanm 0:9b334a45a8ff 25 #define SSP_BASE (0x40020000) // SSP Prime Cell
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
bogdanm 0:9b334a45a8ff 28 #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
bogdanm 0:9b334a45a8ff 29 #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
bogdanm 0:9b334a45a8ff 30 #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
bogdanm 0:9b334a45a8ff 31 #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
bogdanm 0:9b334a45a8ff 32 #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
bogdanm 0:9b334a45a8ff 33 #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
bogdanm 0:9b334a45a8ff 34 #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
bogdanm 0:9b334a45a8ff 35 #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
bogdanm 0:9b334a45a8ff 36 #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
bogdanm 0:9b334a45a8ff 37 #define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 // SSPCR0 Control register 0
bogdanm 0:9b334a45a8ff 40 #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
bogdanm 0:9b334a45a8ff 41 #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
bogdanm 0:9b334a45a8ff 42 #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
bogdanm 0:9b334a45a8ff 43 #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
bogdanm 0:9b334a45a8ff 44 #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
bogdanm 0:9b334a45a8ff 45 #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 // SSPCR1 Control register 1
bogdanm 0:9b334a45a8ff 48 #define SSPCR1_SOD 0x0008 // Slave Output mode Disable
bogdanm 0:9b334a45a8ff 49 #define SSPCR1_MS 0x0004 // Master or Slave mode
bogdanm 0:9b334a45a8ff 50 #define SSPCR1_SSE 0x0002 // Serial port enable
bogdanm 0:9b334a45a8ff 51 #define SSPCR1_LBM 0x0001 // Loop Back Mode
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 // SSPSR Status register
bogdanm 0:9b334a45a8ff 54 #define SSPSR_BSY 0x0010 // Busy
bogdanm 0:9b334a45a8ff 55 #define SSPSR_RFF 0x0008 // Receive FIFO full
bogdanm 0:9b334a45a8ff 56 #define SSPSR_RNE 0x0004 // Receive FIFO not empty
bogdanm 0:9b334a45a8ff 57 #define SSPSR_TNF 0x0002 // Transmit FIFO not full
bogdanm 0:9b334a45a8ff 58 #define SSPSR_TFE 0x0001 // Transmit FIFO empty
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 // SSPCPSR Clock prescale register
bogdanm 0:9b334a45a8ff 61 #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 // SSPIMSC Interrupt mask set and clear register
bogdanm 0:9b334a45a8ff 64 #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
bogdanm 0:9b334a45a8ff 65 #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
bogdanm 0:9b334a45a8ff 66 #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
bogdanm 0:9b334a45a8ff 67 #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 // SSPRIS Raw interrupt status register
bogdanm 0:9b334a45a8ff 70 #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
bogdanm 0:9b334a45a8ff 71 #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
bogdanm 0:9b334a45a8ff 72 #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
bogdanm 0:9b334a45a8ff 73 #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 // SSPMIS Masked interrupt status register
bogdanm 0:9b334a45a8ff 76 #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
bogdanm 0:9b334a45a8ff 77 #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
bogdanm 0:9b334a45a8ff 78 #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
bogdanm 0:9b334a45a8ff 79 #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 // SSPICR Interrupt clear register
bogdanm 0:9b334a45a8ff 82 #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
bogdanm 0:9b334a45a8ff 83 #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 // SSPDMACR DMA control register
bogdanm 0:9b334a45a8ff 86 #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
bogdanm 0:9b334a45a8ff 87 #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 // SPICS register (0=Chip Select low)
bogdanm 0:9b334a45a8ff 90 #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 // SPI defaults
bogdanm 0:9b334a45a8ff 93 #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 // EEPROM instruction set
bogdanm 0:9b334a45a8ff 96 #define EEWRSR 0x0001 // Write status
bogdanm 0:9b334a45a8ff 97 #define EEWRITE 0x0002 // Write data
bogdanm 0:9b334a45a8ff 98 #define EEREAD 0x0003 // Read data
bogdanm 0:9b334a45a8ff 99 #define EEWDI 0x0004 // Write disable
bogdanm 0:9b334a45a8ff 100 #define EEWREN 0x0006 // Write enable
bogdanm 0:9b334a45a8ff 101 #define EERDSR 0x0005 // Read status
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 // EEPROM status register flags
bogdanm 0:9b334a45a8ff 104 #define EERDSR_WIP 0x0001 // Write in process
bogdanm 0:9b334a45a8ff 105 #define EERDSR_WEL 0x0002 // Write enable latch
bogdanm 0:9b334a45a8ff 106 #define EERDSR_BP0 0x0004 // Block protect 0
bogdanm 0:9b334a45a8ff 107 #define EERDSR_BP1 0x0008 // Block protect 1
bogdanm 0:9b334a45a8ff 108 #define EERDSR_WPEN 0x0080 // Write protect enable
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /* ----------------------------------------------------------------
bogdanm 0:9b334a45a8ff 111 *
bogdanm 0:9b334a45a8ff 112 * Color LCD Support
bogdanm 0:9b334a45a8ff 113 * =================
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 // Color LCD Controller Internal Register addresses
bogdanm 0:9b334a45a8ff 117 #define LSSPCS_BASE (0x4002804C) // LSSP chip select register
bogdanm 0:9b334a45a8ff 118 #define LSSP_BASE (0x40021000) // LSSP Prime Cell
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
bogdanm 0:9b334a45a8ff 121 #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
bogdanm 0:9b334a45a8ff 122 #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
bogdanm 0:9b334a45a8ff 123 #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
bogdanm 0:9b334a45a8ff 124 #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
bogdanm 0:9b334a45a8ff 125 #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
bogdanm 0:9b334a45a8ff 126 #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
bogdanm 0:9b334a45a8ff 127 #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
bogdanm 0:9b334a45a8ff 128 #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
bogdanm 0:9b334a45a8ff 129 #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
bogdanm 0:9b334a45a8ff 130 #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 // LSSPCR0 Control register 0
bogdanm 0:9b334a45a8ff 133 #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
bogdanm 0:9b334a45a8ff 134 #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
bogdanm 0:9b334a45a8ff 135 #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
bogdanm 0:9b334a45a8ff 136 #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
bogdanm 0:9b334a45a8ff 137 #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
bogdanm 0:9b334a45a8ff 138 #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 // LSSPCR1 Control register 1
bogdanm 0:9b334a45a8ff 141 #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
bogdanm 0:9b334a45a8ff 142 #define LSSPCR1_MS 0x0004 // Master or Slave mode
bogdanm 0:9b334a45a8ff 143 #define LSSPCR1_SSE 0x0002 // Serial port enable
bogdanm 0:9b334a45a8ff 144 #define LSSPCR1_LBM 0x0001 // Loop Back Mode
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 // LSSPSR Status register
bogdanm 0:9b334a45a8ff 147 #define LSSPSR_BSY 0x0010 // Busy
bogdanm 0:9b334a45a8ff 148 #define LSSPSR_RFF 0x0008 // Receive FIFO full
bogdanm 0:9b334a45a8ff 149 #define LSSPSR_RNE 0x0004 // Receive FIFO not empty
bogdanm 0:9b334a45a8ff 150 #define LSSPSR_TNF 0x0002 // Transmit FIFO not full
bogdanm 0:9b334a45a8ff 151 #define LSSPSR_TFE 0x0001 // Transmit FIFO empty
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 // LSSPCPSR Clock prescale register
bogdanm 0:9b334a45a8ff 154 #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 // SPICS register
bogdanm 0:9b334a45a8ff 157 #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
bogdanm 0:9b334a45a8ff 158 #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
bogdanm 0:9b334a45a8ff 159 #define LCD_RESET 0x0008 // RESET (CLCD_RESET)
bogdanm 0:9b334a45a8ff 160 #define LCD_RS 0x0010 // RS (CLCD_RS)
bogdanm 0:9b334a45a8ff 161 #define LCD_RD 0x0020 // RD (CLCD_RD)
bogdanm 0:9b334a45a8ff 162 #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 // SPI defaults
bogdanm 0:9b334a45a8ff 165 #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
bogdanm 0:9b334a45a8ff 166 #define LSPI_START (0x70) // Start byte for SPI transfer
bogdanm 0:9b334a45a8ff 167 #define LSPI_RD (0x01) // WR bit 1 within start
bogdanm 0:9b334a45a8ff 168 #define LSPI_WR (0x00) // WR bit 0 within start
bogdanm 0:9b334a45a8ff 169 #define LSPI_DATA (0x02) // RS bit 1 within start byte
bogdanm 0:9b334a45a8ff 170 #define LSPI_INDEX (0x00) // RS bit 0 within start byte
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 // Screen size
bogdanm 0:9b334a45a8ff 173 #define LCD_WIDTH 320 // Screen Width (in pixels)
bogdanm 0:9b334a45a8ff 174 #define LCD_HEIGHT 240 // Screen Height (in pixels)