Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* Copyright (c) 2009 - 2012 ARM LIMITED
bogdanm 0:9b334a45a8ff 2
bogdanm 0:9b334a45a8ff 3 All rights reserved.
bogdanm 0:9b334a45a8ff 4 Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 5 modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 6 - Redistributions of source code must retain the above copyright
bogdanm 0:9b334a45a8ff 7 notice, this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 8 - Redistributions in binary form must reproduce the above copyright
bogdanm 0:9b334a45a8ff 9 notice, this list of conditions and the following disclaimer in the
bogdanm 0:9b334a45a8ff 10 documentation and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 11 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 0:9b334a45a8ff 12 to endorse or promote products derived from this software without
bogdanm 0:9b334a45a8ff 13 specific prior written permission.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 17 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 0:9b334a45a8ff 18 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 0:9b334a45a8ff 19 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 0:9b334a45a8ff 20 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 0:9b334a45a8ff 21 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 0:9b334a45a8ff 22 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 0:9b334a45a8ff 23 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 0:9b334a45a8ff 24 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 0:9b334a45a8ff 25 POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 26 ---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 29 * Functions
bogdanm 0:9b334a45a8ff 30 *---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 31 .text
bogdanm 0:9b334a45a8ff 32 .global __v7_all_cache
bogdanm 0:9b334a45a8ff 33 /*
bogdanm 0:9b334a45a8ff 34 * __STATIC_ASM void __v7_all_cache(uint32_t op) {
bogdanm 0:9b334a45a8ff 35 */
bogdanm 0:9b334a45a8ff 36 __v7_all_cache:
bogdanm 0:9b334a45a8ff 37 .arm
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 PUSH {R4-R11}
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */
bogdanm 0:9b334a45a8ff 42 ANDS R3, R6, #0x07000000 /* Extract coherency level */
bogdanm 0:9b334a45a8ff 43 MOV R3, R3, LSR #23 /* Total cache levels << 1 */
bogdanm 0:9b334a45a8ff 44 BEQ Finished /* If 0, no need to clean */
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 MOV R10, #0 /* R10 holds current cache level << 1 */
bogdanm 0:9b334a45a8ff 47 Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */
bogdanm 0:9b334a45a8ff 48 MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */
bogdanm 0:9b334a45a8ff 49 AND R1, R1, #7 /* Isolate those lower 3 bits */
bogdanm 0:9b334a45a8ff 50 CMP R1, #2
bogdanm 0:9b334a45a8ff 51 BLT Skip /* No cache or only instruction cache at this level */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */
bogdanm 0:9b334a45a8ff 54 ISB /* ISB to sync the change to the CacheSizeID reg */
bogdanm 0:9b334a45a8ff 55 MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */
bogdanm 0:9b334a45a8ff 56 AND R2, R1, #7 /* Extract the line length field */
bogdanm 0:9b334a45a8ff 57 ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */
bogdanm 0:9b334a45a8ff 58 LDR R4, =0x3FF
bogdanm 0:9b334a45a8ff 59 ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */
bogdanm 0:9b334a45a8ff 60 CLZ R5, R4 /* R5 is the bit position of the way size increment */
bogdanm 0:9b334a45a8ff 61 LDR R7, =0x7FFF
bogdanm 0:9b334a45a8ff 62 ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */
bogdanm 0:9b334a45a8ff 67 ORR R11, R11, R7, LSL R2 /* Factor in the Set number */
bogdanm 0:9b334a45a8ff 68 CMP R0, #0
bogdanm 0:9b334a45a8ff 69 BNE Dccsw
bogdanm 0:9b334a45a8ff 70 MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */
bogdanm 0:9b334a45a8ff 71 B cont
bogdanm 0:9b334a45a8ff 72 Dccsw: CMP R0, #1
bogdanm 0:9b334a45a8ff 73 BNE Dccisw
bogdanm 0:9b334a45a8ff 74 MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */
bogdanm 0:9b334a45a8ff 75 B cont
bogdanm 0:9b334a45a8ff 76 Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */
bogdanm 0:9b334a45a8ff 77 cont: SUBS R9, R9, #1 /* Decrement the Way number */
bogdanm 0:9b334a45a8ff 78 BGE Loop3
bogdanm 0:9b334a45a8ff 79 SUBS R7, R7, #1 /* Decrement the Set number */
bogdanm 0:9b334a45a8ff 80 BGE Loop2
bogdanm 0:9b334a45a8ff 81 Skip: ADD R10, R10, #2 /* increment the cache number */
bogdanm 0:9b334a45a8ff 82 CMP R3, R10
bogdanm 0:9b334a45a8ff 83 BGT Loop1
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 Finished:
bogdanm 0:9b334a45a8ff 86 DSB
bogdanm 0:9b334a45a8ff 87 POP {R4-R11}
bogdanm 0:9b334a45a8ff 88 BX lr
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 .END
bogdanm 0:9b334a45a8ff 92 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 93 * end of file
bogdanm 0:9b334a45a8ff 94 *---------------------------------------------------------------------------*/