mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sys.h@152:9a67f0b066fc, 2016-12-15 (annotated)
- Committer:
- <>
- Date:
- Thu Dec 15 11:48:27 2016 +0000
- Revision:
- 152:9a67f0b066fc
- Parent:
- 149:156823d33999
This updates the lib to the mbed lib v131
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /**************************************************************************//** |
<> | 149:156823d33999 | 2 | * @file SYS.h |
<> | 149:156823d33999 | 3 | * @version V1.0 |
<> | 149:156823d33999 | 4 | * $Revision 1 $ |
<> | 149:156823d33999 | 5 | * $Date: 15/10/21 1:35p $ |
<> | 149:156823d33999 | 6 | * @brief NUC472/NUC442 SYS Header File |
<> | 149:156823d33999 | 7 | * |
<> | 149:156823d33999 | 8 | * @note |
<> | 149:156823d33999 | 9 | * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. |
<> | 149:156823d33999 | 10 | ******************************************************************************/ |
<> | 149:156823d33999 | 11 | |
<> | 149:156823d33999 | 12 | #ifndef __SYS_H__ |
<> | 149:156823d33999 | 13 | #define __SYS_H__ |
<> | 149:156823d33999 | 14 | |
<> | 149:156823d33999 | 15 | #ifdef __cplusplus |
<> | 149:156823d33999 | 16 | extern "C" |
<> | 149:156823d33999 | 17 | { |
<> | 149:156823d33999 | 18 | #endif |
<> | 149:156823d33999 | 19 | |
<> | 149:156823d33999 | 20 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
<> | 149:156823d33999 | 21 | @{ |
<> | 149:156823d33999 | 22 | */ |
<> | 149:156823d33999 | 23 | |
<> | 149:156823d33999 | 24 | /** @addtogroup NUC472_442_SYS_Driver SYS Driver |
<> | 149:156823d33999 | 25 | @{ |
<> | 149:156823d33999 | 26 | */ |
<> | 149:156823d33999 | 27 | |
<> | 149:156823d33999 | 28 | /** @addtogroup NUC472_442_SYS_EXPORTED_CONSTANTS SYS Exported Constants |
<> | 149:156823d33999 | 29 | @{ |
<> | 149:156823d33999 | 30 | */ |
<> | 149:156823d33999 | 31 | |
<> | 149:156823d33999 | 32 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 33 | /* Module Reset Control Resister constant definitions. */ |
<> | 149:156823d33999 | 34 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 35 | #define PDMA_RST ((0x0<<24)|SYS_IPRST0_PDMARST_Pos) /*!<Reset PDMA \hideinitializer */ |
<> | 149:156823d33999 | 36 | #define EBI_RST ((0x0<<24)|SYS_IPRST0_EBIRST_Pos) /*!<Reset EBI \hideinitializer */ |
<> | 149:156823d33999 | 37 | #define USBH_RST ((0x0<<24)|SYS_IPRST0_USBHRST_Pos) /*!<Reset USBH \hideinitializer */ |
<> | 149:156823d33999 | 38 | #define EMAC_RST ((0x0<<24)|SYS_IPRST0_EMACRST_Pos) /*!<Reset EMAC \hideinitializer */ |
<> | 149:156823d33999 | 39 | #define SDH_RST ((0x0<<24)|SYS_IPRST0_SDHRST_Pos) /*!<Reset SDIO \hideinitializer */ |
<> | 149:156823d33999 | 40 | #define CRC_RST ((0x0<<24)|SYS_IPRST0_CRCRST_Pos) /*!<Reset CRC \hideinitializer */ |
<> | 149:156823d33999 | 41 | #define CAP_RST ((0x0<<24)|SYS_IPRST0_CAPRST_Pos) /*!<Reset CAP \hideinitializer */ |
<> | 149:156823d33999 | 42 | #define CRYPTO_RST ((0x0<<24)|SYS_IPRST0_CRYPTORST_Pos) /*!<Reset CRYPTO \hideinitializer */ |
<> | 149:156823d33999 | 43 | #define GPIO_RST ((0x4<<24)|SYS_IPRST1_GPIORST_Pos) /*!<Reset GPIO \hideinitializer */ |
<> | 149:156823d33999 | 44 | #define TMR0_RST ((0x4<<24)|SYS_IPRST1_TMR0RST_Pos) /*!<Reset TMR0 \hideinitializer */ |
<> | 149:156823d33999 | 45 | #define TMR1_RST ((0x4<<24)|SYS_IPRST1_TMR1RST_Pos) /*!<Reset TMR1 \hideinitializer */ |
<> | 149:156823d33999 | 46 | #define TMR2_RST ((0x4<<24)|SYS_IPRST1_TMR2RST_Pos) /*!<Reset TMR2 \hideinitializer */ |
<> | 149:156823d33999 | 47 | #define TMR3_RST ((0x4<<24)|SYS_IPRST1_TMR3RST_Pos) /*!<Reset TMR3 \hideinitializer */ |
<> | 149:156823d33999 | 48 | #define ACMP_RST ((0x4<<24)|SYS_IPRST1_ACMPRST_Pos) /*!<Reset ACMP \hideinitializer */ |
<> | 149:156823d33999 | 49 | #define I2C0_RST ((0x4<<24)|SYS_IPRST1_I2C0RST_Pos) /*!<Reset I2C0 \hideinitializer */ |
<> | 149:156823d33999 | 50 | #define I2C1_RST ((0x4<<24)|SYS_IPRST1_I2C1RST_Pos) /*!<Reset I2C1 \hideinitializer */ |
<> | 149:156823d33999 | 51 | #define I2C2_RST ((0x4<<24)|SYS_IPRST1_I2C2RST_Pos) /*!<Reset I2C2 \hideinitializer */ |
<> | 149:156823d33999 | 52 | #define I2C3_RST ((0x4<<24)|SYS_IPRST1_I2C3RST_Pos) /*!<Reset I2C3 \hideinitializer */ |
<> | 149:156823d33999 | 53 | #define SPI0_RST ((0x4<<24)|SYS_IPRST1_SPI0RST_Pos) /*!<Reset SPI0 \hideinitializer */ |
<> | 149:156823d33999 | 54 | #define SPI1_RST ((0x4<<24)|SYS_IPRST1_SPI1RST_Pos) /*!<Reset SPI1 \hideinitializer */ |
<> | 149:156823d33999 | 55 | #define SPI2_RST ((0x4<<24)|SYS_IPRST1_SPI2RST_Pos) /*!<Reset SPI2 \hideinitializer */ |
<> | 149:156823d33999 | 56 | #define SPI3_RST ((0x4<<24)|SYS_IPRST1_SPI3RST_Pos) /*!<Reset SPI3 \hideinitializer */ |
<> | 149:156823d33999 | 57 | #define UART0_RST ((0x4<<24)|SYS_IPRST1_UART0RST_Pos) /*!<Reset UART0 \hideinitializer */ |
<> | 149:156823d33999 | 58 | #define UART1_RST ((0x4<<24)|SYS_IPRST1_UART1RST_Pos) /*!<Reset UART1 \hideinitializer */ |
<> | 149:156823d33999 | 59 | #define UART2_RST ((0x4<<24)|SYS_IPRST1_UART2RST_Pos) /*!<Reset UART2 \hideinitializer */ |
<> | 149:156823d33999 | 60 | #define UART3_RST ((0x4<<24)|SYS_IPRST1_UART3RST_Pos) /*!<Reset UART3 \hideinitializer */ |
<> | 149:156823d33999 | 61 | #define UART4_RST ((0x4<<24)|SYS_IPRST1_UART4RST_Pos) /*!<Reset UART4 \hideinitializer */ |
<> | 149:156823d33999 | 62 | #define UART5_RST ((0x4<<24)|SYS_IPRST1_UART5RST_Pos) /*!<Reset UART5 \hideinitializer */ |
<> | 149:156823d33999 | 63 | #define CAN0_RST ((0x4<<24)|SYS_IPRST1_CAN0RST_Pos) /*!<Reset CAN0 \hideinitializer */ |
<> | 149:156823d33999 | 64 | #define CAN1_RST ((0x4<<24)|SYS_IPRST1_CAN1RST_Pos) /*!<Reset CAN1 \hideinitializer */ |
<> | 149:156823d33999 | 65 | #define OTG_RST ((0x4<<24)|SYS_IPRST1_OTGRST_Pos) /*!<Reset OTG \hideinitializer */ |
<> | 149:156823d33999 | 66 | #define USBD_RST ((0x4<<24)|SYS_IPRST1_USBDRST_Pos) /*!<Reset USBD \hideinitializer */ |
<> | 149:156823d33999 | 67 | #define ADC_RST ((0x4<<24)|SYS_IPRST1_ADCRST_Pos) /*!<Reset ADC \hideinitializer */ |
<> | 149:156823d33999 | 68 | #define I2S0_RST ((0x4<<24)|SYS_IPRST1_I2S0RST_Pos) /*!<Reset I2S0 \hideinitializer */ |
<> | 149:156823d33999 | 69 | #define I2S1_RST ((0x4<<24)|SYS_IPRST1_I2S1RST_Pos) /*!<Reset I2S1 \hideinitializer */ |
<> | 149:156823d33999 | 70 | #define PS2_RST ((0x4<<24)|SYS_IPRST1_PS2RST_Pos) /*!<Reset PS2 \hideinitializer */ |
<> | 149:156823d33999 | 71 | #define SC0_RST ((0x8<<24)|SYS_IPRST2_SC0RST_Pos) /*!<Reset SC0 \hideinitializer */ |
<> | 149:156823d33999 | 72 | #define SC1_RST ((0x8<<24)|SYS_IPRST2_SC1RST_Pos) /*!<Reset SC1 \hideinitializer */ |
<> | 149:156823d33999 | 73 | #define SC2_RST ((0x8<<24)|SYS_IPRST2_SC2RST_Pos) /*!<Reset SC2 \hideinitializer */ |
<> | 149:156823d33999 | 74 | #define SC3_RST ((0x8<<24)|SYS_IPRST2_SC3RST_Pos) /*!<Reset SC3 \hideinitializer */ |
<> | 149:156823d33999 | 75 | #define SC4_RST ((0x8<<24)|SYS_IPRST2_SC4RST_Pos) /*!<Reset SC4 \hideinitializer */ |
<> | 149:156823d33999 | 76 | #define SC5_RST ((0x8<<24)|SYS_IPRST2_SC5RST_Pos) /*!<Reset SC5 \hideinitializer */ |
<> | 149:156823d33999 | 77 | #define I2C4_RST ((0x8<<24)|SYS_IPRST2_I2C4RST_Pos) /*!<Reset I2C4 \hideinitializer */ |
<> | 149:156823d33999 | 78 | #define PWM0_RST ((0x8<<24)|SYS_IPRST2_PWM0RST_Pos) /*!<Reset PWM0 \hideinitializer */ |
<> | 149:156823d33999 | 79 | #define PWM1_RST ((0x8<<24)|SYS_IPRST2_PWM1RST_Pos) /*!<Reset PWM1 \hideinitializer */ |
<> | 149:156823d33999 | 80 | #define QEI0_RST ((0x8<<24)|SYS_IPRST2_QEI0RST_Pos) /*!<Reset QEI0 \hideinitializer */ |
<> | 149:156823d33999 | 81 | #define QEI1_RST ((0x8<<24)|SYS_IPRST2_QEI1RST_Pos) /*!<Reset QEI1 \hideinitializer */ |
<> | 149:156823d33999 | 82 | |
<> | 149:156823d33999 | 83 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 84 | /* BODCTL constant definitions. */ |
<> | 149:156823d33999 | 85 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 86 | #define SYS_BODCTL_BODVL_2_2V (0x0UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 2.2V \hideinitializer */ |
<> | 149:156823d33999 | 87 | #define SYS_BODCTL_BODVL_2_7V (0x1UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 2.7V \hideinitializer */ |
<> | 149:156823d33999 | 88 | #define SYS_BODCTL_BODVL_3_8V (0x2UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 3.82V \hideinitializer */ |
<> | 149:156823d33999 | 89 | #define SYS_BODCTL_BODVL_4_5V (0x3UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 4.5V \hideinitializer */ |
<> | 149:156823d33999 | 90 | #define SYS_BODCTL_BODRSTEN (0x1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!<Enable reset function of BOD. \hideinitializer */ |
<> | 149:156823d33999 | 91 | #define SYS_BODCTL_BODINTEN (0x0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!<Enable interrupt function of BOD. \hideinitializer */ |
<> | 149:156823d33999 | 92 | #define SYS_BODCTL_BODLPM (0x1UL<<SYS_BODCTL_BODLPM_Pos) /*!<BOD work in low power mode. \hideinitializer */ |
<> | 149:156823d33999 | 93 | #define SYS_BODCTL_BODOUT (0x1UL<<SYS_BODCTL_BODOUT_Pos) /*!<Output of BOD IP. \hideinitializer */ |
<> | 149:156823d33999 | 94 | #define SYS_BODCTL_LVREN (0x1UL<<SYS_BODCTL_LVREN_Pos) /*!<Enable LVR function. \hideinitializer */ |
<> | 149:156823d33999 | 95 | |
<> | 149:156823d33999 | 96 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 97 | /* VREFCTL constant definitions. (Write-Protection Register) */ |
<> | 149:156823d33999 | 98 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 99 | #define SYS_VREFCTL_VREF_2_65V (0x03UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 2.56V \hideinitializer */ |
<> | 149:156823d33999 | 100 | #define SYS_VREFCTL_VREF_2_048V (0x07UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 2.048V \hideinitializer */ |
<> | 149:156823d33999 | 101 | #define SYS_VREFCTL_VREF_3_072V (0x0BUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 3.072V \hideinitializer */ |
<> | 149:156823d33999 | 102 | #define SYS_VREFCTL_VREF_4_096V (0x0FUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 4.096V \hideinitializer */ |
<> | 149:156823d33999 | 103 | #define SYS_VREFCTL_VREF_AVDD (0x10UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= AVDD \hideinitializer */ |
<> | 149:156823d33999 | 104 | #define SYS_VREFCTL_ADCMODESEL_EADC (0x1UL<<SYS_VREFCTL_ADCMODESEL_Pos) /*!< EADC mode \hideinitializer */ |
<> | 149:156823d33999 | 105 | #define SYS_VREFCTL_ADCMODESEL_ADC (0x0UL<<SYS_VREFCTL_ADCMODESEL_Pos) /*!< ADC mode \hideinitializer */ |
<> | 149:156823d33999 | 106 | #define SYS_VREFCTL_PWMSYNCMODE_EN (0x1UL<<SYS_VREFCTL_PWMSYNCMODE_Pos)/*!<PWM SYNC MODE ENABLED, PWM engine clock is same as HCLK \hideinitializer */ |
<> | 149:156823d33999 | 107 | |
<> | 149:156823d33999 | 108 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 109 | /* USBROLE constant definitions. (Write-Protection Register) */ |
<> | 149:156823d33999 | 110 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 111 | #define SYS_USBPHY_USBROLE_OTG_V33_EN (0x1UL<<SYS_USBPHY_LDO33EN_Pos) /*!< USB LDO33 Enabled \hideinitializer */ |
<> | 149:156823d33999 | 112 | #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */ |
<> | 149:156823d33999 | 113 | #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */ |
<> | 149:156823d33999 | 114 | #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */ |
<> | 149:156823d33999 | 115 | #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */ |
<> | 149:156823d33999 | 116 | |
<> | 149:156823d33999 | 117 | |
<> | 149:156823d33999 | 118 | |
<> | 149:156823d33999 | 119 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 120 | /* Multi-Function constant definitions. */ |
<> | 149:156823d33999 | 121 | /*---------------------------------------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 122 | /* How to use below #define? |
<> | 149:156823d33999 | 123 | Example 1: If user want to set PA.0 as SC0_CD in initial function, |
<> | 149:156823d33999 | 124 | user can issue following command to achieve it. |
<> | 149:156823d33999 | 125 | |
<> | 149:156823d33999 | 126 | SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ; |
<> | 149:156823d33999 | 127 | |
<> | 149:156823d33999 | 128 | */ |
<> | 149:156823d33999 | 129 | //GPA_MFPL_PA0MFP |
<> | 149:156823d33999 | 130 | #define SYS_GPA_MFPL_PA0MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 131 | #define SYS_GPA_MFPL_PA0MFP_TAMPER0 (0x1UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for TAMPER0 \hideinitializer */ |
<> | 149:156823d33999 | 132 | #define SYS_GPA_MFPL_PA0MFP_SC0_CD (0x2UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CD \hideinitializer */ |
<> | 149:156823d33999 | 133 | #define SYS_GPA_MFPL_PA0MFP_CAN1_RXD (0x3UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for CAN1_RXD \hideinitializer */ |
<> | 149:156823d33999 | 134 | #define SYS_GPA_MFPL_PA0MFP_INT0 (0x8UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for INT0 \hideinitializer */ |
<> | 149:156823d33999 | 135 | |
<> | 149:156823d33999 | 136 | //GPA_MFPL_PA1MFP |
<> | 149:156823d33999 | 137 | #define SYS_GPA_MFPL_PA1MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 138 | #define SYS_GPA_MFPL_PA1MFP_TAMPER1 (0x1UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for TAMPER1 \hideinitializer */ |
<> | 149:156823d33999 | 139 | #define SYS_GPA_MFPL_PA1MFP_SC5_CD (0x2UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC5_CD \hideinitializer */ |
<> | 149:156823d33999 | 140 | #define SYS_GPA_MFPL_PA1MFP_CAN1_TXD (0x3UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for CAN1_TXD \hideinitializer */ |
<> | 149:156823d33999 | 141 | #define SYS_GPA_MFPL_PA1MFP_EBI_A22 (0x7UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EBI_A22 \hideinitializer */ |
<> | 149:156823d33999 | 142 | |
<> | 149:156823d33999 | 143 | //GPA_MFPL_PA2MFP |
<> | 149:156823d33999 | 144 | #define SYS_GPA_MFPL_PA2MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 145 | #define SYS_GPA_MFPL_PA2MFP_SC2_DAT (0x1UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC2_DAT \hideinitializer */ |
<> | 149:156823d33999 | 146 | #define SYS_GPA_MFPL_PA2MFP_SPI3_MISO0 (0x2UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SPI3_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 147 | #define SYS_GPA_MFPL_PA2MFP_I2S0_MCLK (0x3UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2S0_MCLK \hideinitializer */ |
<> | 149:156823d33999 | 148 | #define SYS_GPA_MFPL_PA2MFP_BRAKE11 (0x4UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for BRAKE11 \hideinitializer */ |
<> | 149:156823d33999 | 149 | #define SYS_GPA_MFPL_PA2MFP_CAP_SFIELD (0x5UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for CAP_SFIELD \hideinitializer */ |
<> | 149:156823d33999 | 150 | #define SYS_GPA_MFPL_PA2MFP_EBI_A12 (0x7UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EBI_A12 \hideinitializer */ |
<> | 149:156823d33999 | 151 | |
<> | 149:156823d33999 | 152 | //GPA_MFPL_PA3MFP |
<> | 149:156823d33999 | 153 | #define SYS_GPA_MFPL_PA3MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 154 | #define SYS_GPA_MFPL_PA3MFP_SC2_CLK (0x1UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC2_CLK \hideinitializer */ |
<> | 149:156823d33999 | 155 | #define SYS_GPA_MFPL_PA3MFP_SPI3_MOSI0 (0x2UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SPI3_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 156 | #define SYS_GPA_MFPL_PA3MFP_I2S0_DO (0x3UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2S0_D0 \hideinitializer */ |
<> | 149:156823d33999 | 157 | #define SYS_GPA_MFPL_PA3MFP_BRAKE10 (0x4UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for BRAKE10 \hideinitializer */ |
<> | 149:156823d33999 | 158 | #define SYS_GPA_MFPL_PA3MFP_EBI_A13 (0x7UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EBI_A13 \hideinitializer */ |
<> | 149:156823d33999 | 159 | |
<> | 149:156823d33999 | 160 | //GPA_MFPL_PA4MFP |
<> | 149:156823d33999 | 161 | #define SYS_GPA_MFPL_PA4MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 162 | #define SYS_GPA_MFPL_PA4MFP_SC2_PWR (0x1UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SC2_PWR \hideinitializer */ |
<> | 149:156823d33999 | 163 | #define SYS_GPA_MFPL_PA4MFP_SPI3_CLK (0x2UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI3_CLK \hideinitializer */ |
<> | 149:156823d33999 | 164 | #define SYS_GPA_MFPL_PA4MFP_I2S0_DI (0x3UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for I2S0_DI \hideinitializer */ |
<> | 149:156823d33999 | 165 | #define SYS_GPA_MFPL_PA4MFP_QEI1_Z (0x5UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QEI1_Z \hideinitializer */ |
<> | 149:156823d33999 | 166 | #define SYS_GPA_MFPL_PA4MFP_EBI_A14 (0x7UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EBI_A14 \hideinitializer */ |
<> | 149:156823d33999 | 167 | #define SYS_GPA_MFPL_PA4MFP_ECAP1_IC2 (0x8UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for ECAP1_IC2 \hideinitializer */ |
<> | 149:156823d33999 | 168 | |
<> | 149:156823d33999 | 169 | //GPA_MFPL_PA5MFP |
<> | 149:156823d33999 | 170 | #define SYS_GPA_MFPL_PA5MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 171 | #define SYS_GPA_MFPL_PA5MFP_SC2_RST (0x1UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SC2_RST \hideinitializer */ |
<> | 149:156823d33999 | 172 | #define SYS_GPA_MFPL_PA5MFP_SPI3_SS0 (0x2UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI3_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 173 | #define SYS_GPA_MFPL_PA5MFP_I2S0_BCLK (0x3UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for I2S0_BCLK \hideinitializer */ |
<> | 149:156823d33999 | 174 | #define SYS_GPA_MFPL_PA5MFP_PWM0_CH0 (0x4UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for PWM0 CH0 \hideinitializer */ |
<> | 149:156823d33999 | 175 | #define SYS_GPA_MFPL_PA5MFP_QEI1_B (0x5UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QEI1_B \hideinitializer */ |
<> | 149:156823d33999 | 176 | #define SYS_GPA_MFPL_PA5MFP_EBI_A15 (0x7UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EBI_A15 \hideinitializer */ |
<> | 149:156823d33999 | 177 | #define SYS_GPA_MFPL_PA5MFP_ECAP1_IC1 (0x8UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for ECAP1_IC1 \hideinitializer */ |
<> | 149:156823d33999 | 178 | |
<> | 149:156823d33999 | 179 | //GPA_MFPL_PA6MFP |
<> | 149:156823d33999 | 180 | #define SYS_GPA_MFPL_PA6MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 181 | #define SYS_GPA_MFPL_PA6MFP_SC2_CD (0x1UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SC2_CD \hideinitializer */ |
<> | 149:156823d33999 | 182 | #define SYS_GPA_MFPL_PA6MFP_I2S0_LRCK (0x3UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for I2S0_LRCK \hideinitializer */ |
<> | 149:156823d33999 | 183 | #define SYS_GPA_MFPL_PA6MFP_PWM0_CH1 (0x4UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for PWM1 CH1 \hideinitializer */ |
<> | 149:156823d33999 | 184 | #define SYS_GPA_MFPL_PA6MFP_QEI1_A (0x5UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for QEI1_A \hideinitializer */ |
<> | 149:156823d33999 | 185 | #define SYS_GPA_MFPL_PA6MFP_CAN1_TXD (0x6UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for CAN1_TXD \hideinitializer */ |
<> | 149:156823d33999 | 186 | #define SYS_GPA_MFPL_PA6MFP_EBI_A16 (0x7UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_A16 \hideinitializer */ |
<> | 149:156823d33999 | 187 | #define SYS_GPA_MFPL_PA6MFP_ECAP1_IC0 (0x8UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for ECAP1_IC0 \hideinitializer */ |
<> | 149:156823d33999 | 188 | |
<> | 149:156823d33999 | 189 | //GPA_MFPL_PA7MFP |
<> | 149:156823d33999 | 190 | #define SYS_GPA_MFPL_PA7MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 191 | #define SYS_GPA_MFPL_PA7MFP_SC0_CLK (0x2UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SC0_CLK \hideinitializer */ |
<> | 149:156823d33999 | 192 | #define SYS_GPA_MFPL_PA7MFP_SPI3_SS0 (0x3UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI3_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 193 | #define SYS_GPA_MFPL_PA7MFP_PWM1_CH3 (0x4UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for PWM1 CH3 \hideinitializer */ |
<> | 149:156823d33999 | 194 | #define SYS_GPA_MFPL_PA7MFP_EPWM0_CH5 (0x5UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EPWM0 CH5 \hideinitializer */ |
<> | 149:156823d33999 | 195 | #define SYS_GPA_MFPL_PA7MFP_EBI_A17 (0x7UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_A17 \hideinitializer */ |
<> | 149:156823d33999 | 196 | |
<> | 149:156823d33999 | 197 | //GPA_MFPL_PA8MFP |
<> | 149:156823d33999 | 198 | #define SYS_GPA_MFPH_PA8MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 199 | #define SYS_GPA_MFPH_PA8MFP_SC0_RST (0x2UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SC0_RST \hideinitializer */ |
<> | 149:156823d33999 | 200 | #define SYS_GPA_MFPH_PA8MFP_SPI3_CLK (0x3UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SPI3_CLK \hideinitializer */ |
<> | 149:156823d33999 | 201 | #define SYS_GPA_MFPH_PA8MFP_PWM1_CH2 (0x4UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for PWM1 CH2 \hideinitializer */ |
<> | 149:156823d33999 | 202 | #define SYS_GPA_MFPH_PA8MFP_EPWM0_CH4 (0x5UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EPWM0_CH4 \hideinitializer */ |
<> | 149:156823d33999 | 203 | #define SYS_GPA_MFPH_PA8MFP_EBI_A18 (0x7UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EBI_A18 \hideinitializer */ |
<> | 149:156823d33999 | 204 | |
<> | 149:156823d33999 | 205 | //GPA_MFPH_PA9MFP |
<> | 149:156823d33999 | 206 | #define SYS_GPA_MFPH_PA9MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 207 | #define SYS_GPA_MFPH_PA9MFP_SC0_PWR (0x2UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SC0_PWR \hideinitializer */ |
<> | 149:156823d33999 | 208 | #define SYS_GPA_MFPH_PA9MFP_SPI3_MISO0 (0x3UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SPI3_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 209 | #define SYS_GPA_MFPH_PA9MFP_PWM1_CH1 (0x4UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for PWM1 CH1 \hideinitializer */ |
<> | 149:156823d33999 | 210 | #define SYS_GPA_MFPH_PA9MFP_EPWM0_CH3 (0x5UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EPWM0 CH3 \hideinitializer */ |
<> | 149:156823d33999 | 211 | #define SYS_GPA_MFPH_PA9MFP_EBI_A19 (0x7UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EBI_A19 \hideinitializer */ |
<> | 149:156823d33999 | 212 | |
<> | 149:156823d33999 | 213 | //GPA_MFPH_PA10MFP |
<> | 149:156823d33999 | 214 | #define SYS_GPA_MFPH_PA10MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 215 | #define SYS_GPA_MFPH_PA10MFP_SC0_DAT (0x2UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for SC0_DAT \hideinitializer */ |
<> | 149:156823d33999 | 216 | #define SYS_GPA_MFPH_PA10MFP_SPI3_MOSI0 (0x3UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for SPI3_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 217 | #define SYS_GPA_MFPH_PA10MFP_PWM1_CH0 (0x4UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for PWM1_CH0 \hideinitializer */ |
<> | 149:156823d33999 | 218 | #define SYS_GPA_MFPH_PA10MFP_EPWM0_CH2 (0x5UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for EPWM0_CH2 \hideinitializer */ |
<> | 149:156823d33999 | 219 | #define SYS_GPA_MFPH_PA10MFP_EBI_A20 (0x7UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for EBI_A20 \hideinitializer */ |
<> | 149:156823d33999 | 220 | |
<> | 149:156823d33999 | 221 | //GPA_MFPH_PA11MFP |
<> | 149:156823d33999 | 222 | #define SYS_GPA_MFPH_PA11MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 223 | #define SYS_GPA_MFPH_PA11MFP_UART0_RTS (0x1UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for UART0_RTS \hideinitializer */ |
<> | 149:156823d33999 | 224 | #define SYS_GPA_MFPH_PA11MFP_SPI3_MISO1 (0x3UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for SPI3_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 225 | #define SYS_GPA_MFPH_PA11MFP_PWM0_CH5 (0x4UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for PWM0_CH5 \hideinitializer */ |
<> | 149:156823d33999 | 226 | #define SYS_GPA_MFPH_PA11MFP_EPWM0_CH1 (0x5UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for EPWM0_CH1 \hideinitializer */ |
<> | 149:156823d33999 | 227 | #define SYS_GPA_MFPH_PA11MFP_EBI_AD0 (0x7UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for EBI_AD0 \hideinitializer */ |
<> | 149:156823d33999 | 228 | |
<> | 149:156823d33999 | 229 | //GPA_MFPH_PA12MFP |
<> | 149:156823d33999 | 230 | #define SYS_GPA_MFPH_PA12MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 231 | #define SYS_GPA_MFPH_PA12MFP_UART0_CTS (0x1UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for UART0_CTS \hideinitializer */ |
<> | 149:156823d33999 | 232 | #define SYS_GPA_MFPH_PA12MFP_SPI3_MOSI1 (0x3UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SPI3_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 233 | #define SYS_GPA_MFPH_PA12MFP_PWM0_CH4 (0x4UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for PWM0_CH4 \hideinitializer */ |
<> | 149:156823d33999 | 234 | #define SYS_GPA_MFPH_PA12MFP_EPWM0_CH0 (0x5UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for EPWM0_CH0 \hideinitializer */ |
<> | 149:156823d33999 | 235 | #define SYS_GPA_MFPH_PA12MFP_EBI_AD1 (0x7UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for EBI_AD1 \hideinitializer */ |
<> | 149:156823d33999 | 236 | |
<> | 149:156823d33999 | 237 | //GPA_MFPH_PA13MFP |
<> | 149:156823d33999 | 238 | #define SYS_GPA_MFPH_PA13MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 239 | #define SYS_GPA_MFPH_PA13MFP_UART0_RXD (0x1UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for UART0_RXD \hideinitializer */ |
<> | 149:156823d33999 | 240 | #define SYS_GPA_MFPH_PA13MFP_SC3_DAT (0x3UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for SC3_DAT \hideinitializer */ |
<> | 149:156823d33999 | 241 | #define SYS_GPA_MFPH_PA13MFP_PWM1_CH4 (0x4UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for PWM1_CH4 \hideinitializer */ |
<> | 149:156823d33999 | 242 | #define SYS_GPA_MFPH_PA13MFP_EBI_AD2 (0x7UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for EBI_AD2 \hideinitializer */ |
<> | 149:156823d33999 | 243 | |
<> | 149:156823d33999 | 244 | //GPA_MFPH_PA14MFP |
<> | 149:156823d33999 | 245 | #define SYS_GPA_MFPH_PA14MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 246 | #define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x1UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for UART0_TXD \hideinitializer */ |
<> | 149:156823d33999 | 247 | #define SYS_GPA_MFPH_PA14MFP_SC3_CLK (0x3UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for SC3_CLK \hideinitializer */ |
<> | 149:156823d33999 | 248 | #define SYS_GPA_MFPH_PA14MFP_PWM1_CH5 (0x4UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for PWM1_CH5 \hideinitializer */ |
<> | 149:156823d33999 | 249 | #define SYS_GPA_MFPH_PA14MFP_EBI_AD3 (0x7UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for EBI_AD3 \hideinitializer */ |
<> | 149:156823d33999 | 250 | //GPA_MFPH_PA15MFP |
<> | 149:156823d33999 | 251 | #define SYS_GPA_MFPH_PA15MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 252 | #define SYS_GPA_MFPH_PA15MFP_SC3_PWR (0x1UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for SC3_PWR \hideinitializer */ |
<> | 149:156823d33999 | 253 | #define SYS_GPA_MFPH_PA15MFP_UART2_RTS (0x2UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for UART2_RTS \hideinitializer */ |
<> | 149:156823d33999 | 254 | #define SYS_GPA_MFPH_PA15MFP_I2C0_SCL (0x4UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2C0_SCL \hideinitializer */ |
<> | 149:156823d33999 | 255 | #define SYS_GPA_MFPH_PA15MFP_EBI_A21 (0x7UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for EBI_A21 \hideinitializer */ |
<> | 149:156823d33999 | 256 | |
<> | 149:156823d33999 | 257 | |
<> | 149:156823d33999 | 258 | //GPB_MFPL_PB0MFP |
<> | 149:156823d33999 | 259 | #define SYS_GPB_MFPL_PB0MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 260 | #define SYS_GPB_MFPL_PB0MFP_USB0_OTG5V_ST (0x1UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for USB0_OTG5V_ST \hideinitializer */ |
<> | 149:156823d33999 | 261 | #define SYS_GPB_MFPL_PB0MFP_I2C4_SCL (0x2UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C4_SCL \hideinitializer */ |
<> | 149:156823d33999 | 262 | #define SYS_GPB_MFPL_PB0MFP_INT1 (0x8UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for INT1 \hideinitializer */ |
<> | 149:156823d33999 | 263 | |
<> | 149:156823d33999 | 264 | //GPB_MFPL_PB1MFP |
<> | 149:156823d33999 | 265 | #define SYS_GPB_MFPL_PB1MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 266 | #define SYS_GPB_MFPL_PB1MFP_USB0_OTG5V_EN (0x1UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for USB0_OTG5V_EN \hideinitializer */ |
<> | 149:156823d33999 | 267 | #define SYS_GPB_MFPL_PB1MFP_I2C4_SDA (0x2UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2C4_SDA \hideinitializer */ |
<> | 149:156823d33999 | 268 | #define SYS_GPB_MFPL_PB1MFP_TM1_CNT_OUT (0x3UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for TM1_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 269 | |
<> | 149:156823d33999 | 270 | //GPB_MFPL_PB2MFP |
<> | 149:156823d33999 | 271 | #define SYS_GPB_MFPL_PB2MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 272 | #define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x1UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD \hideinitializer */ |
<> | 149:156823d33999 | 273 | #define SYS_GPB_MFPL_PB2MFP_SPI2_SS0 (0x2UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI2_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 274 | #define SYS_GPB_MFPL_PB2MFP_USB1_D_N (0x3UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for USB1_D_N \hideinitializer */ |
<> | 149:156823d33999 | 275 | #define SYS_GPB_MFPL_PB2MFP_EBI_AD4 (0x7UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EBI_AD4 \hideinitializer */ |
<> | 149:156823d33999 | 276 | |
<> | 149:156823d33999 | 277 | //GPB_MFPL_PB3MFP |
<> | 149:156823d33999 | 278 | #define SYS_GPB_MFPL_PB3MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 279 | #define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x1UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD \hideinitializer */ |
<> | 149:156823d33999 | 280 | #define SYS_GPB_MFPL_PB3MFP_SPI2_CLK (0x2UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI2_CLK \hideinitializer */ |
<> | 149:156823d33999 | 281 | #define SYS_GPB_MFPL_PB3MFP_USB1_D_P (0x3UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for USB1_D_P \hideinitializer */ |
<> | 149:156823d33999 | 282 | #define SYS_GPB_MFPL_PB3MFP_EBI_AD5 (0x7UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EBI_AD5 \hideinitializer */ |
<> | 149:156823d33999 | 283 | |
<> | 149:156823d33999 | 284 | //GPB_MFPL_PB4MFP |
<> | 149:156823d33999 | 285 | #define SYS_GPB_MFPL_PB4MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 286 | #define SYS_GPB_MFPL_PB4MFP_UART1_RTS (0x1UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART1_RTS \hideinitializer */ |
<> | 149:156823d33999 | 287 | #define SYS_GPB_MFPL_PB4MFP_SPI2_MISO0 (0x2UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI2_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 288 | #define SYS_GPB_MFPL_PB4MFP_UART4_RXD (0x3UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART4_RXD \hideinitializer */ |
<> | 149:156823d33999 | 289 | #define SYS_GPB_MFPL_PB4MFP_TM0_CNT_OUT (0x4UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for TM0_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 290 | #define SYS_GPB_MFPL_PB4MFP_EBI_AD6 (0x7UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_AD6 \hideinitializer */ |
<> | 149:156823d33999 | 291 | |
<> | 149:156823d33999 | 292 | //GPB_MFPL_PB5MFP |
<> | 149:156823d33999 | 293 | #define SYS_GPB_MFPL_PB5MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 294 | #define SYS_GPB_MFPL_PB5MFP_UART1_CTS (0x1UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART1_CTS \hideinitializer */ |
<> | 149:156823d33999 | 295 | #define SYS_GPB_MFPL_PB5MFP_SPI2_MOSI0 (0x2UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI2_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 296 | #define SYS_GPB_MFPL_PB5MFP_UART4_TXD (0x3UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART4_TXD \hideinitializer */ |
<> | 149:156823d33999 | 297 | #define SYS_GPB_MFPL_PB5MFP_EBI_AD7 (0x7UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_AD7 \hideinitializer */ |
<> | 149:156823d33999 | 298 | |
<> | 149:156823d33999 | 299 | //GPB_MFPL_PB6MFP |
<> | 149:156823d33999 | 300 | #define SYS_GPB_MFPL_PB6MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 301 | #define SYS_GPB_MFPL_PB6MFP_I2C2_SCL (0x1UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for I2C2_SCL \hideinitializer */ |
<> | 149:156823d33999 | 302 | #define SYS_GPB_MFPL_PB6MFP_BRAKE01 (0x2UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for BRAKE01 \hideinitializer */ |
<> | 149:156823d33999 | 303 | #define SYS_GPB_MFPL_PB6MFP_UART4_RTS (0x3UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for UART4_RTS \hideinitializer */ |
<> | 149:156823d33999 | 304 | #define SYS_GPB_MFPL_PB6MFP_PWM1_CH4 (0x4UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for PWM1_CH4 \hideinitializer */ |
<> | 149:156823d33999 | 305 | #define SYS_GPB_MFPL_PB6MFP_EPWM1_CH0 (0x5UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_CH0 \hideinitializer */ |
<> | 149:156823d33999 | 306 | #define SYS_GPB_MFPL_PB6MFP_EBI_AD8 (0x7UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_AD8 \hideinitializer */ |
<> | 149:156823d33999 | 307 | |
<> | 149:156823d33999 | 308 | //GPB_MFPL_PB7MFP |
<> | 149:156823d33999 | 309 | #define SYS_GPB_MFPL_PB7MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 310 | #define SYS_GPB_MFPL_PB7MFP_I2C2_SDA (0x1UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for I2C2_SDA \hideinitializer */ |
<> | 149:156823d33999 | 311 | #define SYS_GPB_MFPL_PB7MFP_BRAKE00 (0x2UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for BRAKE00 \hideinitializer */ |
<> | 149:156823d33999 | 312 | #define SYS_GPB_MFPL_PB7MFP_UART4_CTS (0x3UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for UART4_CTS \hideinitializer */ |
<> | 149:156823d33999 | 313 | #define SYS_GPB_MFPL_PB7MFP_PWM1_CH5 (0x4UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for PWM1_CH5 \hideinitializer */ |
<> | 149:156823d33999 | 314 | #define SYS_GPB_MFPL_PB7MFP_EPWM1_CH1 (0x5UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_CH1 \hideinitializer */ |
<> | 149:156823d33999 | 315 | #define SYS_GPB_MFPL_PB7MFP_ETM_TRACE_DATA3 (0x6UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ETM_TRACE_DATA3 \hideinitializer */ |
<> | 149:156823d33999 | 316 | #define SYS_GPB_MFPL_PB7MFP_EBI_AD9 (0x7UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_AD9 \hideinitializer */ |
<> | 149:156823d33999 | 317 | |
<> | 149:156823d33999 | 318 | //GPB_MFPL_PB8MFP |
<> | 149:156823d33999 | 319 | #define SYS_GPB_MFPH_PB8MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 320 | #define SYS_GPB_MFPH_PB8MFP_UART5_CTS (0x1UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART5_CTS \hideinitializer */ |
<> | 149:156823d33999 | 321 | #define SYS_GPB_MFPH_PB8MFP_EPWM1_CH2 (0x5UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EPWM1_CH2 \hideinitializer */ |
<> | 149:156823d33999 | 322 | #define SYS_GPB_MFPH_PB8MFP_ETM_TRACE_DATA2 (0x6UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for ETM_TRACE_DATA2 \hideinitializer */ |
<> | 149:156823d33999 | 323 | #define SYS_GPB_MFPH_PB8MFP_EBI_AD10 (0x7UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EBI_AD10 \hideinitializer */ |
<> | 149:156823d33999 | 324 | |
<> | 149:156823d33999 | 325 | //GPB_MFPH_PB9MFP |
<> | 149:156823d33999 | 326 | #define SYS_GPB_MFPH_PB9MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 327 | #define SYS_GPB_MFPH_PB9MFP_UART5_RTS (0x1UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART5_RTS \hideinitializer */ |
<> | 149:156823d33999 | 328 | #define SYS_GPB_MFPH_PB9MFP_EPWM1_CH3 (0x5UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EPWM1_CH3 \hideinitializer */ |
<> | 149:156823d33999 | 329 | #define SYS_GPB_MFPH_PB9MFP_ETM_TRACE_DATA1 (0x6UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for ETM_TRACE_DATA1 \hideinitializer */ |
<> | 149:156823d33999 | 330 | #define SYS_GPB_MFPH_PB9MFP_EBI_AD11 (0x7UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EBI_AD11 \hideinitializer */ |
<> | 149:156823d33999 | 331 | |
<> | 149:156823d33999 | 332 | //GPB_MFPH_PB10MFP |
<> | 149:156823d33999 | 333 | #define SYS_GPB_MFPH_PB10MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 334 | #define SYS_GPB_MFPH_PB10MFP_UART5_TXD (0x1UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for UART5_TXD \hideinitializer */ |
<> | 149:156823d33999 | 335 | #define SYS_GPB_MFPH_PB10MFP_EPWM1_CH4 (0x5UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for EPWM1_CH4 \hideinitializer */ |
<> | 149:156823d33999 | 336 | #define SYS_GPB_MFPH_PB10MFP_ETM_TRACE_DATA0 (0x6UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for ETM_TRACE_DATA0 \hideinitializer */ |
<> | 149:156823d33999 | 337 | #define SYS_GPB_MFPH_PB10MFP_EBI_AD12 (0x7UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for EBI_AD12 \hideinitializer */ |
<> | 149:156823d33999 | 338 | |
<> | 149:156823d33999 | 339 | //GPB_MFPH_PB11MFP |
<> | 149:156823d33999 | 340 | #define SYS_GPB_MFPH_PB11MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 341 | #define SYS_GPB_MFPH_PB11MFP_UART5_RXD (0x1UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for UART5_RXD \hideinitializer */ |
<> | 149:156823d33999 | 342 | #define SYS_GPB_MFPH_PB11MFP_EPWM1_CH5 (0x5UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for EPWM1_CH5 \hideinitializer */ |
<> | 149:156823d33999 | 343 | #define SYS_GPB_MFPH_PB11MFP_ETM_TRACE_CLK (0x6UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for ETM_TRACE_CLK \hideinitializer */ |
<> | 149:156823d33999 | 344 | #define SYS_GPB_MFPH_PB11MFP_EBI_AD13 (0x7UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for EBI_AD13 \hideinitializer */ |
<> | 149:156823d33999 | 345 | |
<> | 149:156823d33999 | 346 | //GPB_MFPH_PB12MFP |
<> | 149:156823d33999 | 347 | #define SYS_GPB_MFPH_PB12MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 348 | #define SYS_GPB_MFPH_PB12MFP_UART4_RTS (0x1UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for UART4_RTS \hideinitializer */ |
<> | 149:156823d33999 | 349 | #define SYS_GPB_MFPH_PB12MFP_SPI2_MISO1 (0x2UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for _SPI2_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 350 | #define SYS_GPB_MFPH_PB12MFP_CAN0_RXD (0x3UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for CAN0_RXD \hideinitializer */ |
<> | 149:156823d33999 | 351 | #define SYS_GPB_MFPH_PB12MFP_EMAC_MII_MDC (0x6UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for EMAC_MII_MDC \hideinitializer */ |
<> | 149:156823d33999 | 352 | #define SYS_GPB_MFPH_PB12MFP_EBI_AD14 (0x7UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for EBI_AD4 \hideinitializer */ |
<> | 149:156823d33999 | 353 | |
<> | 149:156823d33999 | 354 | //GPB_MFPH_PB13MFP |
<> | 149:156823d33999 | 355 | #define SYS_GPB_MFPH_PB13MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 356 | #define SYS_GPB_MFPH_PB13MFP_UART4_CTS (0x1UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for UART4_CTS \hideinitializer */ |
<> | 149:156823d33999 | 357 | #define SYS_GPB_MFPH_PB13MFP_SPI2_MOSI1 (0x2UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for SPI2_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 358 | #define SYS_GPB_MFPH_PB13MFP_CAN0_TXD (0x3UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for CAN0_TXD \hideinitializer */ |
<> | 149:156823d33999 | 359 | #define SYS_GPB_MFPH_PB13MFP_EMAC_MII_MDIO (0x6UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EMAC_MII_MDIO \hideinitializer */ |
<> | 149:156823d33999 | 360 | #define SYS_GPB_MFPH_PB13MFP_EBI_AD15 (0x7UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EBI_AD15 \hideinitializer */ |
<> | 149:156823d33999 | 361 | |
<> | 149:156823d33999 | 362 | //GPB_MFPH_PB14MFP |
<> | 149:156823d33999 | 363 | #define SYS_GPB_MFPH_PB14MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 364 | #define SYS_GPB_MFPH_PB14MFP_I2S1_MCLK (0x1UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for I2S1_MCLK \hideinitializer */ |
<> | 149:156823d33999 | 365 | #define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x2UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for SC1_RST \hideinitializer */ |
<> | 149:156823d33999 | 366 | #define SYS_GPB_MFPH_PB14MFP_BRAKE01 (0x4UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for BRAKE01 \hideinitializer */ |
<> | 149:156823d33999 | 367 | #define SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC (0x6UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EMAC_MII_MDC \hideinitializer */ |
<> | 149:156823d33999 | 368 | |
<> | 149:156823d33999 | 369 | //GPB_MFPH_PB15MFP |
<> | 149:156823d33999 | 370 | #define SYS_GPB_MFPH_PB15MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 371 | #define SYS_GPB_MFPH_PB15MFP_I2S1_DO (0x1UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for I2S1_DO \hideinitializer */ |
<> | 149:156823d33999 | 372 | #define SYS_GPB_MFPH_PB15MFP_SC1_DAT (0x2UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for SC1_DAT \hideinitializer */ |
<> | 149:156823d33999 | 373 | #define SYS_GPB_MFPH_PB15MFP_BRAKE00 (0x4UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for BRAKE00 \hideinitializer */ |
<> | 149:156823d33999 | 374 | #define SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO (0x6UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for EMAC_MII_MDIO \hideinitializer */ |
<> | 149:156823d33999 | 375 | |
<> | 149:156823d33999 | 376 | |
<> | 149:156823d33999 | 377 | //GPC_MFPL_PC0MFP |
<> | 149:156823d33999 | 378 | #define SYS_GPC_MFPL_PC0MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 379 | #define SYS_GPC_MFPL_PC0MFP_I2S1_DI (0x1UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2S1_D1 \hideinitializer */ |
<> | 149:156823d33999 | 380 | #define SYS_GPC_MFPL_PC0MFP_SC1_DAT (0x2UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SC1_DAT \hideinitializer */ |
<> | 149:156823d33999 | 381 | #define SYS_GPC_MFPL_PC0MFP_UART4_RXD (0x3UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART4_RXD \hideinitializer */ |
<> | 149:156823d33999 | 382 | #define SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK (0x6UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EMAC_REFCLK \hideinitializer */ |
<> | 149:156823d33999 | 383 | #define SYS_GPC_MFPL_PC0MFP_EBI_MCLK (0x7UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_MCLK \hideinitializer */ |
<> | 149:156823d33999 | 384 | #define SYS_GPC_MFPL_PC0MFP_INT2 (0x8UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for INT2 \hideinitializer */ |
<> | 149:156823d33999 | 385 | |
<> | 149:156823d33999 | 386 | |
<> | 149:156823d33999 | 387 | //GPC_MFPL_PC1MFP |
<> | 149:156823d33999 | 388 | #define SYS_GPC_MFPL_PC1MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 389 | #define SYS_GPC_MFPL_PC1MFP_I2S1_BCLK (0x1UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2S1_BCLK \hideinitializer */ |
<> | 149:156823d33999 | 390 | #define SYS_GPC_MFPL_PC1MFP_SC1_CLK (0x2UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SC1_CLK \hideinitializer */ |
<> | 149:156823d33999 | 391 | #define SYS_GPC_MFPL_PC1MFP_UART4_TXD (0x3UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART4_TXD \hideinitializer */ |
<> | 149:156823d33999 | 392 | #define SYS_GPC_MFPL_PC1MFP_TM3_CNT_OUT (0x5UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for TM3_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 393 | #define SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR (0x6UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EMAC_MII_RXERR \hideinitializer */ |
<> | 149:156823d33999 | 394 | #define SYS_GPC_MFPL_PC1MFP_EBI_AD13 (0x7UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD13 \hideinitializer */ |
<> | 149:156823d33999 | 395 | |
<> | 149:156823d33999 | 396 | //GPC_MFPL_PC2MFP |
<> | 149:156823d33999 | 397 | #define SYS_GPC_MFPL_PC2MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 398 | #define SYS_GPC_MFPL_PC2MFP_I2S1_LRCK (0x1UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2S1_LRCK \hideinitializer */ |
<> | 149:156823d33999 | 399 | #define SYS_GPC_MFPL_PC2MFP_SC1_PWR (0x2UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SC1_PWR \hideinitializer */ |
<> | 149:156823d33999 | 400 | #define SYS_GPC_MFPL_PC2MFP_UART4_RTS (0x3UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART4_RTS \hideinitializer */ |
<> | 149:156823d33999 | 401 | #define SYS_GPC_MFPL_PC2MFP_SPI0_SS0 (0x4UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI0_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 402 | #define SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV (0x6UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EMAC_MII_RXDV \hideinitializer */ |
<> | 149:156823d33999 | 403 | #define SYS_GPC_MFPL_PC2MFP_EBI_AD12 (0x7UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD12 \hideinitializer */ |
<> | 149:156823d33999 | 404 | |
<> | 149:156823d33999 | 405 | //GPC_MFPL_PC3MFP |
<> | 149:156823d33999 | 406 | #define SYS_GPC_MFPL_PC3MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 407 | #define SYS_GPC_MFPL_PC3MFP_I2S1_MCLK (0x1UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2S1_MCLK \hideinitializer */ |
<> | 149:156823d33999 | 408 | #define SYS_GPC_MFPL_PC3MFP_SC1_CD (0x2UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SC1_CD \hideinitializer */ |
<> | 149:156823d33999 | 409 | #define SYS_GPC_MFPL_PC3MFP_UART4_CTS (0x3UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART4_CTS \hideinitializer */ |
<> | 149:156823d33999 | 410 | #define SYS_GPC_MFPL_PC3MFP_SPI0_MISO1 (0x4UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI0_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 411 | #define SYS_GPC_MFPL_PC3MFP_QEI0_Z (0x5UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for QEI0_Z \hideinitializer */ |
<> | 149:156823d33999 | 412 | #define SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 (0x6UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EMAC_MII_RXD1 \hideinitializer */ |
<> | 149:156823d33999 | 413 | #define SYS_GPC_MFPL_PC3MFP_EBI_AD11 (0x7UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD11 \hideinitializer */ |
<> | 149:156823d33999 | 414 | #define SYS_GPC_MFPL_PC3MFP_ECAP0_IC2 (0x8UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for ECAP0_IC2 \hideinitializer */ |
<> | 149:156823d33999 | 415 | |
<> | 149:156823d33999 | 416 | //GPC_MFPL_PC4MFP |
<> | 149:156823d33999 | 417 | #define SYS_GPC_MFPL_PC4MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 418 | #define SYS_GPC_MFPL_PC4MFP_I2S1_DO (0x1UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2S1_DO \hideinitializer */ |
<> | 149:156823d33999 | 419 | #define SYS_GPC_MFPL_PC4MFP_SC1_RST (0x2UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SC1_RST \hideinitializer */ |
<> | 149:156823d33999 | 420 | #define SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1 (0x4UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI0_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 421 | #define SYS_GPC_MFPL_PC4MFP_QEI0_B (0x5UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for QEI0_B \hideinitializer */ |
<> | 149:156823d33999 | 422 | #define SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 (0x6UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EMAC_MII_RXD0 \hideinitializer */ |
<> | 149:156823d33999 | 423 | #define SYS_GPC_MFPL_PC4MFP_EBI_AD10 (0x7UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD10 \hideinitializer */ |
<> | 149:156823d33999 | 424 | #define SYS_GPC_MFPL_PC4MFP_ECAP0_IC1 (0x8UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for ECAP0_IC1 \hideinitializer */ |
<> | 149:156823d33999 | 425 | |
<> | 149:156823d33999 | 426 | //GPC_MFPL_PC5MFP |
<> | 149:156823d33999 | 427 | #define SYS_GPC_MFPL_PC5MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 428 | #define SYS_GPC_MFPL_PC5MFP_CLK_O (0x1UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for CLK_O \hideinitializer */ |
<> | 149:156823d33999 | 429 | #define SYS_GPC_MFPL_PC5MFP_QEI0_A (0x5UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for QEI0_A \hideinitializer */ |
<> | 149:156823d33999 | 430 | #define SYS_GPC_MFPL_PC5MFP_EMAC_MII_RXCLK (0x6UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EMAC_MII_RXCLK \hideinitializer */ |
<> | 149:156823d33999 | 431 | #define SYS_GPC_MFPL_PC5MFP_EBI_MCLK (0x7UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_MCLK \hideinitializer */ |
<> | 149:156823d33999 | 432 | #define SYS_GPC_MFPL_PC5MFP_ECAP0_IC0 (0x8UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for ECAP0_IC0 \hideinitializer */ |
<> | 149:156823d33999 | 433 | |
<> | 149:156823d33999 | 434 | //GPC_MFPL_PC6MFP |
<> | 149:156823d33999 | 435 | #define SYS_GPC_MFPL_PC6MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 436 | #define SYS_GPC_MFPL_PC6MFP_TM2_EXT (0x1UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM2_EXT \hideinitializer */ |
<> | 149:156823d33999 | 437 | #define SYS_GPC_MFPL_PC6MFP_SPI0_MISO0 (0x4UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SPI0_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 438 | #define SYS_GPC_MFPL_PC6MFP_TM2_CNT_OUT (0x5UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM2_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 439 | #define SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 (0x6UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EMAC_MII_TXD0 \hideinitializer */ |
<> | 149:156823d33999 | 440 | #define SYS_GPC_MFPL_PC6MFP_EBI_AD9 (0x7UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD9 \hideinitializer */ |
<> | 149:156823d33999 | 441 | |
<> | 149:156823d33999 | 442 | //GPC_MFPL_PC7MFP |
<> | 149:156823d33999 | 443 | #define SYS_GPC_MFPL_PC7MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 444 | #define SYS_GPC_MFPL_PC7MFP_TM1_EXT (0x1UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for TM1_EXT \hideinitializer */ |
<> | 149:156823d33999 | 445 | #define SYS_GPC_MFPL_PC7MFP_SPI0_MOSI0 (0x4UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SPI0_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 446 | #define SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1 (0x6UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EMAC_MII_TXD1 \hideinitializer */ |
<> | 149:156823d33999 | 447 | #define SYS_GPC_MFPL_PC7MFP_EBI_AD8 (0x7UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD8 \hideinitializer */ |
<> | 149:156823d33999 | 448 | |
<> | 149:156823d33999 | 449 | //GPC_MFPL_PC8MFP |
<> | 149:156823d33999 | 450 | #define SYS_GPC_MFPH_PC8MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 451 | #define SYS_GPC_MFPH_PC8MFP_TM0_EXT (0x1UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for TM0_EXT \hideinitializer */ |
<> | 149:156823d33999 | 452 | #define SYS_GPC_MFPH_PC8MFP_SPI0_CLK (0x4UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for SPI0_CLK \hideinitializer */ |
<> | 149:156823d33999 | 453 | #define SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN (0x6UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EMAC_MII_TXEN \hideinitializer */ |
<> | 149:156823d33999 | 454 | |
<> | 149:156823d33999 | 455 | //GPC_MFPH_PC9MFP |
<> | 149:156823d33999 | 456 | #define SYS_GPC_MFPH_PC9MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 457 | #define SYS_GPC_MFPH_PC9MFP_STADC (0x1UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for STADC \hideinitializer */ |
<> | 149:156823d33999 | 458 | #define SYS_GPC_MFPH_PC9MFP_UART2_CTS (0x2UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for UART2_CTS \hideinitializer */ |
<> | 149:156823d33999 | 459 | #define SYS_GPC_MFPH_PC9MFP_SC3_RST (0x3UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SC3_RST \hideinitializer */ |
<> | 149:156823d33999 | 460 | #define SYS_GPC_MFPH_PC9MFP_I2C0_SDA (0x4UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for I2C0_SDA \hideinitializer */ |
<> | 149:156823d33999 | 461 | #define SYS_GPC_MFPH_PC9MFP_CAP_DATA1 (0x5UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for CAP_DATA1 \hideinitializer */ |
<> | 149:156823d33999 | 462 | #define SYS_GPC_MFPH_PC9MFP_I2C3_SCL (0x6UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for I2C3_SCL \hideinitializer */ |
<> | 149:156823d33999 | 463 | #define SYS_GPC_MFPH_PC9MFP_EBI_A22 (0x7UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_A22 \hideinitializer */ |
<> | 149:156823d33999 | 464 | #define SYS_GPC_MFPH_PC9MFP_SD1_DAT0 (0x8UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SD1_DAT0 \hideinitializer */ |
<> | 149:156823d33999 | 465 | #define SYS_GPC_MFPH_PC9MFP_EBI_A6 (0x9UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_A6 \hideinitializer */ |
<> | 149:156823d33999 | 466 | //GPC_MFPH_PC10MFP |
<> | 149:156823d33999 | 467 | #define SYS_GPC_MFPH_PC10MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 468 | #define SYS_GPC_MFPH_PC10MFP_SC3_CD (0x1UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for SC3_CD \hideinitializer */ |
<> | 149:156823d33999 | 469 | #define SYS_GPC_MFPH_PC10MFP_UART2_RXD (0x2UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for UART2_RXD \hideinitializer */ |
<> | 149:156823d33999 | 470 | #define SYS_GPC_MFPH_PC10MFP_PWM0_CH2 (0x4UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for PWM0_CH2 \hideinitializer */ |
<> | 149:156823d33999 | 471 | #define SYS_GPC_MFPH_PC10MFP_EBI_A23 (0x6UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for EBI_A23 \hideinitializer */ |
<> | 149:156823d33999 | 472 | #define SYS_GPC_MFPH_PC10MFP_EBI_AD2 (0x7UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for EBI_AD2 \hideinitializer */ |
<> | 149:156823d33999 | 473 | |
<> | 149:156823d33999 | 474 | //GPC_MFPH_PC11MFP |
<> | 149:156823d33999 | 475 | #define SYS_GPC_MFPH_PC11MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 476 | #define SYS_GPC_MFPH_PC11MFP_UART2_TXD (0x2UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for UART2_TXD \hideinitializer */ |
<> | 149:156823d33999 | 477 | #define SYS_GPC_MFPH_PC11MFP_PWM0_CH3 (0x4UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for PWM0_CH3 \hideinitializer */ |
<> | 149:156823d33999 | 478 | #define SYS_GPC_MFPH_PC11MFP_EBI_A24 (0x6UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for EBI_A24 \hideinitializer */ |
<> | 149:156823d33999 | 479 | #define SYS_GPC_MFPH_PC11MFP_EBI_AD3 (0x7UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for EBI_AD3 \hideinitializer */ |
<> | 149:156823d33999 | 480 | |
<> | 149:156823d33999 | 481 | //GPC_MFPH_PC12MFP |
<> | 149:156823d33999 | 482 | #define SYS_GPC_MFPH_PC12MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 483 | #define SYS_GPC_MFPH_PC12MFP_SPI1_SS0 (0x1UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SPI1_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 484 | #define SYS_GPC_MFPH_PC12MFP_SC4_CD (0x2UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SC4_CD \hideinitializer */ |
<> | 149:156823d33999 | 485 | #define SYS_GPC_MFPH_PC12MFP_SD1_CDn (0x4UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SD1_CDn \hideinitializer */ |
<> | 149:156823d33999 | 486 | #define SYS_GPC_MFPH_PC12MFP_CAP_DATA7 (0x5UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for CAP_DATA7 \hideinitializer */ |
<> | 149:156823d33999 | 487 | #define SYS_GPC_MFPH_PC12MFP_ETM_TRACE_DATA3 (0x6UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for ETM_TRACE_DATA3 \hideinitializer */ |
<> | 149:156823d33999 | 488 | #define SYS_GPC_MFPH_PC12MFP_EBI_A0 (0x7UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for MFP_EBI_A0 \hideinitializer */ |
<> | 149:156823d33999 | 489 | |
<> | 149:156823d33999 | 490 | //GPC_MFPH_PC13MFP |
<> | 149:156823d33999 | 491 | #define SYS_GPC_MFPH_PC13MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 492 | #define SYS_GPC_MFPH_PC13MFP_SPI1_MOSI1 (0x1UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SPI1_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 493 | #define SYS_GPC_MFPH_PC13MFP_SC4_RST (0x2UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SC4_RST \hideinitializer */ |
<> | 149:156823d33999 | 494 | #define SYS_GPC_MFPH_PC13MFP_SD1_CMD (0x4UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SD1_CMD \hideinitializer */ |
<> | 149:156823d33999 | 495 | #define SYS_GPC_MFPH_PC13MFP_CAP_DATA6 (0x5UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for CAP_DATA6 \hideinitializer */ |
<> | 149:156823d33999 | 496 | #define SYS_GPC_MFPH_PC13MFP_ETM_TRACE_DATA2 (0x6UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for ETM_TRACE_DATA2 \hideinitializer */ |
<> | 149:156823d33999 | 497 | #define SYS_GPC_MFPH_PC13MFP_EBI_A1 (0x7UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for EBI_A1 \hideinitializer */ |
<> | 149:156823d33999 | 498 | |
<> | 149:156823d33999 | 499 | //GPC_MFPH_PC14MFP |
<> | 149:156823d33999 | 500 | #define SYS_GPC_MFPH_PC14MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 501 | #define SYS_GPC_MFPH_PC14MFP_SPI1_MISO1 (0x1UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for SPI1_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 502 | #define SYS_GPC_MFPH_PC14MFP_SC4_PWR (0x2UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for SC4_PWR \hideinitializer */ |
<> | 149:156823d33999 | 503 | #define SYS_GPC_MFPH_PC14MFP_TM3_EXT (0x3UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for TM3_EXT \hideinitializer */ |
<> | 149:156823d33999 | 504 | #define SYS_GPC_MFPH_PC14MFP_SD1_CLK (0x4UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for SD1_CLK \hideinitializer */ |
<> | 149:156823d33999 | 505 | #define SYS_GPC_MFPH_PC14MFP_CAP_DATA5 (0x5UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for CAP_DATA5 \hideinitializer */ |
<> | 149:156823d33999 | 506 | #define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_DATA1 (0x6UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for ETM_TRACE_DATA1 \hideinitializer */ |
<> | 149:156823d33999 | 507 | #define SYS_GPC_MFPH_PC14MFP_EBI_A2 (0x7UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for EBI_A2 \hideinitializer */ |
<> | 149:156823d33999 | 508 | |
<> | 149:156823d33999 | 509 | //GPC_MFPH_PC15MFP |
<> | 149:156823d33999 | 510 | #define SYS_GPC_MFPH_PC15MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 511 | #define SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0 (0x1UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for SPI1_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 512 | #define SYS_GPC_MFPH_PC15MFP_SC4_DAT (0x2UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for SC4_DAT \hideinitializer */ |
<> | 149:156823d33999 | 513 | #define SYS_GPC_MFPH_PC15MFP_SD1_DAT3 (0x4UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for SD1_DAT3 \hideinitializer */ |
<> | 149:156823d33999 | 514 | #define SYS_GPC_MFPH_PC15MFP_CAP_DATA4 (0x5UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for CAP_DATA4 \hideinitializer */ |
<> | 149:156823d33999 | 515 | #define SYS_GPC_MFPH_PC15MFP_ETM_TRACE_DATA0 (0x6UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for ETM_TRACE_DATA0 \hideinitializer */ |
<> | 149:156823d33999 | 516 | #define SYS_GPC_MFPH_PC15MFP_EBI_A3 (0x7UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for EBI_A3 \hideinitializer */ |
<> | 149:156823d33999 | 517 | |
<> | 149:156823d33999 | 518 | //GPD_MFPL_PD0MFP |
<> | 149:156823d33999 | 519 | #define SYS_GPD_MFPL_PD0MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 520 | #define SYS_GPD_MFPL_PD0MFP_SPI1_MISO0 (0x1UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI1_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 521 | #define SYS_GPD_MFPL_PD0MFP_SC4_CLK (0x2UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SC4_CLK \hideinitializer */ |
<> | 149:156823d33999 | 522 | #define SYS_GPD_MFPL_PD0MFP_SD1_DAT2 (0x4UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SD1_DAT2 \hideinitializer */ |
<> | 149:156823d33999 | 523 | #define SYS_GPD_MFPL_PD0MFP_CAP_DATA3 (0x5UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for CAP_DATA3 \hideinitializer */ |
<> | 149:156823d33999 | 524 | #define SYS_GPD_MFPL_PD0MFP_ETM_TRACE_CLK (0x6UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for ETM_TRACE_CLK \hideinitializer */ |
<> | 149:156823d33999 | 525 | #define SYS_GPD_MFPL_PD0MFP_EBI_A4 (0x7UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EBI_A4 \hideinitializer */ |
<> | 149:156823d33999 | 526 | #define SYS_GPD_MFPL_PD0MFP_INT3 (0x8UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for INT3 \hideinitializer */ |
<> | 149:156823d33999 | 527 | |
<> | 149:156823d33999 | 528 | //GPD_MFPL_PD1MFP |
<> | 149:156823d33999 | 529 | #define SYS_GPD_MFPL_PD1MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 530 | #define SYS_GPD_MFPL_PD1MFP_SPI1_CLK (0x1UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SPI1_CLK \hideinitializer */ |
<> | 149:156823d33999 | 531 | #define SYS_GPD_MFPL_PD1MFP_TM0_CNT_OUT (0x3UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for TM0_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 532 | #define SYS_GPD_MFPL_PD1MFP_SD1_DAT1 (0x4UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SD1_DAT1 \hideinitializer */ |
<> | 149:156823d33999 | 533 | #define SYS_GPD_MFPL_PD1MFP_CAP_DATA2 (0x5UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for CAP_DATA2 \hideinitializer */ |
<> | 149:156823d33999 | 534 | #define SYS_GPD_MFPL_PD1MFP_EBI_A5 (0x7UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_A5 \hideinitializer */ |
<> | 149:156823d33999 | 535 | |
<> | 149:156823d33999 | 536 | //GPD_MFPL_PD2MFP |
<> | 149:156823d33999 | 537 | #define SYS_GPD_MFPL_PD2MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 538 | #define SYS_GPD_MFPL_PD2MFP_STADC (0x1UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for STADC \hideinitializer */ |
<> | 149:156823d33999 | 539 | #define SYS_GPD_MFPL_PD2MFP_I2C3_SCL (0x2UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for I2C3_SCL \hideinitializer */ |
<> | 149:156823d33999 | 540 | #define SYS_GPD_MFPL_PD2MFP_SD1_DAT0 (0x4UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SD1_DAT0 \hideinitializer */ |
<> | 149:156823d33999 | 541 | #define SYS_GPD_MFPL_PD2MFP_CAP_DATA1 (0x5UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for CAP_DATA1 \hideinitializer */ |
<> | 149:156823d33999 | 542 | #define SYS_GPD_MFPL_PD2MFP_EBI_A6 (0x7UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_A6 \hideinitializer */ |
<> | 149:156823d33999 | 543 | |
<> | 149:156823d33999 | 544 | //GPD_MFPL_PD3MFP |
<> | 149:156823d33999 | 545 | #define SYS_GPD_MFPL_PD3MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 546 | #define SYS_GPD_MFPL_PD3MFP_SC5_CLK (0x1UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC5_CLK \hideinitializer */ |
<> | 149:156823d33999 | 547 | #define SYS_GPD_MFPL_PD3MFP_I2C3_SDA (0x2UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for I2C3_SDA \hideinitializer */ |
<> | 149:156823d33999 | 548 | #define SYS_GPD_MFPL_PD3MFP_ACMP2_O (0x3UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for ACMP2_O \hideinitializer */ |
<> | 149:156823d33999 | 549 | #define SYS_GPD_MFPL_PD3MFP_SD0_CDn (0x4UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SD0_CDn \hideinitializer */ |
<> | 149:156823d33999 | 550 | #define SYS_GPD_MFPL_PD3MFP_CAP_DATA0 (0x5UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for CAP_DATA0 \hideinitializer */ |
<> | 149:156823d33999 | 551 | #define SYS_GPD_MFPL_PD3MFP_JTAG_TDO (0x6UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for JTAG_TDO \hideinitializer */ |
<> | 149:156823d33999 | 552 | #define SYS_GPD_MFPL_PD3MFP_EBI_A7 (0x7UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_A7 \hideinitializer */ |
<> | 149:156823d33999 | 553 | |
<> | 149:156823d33999 | 554 | //GPD_MFPL_PD4MFP |
<> | 149:156823d33999 | 555 | #define SYS_GPD_MFPL_PD4MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 556 | #define SYS_GPD_MFPL_PD4MFP_SC5_CD (0x1UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SC5_CD \hideinitializer */ |
<> | 149:156823d33999 | 557 | #define SYS_GPD_MFPL_PD4MFP_UART3_RXD (0x2UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for UART3_RXD \hideinitializer */ |
<> | 149:156823d33999 | 558 | #define SYS_GPD_MFPL_PD4MFP_ACMP1_O (0x3UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for ACMP1_O \hideinitializer */ |
<> | 149:156823d33999 | 559 | #define SYS_GPD_MFPL_PD4MFP_CAP_SCLK (0x5UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for CAP_SCLK \hideinitializer */ |
<> | 149:156823d33999 | 560 | #define SYS_GPD_MFPL_PD4MFP_JTAG_TDI (0x6UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for JTAG_TDI \hideinitializer */ |
<> | 149:156823d33999 | 561 | #define SYS_GPD_MFPL_PD4MFP_EBI_A8 (0x7UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for EBI_A8 \hideinitializer */ |
<> | 149:156823d33999 | 562 | |
<> | 149:156823d33999 | 563 | //GPD_MFPL_PD5MFP |
<> | 149:156823d33999 | 564 | #define SYS_GPD_MFPL_PD5MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 565 | #define SYS_GPD_MFPL_PD5MFP_SC5_RST (0x1UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SC5_RST \hideinitializer */ |
<> | 149:156823d33999 | 566 | #define SYS_GPD_MFPL_PD5MFP_UART3_TXD (0x2UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for UART3_TXD \hideinitializer */ |
<> | 149:156823d33999 | 567 | #define SYS_GPD_MFPL_PD5MFP_CAP_VSYNC (0x5UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for CAP_VSYNC \hideinitializer */ |
<> | 149:156823d33999 | 568 | #define SYS_GPD_MFPL_PD5MFP_JTAG_nTRST (0x6UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for JTAG_nTRST \hideinitializer */ |
<> | 149:156823d33999 | 569 | #define SYS_GPD_MFPL_PD5MFP_EBI_A9 (0x7UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for EBI_A9 \hideinitializer */ |
<> | 149:156823d33999 | 570 | |
<> | 149:156823d33999 | 571 | //GPD_MFPL_PD6MFP |
<> | 149:156823d33999 | 572 | #define SYS_GPD_MFPL_PD6MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 573 | #define SYS_GPD_MFPL_PD6MFP_SC5_PWR (0x1UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SC5_PWR \hideinitializer */ |
<> | 149:156823d33999 | 574 | #define SYS_GPD_MFPL_PD6MFP_UART3_RTS (0x2UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART3_RTS \hideinitializer */ |
<> | 149:156823d33999 | 575 | #define SYS_GPD_MFPL_PD6MFP_SD0_CMD (0x4UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SD0_CMD \hideinitializer */ |
<> | 149:156823d33999 | 576 | #define SYS_GPD_MFPL_PD6MFP_CAP_HSYNC (0x5UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for CAP_HSYNC \hideinitializer */ |
<> | 149:156823d33999 | 577 | #define SYS_GPD_MFPL_PD6MFP_EBI_A10 (0x7UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for EBI_A10 \hideinitializer */ |
<> | 149:156823d33999 | 578 | |
<> | 149:156823d33999 | 579 | //GPD_MFPL_PD7MFP |
<> | 149:156823d33999 | 580 | #define SYS_GPD_MFPL_PD7MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 581 | #define SYS_GPD_MFPL_PD7MFP_SC5_DAT (0x1UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SC5_DAT \hideinitializer */ |
<> | 149:156823d33999 | 582 | #define SYS_GPD_MFPL_PD7MFP_UART3_CTS (0x2UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for UART3_CTS \hideinitializer */ |
<> | 149:156823d33999 | 583 | #define SYS_GPD_MFPL_PD7MFP_SD0_CLK (0x4UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SD0_CLK \hideinitializer */ |
<> | 149:156823d33999 | 584 | #define SYS_GPD_MFPL_PD7MFP_CAP_PIXCLK (0x5UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for CAP_PIXCLK \hideinitializer */ |
<> | 149:156823d33999 | 585 | #define SYS_GPD_MFPL_PD7MFP_EBI_A11 (0x7UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for EBI_A11 \hideinitializer */ |
<> | 149:156823d33999 | 586 | |
<> | 149:156823d33999 | 587 | //GPD_MFPL_PD8MFP |
<> | 149:156823d33999 | 588 | #define SYS_GPD_MFPH_PD8MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 589 | #define SYS_GPD_MFPH_PD8MFP_SPI3_MISO1 (0x1UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for SPI3_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 590 | #define SYS_GPD_MFPH_PD8MFP_I2C0_SCL (0x2UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for I2C0_SCL \hideinitializer */ |
<> | 149:156823d33999 | 591 | |
<> | 149:156823d33999 | 592 | //GPD_MFPH_PD9MFP |
<> | 149:156823d33999 | 593 | #define SYS_GPD_MFPH_PD9MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 594 | #define SYS_GPD_MFPH_PD9MFP_SPI3_MOSI1 (0x1UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for SPI3_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 595 | #define SYS_GPD_MFPH_PD9MFP_I2C0_SDA (0x2UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for I2C0_SDA \hideinitializer */ |
<> | 149:156823d33999 | 596 | |
<> | 149:156823d33999 | 597 | //GPD_MFPH_PD10MFP |
<> | 149:156823d33999 | 598 | #define SYS_GPD_MFPH_PD10MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 599 | #define SYS_GPD_MFPH_PD10MFP_SC3_DAT (0x1UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for SC3_DAT \hideinitializer */ |
<> | 149:156823d33999 | 600 | #define SYS_GPD_MFPH_PD10MFP_I2C4_SCL (0x2UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for I2C4_SCL \hideinitializer */ |
<> | 149:156823d33999 | 601 | |
<> | 149:156823d33999 | 602 | //GPD_MFPH_PD11MFP |
<> | 149:156823d33999 | 603 | #define SYS_GPD_MFPH_PD11MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 604 | #define SYS_GPD_MFPH_PD11MFP_SC3_RST (0x1UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for SC3_RST \hideinitializer */ |
<> | 149:156823d33999 | 605 | #define SYS_GPD_MFPH_PD11MFP_TM3_CNT_OUT (0x3UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for TM3_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 606 | |
<> | 149:156823d33999 | 607 | //GPD_MFPH_PD12MFP |
<> | 149:156823d33999 | 608 | #define SYS_GPD_MFPH_PD12MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 609 | #define SYS_GPD_MFPH_PD12MFP_SC3_CLK (0x1UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for SC3_CLK \hideinitializer */ |
<> | 149:156823d33999 | 610 | #define SYS_GPD_MFPH_PD12MFP_I2C4_SDA (0x2UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for I2C4_SDA \hideinitializer */ |
<> | 149:156823d33999 | 611 | |
<> | 149:156823d33999 | 612 | //GPD_MFPH_PD13MFP |
<> | 149:156823d33999 | 613 | #define SYS_GPD_MFPH_PD13MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 614 | #define SYS_GPD_MFPH_PD13MFP_SPI1_SS0 (0x1UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for SPI1_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 615 | #define SYS_GPD_MFPH_PD13MFP_UART5_CTS (0x2UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for UART5_CTS \hideinitializer */ |
<> | 149:156823d33999 | 616 | #define SYS_GPD_MFPH_PD13MFP_ECAP0_IC2 (0x3UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for ECAP0_IC2 \hideinitializer */ |
<> | 149:156823d33999 | 617 | |
<> | 149:156823d33999 | 618 | //GPD_MFPH_PD14MFP |
<> | 149:156823d33999 | 619 | #define SYS_GPD_MFPH_PD14MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 620 | #define SYS_GPD_MFPH_PD14MFP_SPI1_CLK (0x1UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for SPI1_CLK \hideinitializer */ |
<> | 149:156823d33999 | 621 | #define SYS_GPD_MFPH_PD14MFP_UART5_RTS (0x2UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for UART5_RTS \hideinitializer */ |
<> | 149:156823d33999 | 622 | #define SYS_GPD_MFPH_PD14MFP_ECAP0_IC1 (0x3UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for ECAP0_IC1 \hideinitializer */ |
<> | 149:156823d33999 | 623 | |
<> | 149:156823d33999 | 624 | //GPD_MFPH_PD15MFP |
<> | 149:156823d33999 | 625 | #define SYS_GPD_MFPH_PD15MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 626 | #define SYS_GPD_MFPH_PD15MFP_SPI1_MISO0 (0x1UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for SPI1_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 627 | #define SYS_GPD_MFPH_PD15MFP_UART5_TXD (0x2UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for UART5_TXD \hideinitializer */ |
<> | 149:156823d33999 | 628 | #define SYS_GPD_MFPH_PD15MFP_ECAP0_IC0 (0x3UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for ECAP0_IC0 \hideinitializer */ |
<> | 149:156823d33999 | 629 | |
<> | 149:156823d33999 | 630 | //GPE_MFPL_PE0MFP |
<> | 149:156823d33999 | 631 | #define SYS_GPE_MFPL_PE0MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 632 | #define SYS_GPE_MFPL_PE0MFP_ADC0_0 (0x1UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for ADC0_0 \hideinitializer */ |
<> | 149:156823d33999 | 633 | #define SYS_GPE_MFPL_PE0MFP_INT4 (0x8UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for INT4 \hideinitializer */ |
<> | 149:156823d33999 | 634 | |
<> | 149:156823d33999 | 635 | //GPE_MFPL_PE1MFP |
<> | 149:156823d33999 | 636 | #define SYS_GPE_MFPL_PE1MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 637 | #define SYS_GPE_MFPL_PE1MFP_ADC0_1 (0x1UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for ADC0_1 \hideinitializer */ |
<> | 149:156823d33999 | 638 | #define SYS_GPE_MFPL_PE1MFP_TM2_CNT_OUT (0x3UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for TM2_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 639 | |
<> | 149:156823d33999 | 640 | //GPE_MFPL_PE2MFP |
<> | 149:156823d33999 | 641 | #define SYS_GPE_MFPL_PE2MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 642 | #define SYS_GPE_MFPL_PE2MFP_ADC0_2 (0x1UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for ADC0_2 \hideinitializer */ |
<> | 149:156823d33999 | 643 | #define SYS_GPE_MFPL_PE2MFP_ACMP0_O (0x2UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for ACMP0_O \hideinitializer */ |
<> | 149:156823d33999 | 644 | #define SYS_GPE_MFPL_PE2MFP_SPI0_MISO0 (0x3UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI0_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 645 | |
<> | 149:156823d33999 | 646 | //GPE_MFPL_PE3MFP |
<> | 149:156823d33999 | 647 | #define SYS_GPE_MFPL_PE3MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 648 | #define SYS_GPE_MFPL_PE3MFP_ADC0_3 (0x1UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for ADC0_3 \hideinitializer */ |
<> | 149:156823d33999 | 649 | #define SYS_GPE_MFPL_PE3MFP_ACMP0_P3 (0x2UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for ACMP0_P3 \hideinitializer */ |
<> | 149:156823d33999 | 650 | #define SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0 (0x3UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI0_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 651 | |
<> | 149:156823d33999 | 652 | //GPE_MFPL_PE4MFP |
<> | 149:156823d33999 | 653 | #define SYS_GPE_MFPL_PE4MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 654 | #define SYS_GPE_MFPL_PE4MFP_ADC0_4 (0x1UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for ADC0_4 \hideinitializer */ |
<> | 149:156823d33999 | 655 | #define SYS_GPE_MFPL_PE4MFP_ACMP0_P2 (0x2UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for ACMP0_P2 \hideinitializer */ |
<> | 149:156823d33999 | 656 | #define SYS_GPE_MFPL_PE4MFP_SPI0_SS0 (0x3UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI0_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 657 | |
<> | 149:156823d33999 | 658 | //GPE_MFPL_PE5MFP |
<> | 149:156823d33999 | 659 | #define SYS_GPE_MFPL_PE5MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 660 | #define SYS_GPE_MFPL_PE5MFP_ADC0_5 (0x1UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for ADC0_5 \hideinitializer */ |
<> | 149:156823d33999 | 661 | #define SYS_GPE_MFPL_PE5MFP_ACMP0_P1 (0x2UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for ACMP0_P1 \hideinitializer */ |
<> | 149:156823d33999 | 662 | #define SYS_GPE_MFPL_PE5MFP_SPI0_CLK (0x3UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI0_CLK \hideinitializer */ |
<> | 149:156823d33999 | 663 | #define SYS_GPE_MFPL_PE5MFP_SD0_CDn (0x4UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SD0_CDn \hideinitializer */ |
<> | 149:156823d33999 | 664 | |
<> | 149:156823d33999 | 665 | //GPE_MFPL_PE6MFP |
<> | 149:156823d33999 | 666 | #define SYS_GPE_MFPL_PE6MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 667 | #define SYS_GPE_MFPL_PE6MFP_ADC0_6 (0x1UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for ADC0_6 \hideinitializer */ |
<> | 149:156823d33999 | 668 | #define SYS_GPE_MFPL_PE6MFP_ACMP0_P0 (0x2UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for ACMP0_P0 \hideinitializer */ |
<> | 149:156823d33999 | 669 | #define SYS_GPE_MFPL_PE6MFP_SPI0_MISO0 (0x3UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SPI0_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 670 | #define SYS_GPE_MFPL_PE6MFP_SD0_CMD (0x4UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SD0_CMD \hideinitializer */ |
<> | 149:156823d33999 | 671 | #define SYS_GPE_MFPL_PE6MFP_EBI_nWR (0x7UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for EBI_nWR \hideinitializer */ |
<> | 149:156823d33999 | 672 | |
<> | 149:156823d33999 | 673 | //GPE_MFPL_PE7MFP |
<> | 149:156823d33999 | 674 | #define SYS_GPE_MFPL_PE7MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 675 | #define SYS_GPE_MFPL_PE7MFP_ADC0_7 (0x1UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for ADC0_7 \hideinitializer */ |
<> | 149:156823d33999 | 676 | #define SYS_GPE_MFPL_PE7MFP_ACMP0_N (0x2UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for ACMP0_N \hideinitializer */ |
<> | 149:156823d33999 | 677 | #define SYS_GPE_MFPL_PE7MFP_SPI0_MOSI0 (0x3UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SPI0_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 678 | #define SYS_GPE_MFPL_PE7MFP_SD0_CLK (0x4UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SD0_CLK \hideinitializer */ |
<> | 149:156823d33999 | 679 | #define SYS_GPE_MFPL_PE7MFP_EBI_nRD (0x7UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for _EBI_nRD \hideinitializer */ |
<> | 149:156823d33999 | 680 | |
<> | 149:156823d33999 | 681 | //GPE_MFPL_PE8MFP |
<> | 149:156823d33999 | 682 | #define SYS_GPE_MFPH_PE8MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 683 | #define SYS_GPE_MFPH_PE8MFP_ADC0_8 (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ADC0_8 \hideinitializer */ |
<> | 149:156823d33999 | 684 | #define SYS_GPE_MFPH_PE8MFP_ADC1_0 (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ADC1_0 \hideinitializer */ |
<> | 149:156823d33999 | 685 | #define SYS_GPE_MFPH_PE8MFP_ACMP1_N (0x2UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ACMP1_N \hideinitializer */ |
<> | 149:156823d33999 | 686 | #define SYS_GPE_MFPH_PE8MFP_TM1_CNT_OUT (0x3UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for TM1_CNT_OUT \hideinitializer */ |
<> | 149:156823d33999 | 687 | #define SYS_GPE_MFPH_PE8MFP_SD0_DAT3 (0x4UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SD0_DAT3 \hideinitializer */ |
<> | 149:156823d33999 | 688 | #define SYS_GPE_MFPH_PE8MFP_EBI_ALE (0x7UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EBI_ALE \hideinitializer */ |
<> | 149:156823d33999 | 689 | |
<> | 149:156823d33999 | 690 | //GPE_MFPH_PE9MFP |
<> | 149:156823d33999 | 691 | #define SYS_GPE_MFPH_PE9MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 692 | #define SYS_GPE_MFPH_PE9MFP_ADC0_9 (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ADC0_9 \hideinitializer */ |
<> | 149:156823d33999 | 693 | #define SYS_GPE_MFPH_PE9MFP_ADC1_1 (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ADC1_1 \hideinitializer */ |
<> | 149:156823d33999 | 694 | #define SYS_GPE_MFPH_PE9MFP_ACMP1_P0 (0x2UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ACMP1_P0 \hideinitializer */ |
<> | 149:156823d33999 | 695 | #define SYS_GPE_MFPH_PE9MFP_SD0_DAT2 (0x4UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SD0_DAT2 \hideinitializer */ |
<> | 149:156823d33999 | 696 | #define SYS_GPE_MFPH_PE9MFP_EBI_nWRH (0x7UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EBI_nWRH \hideinitializer */ |
<> | 149:156823d33999 | 697 | |
<> | 149:156823d33999 | 698 | //GPE_MFPH_PE10MFP |
<> | 149:156823d33999 | 699 | #define SYS_GPE_MFPH_PE10MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 700 | #define SYS_GPE_MFPH_PE10MFP_ADC0_10 (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for ADC0_10 \hideinitializer */ |
<> | 149:156823d33999 | 701 | #define SYS_GPE_MFPH_PE10MFP_ADC1_2 (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for ADC1_2 \hideinitializer */ |
<> | 149:156823d33999 | 702 | #define SYS_GPE_MFPH_PE10MFP_ACMP1_P1 (0x2UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for ACMP1_P1 \hideinitializer */ |
<> | 149:156823d33999 | 703 | #define SYS_GPE_MFPH_PE10MFP_SPI0_MISO1 (0x3UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI0_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 704 | #define SYS_GPE_MFPH_PE10MFP_SD0_DAT1 (0x4UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SD0_DAT1 \hideinitializer */ |
<> | 149:156823d33999 | 705 | #define SYS_GPE_MFPH_PE10MFP_EBI_nWRL (0x7UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for EBI_nWRL \hideinitializer */ |
<> | 149:156823d33999 | 706 | |
<> | 149:156823d33999 | 707 | //GPE_MFPH_PE11MFP |
<> | 149:156823d33999 | 708 | #define SYS_GPE_MFPH_PE11MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 709 | #define SYS_GPE_MFPH_PE11MFP_ADC0_11 (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ADC0_11 \hideinitializer */ |
<> | 149:156823d33999 | 710 | #define SYS_GPE_MFPH_PE11MFP_ADC1_3 (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ADC1_3 \hideinitializer */ |
<> | 149:156823d33999 | 711 | #define SYS_GPE_MFPH_PE11MFP_ACMP1_P2 (0x2UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ACMP1_P2 \hideinitializer */ |
<> | 149:156823d33999 | 712 | #define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI1 (0x3UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI0_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 713 | #define SYS_GPE_MFPH_PE11MFP_SD0_DAT0 (0x4UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SD0_DAT0 \hideinitializer */ |
<> | 149:156823d33999 | 714 | #define SYS_GPE_MFPH_PE11MFP_ACMP2_P3 (0x5UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ACMP2_P3 \hideinitializer */ |
<> | 149:156823d33999 | 715 | #define SYS_GPE_MFPH_PE11MFP_EBI_nCS0 (0x7UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for EBI_nCS0 \hideinitializer */ |
<> | 149:156823d33999 | 716 | |
<> | 149:156823d33999 | 717 | //GPE_MFPH_PE12MFP |
<> | 149:156823d33999 | 718 | #define SYS_GPE_MFPH_PE12MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 719 | #define SYS_GPE_MFPH_PE12MFP_ADC1_4 (0x1UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for ADC1_4 \hideinitializer */ |
<> | 149:156823d33999 | 720 | #define SYS_GPE_MFPH_PE12MFP_ACMP1_P3 (0x2UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for ACMP1_P3 \hideinitializer */ |
<> | 149:156823d33999 | 721 | #define SYS_GPE_MFPH_PE12MFP_ACMP2_P2 (0x3UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for ACMP2_P2 \hideinitializer */ |
<> | 149:156823d33999 | 722 | #define SYS_GPE_MFPH_PE12MFP_EBI_nCS1 (0x7UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for EBI_nCS1 \hideinitializer */ |
<> | 149:156823d33999 | 723 | //GPE_MFPH_PE13MFP |
<> | 149:156823d33999 | 724 | #define SYS_GPE_MFPH_PE13MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 725 | #define SYS_GPE_MFPH_PE13MFP_ADC1_5 (0x1UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for ADC1_5 \hideinitializer */ |
<> | 149:156823d33999 | 726 | #define SYS_GPE_MFPH_PE13MFP_ACMP2_P1 (0x3UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for ACMP2_P1 \hideinitializer */ |
<> | 149:156823d33999 | 727 | #define SYS_GPE_MFPH_PE13MFP_EBI_nCS2 (0x7UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for EBI_nCS2 \hideinitializer */ |
<> | 149:156823d33999 | 728 | |
<> | 149:156823d33999 | 729 | //GPE_MFPH_PE14MFP |
<> | 149:156823d33999 | 730 | #define SYS_GPE_MFPH_PE14MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 731 | #define SYS_GPE_MFPH_PE14MFP_ADC1_6 (0x1UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for ADC1_6 \hideinitializer */ |
<> | 149:156823d33999 | 732 | #define SYS_GPE_MFPH_PE14MFP_ACMP2_P0 (0x3UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for ACMP2_P0 \hideinitializer */ |
<> | 149:156823d33999 | 733 | #define SYS_GPE_MFPH_PE14MFP_EBI_nCS3 (0x7UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for EBI_nCS3 \hideinitializer */ |
<> | 149:156823d33999 | 734 | |
<> | 149:156823d33999 | 735 | //GPE_MFPH_PE15MFP |
<> | 149:156823d33999 | 736 | #define SYS_GPE_MFPH_PE15MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 737 | #define SYS_GPE_MFPH_PE15MFP_ADC1_7 (0x1UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for ADC1_7 \hideinitializer */ |
<> | 149:156823d33999 | 738 | #define SYS_GPE_MFPH_PE15MFP_ACMP2_N (0x3UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for ACMP2_N \hideinitializer */ |
<> | 149:156823d33999 | 739 | |
<> | 149:156823d33999 | 740 | //GPF_MFPL_PF0MFP |
<> | 149:156823d33999 | 741 | #define SYS_GPF_MFPL_PF0MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 742 | #define SYS_GPF_MFPL_PF0MFP_SPI1_MOSI0 (0x1UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for SPI1_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 743 | #define SYS_GPF_MFPL_PF0MFP_UART5_RXD (0x2UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART5_RXD \hideinitializer */ |
<> | 149:156823d33999 | 744 | #define SYS_GPF_MFPL_PF0MFP_INT5 (0x8UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for INT5 \hideinitializer */ |
<> | 149:156823d33999 | 745 | |
<> | 149:156823d33999 | 746 | //GPF_MFPL_PF1MFP |
<> | 149:156823d33999 | 747 | #define SYS_GPF_MFPL_PF1MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 748 | #define SYS_GPF_MFPL_PF1MFP_SPI2_MOSI1 (0x1UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for SPI2_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 749 | |
<> | 149:156823d33999 | 750 | //GPF_MFPL_PF2MFP |
<> | 149:156823d33999 | 751 | #define SYS_GPF_MFPL_PF2MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 752 | #define SYS_GPF_MFPL_PF2MFP_SPI3_SS0 (0x1UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for SPI3_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 753 | #define SYS_GPF_MFPL_PF2MFP_SD0_DAT3 (0x4UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for SD0_DAT3 \hideinitializer */ |
<> | 149:156823d33999 | 754 | #define SYS_GPF_MFPL_PF2MFP_EMAC_MII_RXD3 (0x6UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for EMAC_MII_RXD3 \hideinitializer */ |
<> | 149:156823d33999 | 755 | |
<> | 149:156823d33999 | 756 | //GPF_MFPL_PF3MFP |
<> | 149:156823d33999 | 757 | #define SYS_GPF_MFPL_PF3MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 758 | #define SYS_GPF_MFPL_PF3MFP_SPI3_CLK (0x1UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for SPI3_CLK \hideinitializer */ |
<> | 149:156823d33999 | 759 | #define SYS_GPF_MFPL_PF3MFP_SD0_DAT2 (0x4UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for SD0_DAT2 \hideinitializer */ |
<> | 149:156823d33999 | 760 | #define SYS_GPF_MFPL_PF3MFP_EMAC_MII_RXD2 (0x6UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for EMAC_MII_RXD2 \hideinitializer */ |
<> | 149:156823d33999 | 761 | |
<> | 149:156823d33999 | 762 | //GPF_MFPL_PF4MFP |
<> | 149:156823d33999 | 763 | #define SYS_GPF_MFPL_PF4MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 764 | #define SYS_GPF_MFPL_PF4MFP_SPI3_MISO0 (0x1UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for SPI3_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 765 | #define SYS_GPF_MFPL_PF4MFP_SD0_DAT1 (0x4UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for SD0_DAT1 \hideinitializer */ |
<> | 149:156823d33999 | 766 | #define SYS_GPF_MFPL_PF4MFP_EMAC_MII_COL0 (0x6UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for EMAC_MII_COL0 \hideinitializer */ |
<> | 149:156823d33999 | 767 | |
<> | 149:156823d33999 | 768 | //GPF_MFPL_PF5MFP |
<> | 149:156823d33999 | 769 | #define SYS_GPF_MFPL_PF5MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 770 | #define SYS_GPF_MFPL_PF5MFP_SPI3_MOSI0 (0x1UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for SPI3_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 771 | #define SYS_GPF_MFPL_PF5MFP_SD0_DAT0 (0x4UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for SD0_DAT0 \hideinitializer */ |
<> | 149:156823d33999 | 772 | #define SYS_GPF_MFPL_PF5MFP_EMAC_MII_CRS (0x6UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EMAC_MII_CRS \hideinitializer */ |
<> | 149:156823d33999 | 773 | |
<> | 149:156823d33999 | 774 | //GPF_MFPL_PF6MFP |
<> | 149:156823d33999 | 775 | #define SYS_GPF_MFPL_PF6MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 776 | #define SYS_GPF_MFPL_PF6MFP_UART2_RXD (0x1UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for UART2_RXD \hideinitializer */ |
<> | 149:156823d33999 | 777 | #define SYS_GPF_MFPL_PF6MFP_SD0_CDn (0x4UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SD0_CDn \hideinitializer */ |
<> | 149:156823d33999 | 778 | #define SYS_GPF_MFPL_PF6MFP_EMAC_MII_TXCLK (0x6UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EMAC_MII_TXCLK \hideinitializer */ |
<> | 149:156823d33999 | 779 | |
<> | 149:156823d33999 | 780 | //GPF_MFPL_PF7MFP |
<> | 149:156823d33999 | 781 | #define SYS_GPF_MFPL_PF7MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 782 | #define SYS_GPF_MFPL_PF7MFP_UART2_TXD (0x1UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for UART2_TXD \hideinitializer */ |
<> | 149:156823d33999 | 783 | #define SYS_GPF_MFPL_PF7MFP_SD0_CMD (0x4UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SD0_CMD \hideinitializer */ |
<> | 149:156823d33999 | 784 | #define SYS_GPF_MFPL_PF7MFP_EMAC_MII_TXD3 (0x6UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for EMAC_MII_TXD3 \hideinitializer */ |
<> | 149:156823d33999 | 785 | |
<> | 149:156823d33999 | 786 | //GPF_MFPL_PF8MFP |
<> | 149:156823d33999 | 787 | #define SYS_GPF_MFPH_PF8MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 788 | #define SYS_GPF_MFPH_PF8MFP_UART2_RTS (0x1UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for UART2_RTS \hideinitializer */ |
<> | 149:156823d33999 | 789 | #define SYS_GPF_MFPH_PF8MFP_SD0_CLK (0x4UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SD0_CLK \hideinitializer */ |
<> | 149:156823d33999 | 790 | #define SYS_GPF_MFPH_PF8MFP_EMAC_MII_TXD2 (0x6UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for EMAC_MII_TXD2 \hideinitializer */ |
<> | 149:156823d33999 | 791 | |
<> | 149:156823d33999 | 792 | //GPF_MFPH_PF9MFP |
<> | 149:156823d33999 | 793 | #define SYS_GPF_MFPH_PF9MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 794 | #define SYS_GPF_MFPH_PF9MFP_OPA0_IN_P (0x1UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for OPA0_IN_P \hideinitializer */ |
<> | 149:156823d33999 | 795 | #define SYS_GPF_MFPH_PF9MFP_PWM0_CH0 (0x4UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for PWM0_CH0 \hideinitializer */ |
<> | 149:156823d33999 | 796 | |
<> | 149:156823d33999 | 797 | //GPF_MFPH_PF10MFP |
<> | 149:156823d33999 | 798 | #define SYS_GPF_MFPH_PF10MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 799 | #define SYS_GPF_MFPH_PF10MFP_OPA0_IN_N (0x1UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for OPA0_IN_N \hideinitializer */ |
<> | 149:156823d33999 | 800 | #define SYS_GPF_MFPH_PF10MFP_PWM0_CH1 (0x4UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for PWM0_CH1 \hideinitializer */ |
<> | 149:156823d33999 | 801 | |
<> | 149:156823d33999 | 802 | //GPF_MFPH_PF11MFP |
<> | 149:156823d33999 | 803 | #define SYS_GPF_MFPH_PF11MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 804 | #define SYS_GPF_MFPH_PF11MFP_OPA0_O (0x1UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for OPA0_O \hideinitializer */ |
<> | 149:156823d33999 | 805 | #define SYS_GPF_MFPH_PF11MFP_UART1_RTS (0x2UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for UART1_RTS \hideinitializer */ |
<> | 149:156823d33999 | 806 | |
<> | 149:156823d33999 | 807 | //GPF_MFPH_PF12MFP |
<> | 149:156823d33999 | 808 | #define SYS_GPF_MFPH_PF12MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF12MFP_Pos) /*!< GPF_MFPH PF12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 809 | #define SYS_GPF_MFPH_PF12MFP_OPA1_IN_P (0x1UL<<SYS_GPF_MFPH_PF12MFP_Pos) /*!< GPF_MFPH PF12 setting for OPA1_IN_P \hideinitializer */ |
<> | 149:156823d33999 | 810 | #define SYS_GPF_MFPH_PF12MFP_UART1_CTS (0x2UL<<SYS_GPF_MFPH_PF12MFP_Pos) /*!< GPF_MFPH PF12 setting for UART1_CTS \hideinitializer */ |
<> | 149:156823d33999 | 811 | //GPF_MFPH_PF13MFP |
<> | 149:156823d33999 | 812 | #define SYS_GPF_MFPH_PF13MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF13MFP_Pos) /*!< GPF_MFPH PF13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 813 | #define SYS_GPF_MFPH_PF13MFP_OPA1_IN_N (0x1UL<<SYS_GPF_MFPH_PF13MFP_Pos) /*!< GPF_MFPH PF13 setting for OPA1_IN_N \hideinitializer */ |
<> | 149:156823d33999 | 814 | #define SYS_GPF_MFPH_PF13MFP_UART1_TXD (0x2UL<<SYS_GPF_MFPH_PF13MFP_Pos) /*!< GPF_MFPH PF13 setting for UART1_TXD \hideinitializer */ |
<> | 149:156823d33999 | 815 | |
<> | 149:156823d33999 | 816 | //GPF_MFPH_PF14MFP |
<> | 149:156823d33999 | 817 | #define SYS_GPF_MFPH_PF14MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 818 | #define SYS_GPF_MFPH_PF14MFP_OPA1_O (0x1UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for OPA1_O \hideinitializer */ |
<> | 149:156823d33999 | 819 | #define SYS_GPF_MFPH_PF14MFP_UART1_RXD (0x2UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for UART1_RXD \hideinitializer */ |
<> | 149:156823d33999 | 820 | |
<> | 149:156823d33999 | 821 | //GPF_MFPH_PF15MFP |
<> | 149:156823d33999 | 822 | #define SYS_GPF_MFPH_PF15MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 823 | #define SYS_GPF_MFPH_PF15MFP_UART0_RTS (0x1UL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for UART0_RTS \hideinitializer */ |
<> | 149:156823d33999 | 824 | |
<> | 149:156823d33999 | 825 | |
<> | 149:156823d33999 | 826 | //GPG_MFPL_PG0MFP |
<> | 149:156823d33999 | 827 | #define SYS_GPG_MFPL_PG0MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< GPG_MFPL PG0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 828 | #define SYS_GPG_MFPL_PG0MFP_UART0_CTS (0x1UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< GPG_MFPL PG0 setting for UART0_CTS \hideinitializer */ |
<> | 149:156823d33999 | 829 | #define SYS_GPG_MFPL_PG0MFP_INT6 (0x8UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< GPG_MFPL PG0 setting for INT6 \hideinitializer */ |
<> | 149:156823d33999 | 830 | |
<> | 149:156823d33999 | 831 | //GPG_MFPL_PG1MFP |
<> | 149:156823d33999 | 832 | #define SYS_GPG_MFPL_PG1MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< GPG_MFPL PG1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 833 | #define SYS_GPG_MFPL_PG1MFP_UART0_RXD (0x1UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< GPG_MFPL PG1 setting for UART0_RXD \hideinitializer */ |
<> | 149:156823d33999 | 834 | |
<> | 149:156823d33999 | 835 | //GPG_MFPL_PG2MFP |
<> | 149:156823d33999 | 836 | #define SYS_GPG_MFPL_PG2MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 837 | #define SYS_GPG_MFPL_PG2MFP_UART0_TXD (0x1UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for UART0_TXD \hideinitializer */ |
<> | 149:156823d33999 | 838 | |
<> | 149:156823d33999 | 839 | //GPG_MFPL_PG3MFP |
<> | 149:156823d33999 | 840 | #define SYS_GPG_MFPL_PG3MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 841 | #define SYS_GPG_MFPL_PG3MFP_PS2_CLK (0x1UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for PS2_CLK \hideinitializer */ |
<> | 149:156823d33999 | 842 | #define SYS_GPG_MFPL_PG3MFP_I2S1_DO (0x2UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2S1_DO \hideinitializer */ |
<> | 149:156823d33999 | 843 | #define SYS_GPG_MFPL_PG3MFP_SC1_RST (0x3UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for SC1_RST \hideinitializer */ |
<> | 149:156823d33999 | 844 | //GPG_MFPL_PG4MFP |
<> | 149:156823d33999 | 845 | #define SYS_GPG_MFPL_PG4MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 846 | #define SYS_GPG_MFPL_PG4MFP_PS2_DAT (0x1UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for PS2_DAT \hideinitializer */ |
<> | 149:156823d33999 | 847 | #define SYS_GPG_MFPL_PG4MFP_I2S1_DI (0x2UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for I2S1_DI \hideinitializer */ |
<> | 149:156823d33999 | 848 | #define SYS_GPG_MFPL_PG4MFP_SC1_PWR (0x3UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for SC1_PWR \hideinitializer */ |
<> | 149:156823d33999 | 849 | |
<> | 149:156823d33999 | 850 | //GPG_MFPL_PG5MFP |
<> | 149:156823d33999 | 851 | #define SYS_GPG_MFPL_PG5MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< GPG_MFPL PG5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 852 | #define SYS_GPG_MFPL_PG5MFP_I2S1_BCLK (0x2UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< GPG_MFPL PG5 setting for I2S1_BCLK \hideinitializer */ |
<> | 149:156823d33999 | 853 | #define SYS_GPG_MFPL_PG5MFP_SC1_DAT (0x3UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< GPG_MFPL PG5 setting for SC1_DAT \hideinitializer */ |
<> | 149:156823d33999 | 854 | //GPG_MFPL_PG6MFP |
<> | 149:156823d33999 | 855 | #define SYS_GPG_MFPL_PG6MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< GPG_MFPL PG6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 856 | #define SYS_GPG_MFPL_PG6MFP_I2S1_LRCK (0x2UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< GPG_MFPL PG6 setting for I2S1_LRCK \hideinitializer */ |
<> | 149:156823d33999 | 857 | #define SYS_GPG_MFPL_PG6MFP_SC1_CLK (0x3UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< GPG_MFPL PG6 setting for SC1_CLK \hideinitializer */ |
<> | 149:156823d33999 | 858 | |
<> | 149:156823d33999 | 859 | //GPG_MFPL_PG7MFP |
<> | 149:156823d33999 | 860 | #define SYS_GPG_MFPL_PG7MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 861 | #define SYS_GPG_MFPL_PG7MFP_SPI2_MISO0 (0x1UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for SPI2_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 862 | #define SYS_GPG_MFPL_PG7MFP_I2S1_MCLK (0x2UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for I2S1_MCLK \hideinitializer */ |
<> | 149:156823d33999 | 863 | #define SYS_GPG_MFPL_PG7MFP_SC1_CD (0x3UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for SC1_CD \hideinitializer */ |
<> | 149:156823d33999 | 864 | #define SYS_GPG_MFPL_PG7MFP_SC3_RST (0x4UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for SC3_RST \hideinitializer */ |
<> | 149:156823d33999 | 865 | |
<> | 149:156823d33999 | 866 | //GPG_MFPL_PG8MFP |
<> | 149:156823d33999 | 867 | #define SYS_GPG_MFPH_PG8MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 868 | #define SYS_GPG_MFPH_PG8MFP_SPI2_MOSI0 (0x1UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for SPI2_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 869 | #define SYS_GPG_MFPH_PG8MFP_I2S1_DO (0x2UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for I2S1_DO \hideinitializer */ |
<> | 149:156823d33999 | 870 | #define SYS_GPG_MFPH_PG8MFP_UART4_RTS (0x3UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for UART4_RTS \hideinitializer */ |
<> | 149:156823d33999 | 871 | #define SYS_GPG_MFPH_PG8MFP_SC3_DAT (0x4UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for SC3_DAT \hideinitializer */ |
<> | 149:156823d33999 | 872 | |
<> | 149:156823d33999 | 873 | //GPG_MFPH_PG9MFP |
<> | 149:156823d33999 | 874 | #define SYS_GPG_MFPH_PG9MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 875 | #define SYS_GPG_MFPH_PG9MFP_SPI2_CLK (0x1UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for SPI2_CLK \hideinitializer */ |
<> | 149:156823d33999 | 876 | #define SYS_GPG_MFPH_PG9MFP_I2S1_DI (0x2UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for I2S1_DI \hideinitializer */ |
<> | 149:156823d33999 | 877 | #define SYS_GPG_MFPH_PG9MFP_UART4_CTS (0x3UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for UART4_CTS \hideinitializer */ |
<> | 149:156823d33999 | 878 | #define SYS_GPG_MFPH_PG9MFP_SC3_CLK (0x4UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for SC3_CLK \hideinitializer */ |
<> | 149:156823d33999 | 879 | |
<> | 149:156823d33999 | 880 | //GPG_MFPH_PG10MFP |
<> | 149:156823d33999 | 881 | #define SYS_GPG_MFPH_PG10MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 882 | #define SYS_GPG_MFPH_PG10MFP_ICE_CLK (0x1UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for ICE_CLK \hideinitializer */ |
<> | 149:156823d33999 | 883 | #define SYS_GPG_MFPH_PG10MFP_JTAG_TCLK (0x6UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for JTAG_TCLK \hideinitializer */ |
<> | 149:156823d33999 | 884 | |
<> | 149:156823d33999 | 885 | //GPG_MFPH_PG11MFP |
<> | 149:156823d33999 | 886 | #define SYS_GPG_MFPH_PG11MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 887 | #define SYS_GPG_MFPH_PG11MFP_ICE_DAT (0x1UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for ICE_DAT \hideinitializer */ |
<> | 149:156823d33999 | 888 | #define SYS_GPG_MFPH_PG11MFP_JTAG_TMS (0x6UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for JTAG_TMS \hideinitializer */ |
<> | 149:156823d33999 | 889 | |
<> | 149:156823d33999 | 890 | //GPG_MFPH_PG12MFP |
<> | 149:156823d33999 | 891 | #define SYS_GPG_MFPH_PG12MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 892 | #define SYS_GPG_MFPH_PG12MFP_XT1_OUT (0x1UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for XT1_OUT \hideinitializer */ |
<> | 149:156823d33999 | 893 | |
<> | 149:156823d33999 | 894 | //GPG_MFPH_PG13MFP |
<> | 149:156823d33999 | 895 | #define SYS_GPG_MFPH_PG13MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 896 | #define SYS_GPG_MFPH_PG13MFP_XT1_IN (0x1UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for XT1_IN \hideinitializer */ |
<> | 149:156823d33999 | 897 | |
<> | 149:156823d33999 | 898 | //GPG_MFPH_PG14MFP |
<> | 149:156823d33999 | 899 | #define SYS_GPG_MFPH_PG14MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 900 | #define SYS_GPG_MFPH_PG14MFP_X32K_OUT (0x1UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for X32K_OUT \hideinitializer */ |
<> | 149:156823d33999 | 901 | #define SYS_GPG_MFPH_PG14MFP_I2C1_SDA (0x3UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for I2C1_SDA \hideinitializer */ |
<> | 149:156823d33999 | 902 | |
<> | 149:156823d33999 | 903 | //GPG_MFPH_PG15MFP |
<> | 149:156823d33999 | 904 | #define SYS_GPG_MFPH_PG15MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 905 | #define SYS_GPG_MFPH_PG15MFP_X32K_IN (0x1UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for X32K_IN \hideinitializer */ |
<> | 149:156823d33999 | 906 | #define SYS_GPG_MFPH_PG15MFP_I2C1_SCL (0x3UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for I2C1_SCL \hideinitializer */ |
<> | 149:156823d33999 | 907 | |
<> | 149:156823d33999 | 908 | |
<> | 149:156823d33999 | 909 | //GPH_MFPL_PH0MFP |
<> | 149:156823d33999 | 910 | #define SYS_GPH_MFPL_PH0MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 911 | #define SYS_GPH_MFPL_PH0MFP_I2C1_SCL (0x1UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for I2C1_SCL \hideinitializer */ |
<> | 149:156823d33999 | 912 | #define SYS_GPH_MFPL_PH0MFP_UART4_RXD (0x2UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for UART4_RXD \hideinitializer */ |
<> | 149:156823d33999 | 913 | #define SYS_GPH_MFPL_PH0MFP_CAN1_RXD (0x3UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for CAN1_RXD \hideinitializer */ |
<> | 149:156823d33999 | 914 | #define SYS_GPH_MFPL_PH0MFP_INT7 (0x8UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for INT7 \hideinitializer */ |
<> | 149:156823d33999 | 915 | |
<> | 149:156823d33999 | 916 | //GPH_MFPL_PH1MFP |
<> | 149:156823d33999 | 917 | #define SYS_GPH_MFPL_PH1MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 918 | #define SYS_GPH_MFPL_PH1MFP_UART4_TXD (0x1UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for UART4_TXD \hideinitializer */ |
<> | 149:156823d33999 | 919 | #define SYS_GPH_MFPL_PH1MFP_I2C1_SDA (0x2UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for I2C1_SDA \hideinitializer */ |
<> | 149:156823d33999 | 920 | #define SYS_GPH_MFPL_PH1MFP_CAN1_TXD (0x3UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for CAN1_TXD \hideinitializer */ |
<> | 149:156823d33999 | 921 | |
<> | 149:156823d33999 | 922 | //GPH_MFPL_PH2MFP |
<> | 149:156823d33999 | 923 | #define SYS_GPH_MFPL_PH2MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< GPH_MFPL PH2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 924 | #define SYS_GPH_MFPL_PH2MFP_UART2_CTS (0x1UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< GPH_MFPL PH2 setting for UART2_CTS \hideinitializer */ |
<> | 149:156823d33999 | 925 | |
<> | 149:156823d33999 | 926 | //GPH_MFPL_PH3MFP |
<> | 149:156823d33999 | 927 | #define SYS_GPH_MFPL_PH3MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< GPH_MFPL PH3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 928 | #define SYS_GPH_MFPL_PH3MFP_I2C3_SCL (0x1UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< GPH_MFPL PH3 setting for I2C3_SCL \hideinitializer */ |
<> | 149:156823d33999 | 929 | |
<> | 149:156823d33999 | 930 | //GPH_MFPL_PH4MFP |
<> | 149:156823d33999 | 931 | #define SYS_GPH_MFPL_PH4MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 932 | #define SYS_GPH_MFPL_PH4MFP_I2C3_SDA (0x1UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for I2C3_SDA \hideinitializer */ |
<> | 149:156823d33999 | 933 | |
<> | 149:156823d33999 | 934 | //GPH_MFPL_PH5MFP |
<> | 149:156823d33999 | 935 | #define SYS_GPH_MFPL_PH5MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 936 | #define SYS_GPH_MFPL_PH5MFP_SPI2_SS0 (0x1UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for SPI2_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 937 | |
<> | 149:156823d33999 | 938 | //GPH_MFPL_PH6MFP |
<> | 149:156823d33999 | 939 | #define SYS_GPH_MFPL_PH6MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 940 | #define SYS_GPH_MFPL_PH6MFP_SPI2_CLK (0x1UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for SPI2_CLK \hideinitializer */ |
<> | 149:156823d33999 | 941 | |
<> | 149:156823d33999 | 942 | //GPH_MFPL_PH7MFP |
<> | 149:156823d33999 | 943 | #define SYS_GPH_MFPL_PH7MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 944 | #define SYS_GPH_MFPL_PH7MFP_SPI2_MISO0 (0x1UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for SPI2_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 945 | |
<> | 149:156823d33999 | 946 | //GPH_MFPL_PH8MFP |
<> | 149:156823d33999 | 947 | #define SYS_GPH_MFPH_PH8MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 948 | #define SYS_GPH_MFPH_PH8MFP_SPI2_MOSI0 (0x1UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SPI2_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 949 | |
<> | 149:156823d33999 | 950 | //GPH_MFPH_PH9MFP |
<> | 149:156823d33999 | 951 | #define SYS_GPH_MFPH_PH9MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 952 | #define SYS_GPH_MFPH_PH9MFP_SPI2_MISO1 (0x1UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SPI2_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 953 | |
<> | 149:156823d33999 | 954 | //GPH_MFPH_PH10MFP |
<> | 149:156823d33999 | 955 | #define SYS_GPH_MFPH_PH10MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 956 | #define SYS_GPH_MFPH_PH10MFP_SPI2_MOSI1 (0x1UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for SPI2_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 957 | |
<> | 149:156823d33999 | 958 | //GPH_MFPH_PH11MFP |
<> | 149:156823d33999 | 959 | #define SYS_GPH_MFPH_PH11MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 960 | #define SYS_GPH_MFPH_PH11MFP_UART3_RXD (0x1UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for UART3_RXD \hideinitializer */ |
<> | 149:156823d33999 | 961 | |
<> | 149:156823d33999 | 962 | //GPH_MFPH_PH12MFP |
<> | 149:156823d33999 | 963 | #define SYS_GPH_MFPH_PH12MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH12MFP_Pos) /*!< GPH_MFPH PH12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 964 | #define SYS_GPH_MFPH_PH12MFP_UART3_TXD (0x1UL<<SYS_GPH_MFPH_PH12MFP_Pos) /*!< GPH_MFPH PH12 setting for UART3_TXD \hideinitializer */ |
<> | 149:156823d33999 | 965 | |
<> | 149:156823d33999 | 966 | //GPH_MFPH_PH13MFP |
<> | 149:156823d33999 | 967 | #define SYS_GPH_MFPH_PH13MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH13MFP_Pos) /*!< GPH_MFPH PH13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 968 | #define SYS_GPH_MFPH_PH13MFP_UART3_RTS (0x1UL<<SYS_GPH_MFPH_PH13MFP_Pos) /*!< GPH_MFPH PH13 setting for UART3_RTS \hideinitializer */ |
<> | 149:156823d33999 | 969 | |
<> | 149:156823d33999 | 970 | //GPH_MFPH_PH14MFP |
<> | 149:156823d33999 | 971 | #define SYS_GPH_MFPH_PH14MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH14MFP_Pos) /*!< GPH_MFPH PH14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 972 | #define SYS_GPH_MFPH_PH14MFP_UART3_CTS (0x1UL<<SYS_GPH_MFPH_PH14MFP_Pos) /*!< GPH_MFPH PH14 setting for UART3_CTS \hideinitializer */ |
<> | 149:156823d33999 | 973 | |
<> | 149:156823d33999 | 974 | //GPH_MFPH_PH15MFP |
<> | 149:156823d33999 | 975 | #define SYS_GPH_MFPH_PH15MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH15MFP_Pos) /*!< GPH_MFPH PH15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 976 | #define SYS_GPH_MFPH_PH15MFP_SC5_CLK (0x2UL<<SYS_GPH_MFPH_PH15MFP_Pos) /*!< GPH_MFPH PH15 setting for SC5_CLK \hideinitializer */ |
<> | 149:156823d33999 | 977 | |
<> | 149:156823d33999 | 978 | //GPI_MFPL_PI0MFP |
<> | 149:156823d33999 | 979 | #define SYS_GPI_MFPL_PI0MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI0MFP_Pos) /*!< GPI_MFPL PI0 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 980 | #define SYS_GPI_MFPL_PI0MFP_SC5_RST (0x2UL<<SYS_GPI_MFPL_PI0MFP_Pos) /*!< GPI_MFPL PI0 setting for SC5_RST \hideinitializer */ |
<> | 149:156823d33999 | 981 | |
<> | 149:156823d33999 | 982 | //GPI_MFPL_PI1MFP |
<> | 149:156823d33999 | 983 | #define SYS_GPI_MFPL_PI1MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI1MFP_Pos) /*!< GPI_MFPL PI1 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 984 | #define SYS_GPI_MFPL_PI1MFP_SC5_PWR (0x2UL<<SYS_GPI_MFPL_PI1MFP_Pos) /*!< GPI_MFPL PI1 setting for SC5_PWR \hideinitializer */ |
<> | 149:156823d33999 | 985 | |
<> | 149:156823d33999 | 986 | //GPI_MFPL_PI2MFP |
<> | 149:156823d33999 | 987 | #define SYS_GPI_MFPL_PI2MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI2MFP_Pos) /*!< GPI_MFPL PI2 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 988 | #define SYS_GPI_MFPL_PI2MFP_SC5_DAT (0x2UL<<SYS_GPI_MFPL_PI2MFP_Pos) /*!< GPI_MFPL PI2 setting for SC5_DAT \hideinitializer */ |
<> | 149:156823d33999 | 989 | |
<> | 149:156823d33999 | 990 | //GPI_MFPL_PI3MFP |
<> | 149:156823d33999 | 991 | #define SYS_GPI_MFPL_PI3MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI3MFP_Pos) /*!< GPI_MFPL PI3 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 992 | #define SYS_GPI_MFPL_PI3MFP_SPI3_SS0 (0x1UL<<SYS_GPI_MFPL_PI3MFP_Pos) /*!< GPI_MFPL PI3 setting for SPI3_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 993 | |
<> | 149:156823d33999 | 994 | //GPI_MFPL_PI4MFP |
<> | 149:156823d33999 | 995 | #define SYS_GPI_MFPL_PI4MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI4MFP_Pos) /*!< GPI_MFPL PI4 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 996 | #define SYS_GPI_MFPL_PI4MFP_SPI3_CLK (0x1UL<<SYS_GPI_MFPL_PI4MFP_Pos) /*!< GPI_MFPL PI4 setting for SPI3_CLK \hideinitializer */ |
<> | 149:156823d33999 | 997 | |
<> | 149:156823d33999 | 998 | //GPI_MFPL_PI5MFP |
<> | 149:156823d33999 | 999 | #define SYS_GPI_MFPL_PI5MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI5MFP_Pos) /*!< GPI_MFPL PI5 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1000 | #define SYS_GPI_MFPL_PI5MFP_SPI3_MISO0 (0x1UL<<SYS_GPI_MFPL_PI5MFP_Pos) /*!< GPI_MFPL PI5 setting for SPI3_MISO0 \hideinitializer */ |
<> | 149:156823d33999 | 1001 | |
<> | 149:156823d33999 | 1002 | //GPI_MFPL_PI6MFP |
<> | 149:156823d33999 | 1003 | #define SYS_GPI_MFPL_PI6MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI6MFP_Pos) /*!< GPI_MFPL PI6 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1004 | #define SYS_GPI_MFPL_PI6MFP_SPI3_MOSI0 (0x1UL<<SYS_GPI_MFPL_PI6MFP_Pos) /*!< GPI_MFPL PI6 setting for SPI3_MOSI0 \hideinitializer */ |
<> | 149:156823d33999 | 1005 | |
<> | 149:156823d33999 | 1006 | //GPI_MFPL_PI7MFP |
<> | 149:156823d33999 | 1007 | #define SYS_GPI_MFPL_PI7MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI7MFP_Pos) /*!< GPI_MFPL PI7 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1008 | #define SYS_GPI_MFPL_PI7MFP_I2C2_SCL (0x1UL<<SYS_GPI_MFPL_PI7MFP_Pos) /*!< GPI_MFPL PI7 setting for I2C2_SCL \hideinitializer */ |
<> | 149:156823d33999 | 1009 | #define SYS_GPI_MFPL_PI7MFP_SPI3_MISO1 (0x2UL<<SYS_GPI_MFPL_PI7MFP_Pos) /*!< GPI_MFPL PI7 setting for SPI3_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 1010 | |
<> | 149:156823d33999 | 1011 | //GPI_MFPL_PI8MFP |
<> | 149:156823d33999 | 1012 | #define SYS_GPI_MFPH_PI8MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI8MFP_Pos) /*!< GPI_MFPH PI8 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1013 | #define SYS_GPI_MFPH_PI8MFP_I2C2_SDA (0x1UL<<SYS_GPI_MFPH_PI8MFP_Pos) /*!< GPI_MFPH PI8 setting for I2C2_SDA \hideinitializer */ |
<> | 149:156823d33999 | 1014 | #define SYS_GPI_MFPH_PI8MFP_SPI3_MOSI1 (0x2UL<<SYS_GPI_MFPH_PI8MFP_Pos) /*!< GPI_MFPH PI8 setting for SPI3_MOSI1 \hideinitializer */ |
<> | 149:156823d33999 | 1015 | |
<> | 149:156823d33999 | 1016 | //GPI_MFPH_PI9MFP |
<> | 149:156823d33999 | 1017 | #define SYS_GPI_MFPH_PI9MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI9MFP_Pos) /*!< GPI_MFPH PI9 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1018 | #define SYS_GPI_MFPH_PI9MFP_I2C4_SCL (0x4UL<<SYS_GPI_MFPH_PI9MFP_Pos) /*!< GPI_MFPH PI9 setting for I2C4_SCL \hideinitializer */ |
<> | 149:156823d33999 | 1019 | |
<> | 149:156823d33999 | 1020 | //GPI_MFPH_PI10MFP |
<> | 149:156823d33999 | 1021 | #define SYS_GPI_MFPH_PI10MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI10MFP_Pos) /*!< GPI_MFPH PI10 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1022 | |
<> | 149:156823d33999 | 1023 | //GPI_MFPH_PI11MFP |
<> | 149:156823d33999 | 1024 | #define SYS_GPI_MFPH_PI11MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1025 | #define SYS_GPI_MFPH_PI11MFP_SPI2_SS0 (0x1UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for SPI2_SS0 \hideinitializer */ |
<> | 149:156823d33999 | 1026 | #define SYS_GPI_MFPH_PI11MFP_I2S1_BCLK (0x2UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for I2S1_BCLK \hideinitializer */ |
<> | 149:156823d33999 | 1027 | #define SYS_GPI_MFPH_PI11MFP_I2C4_SCL (0x3UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for I2C4_SCL \hideinitializer */ |
<> | 149:156823d33999 | 1028 | #define SYS_GPI_MFPH_PI11MFP_SC3_PWR (0x4UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for SC3_PWR \hideinitializer */ |
<> | 149:156823d33999 | 1029 | |
<> | 149:156823d33999 | 1030 | //GPI_MFPH_PI12MFP |
<> | 149:156823d33999 | 1031 | #define SYS_GPI_MFPH_PI12MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1032 | #define SYS_GPI_MFPH_PI12MFP_SPI2_MISO1 (0x1UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for SPI2_MISO1 \hideinitializer */ |
<> | 149:156823d33999 | 1033 | #define SYS_GPI_MFPH_PI12MFP_I2S1_LRCK (0x2UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for I2S1_LRCK \hideinitializer */ |
<> | 149:156823d33999 | 1034 | #define SYS_GPI_MFPH_PI12MFP_I2C4_SDA (0x3UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for I2C4_SDA \hideinitializer */ |
<> | 149:156823d33999 | 1035 | #define SYS_GPI_MFPH_PI12MFP_SC3_CD (0x4UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for SC3_CD \hideinitializer */ |
<> | 149:156823d33999 | 1036 | |
<> | 149:156823d33999 | 1037 | //GPI_MFPH_PI13MFP |
<> | 149:156823d33999 | 1038 | #define SYS_GPI_MFPH_PI13MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI13MFP_Pos) /*!< GPI_MFPH PI13 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1039 | |
<> | 149:156823d33999 | 1040 | //GPI_MFPH_PI14MFP |
<> | 149:156823d33999 | 1041 | #define SYS_GPI_MFPH_PI14MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI14MFP_Pos) /*!< GPI_MFPH PI14 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1042 | |
<> | 149:156823d33999 | 1043 | //GPI_MFPH_PI15MFP |
<> | 149:156823d33999 | 1044 | #define SYS_GPI_MFPH_PI15MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI15MFP_Pos) /*!< GPI_MFPH PI15 setting for GPIO \hideinitializer */ |
<> | 149:156823d33999 | 1045 | |
<> | 149:156823d33999 | 1046 | /*@}*/ /* end of group NUC472_442_SYS_EXPORTED_CONSTANTS */ |
<> | 149:156823d33999 | 1047 | |
<> | 149:156823d33999 | 1048 | /** @addtogroup NUC472_442_SYS_EXPORTED_FUNCTIONS SYS Exported Functions |
<> | 149:156823d33999 | 1049 | @{ |
<> | 149:156823d33999 | 1050 | */ |
<> | 149:156823d33999 | 1051 | |
<> | 149:156823d33999 | 1052 | /** |
<> | 149:156823d33999 | 1053 | * @brief Clear Brown-out detector interrupt flag |
<> | 149:156823d33999 | 1054 | * @param None |
<> | 149:156823d33999 | 1055 | * @return None |
<> | 149:156823d33999 | 1056 | * @details This macro clear Brown-out detector interrupt flag. |
<> | 149:156823d33999 | 1057 | */ |
<> | 149:156823d33999 | 1058 | #define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODINTF_Msk) |
<> | 149:156823d33999 | 1059 | |
<> | 149:156823d33999 | 1060 | /** |
<> | 149:156823d33999 | 1061 | * @brief Set Brown-out detector function to normal mode |
<> | 149:156823d33999 | 1062 | * @param None |
<> | 149:156823d33999 | 1063 | * @return None |
<> | 149:156823d33999 | 1064 | * @details This macro set Brown-out detector to normal mode. |
<> | 149:156823d33999 | 1065 | */ |
<> | 149:156823d33999 | 1066 | #define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) |
<> | 149:156823d33999 | 1067 | |
<> | 149:156823d33999 | 1068 | /** |
<> | 149:156823d33999 | 1069 | * @brief Disable Brown-out detector function |
<> | 149:156823d33999 | 1070 | * @param None |
<> | 149:156823d33999 | 1071 | * @return None |
<> | 149:156823d33999 | 1072 | * @details This macro disable Brown-out detector function. |
<> | 149:156823d33999 | 1073 | */ |
<> | 149:156823d33999 | 1074 | #define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) |
<> | 149:156823d33999 | 1075 | |
<> | 149:156823d33999 | 1076 | /** |
<> | 149:156823d33999 | 1077 | * @brief Enable Brown-out detector function |
<> | 149:156823d33999 | 1078 | * @param None |
<> | 149:156823d33999 | 1079 | * @return None |
<> | 149:156823d33999 | 1080 | * @details This macro enable Brown-out detector function. |
<> | 149:156823d33999 | 1081 | */ |
<> | 149:156823d33999 | 1082 | #define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) |
<> | 149:156823d33999 | 1083 | /** |
<> | 149:156823d33999 | 1084 | * @brief Get Brown-out detector interrupt flag |
<> | 149:156823d33999 | 1085 | * @param None |
<> | 149:156823d33999 | 1086 | * @retval 0 Brown-out detect interrupt flag is not set. |
<> | 149:156823d33999 | 1087 | * @retval >=1 Brown-out detect interrupt flag is set. |
<> | 149:156823d33999 | 1088 | * @details This macro get Brown-out detector interrupt flag. |
<> | 149:156823d33999 | 1089 | */ |
<> | 149:156823d33999 | 1090 | #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODINTF_Msk) |
<> | 149:156823d33999 | 1091 | |
<> | 149:156823d33999 | 1092 | /** |
<> | 149:156823d33999 | 1093 | * @brief Get Brown-out detector status |
<> | 149:156823d33999 | 1094 | * @param None |
<> | 149:156823d33999 | 1095 | * @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0. |
<> | 149:156823d33999 | 1096 | * @retval >=1 System voltage is lower than BOD_VL setting. |
<> | 149:156823d33999 | 1097 | * @details This macro get Brown-out detector output status. |
<> | 149:156823d33999 | 1098 | * If the BOD_EN is 0, this function always return 0. |
<> | 149:156823d33999 | 1099 | */ |
<> | 149:156823d33999 | 1100 | #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) |
<> | 149:156823d33999 | 1101 | |
<> | 149:156823d33999 | 1102 | /** |
<> | 149:156823d33999 | 1103 | * @brief Disable Brown-out detector interrupt function |
<> | 149:156823d33999 | 1104 | * @param None |
<> | 149:156823d33999 | 1105 | * @return None |
<> | 149:156823d33999 | 1106 | * @details This macro enable Brown-out detector interrupt function. |
<> | 149:156823d33999 | 1107 | */ |
<> | 149:156823d33999 | 1108 | #define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) |
<> | 149:156823d33999 | 1109 | |
<> | 149:156823d33999 | 1110 | /** |
<> | 149:156823d33999 | 1111 | * @brief Enable Brown-out detector reset function |
<> | 149:156823d33999 | 1112 | * @param None |
<> | 149:156823d33999 | 1113 | * @return None |
<> | 149:156823d33999 | 1114 | * @details This macro enable Brown-out detect reset function. |
<> | 149:156823d33999 | 1115 | */ |
<> | 149:156823d33999 | 1116 | #define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) |
<> | 149:156823d33999 | 1117 | |
<> | 149:156823d33999 | 1118 | |
<> | 149:156823d33999 | 1119 | /** |
<> | 149:156823d33999 | 1120 | * @brief Set Brown-out detector function low power mode |
<> | 149:156823d33999 | 1121 | * @param None |
<> | 149:156823d33999 | 1122 | * @return None |
<> | 149:156823d33999 | 1123 | * @details This macro set Brown-out detector to low power mode. |
<> | 149:156823d33999 | 1124 | */ |
<> | 149:156823d33999 | 1125 | #define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) |
<> | 149:156823d33999 | 1126 | |
<> | 149:156823d33999 | 1127 | /** |
<> | 149:156823d33999 | 1128 | * @brief Set Brown-out detector voltage level |
<> | 149:156823d33999 | 1129 | * @param[in] u32Level is Brown-out voltage level. Including : |
<> | 149:156823d33999 | 1130 | * - \ref SYS_BODCTL_BODVL_4_5V |
<> | 149:156823d33999 | 1131 | * - \ref SYS_BODCTL_BODVL_3_8V |
<> | 149:156823d33999 | 1132 | * - \ref SYS_BODCTL_BODVL_2_7V |
<> | 149:156823d33999 | 1133 | * - \ref SYS_BODCTL_BODVL_2_2V |
<> | 149:156823d33999 | 1134 | * @return None |
<> | 149:156823d33999 | 1135 | * @details This macro set Brown-out detector voltage level. |
<> | 149:156823d33999 | 1136 | */ |
<> | 149:156823d33999 | 1137 | #define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32Level) |
<> | 149:156823d33999 | 1138 | |
<> | 149:156823d33999 | 1139 | /** |
<> | 149:156823d33999 | 1140 | * @brief Get reset source is from Brown-out detector reset |
<> | 149:156823d33999 | 1141 | * @param None |
<> | 149:156823d33999 | 1142 | * @retval 0 Previous reset source is not from Brown-out detector reset |
<> | 149:156823d33999 | 1143 | * @retval >=1 Previous reset source is from Brown-out detector reset |
<> | 149:156823d33999 | 1144 | * @details This macro get previous reset source is from Brown-out detect reset or not. |
<> | 149:156823d33999 | 1145 | */ |
<> | 149:156823d33999 | 1146 | #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) |
<> | 149:156823d33999 | 1147 | |
<> | 149:156823d33999 | 1148 | /** |
<> | 149:156823d33999 | 1149 | * @brief Get reset source is from CPU reset |
<> | 149:156823d33999 | 1150 | * @param None |
<> | 149:156823d33999 | 1151 | * @retval 0 Previous reset source is not from CPU reset |
<> | 149:156823d33999 | 1152 | * @retval >=1 Previous reset source is from CPU reset |
<> | 149:156823d33999 | 1153 | * @details This macro get previous reset source is from CPU reset. |
<> | 149:156823d33999 | 1154 | */ |
<> | 149:156823d33999 | 1155 | #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) |
<> | 149:156823d33999 | 1156 | |
<> | 149:156823d33999 | 1157 | /** |
<> | 149:156823d33999 | 1158 | * @brief Get reset source is from LVR Reset |
<> | 149:156823d33999 | 1159 | * @param None |
<> | 149:156823d33999 | 1160 | * @retval 0 Previous reset source is not from LVR Reset |
<> | 149:156823d33999 | 1161 | * @retval >=1 Previous reset source is from LVR Reset |
<> | 149:156823d33999 | 1162 | * @details This macro get previous reset source is from Power-on Reset. |
<> | 149:156823d33999 | 1163 | */ |
<> | 149:156823d33999 | 1164 | #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) |
<> | 149:156823d33999 | 1165 | |
<> | 149:156823d33999 | 1166 | /** |
<> | 149:156823d33999 | 1167 | * @brief Get reset source is from Power-on Reset |
<> | 149:156823d33999 | 1168 | * @param None |
<> | 149:156823d33999 | 1169 | * @retval 0 Previous reset source is not from Power-on Reset |
<> | 149:156823d33999 | 1170 | * @retval >=1 Previous reset source is from Power-on Reset |
<> | 149:156823d33999 | 1171 | * @details This macro get previous reset source is from Power-on Reset. |
<> | 149:156823d33999 | 1172 | */ |
<> | 149:156823d33999 | 1173 | #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) |
<> | 149:156823d33999 | 1174 | |
<> | 149:156823d33999 | 1175 | /** |
<> | 149:156823d33999 | 1176 | * @brief Get reset source is from reset pin reset |
<> | 149:156823d33999 | 1177 | * @param None |
<> | 149:156823d33999 | 1178 | * @retval 0 Previous reset source is not from reset pin reset |
<> | 149:156823d33999 | 1179 | * @retval >=1 Previous reset source is from reset pin reset |
<> | 149:156823d33999 | 1180 | * @details This macro get previous reset source is from reset pin reset. |
<> | 149:156823d33999 | 1181 | */ |
<> | 149:156823d33999 | 1182 | #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) |
<> | 149:156823d33999 | 1183 | |
<> | 149:156823d33999 | 1184 | /** |
<> | 149:156823d33999 | 1185 | * @brief Get reset source is from system reset |
<> | 149:156823d33999 | 1186 | * @param None |
<> | 149:156823d33999 | 1187 | * @retval 0 Previous reset source is not from system reset |
<> | 149:156823d33999 | 1188 | * @retval >=1 Previous reset source is from system reset |
<> | 149:156823d33999 | 1189 | * @details This macro get previous reset source is from system reset. |
<> | 149:156823d33999 | 1190 | */ |
<> | 149:156823d33999 | 1191 | #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) |
<> | 149:156823d33999 | 1192 | |
<> | 149:156823d33999 | 1193 | /** |
<> | 149:156823d33999 | 1194 | * @brief Get reset source is from window watch dog reset |
<> | 149:156823d33999 | 1195 | * @param None |
<> | 149:156823d33999 | 1196 | * @retval 0 Previous reset source is not from window watch dog reset |
<> | 149:156823d33999 | 1197 | * @retval >=1 Previous reset source is from window watch dog reset |
<> | 149:156823d33999 | 1198 | * @details This macro get previous reset source is from window watch dog reset. |
<> | 149:156823d33999 | 1199 | */ |
<> | 149:156823d33999 | 1200 | #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) |
<> | 149:156823d33999 | 1201 | |
<> | 149:156823d33999 | 1202 | /** |
<> | 149:156823d33999 | 1203 | * @brief Disable Low-Voltage-Reset function |
<> | 149:156823d33999 | 1204 | * @param None |
<> | 149:156823d33999 | 1205 | * @return None |
<> | 149:156823d33999 | 1206 | * @details This macro disable Low-Voltage-Reset function. |
<> | 149:156823d33999 | 1207 | */ |
<> | 149:156823d33999 | 1208 | #define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) |
<> | 149:156823d33999 | 1209 | |
<> | 149:156823d33999 | 1210 | /** |
<> | 149:156823d33999 | 1211 | * @brief Enable Low-Voltage-Reset function |
<> | 149:156823d33999 | 1212 | * @param None |
<> | 149:156823d33999 | 1213 | * @return None |
<> | 149:156823d33999 | 1214 | * @details This macro enable Low-Voltage-Reset function. |
<> | 149:156823d33999 | 1215 | */ |
<> | 149:156823d33999 | 1216 | #define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) |
<> | 149:156823d33999 | 1217 | |
<> | 149:156823d33999 | 1218 | /** |
<> | 149:156823d33999 | 1219 | * @brief Disable Power-on Reset function |
<> | 149:156823d33999 | 1220 | * @param None |
<> | 149:156823d33999 | 1221 | * @return None |
<> | 149:156823d33999 | 1222 | * @details This macro disable Power-on Reset function. |
<> | 149:156823d33999 | 1223 | */ |
<> | 149:156823d33999 | 1224 | #define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5) |
<> | 149:156823d33999 | 1225 | |
<> | 149:156823d33999 | 1226 | /** |
<> | 149:156823d33999 | 1227 | * @brief Enable Power-on Reset function |
<> | 149:156823d33999 | 1228 | * @param None |
<> | 149:156823d33999 | 1229 | * @return None |
<> | 149:156823d33999 | 1230 | * @details This macro enable Power-on Reset function. |
<> | 149:156823d33999 | 1231 | */ |
<> | 149:156823d33999 | 1232 | #define SYS_ENABLE_POR() (SYS->PORCTL = 0) |
<> | 149:156823d33999 | 1233 | |
<> | 149:156823d33999 | 1234 | |
<> | 149:156823d33999 | 1235 | /** |
<> | 149:156823d33999 | 1236 | * @brief Clear reset source flag |
<> | 149:156823d33999 | 1237 | * @param[in] u32RstSrc is reset source. Including: |
<> | 149:156823d33999 | 1238 | * - \ref SYS_RSTSTS_PORF_Msk |
<> | 149:156823d33999 | 1239 | * - \ref SYS_RSTSTS_PINRF_Msk |
<> | 149:156823d33999 | 1240 | * - \ref SYS_RSTSTS_WDTRF_Msk |
<> | 149:156823d33999 | 1241 | * - \ref SYS_RSTSTS_LVRF_Msk |
<> | 149:156823d33999 | 1242 | * - \ref SYS_RSTSTS_BODRF_Msk |
<> | 149:156823d33999 | 1243 | * - \ref SYS_RSTSTS_SYSRF_Msk |
<> | 149:156823d33999 | 1244 | * - \ref SYS_RSTSTS_CPURF_Msk |
<> | 149:156823d33999 | 1245 | * @return None |
<> | 149:156823d33999 | 1246 | * @details This macro clear reset source flag. |
<> | 149:156823d33999 | 1247 | */ |
<> | 149:156823d33999 | 1248 | #define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSTS = u32RstSrc ) |
<> | 149:156823d33999 | 1249 | |
<> | 149:156823d33999 | 1250 | void SYS_ClearResetSrc(uint32_t u32Src); |
<> | 149:156823d33999 | 1251 | uint32_t SYS_GetBODStatus(void); |
<> | 149:156823d33999 | 1252 | uint32_t SYS_GetResetSrc(void); |
<> | 149:156823d33999 | 1253 | uint32_t SYS_IsRegLocked(void); |
<> | 149:156823d33999 | 1254 | void SYS_LockReg(void); |
<> | 149:156823d33999 | 1255 | void SYS_UnlockReg(void); |
<> | 149:156823d33999 | 1256 | uint32_t SYS_ReadPDID(void); |
<> | 149:156823d33999 | 1257 | void SYS_ResetChip(void); |
<> | 149:156823d33999 | 1258 | void SYS_ResetCPU(void); |
<> | 149:156823d33999 | 1259 | void SYS_ResetModule(uint32_t u32ModuleIndex); |
<> | 149:156823d33999 | 1260 | void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); |
<> | 149:156823d33999 | 1261 | void SYS_DisableBOD(void); |
<> | 149:156823d33999 | 1262 | |
<> | 149:156823d33999 | 1263 | /*@}*/ /* end of group NUC472_442_SYS_EXPORTED_FUNCTIONS */ |
<> | 149:156823d33999 | 1264 | |
<> | 149:156823d33999 | 1265 | /*@}*/ /* end of group NUC472_442_SYS_Driver */ |
<> | 149:156823d33999 | 1266 | |
<> | 149:156823d33999 | 1267 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
<> | 149:156823d33999 | 1268 | |
<> | 149:156823d33999 | 1269 | #ifdef __cplusplus |
<> | 149:156823d33999 | 1270 | } |
<> | 149:156823d33999 | 1271 | #endif |
<> | 149:156823d33999 | 1272 | |
<> | 149:156823d33999 | 1273 | #endif //__SYS_H__ |
<> | 149:156823d33999 | 1274 | |
<> | 149:156823d33999 | 1275 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |