Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 12 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 13 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 * 3. Neither the name of ARM Limited nor the names of its contributors
<> 144:ef7eb2e8f9f7 15 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 16 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 28 *******************************************************************************
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include <stddef.h>
<> 144:ef7eb2e8f9f7 32 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 33 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 34 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 35 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #define EDGE_NONE (0)
<> 144:ef7eb2e8f9f7 38 #define EDGE_RISE (1)
<> 144:ef7eb2e8f9f7 39 #define EDGE_FALL (2)
<> 144:ef7eb2e8f9f7 40 #define EDGE_BOTH (3)
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 static uint32_t channel_ids[4][16];
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 47 extern "C"{
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num);
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 void PORT0_Handler(void)
<> 144:ef7eb2e8f9f7 52 {
<> 144:ef7eb2e8f9f7 53 port_generic_handler(GPIOA, 0);
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 void PORT1_Handler(void)
<> 144:ef7eb2e8f9f7 57 {
<> 144:ef7eb2e8f9f7 58 port_generic_handler(GPIOB, 1);
<> 144:ef7eb2e8f9f7 59 }
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 void PORT2_Handler(void)
<> 144:ef7eb2e8f9f7 62 {
<> 144:ef7eb2e8f9f7 63 port_generic_handler(GPIOC, 2);
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 void PORT3_Handler(void)
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 port_generic_handler(GPIOD, 3);
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num)
<> 144:ef7eb2e8f9f7 72 {
<> 144:ef7eb2e8f9f7 73 int i = 0;
<> 144:ef7eb2e8f9f7 74 int loop = 16;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 if(GPIOx == GPIOD) loop = 5;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 for(i=0; i<loop; i++)
<> 144:ef7eb2e8f9f7 79 {
<> 144:ef7eb2e8f9f7 80 if(GPIOx->Interrupt.INTSTATUS & (1 << i))
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 GPIOx->Interrupt.INTCLEAR |= (1 << i);
<> 144:ef7eb2e8f9f7 83 if(GPIOx->INTPOLSET >> i) //rising
<> 144:ef7eb2e8f9f7 84 irq_handler(channel_ids[port_num][i], IRQ_RISE);
<> 144:ef7eb2e8f9f7 85 else //falling
<> 144:ef7eb2e8f9f7 86 irq_handler(channel_ids[port_num][i], IRQ_FALL);
<> 144:ef7eb2e8f9f7 87 }
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89 }
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93 #endif
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 97 {
<> 144:ef7eb2e8f9f7 98 obj->port_num = WIZ_PORT(pin);
<> 144:ef7eb2e8f9f7 99 obj->pin_num = WIZ_PIN_NUM(pin);
<> 144:ef7eb2e8f9f7 100 obj->pin_index = WIZ_PIN_INDEX(pin);
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 if (pin == NC) return -1;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 if(obj->port_num == 0)
<> 144:ef7eb2e8f9f7 105 obj->irq_n = PORT0_IRQn;
<> 144:ef7eb2e8f9f7 106 else if(obj->port_num == 1)
<> 144:ef7eb2e8f9f7 107 obj->irq_n = PORT1_IRQn;
<> 144:ef7eb2e8f9f7 108 else if(obj->port_num == 2)
<> 144:ef7eb2e8f9f7 109 obj->irq_n = PORT2_IRQn;
<> 144:ef7eb2e8f9f7 110 else
<> 144:ef7eb2e8f9f7 111 obj->irq_n = PORT3_IRQn;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 //obj->event = EDGE_FALL;
<> 144:ef7eb2e8f9f7 114 obj->pin = pin;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // Enable EXTI interrupt
<> 144:ef7eb2e8f9f7 117 NVIC_EnableIRQ(obj->irq_n);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 channel_ids[obj->port_num][obj->pin_num] = id;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 irq_handler = handler;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 return 0;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 void gpio_irq_free(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 127 {
<> 144:ef7eb2e8f9f7 128 channel_ids[obj->port_num][obj->pin_num] = 0;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 obj->event = EDGE_NONE;
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 144:ef7eb2e8f9f7 134 {
<> 144:ef7eb2e8f9f7 135 GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(obj->port_num);
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 if (enable) {
<> 144:ef7eb2e8f9f7 138 if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 139 gpio->INTPOLSET |= obj->pin_index;
<> 144:ef7eb2e8f9f7 140 obj->event = EDGE_RISE;
<> 144:ef7eb2e8f9f7 141 obj->rise_null = 0;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143 else if (event == IRQ_FALL) {
<> 144:ef7eb2e8f9f7 144 gpio->INTPOLSET &= ~obj->pin_index;
<> 144:ef7eb2e8f9f7 145 obj->event = EDGE_FALL;
<> 144:ef7eb2e8f9f7 146 obj->fall_null = 0;
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148 gpio->INTTYPESET |= obj->pin_index;
<> 144:ef7eb2e8f9f7 149 gpio->INTENSET |= obj->pin_index;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 } else {
<> 144:ef7eb2e8f9f7 153 if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 154 obj->rise_null = 1;
<> 144:ef7eb2e8f9f7 155 if(obj->fall_null)
<> 144:ef7eb2e8f9f7 156 gpio->INTENCLR |= obj->pin_index;
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158 else if (event == IRQ_FALL) {
<> 144:ef7eb2e8f9f7 159 obj->fall_null = 1;
<> 144:ef7eb2e8f9f7 160 if(obj->rise_null)
<> 144:ef7eb2e8f9f7 161 gpio->INTENCLR |= obj->pin_index;
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 void gpio_irq_enable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 NVIC_EnableIRQ(obj->irq_n);
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 void gpio_irq_disable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 NVIC_DisableIRQ(obj->irq_n);
<> 144:ef7eb2e8f9f7 174 obj->event = EDGE_NONE;
<> 144:ef7eb2e8f9f7 175 }