Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F0/us_ticker.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2014, STMicroelectronics
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 6 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 9 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 11 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 12 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 13 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 14 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 15 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 20 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 23 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 24 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 27 */
<> 144:ef7eb2e8f9f7 28 #include <stddef.h>
<> 144:ef7eb2e8f9f7 29 #include "us_ticker_api.h"
<> 144:ef7eb2e8f9f7 30 #include "PeripheralNames.h"
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #if defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB)
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 // Timer selection
<> 144:ef7eb2e8f9f7 36 #define TIM_MST TIM1
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 static TIM_HandleTypeDef TimMasterHandle;
<> 144:ef7eb2e8f9f7 39 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 volatile uint32_t SlaveCounter = 0;
<> 144:ef7eb2e8f9f7 42 volatile uint32_t oc_int_part = 0;
<> 144:ef7eb2e8f9f7 43 volatile uint16_t oc_rem_part = 0;
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 void set_compare(uint16_t count) {
<> 144:ef7eb2e8f9f7 46 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 47 // Set new output compare value
<> 144:ef7eb2e8f9f7 48 __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count);
<> 144:ef7eb2e8f9f7 49 // Enable IT
<> 144:ef7eb2e8f9f7 50 __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 51 }
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 void us_ticker_init(void) {
<> 144:ef7eb2e8f9f7 54 if (us_ticker_inited) return;
<> 144:ef7eb2e8f9f7 55 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 HAL_InitTick(0); // The passed value is not used
<> 144:ef7eb2e8f9f7 58 }
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 uint32_t us_ticker_read() {
<> 144:ef7eb2e8f9f7 61 uint32_t counter, counter2;
<> 144:ef7eb2e8f9f7 62 if (!us_ticker_inited) us_ticker_init();
<> 144:ef7eb2e8f9f7 63 // A situation might appear when Master overflows right after Slave is read and before the
<> 144:ef7eb2e8f9f7 64 // new (overflowed) value of Master is read. Which would make the code below consider the
<> 144:ef7eb2e8f9f7 65 // previous (incorrect) value of Slave and the new value of Master, which would return a
<> 144:ef7eb2e8f9f7 66 // value in the past. Avoid this by computing consecutive values of the timer until they
<> 144:ef7eb2e8f9f7 67 // are properly ordered.
<> 144:ef7eb2e8f9f7 68 counter = (uint32_t)(SlaveCounter << 16);
<> 144:ef7eb2e8f9f7 69 counter += TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 70 while (1) {
<> 144:ef7eb2e8f9f7 71 counter2 = (uint32_t)(SlaveCounter << 16);
<> 144:ef7eb2e8f9f7 72 counter2 += TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 73 if (counter2 > counter) {
<> 144:ef7eb2e8f9f7 74 break;
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76 counter = counter2;
<> 144:ef7eb2e8f9f7 77 }
<> 144:ef7eb2e8f9f7 78 return counter2;
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 void us_ticker_set_interrupt(timestamp_t timestamp) {
<> 144:ef7eb2e8f9f7 82 int delta = (int)((uint32_t)timestamp - us_ticker_read());
<> 144:ef7eb2e8f9f7 83 uint16_t cval = TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 if (delta <= 0) { // This event was in the past
<> 144:ef7eb2e8f9f7 86 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 87 } else {
<> 144:ef7eb2e8f9f7 88 oc_int_part = (uint32_t)(delta >> 16);
<> 144:ef7eb2e8f9f7 89 oc_rem_part = (uint16_t)(delta & 0xFFFF);
<> 144:ef7eb2e8f9f7 90 if (oc_rem_part <= (0xFFFF - cval)) {
<> 144:ef7eb2e8f9f7 91 set_compare(cval + oc_rem_part);
<> 144:ef7eb2e8f9f7 92 oc_rem_part = 0;
<> 144:ef7eb2e8f9f7 93 } else {
<> 144:ef7eb2e8f9f7 94 set_compare(0xFFFF);
<> 144:ef7eb2e8f9f7 95 oc_rem_part = oc_rem_part - (0xFFFF - cval);
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 void us_ticker_disable_interrupt(void) {
<> 144:ef7eb2e8f9f7 101 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 102 __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 void us_ticker_clear_interrupt(void) {
<> 144:ef7eb2e8f9f7 106 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 107 if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
<> 144:ef7eb2e8f9f7 108 __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110 }
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #elif defined (TARGET_STM32F051R8)
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 // Timer selection:
<> 144:ef7eb2e8f9f7 115 #define TIM_MST TIM1
<> 144:ef7eb2e8f9f7 116 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn
<> 144:ef7eb2e8f9f7 117 #define TIM_MST_OC_IRQ TIM1_CC_IRQn
<> 144:ef7eb2e8f9f7 118 #define TIM_MST_RCC __TIM1_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 static TIM_HandleTypeDef TimMasterHandle;
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 124 static volatile uint32_t SlaveCounter = 0;
<> 144:ef7eb2e8f9f7 125 static volatile uint32_t oc_int_part = 0;
<> 144:ef7eb2e8f9f7 126 static volatile uint16_t oc_rem_part = 0;
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 void set_compare(uint16_t count) {
<> 144:ef7eb2e8f9f7 129 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 // Set new output compare value
<> 144:ef7eb2e8f9f7 132 __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count);
<> 144:ef7eb2e8f9f7 133 // Enable IT
<> 144:ef7eb2e8f9f7 134 __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 // Used to increment the slave counter
<> 144:ef7eb2e8f9f7 138 static void tim_update_irq_handler(void) {
<> 144:ef7eb2e8f9f7 139 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 // Clear Update interrupt flag
<> 144:ef7eb2e8f9f7 142 if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
<> 144:ef7eb2e8f9f7 143 __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
<> 144:ef7eb2e8f9f7 144 SlaveCounter++;
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 // Used by interrupt system
<> 144:ef7eb2e8f9f7 149 static void tim_oc_irq_handler(void) {
<> 144:ef7eb2e8f9f7 150 uint16_t cval = TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 151 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 // Clear CC1 interrupt flag
<> 144:ef7eb2e8f9f7 154 if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
<> 144:ef7eb2e8f9f7 155 __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
<> 144:ef7eb2e8f9f7 156 }
<> 144:ef7eb2e8f9f7 157 if (oc_rem_part > 0) {
<> 144:ef7eb2e8f9f7 158 set_compare(oc_rem_part); // Finish the remaining time left
<> 144:ef7eb2e8f9f7 159 oc_rem_part = 0;
<> 144:ef7eb2e8f9f7 160 } else {
<> 144:ef7eb2e8f9f7 161 if (oc_int_part > 0) {
<> 144:ef7eb2e8f9f7 162 set_compare(0xFFFF);
<> 144:ef7eb2e8f9f7 163 oc_rem_part = cval; // To finish the counter loop the next time
<> 144:ef7eb2e8f9f7 164 oc_int_part--;
<> 144:ef7eb2e8f9f7 165 } else {
<> 144:ef7eb2e8f9f7 166 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 void us_ticker_init(void) {
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 if (us_ticker_inited) return;
<> 144:ef7eb2e8f9f7 175 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 // Enable timer clock
<> 144:ef7eb2e8f9f7 178 TIM_MST_RCC;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 // Configure time base
<> 144:ef7eb2e8f9f7 181 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 182 TimMasterHandle.Init.Period = 0xFFFF;
<> 144:ef7eb2e8f9f7 183 TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
<> 144:ef7eb2e8f9f7 184 TimMasterHandle.Init.ClockDivision = 0;
<> 144:ef7eb2e8f9f7 185 TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
<> 144:ef7eb2e8f9f7 186 HAL_TIM_Base_Init(&TimMasterHandle);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 // Configure interrupts
<> 144:ef7eb2e8f9f7 189 __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 // Update interrupt used for 32-bit counter
<> 144:ef7eb2e8f9f7 192 NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler);
<> 144:ef7eb2e8f9f7 193 NVIC_EnableIRQ(TIM_MST_UP_IRQ);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 // Output compare interrupt used for timeout feature
<> 144:ef7eb2e8f9f7 196 NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler);
<> 144:ef7eb2e8f9f7 197 NVIC_EnableIRQ(TIM_MST_OC_IRQ);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 // Enable timer
<> 144:ef7eb2e8f9f7 200 HAL_TIM_Base_Start(&TimMasterHandle);
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 uint32_t us_ticker_read() {
<> 144:ef7eb2e8f9f7 204 uint32_t counter, counter2;
<> 144:ef7eb2e8f9f7 205 if (!us_ticker_inited) us_ticker_init();
<> 144:ef7eb2e8f9f7 206 // A situation might appear when Master overflows right after Slave is read and before the
<> 144:ef7eb2e8f9f7 207 // new (overflowed) value of Master is read. Which would make the code below consider the
<> 144:ef7eb2e8f9f7 208 // previous (incorrect) value of Slave and the new value of Master, which would return a
<> 144:ef7eb2e8f9f7 209 // value in the past. Avoid this by computing consecutive values of the timer until they
<> 144:ef7eb2e8f9f7 210 // are properly ordered.
<> 144:ef7eb2e8f9f7 211 counter = (uint32_t)(SlaveCounter << 16);
<> 144:ef7eb2e8f9f7 212 counter += TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 213 while (1) {
<> 144:ef7eb2e8f9f7 214 counter2 = (uint32_t)(SlaveCounter << 16);
<> 144:ef7eb2e8f9f7 215 counter2 += TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 216 if (counter2 > counter) {
<> 144:ef7eb2e8f9f7 217 break;
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219 counter = counter2;
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221 return counter2;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 void us_ticker_set_interrupt(timestamp_t timestamp) {
<> 144:ef7eb2e8f9f7 225 int delta = (int)((uint32_t)timestamp - us_ticker_read());
<> 144:ef7eb2e8f9f7 226 uint16_t cval = TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 if (delta <= 0) { // This event was in the past
<> 144:ef7eb2e8f9f7 229 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 230 } else {
<> 144:ef7eb2e8f9f7 231 oc_int_part = (uint32_t)(delta >> 16);
<> 144:ef7eb2e8f9f7 232 oc_rem_part = (uint16_t)(delta & 0xFFFF);
<> 144:ef7eb2e8f9f7 233 if (oc_rem_part <= (0xFFFF - cval)) {
<> 144:ef7eb2e8f9f7 234 set_compare(cval + oc_rem_part);
<> 144:ef7eb2e8f9f7 235 oc_rem_part = 0;
<> 144:ef7eb2e8f9f7 236 } else {
<> 144:ef7eb2e8f9f7 237 set_compare(0xFFFF);
<> 144:ef7eb2e8f9f7 238 oc_rem_part = oc_rem_part - (0xFFFF - cval);
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 void us_ticker_disable_interrupt(void) {
<> 144:ef7eb2e8f9f7 244 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 245 __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 void us_ticker_clear_interrupt(void) {
<> 144:ef7eb2e8f9f7 249 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 250 if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
<> 144:ef7eb2e8f9f7 251 __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 #else
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 // 32-bit timer selection
<> 144:ef7eb2e8f9f7 258 #define TIM_MST TIM2
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 static TIM_HandleTypeDef TimMasterHandle;
<> 144:ef7eb2e8f9f7 261 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 void us_ticker_init(void) {
<> 144:ef7eb2e8f9f7 264 if (us_ticker_inited) return;
<> 144:ef7eb2e8f9f7 265 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 HAL_InitTick(0); // The passed value is not used
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 uint32_t us_ticker_read() {
<> 144:ef7eb2e8f9f7 273 if (!us_ticker_inited) us_ticker_init();
<> 144:ef7eb2e8f9f7 274 return TIM_MST->CNT;
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 void us_ticker_set_interrupt(timestamp_t timestamp) {
<> 144:ef7eb2e8f9f7 278 // Set new output compare value
<> 144:ef7eb2e8f9f7 279 __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp);
<> 144:ef7eb2e8f9f7 280 // Enable IT
<> 144:ef7eb2e8f9f7 281 __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 void us_ticker_disable_interrupt(void) {
<> 144:ef7eb2e8f9f7 285 __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 void us_ticker_clear_interrupt(void) {
<> 144:ef7eb2e8f9f7 289 __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 #endif