Fawwaz Nadzmy / mbed-STM

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer Extended peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The Timer Extended features include:
<> 144:ef7eb2e8f9f7 21 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 22 (++) Output Compare
<> 144:ef7eb2e8f9f7 23 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 24 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 25 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 26 interconnect several timers together.
<> 144:ef7eb2e8f9f7 27 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 28 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 29 positioning purposes
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 32 ==============================================================================
<> 144:ef7eb2e8f9f7 33 [..]
<> 144:ef7eb2e8f9f7 34 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 35 depending from feature used :
<> 144:ef7eb2e8f9f7 36 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 37 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 38 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 39 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 42 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 43 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 44 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 45 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 46 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 49 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 50 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 51 any start function.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 54 initialization function of this driver:
<> 144:ef7eb2e8f9f7 55 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 56 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 57 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 58 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 59 the commutation event).
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 62 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 64 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 65 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 @endverbatim
<> 144:ef7eb2e8f9f7 69 ******************************************************************************
<> 144:ef7eb2e8f9f7 70 * @attention
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 75 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 76 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 77 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 78 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 79 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 80 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 81 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 82 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 83 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 88 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 92 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 93 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 94 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 107 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 134 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 @verbatim
<> 144:ef7eb2e8f9f7 137 ==============================================================================
<> 144:ef7eb2e8f9f7 138 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 139 ==============================================================================
<> 144:ef7eb2e8f9f7 140 [..]
<> 144:ef7eb2e8f9f7 141 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 142 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 143 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 144 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 145 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 146 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 147 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 148 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 149 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 @endverbatim
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 156 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 157 * @param sConfig : TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 158 * @retval HAL status
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 165 if(htim == NULL)
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 175 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 180 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 183 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 187 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 190 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 193 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 196 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 197 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 198 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 201 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 204 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 205 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 208 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 209 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 212 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 213 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 214 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 215 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 216 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 217 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 218 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 223 register to 101 */
<> 144:ef7eb2e8f9f7 224 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 225 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 228 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 return HAL_OK;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 235 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 236 * @retval HAL status
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 /* Check the parameters */
<> 144:ef7eb2e8f9f7 241 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 246 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 249 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Change TIM state */
<> 144:ef7eb2e8f9f7 252 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Release Lock */
<> 144:ef7eb2e8f9f7 255 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 return HAL_OK;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 262 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 263 * @retval None
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 268 UNUSED(htim);
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 271 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /**
<> 144:ef7eb2e8f9f7 276 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 277 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 278 * @retval None
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 283 UNUSED(htim);
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 286 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 292 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 293 * @retval HAL status
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Check the parameters */
<> 144:ef7eb2e8f9f7 298 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 301 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 302 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 305 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Return function status */
<> 144:ef7eb2e8f9f7 308 return HAL_OK;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 313 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 314 * @retval HAL status
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 /* Check the parameters */
<> 144:ef7eb2e8f9f7 319 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 322 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 323 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 326 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Return function status */
<> 144:ef7eb2e8f9f7 329 return HAL_OK;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 334 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 335 * @retval HAL status
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 /* Check the parameters */
<> 144:ef7eb2e8f9f7 340 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 343 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 346 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 347 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 350 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Return function status */
<> 144:ef7eb2e8f9f7 353 return HAL_OK;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 358 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 359 * @retval HAL status
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 /* Check the parameters */
<> 144:ef7eb2e8f9f7 364 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 367 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 368 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 371 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 374 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Return function status */
<> 144:ef7eb2e8f9f7 377 return HAL_OK;
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 382 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 383 * @param pData : The destination Buffer address.
<> 144:ef7eb2e8f9f7 384 * @param Length : The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 385 * @retval HAL status
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Check the parameters */
<> 144:ef7eb2e8f9f7 390 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402 else
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 408 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 409 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 412 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 413 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 414 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Enable the DMA channel for Capture 1*/
<> 144:ef7eb2e8f9f7 417 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 420 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 423 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Return function status */
<> 144:ef7eb2e8f9f7 426 return HAL_OK;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 431 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 432 * @retval HAL status
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 /* Check the parameters */
<> 144:ef7eb2e8f9f7 437 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 440 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 441 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 445 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 448 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Return function status */
<> 144:ef7eb2e8f9f7 451 return HAL_OK;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @}
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 459 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 460 *
<> 144:ef7eb2e8f9f7 461 @verbatim
<> 144:ef7eb2e8f9f7 462 ==============================================================================
<> 144:ef7eb2e8f9f7 463 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 464 ==============================================================================
<> 144:ef7eb2e8f9f7 465 [..]
<> 144:ef7eb2e8f9f7 466 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 467 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 468 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 469 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 470 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 471 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 472 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 @endverbatim
<> 144:ef7eb2e8f9f7 475 * @{
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 480 * output.
<> 144:ef7eb2e8f9f7 481 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 482 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 483 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 484 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 485 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 486 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 487 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 488 * @retval HAL status
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 /* Check the parameters */
<> 144:ef7eb2e8f9f7 493 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 496 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 499 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 502 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Return function status */
<> 144:ef7eb2e8f9f7 505 return HAL_OK;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 510 * output.
<> 144:ef7eb2e8f9f7 511 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 512 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 513 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 514 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 515 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 516 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 517 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 518 * @retval HAL status
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 /* Check the parameters */
<> 144:ef7eb2e8f9f7 523 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 526 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 529 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 532 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Return function status */
<> 144:ef7eb2e8f9f7 535 return HAL_OK;
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /**
<> 144:ef7eb2e8f9f7 539 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 540 * on the complementary output.
<> 144:ef7eb2e8f9f7 541 * @param htim : TIM OC handle
<> 144:ef7eb2e8f9f7 542 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 543 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 546 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 547 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 548 * @retval HAL status
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 /* Check the parameters */
<> 144:ef7eb2e8f9f7 553 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 switch (Channel)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 560 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562 break;
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 567 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569 break;
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 574 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 break;
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 581 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 break;
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 default:
<> 144:ef7eb2e8f9f7 586 break;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 590 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 593 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 596 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 599 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Return function status */
<> 144:ef7eb2e8f9f7 602 return HAL_OK;
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /**
<> 144:ef7eb2e8f9f7 606 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 607 * on the complementary output.
<> 144:ef7eb2e8f9f7 608 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 609 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 610 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 611 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 612 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 613 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 614 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 615 * @retval HAL status
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Check the parameters */
<> 144:ef7eb2e8f9f7 622 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 switch (Channel)
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 629 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631 break;
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 636 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638 break;
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 643 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 644 }
<> 144:ef7eb2e8f9f7 645 break;
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 650 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652 break;
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 default:
<> 144:ef7eb2e8f9f7 655 break;
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 659 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 662 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 663 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 669 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 672 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Return function status */
<> 144:ef7eb2e8f9f7 675 return HAL_OK;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /**
<> 144:ef7eb2e8f9f7 679 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 680 * on the complementary output.
<> 144:ef7eb2e8f9f7 681 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 682 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 683 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 684 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 685 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 686 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 687 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 688 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 689 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 690 * @retval HAL status
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 /* Check the parameters */
<> 144:ef7eb2e8f9f7 695 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 698 {
<> 144:ef7eb2e8f9f7 699 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707 else
<> 144:ef7eb2e8f9f7 708 {
<> 144:ef7eb2e8f9f7 709 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712 switch (Channel)
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 717 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 720 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 723 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 726 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 break;
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 733 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 736 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 739 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 742 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744 break;
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 749 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 752 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 755 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 758 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760 break;
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 763 {
<> 144:ef7eb2e8f9f7 764 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 765 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 768 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 771 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 774 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 775 }
<> 144:ef7eb2e8f9f7 776 break;
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 default:
<> 144:ef7eb2e8f9f7 779 break;
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 783 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 786 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 789 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Return function status */
<> 144:ef7eb2e8f9f7 792 return HAL_OK;
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 797 * on the complementary output.
<> 144:ef7eb2e8f9f7 798 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 799 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 800 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 801 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 802 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 803 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 804 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 805 * @retval HAL status
<> 144:ef7eb2e8f9f7 806 */
<> 144:ef7eb2e8f9f7 807 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 /* Check the parameters */
<> 144:ef7eb2e8f9f7 810 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 switch (Channel)
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 817 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 break;
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 824 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 break;
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 831 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833 break;
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 838 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 break;
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 default:
<> 144:ef7eb2e8f9f7 843 break;
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 847 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 850 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 853 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Change the htim state */
<> 144:ef7eb2e8f9f7 856 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Return function status */
<> 144:ef7eb2e8f9f7 859 return HAL_OK;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /**
<> 144:ef7eb2e8f9f7 863 * @}
<> 144:ef7eb2e8f9f7 864 */
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 867 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 868 *
<> 144:ef7eb2e8f9f7 869 @verbatim
<> 144:ef7eb2e8f9f7 870 ==============================================================================
<> 144:ef7eb2e8f9f7 871 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 872 ==============================================================================
<> 144:ef7eb2e8f9f7 873 [..]
<> 144:ef7eb2e8f9f7 874 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 875 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 876 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 877 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 878 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 879 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 880 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 881 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 882 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 883 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 884 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 885 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 886 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 887 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 888 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 889 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 890 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 @endverbatim
<> 144:ef7eb2e8f9f7 893 * @{
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 898 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 899 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 900 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 901 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 902 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 903 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 904 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 905 * @retval HAL status
<> 144:ef7eb2e8f9f7 906 */
<> 144:ef7eb2e8f9f7 907 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 /* Check the parameters */
<> 144:ef7eb2e8f9f7 910 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 913 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 916 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 919 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Return function status */
<> 144:ef7eb2e8f9f7 922 return HAL_OK;
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /**
<> 144:ef7eb2e8f9f7 926 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 927 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 928 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 929 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 930 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 931 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 932 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 933 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 934 * @retval HAL status
<> 144:ef7eb2e8f9f7 935 */
<> 144:ef7eb2e8f9f7 936 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 /* Check the parameters */
<> 144:ef7eb2e8f9f7 939 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 942 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 945 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 948 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Return function status */
<> 144:ef7eb2e8f9f7 951 return HAL_OK;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
<> 144:ef7eb2e8f9f7 955 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 956 * complementary output.
<> 144:ef7eb2e8f9f7 957 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 958 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 959 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 960 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 961 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 962 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 963 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 964 * @retval HAL status
<> 144:ef7eb2e8f9f7 965 */
<> 144:ef7eb2e8f9f7 966 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 967 {
<> 144:ef7eb2e8f9f7 968 /* Check the parameters */
<> 144:ef7eb2e8f9f7 969 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 switch (Channel)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 974 {
<> 144:ef7eb2e8f9f7 975 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 976 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 977 }
<> 144:ef7eb2e8f9f7 978 break;
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 981 {
<> 144:ef7eb2e8f9f7 982 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 983 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 984 }
<> 144:ef7eb2e8f9f7 985 break;
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 990 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992 break;
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 997 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999 break;
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 default:
<> 144:ef7eb2e8f9f7 1002 break;
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1006 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1009 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1012 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1015 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /* Return function status */
<> 144:ef7eb2e8f9f7 1018 return HAL_OK;
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /**
<> 144:ef7eb2e8f9f7 1022 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1023 * complementary output.
<> 144:ef7eb2e8f9f7 1024 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1025 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1026 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1027 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1028 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1029 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1030 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1031 * @retval HAL status
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1034 {
<> 144:ef7eb2e8f9f7 1035 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1038 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 switch (Channel)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1045 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1046 }
<> 144:ef7eb2e8f9f7 1047 break;
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1052 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054 break;
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1059 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1060 }
<> 144:ef7eb2e8f9f7 1061 break;
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1064 {
<> 144:ef7eb2e8f9f7 1065 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1066 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1067 }
<> 144:ef7eb2e8f9f7 1068 break;
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 default:
<> 144:ef7eb2e8f9f7 1071 break;
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1075 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1078 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1079 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1085 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1088 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* Return function status */
<> 144:ef7eb2e8f9f7 1091 return HAL_OK;
<> 144:ef7eb2e8f9f7 1092 }
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /**
<> 144:ef7eb2e8f9f7 1095 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1096 * complementary output
<> 144:ef7eb2e8f9f7 1097 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1098 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1099 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1100 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1101 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1102 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1103 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1104 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 1105 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1106 * @retval HAL status
<> 144:ef7eb2e8f9f7 1107 */
<> 144:ef7eb2e8f9f7 1108 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1111 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1114 {
<> 144:ef7eb2e8f9f7 1115 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1120 {
<> 144:ef7eb2e8f9f7 1121 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123 else
<> 144:ef7eb2e8f9f7 1124 {
<> 144:ef7eb2e8f9f7 1125 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128 switch (Channel)
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1131 {
<> 144:ef7eb2e8f9f7 1132 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1133 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1136 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1139 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1142 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144 break;
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1147 {
<> 144:ef7eb2e8f9f7 1148 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1149 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1152 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1155 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1158 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160 break;
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1165 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1168 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1171 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1174 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1175 }
<> 144:ef7eb2e8f9f7 1176 break;
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1181 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1184 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1187 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1190 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 break;
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 default:
<> 144:ef7eb2e8f9f7 1195 break;
<> 144:ef7eb2e8f9f7 1196 }
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1199 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1202 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1205 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /* Return function status */
<> 144:ef7eb2e8f9f7 1208 return HAL_OK;
<> 144:ef7eb2e8f9f7 1209 }
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /**
<> 144:ef7eb2e8f9f7 1212 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1213 * output
<> 144:ef7eb2e8f9f7 1214 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1215 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1216 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1217 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1218 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1219 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1220 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1221 * @retval HAL status
<> 144:ef7eb2e8f9f7 1222 */
<> 144:ef7eb2e8f9f7 1223 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1224 {
<> 144:ef7eb2e8f9f7 1225 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1226 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 switch (Channel)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1231 {
<> 144:ef7eb2e8f9f7 1232 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1233 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1234 }
<> 144:ef7eb2e8f9f7 1235 break;
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1238 {
<> 144:ef7eb2e8f9f7 1239 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1240 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1241 }
<> 144:ef7eb2e8f9f7 1242 break;
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1247 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1248 }
<> 144:ef7eb2e8f9f7 1249 break;
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1252 {
<> 144:ef7eb2e8f9f7 1253 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1254 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1255 }
<> 144:ef7eb2e8f9f7 1256 break;
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 default:
<> 144:ef7eb2e8f9f7 1259 break;
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1263 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1266 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1269 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1272 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /* Return function status */
<> 144:ef7eb2e8f9f7 1275 return HAL_OK;
<> 144:ef7eb2e8f9f7 1276 }
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /**
<> 144:ef7eb2e8f9f7 1279 * @}
<> 144:ef7eb2e8f9f7 1280 */
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1283 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1284 *
<> 144:ef7eb2e8f9f7 1285 @verbatim
<> 144:ef7eb2e8f9f7 1286 ==============================================================================
<> 144:ef7eb2e8f9f7 1287 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1288 ==============================================================================
<> 144:ef7eb2e8f9f7 1289 [..]
<> 144:ef7eb2e8f9f7 1290 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1291 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1292 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1293 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1294 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 @endverbatim
<> 144:ef7eb2e8f9f7 1297 * @{
<> 144:ef7eb2e8f9f7 1298 */
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 /**
<> 144:ef7eb2e8f9f7 1301 * @brief Starts the TIM One Pulse signal generation on the complemetary
<> 144:ef7eb2e8f9f7 1302 * output.
<> 144:ef7eb2e8f9f7 1303 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1304 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1305 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1306 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1307 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1308 * @retval HAL status
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1311 {
<> 144:ef7eb2e8f9f7 1312 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1313 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1316 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1319 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* Return function status */
<> 144:ef7eb2e8f9f7 1322 return HAL_OK;
<> 144:ef7eb2e8f9f7 1323 }
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /**
<> 144:ef7eb2e8f9f7 1326 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1327 * output.
<> 144:ef7eb2e8f9f7 1328 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1329 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1330 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1331 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1332 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1333 * @retval HAL status
<> 144:ef7eb2e8f9f7 1334 */
<> 144:ef7eb2e8f9f7 1335 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1336 {
<> 144:ef7eb2e8f9f7 1337
<> 144:ef7eb2e8f9f7 1338 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1339 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1342 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1345 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1348 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /* Return function status */
<> 144:ef7eb2e8f9f7 1351 return HAL_OK;
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 /**
<> 144:ef7eb2e8f9f7 1355 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1356 * complementary channel.
<> 144:ef7eb2e8f9f7 1357 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1358 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1359 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1360 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1361 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1362 * @retval HAL status
<> 144:ef7eb2e8f9f7 1363 */
<> 144:ef7eb2e8f9f7 1364 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1365 {
<> 144:ef7eb2e8f9f7 1366 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1367 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1370 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1373 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1376 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1379 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 /* Return function status */
<> 144:ef7eb2e8f9f7 1382 return HAL_OK;
<> 144:ef7eb2e8f9f7 1383 }
<> 144:ef7eb2e8f9f7 1384
<> 144:ef7eb2e8f9f7 1385 /**
<> 144:ef7eb2e8f9f7 1386 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1387 * complementary channel.
<> 144:ef7eb2e8f9f7 1388 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1389 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1390 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1391 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1392 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1393 * @retval HAL status
<> 144:ef7eb2e8f9f7 1394 */
<> 144:ef7eb2e8f9f7 1395 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1396 {
<> 144:ef7eb2e8f9f7 1397 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1398 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1401 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1404 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1407 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1410 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1413 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /* Return function status */
<> 144:ef7eb2e8f9f7 1416 return HAL_OK;
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 /**
<> 144:ef7eb2e8f9f7 1420 * @}
<> 144:ef7eb2e8f9f7 1421 */
<> 144:ef7eb2e8f9f7 1422 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1423 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1424 *
<> 144:ef7eb2e8f9f7 1425 @verbatim
<> 144:ef7eb2e8f9f7 1426 ==============================================================================
<> 144:ef7eb2e8f9f7 1427 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1428 ==============================================================================
<> 144:ef7eb2e8f9f7 1429 [..]
<> 144:ef7eb2e8f9f7 1430 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1431 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1432 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1433 (+) Configure Master synchronization.
<> 144:ef7eb2e8f9f7 1434 (+) Configure timer remapping capabilities.
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 @endverbatim
<> 144:ef7eb2e8f9f7 1437 * @{
<> 144:ef7eb2e8f9f7 1438 */
<> 144:ef7eb2e8f9f7 1439 /**
<> 144:ef7eb2e8f9f7 1440 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1441 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1442 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1443 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1444 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1445 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1446 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1447 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1448 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1449 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1450 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1451 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1452 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1453 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1454 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1455 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1456 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1457 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1458 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1459 * @retval HAL status
<> 144:ef7eb2e8f9f7 1460 */
<> 144:ef7eb2e8f9f7 1461 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1462 {
<> 144:ef7eb2e8f9f7 1463 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1464 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1465 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1470 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1471 {
<> 144:ef7eb2e8f9f7 1472 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1473 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1474 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1475 }
<> 144:ef7eb2e8f9f7 1476
<> 144:ef7eb2e8f9f7 1477 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1478 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1479 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1480 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1481 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 return HAL_OK;
<> 144:ef7eb2e8f9f7 1486 }
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /**
<> 144:ef7eb2e8f9f7 1489 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1490 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1491 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1492 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1493 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1494 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1495 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1496 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1497 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1498 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1499 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1500 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1501 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1502 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1503 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1504 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1505 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1506 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1507 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1508 * @retval HAL status
<> 144:ef7eb2e8f9f7 1509 */
<> 144:ef7eb2e8f9f7 1510 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1511 {
<> 144:ef7eb2e8f9f7 1512 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1513 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1514 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1517
<> 144:ef7eb2e8f9f7 1518 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1519 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1520 {
<> 144:ef7eb2e8f9f7 1521 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1522 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1523 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1524 }
<> 144:ef7eb2e8f9f7 1525
<> 144:ef7eb2e8f9f7 1526 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1527 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1528 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1529 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1530 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1533 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 return HAL_OK;
<> 144:ef7eb2e8f9f7 1538 }
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 /**
<> 144:ef7eb2e8f9f7 1541 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1542 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1543 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1544 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1545 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1546 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1547 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1548 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1549 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1550 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1551 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1552 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1553 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1554 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1555 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1556 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1557 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1558 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1559 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1560 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1561 * @retval HAL status
<> 144:ef7eb2e8f9f7 1562 */
<> 144:ef7eb2e8f9f7 1563 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1564 {
<> 144:ef7eb2e8f9f7 1565 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1566 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1567 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1572 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1573 {
<> 144:ef7eb2e8f9f7 1574 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1575 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1576 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1577 }
<> 144:ef7eb2e8f9f7 1578
<> 144:ef7eb2e8f9f7 1579 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1580 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1581 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1582 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1583 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1586 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1587 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1588 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1589 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1592 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 return HAL_OK;
<> 144:ef7eb2e8f9f7 1597 }
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 /**
<> 144:ef7eb2e8f9f7 1600 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 1601 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 1602 * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1603 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1604 * mode.
<> 144:ef7eb2e8f9f7 1605 * @retval HAL status
<> 144:ef7eb2e8f9f7 1606 */
<> 144:ef7eb2e8f9f7 1607 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1608 {
<> 144:ef7eb2e8f9f7 1609 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1610 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1611 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1612 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1615
<> 144:ef7eb2e8f9f7 1616 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1619 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1620 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1621 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1622
<> 144:ef7eb2e8f9f7 1623 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1624 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1625 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1626 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 return HAL_OK;
<> 144:ef7eb2e8f9f7 1633 }
<> 144:ef7eb2e8f9f7 1634
<> 144:ef7eb2e8f9f7 1635 /**
<> 144:ef7eb2e8f9f7 1636 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1637 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 1638 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1639 * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1640 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1641 * @retval HAL status
<> 144:ef7eb2e8f9f7 1642 */
<> 144:ef7eb2e8f9f7 1643 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1644 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1645 {
<> 144:ef7eb2e8f9f7 1646 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1647 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1648 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1649 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1650 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 1651 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1652 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1653 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1654 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656 /* Process Locked */
<> 144:ef7eb2e8f9f7 1657 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 1662 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 144:ef7eb2e8f9f7 1663 htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
<> 144:ef7eb2e8f9f7 1664 sBreakDeadTimeConfig->OffStateIDLEMode |
<> 144:ef7eb2e8f9f7 1665 sBreakDeadTimeConfig->LockLevel |
<> 144:ef7eb2e8f9f7 1666 sBreakDeadTimeConfig->DeadTime |
<> 144:ef7eb2e8f9f7 1667 sBreakDeadTimeConfig->BreakState |
<> 144:ef7eb2e8f9f7 1668 sBreakDeadTimeConfig->BreakPolarity |
<> 144:ef7eb2e8f9f7 1669 sBreakDeadTimeConfig->AutomaticOutput;
<> 144:ef7eb2e8f9f7 1670
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 return HAL_OK;
<> 144:ef7eb2e8f9f7 1677 }
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 /**
<> 144:ef7eb2e8f9f7 1680 * @brief Configures the TIM14 Remapping input capabilities.
<> 144:ef7eb2e8f9f7 1681 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 1682 * @param Remap : specifies the TIM remapping source.
<> 144:ef7eb2e8f9f7 1683 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1684 * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 1685 * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
<> 144:ef7eb2e8f9f7 1686 * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
<> 144:ef7eb2e8f9f7 1687 * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
<> 144:ef7eb2e8f9f7 1688 * @retval HAL status
<> 144:ef7eb2e8f9f7 1689 */
<> 144:ef7eb2e8f9f7 1690 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 1691 {
<> 144:ef7eb2e8f9f7 1692 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 /* Check parameters */
<> 144:ef7eb2e8f9f7 1695 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1696 assert_param(IS_TIM_REMAP(Remap));
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 /* Set the Timer remapping configuration */
<> 144:ef7eb2e8f9f7 1699 htim->Instance->OR = Remap;
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1702
<> 144:ef7eb2e8f9f7 1703 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 return HAL_OK;
<> 144:ef7eb2e8f9f7 1706 }
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 /**
<> 144:ef7eb2e8f9f7 1709 * @}
<> 144:ef7eb2e8f9f7 1710 */
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 /** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1713 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1714 *
<> 144:ef7eb2e8f9f7 1715 * @{
<> 144:ef7eb2e8f9f7 1716 */
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 1719 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 1720 defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 1721 /**
<> 144:ef7eb2e8f9f7 1722 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 1723 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1724 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1725 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1726 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1727 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1728 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1729 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1730 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1731 * @arg TIM_CHANNEL_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 1732 * @arg TIM_Channel_5: TIM Channel 5
<> 144:ef7eb2e8f9f7 1733 * @retval None
<> 144:ef7eb2e8f9f7 1734 */
<> 144:ef7eb2e8f9f7 1735 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1736 TIM_ClearInputConfigTypeDef *sClearInputConfig,
<> 144:ef7eb2e8f9f7 1737 uint32_t Channel)
<> 144:ef7eb2e8f9f7 1738 {
<> 144:ef7eb2e8f9f7 1739 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 1740
<> 144:ef7eb2e8f9f7 1741 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1742 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1743 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 1744
<> 144:ef7eb2e8f9f7 1745 /* Check input state */
<> 144:ef7eb2e8f9f7 1746 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 switch (sClearInputConfig->ClearInputSource)
<> 144:ef7eb2e8f9f7 1751 {
<> 144:ef7eb2e8f9f7 1752 case TIM_CLEARINPUTSOURCE_NONE:
<> 144:ef7eb2e8f9f7 1753 {
<> 144:ef7eb2e8f9f7 1754 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 1755 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1758 tmpsmcr &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 /* Clear the ETR Bits */
<> 144:ef7eb2e8f9f7 1761 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /* Set TIMx_SMCR */
<> 144:ef7eb2e8f9f7 1764 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 1765 }
<> 144:ef7eb2e8f9f7 1766 break;
<> 144:ef7eb2e8f9f7 1767
<> 144:ef7eb2e8f9f7 1768 case TIM_CLEARINPUTSOURCE_OCREFCLR:
<> 144:ef7eb2e8f9f7 1769 {
<> 144:ef7eb2e8f9f7 1770 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1771 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1772 }
<> 144:ef7eb2e8f9f7 1773 break;
<> 144:ef7eb2e8f9f7 1774
<> 144:ef7eb2e8f9f7 1775 case TIM_CLEARINPUTSOURCE_ETR:
<> 144:ef7eb2e8f9f7 1776 {
<> 144:ef7eb2e8f9f7 1777 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1778 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 1779 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 1780 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 1781
<> 144:ef7eb2e8f9f7 1782 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 1783 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 1784 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 1785 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 /* Set the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1788 htim->Instance->SMCR |= TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1789 }
<> 144:ef7eb2e8f9f7 1790 break;
<> 144:ef7eb2e8f9f7 1791 default:
<> 144:ef7eb2e8f9f7 1792 break;
<> 144:ef7eb2e8f9f7 1793 }
<> 144:ef7eb2e8f9f7 1794
<> 144:ef7eb2e8f9f7 1795 switch (Channel)
<> 144:ef7eb2e8f9f7 1796 {
<> 144:ef7eb2e8f9f7 1797 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1798 {
<> 144:ef7eb2e8f9f7 1799 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1800 {
<> 144:ef7eb2e8f9f7 1801 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1802 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1803 }
<> 144:ef7eb2e8f9f7 1804 else
<> 144:ef7eb2e8f9f7 1805 {
<> 144:ef7eb2e8f9f7 1806 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1807 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1808 }
<> 144:ef7eb2e8f9f7 1809 }
<> 144:ef7eb2e8f9f7 1810 break;
<> 144:ef7eb2e8f9f7 1811 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1812 {
<> 144:ef7eb2e8f9f7 1813 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1814 {
<> 144:ef7eb2e8f9f7 1815 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1816 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1817 }
<> 144:ef7eb2e8f9f7 1818 else
<> 144:ef7eb2e8f9f7 1819 {
<> 144:ef7eb2e8f9f7 1820 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1821 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1822 }
<> 144:ef7eb2e8f9f7 1823 }
<> 144:ef7eb2e8f9f7 1824 break;
<> 144:ef7eb2e8f9f7 1825 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1826 {
<> 144:ef7eb2e8f9f7 1827 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1828 {
<> 144:ef7eb2e8f9f7 1829 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1830 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1831 }
<> 144:ef7eb2e8f9f7 1832 else
<> 144:ef7eb2e8f9f7 1833 {
<> 144:ef7eb2e8f9f7 1834 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1835 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1836 }
<> 144:ef7eb2e8f9f7 1837 }
<> 144:ef7eb2e8f9f7 1838 break;
<> 144:ef7eb2e8f9f7 1839 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1840 {
<> 144:ef7eb2e8f9f7 1841 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1842 {
<> 144:ef7eb2e8f9f7 1843 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 1844 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 1845 }
<> 144:ef7eb2e8f9f7 1846 else
<> 144:ef7eb2e8f9f7 1847 {
<> 144:ef7eb2e8f9f7 1848 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 1849 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 1850 }
<> 144:ef7eb2e8f9f7 1851 }
<> 144:ef7eb2e8f9f7 1852 break;
<> 144:ef7eb2e8f9f7 1853 default:
<> 144:ef7eb2e8f9f7 1854 break;
<> 144:ef7eb2e8f9f7 1855 }
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1858
<> 144:ef7eb2e8f9f7 1859 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 return HAL_OK;
<> 144:ef7eb2e8f9f7 1862 }
<> 144:ef7eb2e8f9f7 1863 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1864 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1865 /* STM32F091xC || defined (STM32F098xx) */
<> 144:ef7eb2e8f9f7 1866 /**
<> 144:ef7eb2e8f9f7 1867 * @}
<> 144:ef7eb2e8f9f7 1868 */
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1871 * @brief Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1872 *
<> 144:ef7eb2e8f9f7 1873 @verbatim
<> 144:ef7eb2e8f9f7 1874 ==============================================================================
<> 144:ef7eb2e8f9f7 1875 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 1876 ==============================================================================
<> 144:ef7eb2e8f9f7 1877 [..]
<> 144:ef7eb2e8f9f7 1878 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 1879 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 1880 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 1881
<> 144:ef7eb2e8f9f7 1882 @endverbatim
<> 144:ef7eb2e8f9f7 1883 * @{
<> 144:ef7eb2e8f9f7 1884 */
<> 144:ef7eb2e8f9f7 1885
<> 144:ef7eb2e8f9f7 1886 /**
<> 144:ef7eb2e8f9f7 1887 * @brief Hall commutation changed callback in non blocking mode
<> 144:ef7eb2e8f9f7 1888 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1889 * @retval None
<> 144:ef7eb2e8f9f7 1890 */
<> 144:ef7eb2e8f9f7 1891 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1892 {
<> 144:ef7eb2e8f9f7 1893 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1894 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1897 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1898 */
<> 144:ef7eb2e8f9f7 1899 }
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 /**
<> 144:ef7eb2e8f9f7 1902 * @brief Hall Break detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 1903 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1904 * @retval None
<> 144:ef7eb2e8f9f7 1905 */
<> 144:ef7eb2e8f9f7 1906 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1907 {
<> 144:ef7eb2e8f9f7 1908 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1909 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1912 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1913 */
<> 144:ef7eb2e8f9f7 1914 }
<> 144:ef7eb2e8f9f7 1915
<> 144:ef7eb2e8f9f7 1916 /**
<> 144:ef7eb2e8f9f7 1917 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 1918 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 1919 * @retval None
<> 144:ef7eb2e8f9f7 1920 */
<> 144:ef7eb2e8f9f7 1921 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1922 {
<> 144:ef7eb2e8f9f7 1923 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1926
<> 144:ef7eb2e8f9f7 1927 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 1928 }
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 /**
<> 144:ef7eb2e8f9f7 1931 * @}
<> 144:ef7eb2e8f9f7 1932 */
<> 144:ef7eb2e8f9f7 1933
<> 144:ef7eb2e8f9f7 1934 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1935 * @brief Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1936 *
<> 144:ef7eb2e8f9f7 1937 @verbatim
<> 144:ef7eb2e8f9f7 1938 ==============================================================================
<> 144:ef7eb2e8f9f7 1939 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1940 ==============================================================================
<> 144:ef7eb2e8f9f7 1941 [..]
<> 144:ef7eb2e8f9f7 1942 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1943 and the data flow.
<> 144:ef7eb2e8f9f7 1944
<> 144:ef7eb2e8f9f7 1945 @endverbatim
<> 144:ef7eb2e8f9f7 1946 * @{
<> 144:ef7eb2e8f9f7 1947 */
<> 144:ef7eb2e8f9f7 1948
<> 144:ef7eb2e8f9f7 1949 /**
<> 144:ef7eb2e8f9f7 1950 * @brief Return the TIM Hall Sensor interface state
<> 144:ef7eb2e8f9f7 1951 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 1952 * @retval HAL state
<> 144:ef7eb2e8f9f7 1953 */
<> 144:ef7eb2e8f9f7 1954 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1955 {
<> 144:ef7eb2e8f9f7 1956 return htim->State;
<> 144:ef7eb2e8f9f7 1957 }
<> 144:ef7eb2e8f9f7 1958
<> 144:ef7eb2e8f9f7 1959 /**
<> 144:ef7eb2e8f9f7 1960 * @}
<> 144:ef7eb2e8f9f7 1961 */
<> 144:ef7eb2e8f9f7 1962
<> 144:ef7eb2e8f9f7 1963 /**
<> 144:ef7eb2e8f9f7 1964 * @}
<> 144:ef7eb2e8f9f7 1965 */
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 1968 * @{
<> 144:ef7eb2e8f9f7 1969 */
<> 144:ef7eb2e8f9f7 1970
<> 144:ef7eb2e8f9f7 1971 /**
<> 144:ef7eb2e8f9f7 1972 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 1973 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 1974 * @param Channel : specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1975 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1976 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1977 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1978 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1979 * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 1980 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 1981 * @retval None
<> 144:ef7eb2e8f9f7 1982 */
<> 144:ef7eb2e8f9f7 1983 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 1984 {
<> 144:ef7eb2e8f9f7 1985 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 1986
<> 144:ef7eb2e8f9f7 1987 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 1988
<> 144:ef7eb2e8f9f7 1989 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1990 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 1991
<> 144:ef7eb2e8f9f7 1992 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1993 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 1994 }
<> 144:ef7eb2e8f9f7 1995
<> 144:ef7eb2e8f9f7 1996 /**
<> 144:ef7eb2e8f9f7 1997 * @}
<> 144:ef7eb2e8f9f7 1998 */
<> 144:ef7eb2e8f9f7 1999
<> 144:ef7eb2e8f9f7 2000 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2001 /**
<> 144:ef7eb2e8f9f7 2002 * @}
<> 144:ef7eb2e8f9f7 2003 */
<> 144:ef7eb2e8f9f7 2004
<> 144:ef7eb2e8f9f7 2005 /**
<> 144:ef7eb2e8f9f7 2006 * @}
<> 144:ef7eb2e8f9f7 2007 */
<> 144:ef7eb2e8f9f7 2008
<> 144:ef7eb2e8f9f7 2009 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/