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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c@153:9398a535854b, 2016-12-22 (annotated)
- Committer:
- fwndz
- Date:
- Thu Dec 22 05:12:40 2016 +0000
- Revision:
- 153:9398a535854b
- Parent:
- 149:156823d33999
device target maximize
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f0xx_hal_i2s.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.4.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 27-May-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief I2S HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 9 | * functionalities of the Integrated Interchip Sound (I2S) peripheral: |
<> | 144:ef7eb2e8f9f7 | 10 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + IO operation functions |
<> | 144:ef7eb2e8f9f7 | 12 | * + Peripheral State and Errors functions |
<> | 144:ef7eb2e8f9f7 | 13 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 14 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 15 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 16 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | [..] |
<> | 144:ef7eb2e8f9f7 | 18 | The I2S HAL driver can be used as follow: |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | (#) Declare a I2S_HandleTypeDef handle structure. |
<> | 144:ef7eb2e8f9f7 | 21 | (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: |
<> | 144:ef7eb2e8f9f7 | 22 | (##) Enable the SPIx interface clock. |
<> | 144:ef7eb2e8f9f7 | 23 | (##) I2S pins configuration: |
<> | 144:ef7eb2e8f9f7 | 24 | (+++) Enable the clock for the I2S GPIOs. |
<> | 144:ef7eb2e8f9f7 | 25 | (+++) Configure these I2S pins as alternate function pull-up. |
<> | 144:ef7eb2e8f9f7 | 26 | (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 27 | and HAL_I2S_Receive_IT() APIs). |
<> | 144:ef7eb2e8f9f7 | 28 | (+++) Configure the I2Sx interrupt priority. |
<> | 144:ef7eb2e8f9f7 | 29 | (+++) Enable the NVIC I2S IRQ handle. |
<> | 144:ef7eb2e8f9f7 | 30 | (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 31 | and HAL_I2S_Receive_DMA() APIs: |
<> | 144:ef7eb2e8f9f7 | 32 | (+++) Declare a DMA handle structure for the Tx/Rx Channel. |
<> | 144:ef7eb2e8f9f7 | 33 | (+++) Enable the DMAx interface clock. |
<> | 144:ef7eb2e8f9f7 | 34 | (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. |
<> | 144:ef7eb2e8f9f7 | 35 | (+++) Configure the DMA Tx/Rx Channel. |
<> | 144:ef7eb2e8f9f7 | 36 | (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. |
<> | 144:ef7eb2e8f9f7 | 37 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the |
<> | 144:ef7eb2e8f9f7 | 38 | DMA Tx/Rx Channel. |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity |
<> | 144:ef7eb2e8f9f7 | 41 | using HAL_I2S_Init() function. |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | -@- The specific I2S interrupts (Transmission complete interrupt, |
<> | 144:ef7eb2e8f9f7 | 44 | RXNE interrupt and Error Interrupts) will be managed using the macros |
<> | 144:ef7eb2e8f9f7 | 45 | __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. |
<> | 144:ef7eb2e8f9f7 | 46 | -@- Make sure that either: |
<> | 144:ef7eb2e8f9f7 | 47 | (+@) External clock source is configured after setting correctly |
<> | 144:ef7eb2e8f9f7 | 48 | the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file. |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | (#) Three mode of operations are available within this driver : |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | *** Polling mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 53 | ================================= |
<> | 144:ef7eb2e8f9f7 | 54 | [..] |
<> | 144:ef7eb2e8f9f7 | 55 | (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() |
<> | 144:ef7eb2e8f9f7 | 56 | (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | *** Interrupt mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 59 | =================================== |
<> | 144:ef7eb2e8f9f7 | 60 | [..] |
<> | 144:ef7eb2e8f9f7 | 61 | (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 62 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 63 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 64 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 65 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
<> | 144:ef7eb2e8f9f7 | 66 | (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 67 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 68 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 69 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 70 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
<> | 144:ef7eb2e8f9f7 | 71 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 72 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | *** DMA mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 75 | ============================== |
<> | 144:ef7eb2e8f9f7 | 76 | [..] |
<> | 144:ef7eb2e8f9f7 | 77 | (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 78 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 79 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 80 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 81 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
<> | 144:ef7eb2e8f9f7 | 82 | (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 83 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 84 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 85 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 86 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
<> | 144:ef7eb2e8f9f7 | 87 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 88 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
<> | 144:ef7eb2e8f9f7 | 89 | (+) Pause the DMA Transfer using HAL_I2S_DMAPause() |
<> | 144:ef7eb2e8f9f7 | 90 | (+) Resume the DMA Transfer using HAL_I2S_DMAResume() |
<> | 144:ef7eb2e8f9f7 | 91 | (+) Stop the DMA Transfer using HAL_I2S_DMAStop() |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | *** I2S HAL driver macros list *** |
<> | 144:ef7eb2e8f9f7 | 94 | ============================================= |
<> | 144:ef7eb2e8f9f7 | 95 | [..] |
<> | 144:ef7eb2e8f9f7 | 96 | Below the list of most used macros in I2S HAL driver. |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) |
<> | 144:ef7eb2e8f9f7 | 99 | (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) |
<> | 144:ef7eb2e8f9f7 | 100 | (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts |
<> | 144:ef7eb2e8f9f7 | 101 | (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts |
<> | 144:ef7eb2e8f9f7 | 102 | (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | [..] |
<> | 144:ef7eb2e8f9f7 | 105 | (@) You can refer to the I2S HAL driver header file for more useful macros |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 108 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 109 | * @attention |
<> | 144:ef7eb2e8f9f7 | 110 | * |
<> | 144:ef7eb2e8f9f7 | 111 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 112 | * |
<> | 144:ef7eb2e8f9f7 | 113 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 114 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 115 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 116 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 117 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 118 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 119 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 120 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 121 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 122 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 123 | * |
<> | 144:ef7eb2e8f9f7 | 124 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 125 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 126 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 127 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 128 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 129 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 130 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 131 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 132 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 133 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 134 | * |
<> | 144:ef7eb2e8f9f7 | 135 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 136 | */ |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 139 | #include "stm32f0xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | #ifdef HAL_I2S_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | #if defined(STM32F031x6) || defined(STM32F038xx) || \ |
<> | 144:ef7eb2e8f9f7 | 144 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
<> | 144:ef7eb2e8f9f7 | 145 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
<> | 144:ef7eb2e8f9f7 | 146 | defined(STM32F042x6) || defined(STM32F048xx) || \ |
<> | 144:ef7eb2e8f9f7 | 147 | defined(STM32F091xC) || defined(STM32F098xx) |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | /** @addtogroup STM32F0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 150 | * @{ |
<> | 144:ef7eb2e8f9f7 | 151 | */ |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | /** @defgroup I2S I2S |
<> | 144:ef7eb2e8f9f7 | 154 | * @brief I2S HAL module driver |
<> | 144:ef7eb2e8f9f7 | 155 | * @{ |
<> | 144:ef7eb2e8f9f7 | 156 | */ |
<> | 144:ef7eb2e8f9f7 | 157 | |
<> | 144:ef7eb2e8f9f7 | 158 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 159 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 160 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 161 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 162 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 163 | /** @defgroup I2S_Private_Functions I2S Private Functions |
<> | 144:ef7eb2e8f9f7 | 164 | * @{ |
<> | 144:ef7eb2e8f9f7 | 165 | */ |
<> | 144:ef7eb2e8f9f7 | 166 | static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 167 | static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 168 | static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 169 | static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 170 | static void I2S_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 171 | static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); |
<> | 144:ef7eb2e8f9f7 | 172 | static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); |
<> | 144:ef7eb2e8f9f7 | 173 | static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 174 | /** |
<> | 144:ef7eb2e8f9f7 | 175 | * @} |
<> | 144:ef7eb2e8f9f7 | 176 | */ |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | /** @defgroup I2S_Exported_Functions I2S Exported Functions |
<> | 144:ef7eb2e8f9f7 | 181 | * @{ |
<> | 144:ef7eb2e8f9f7 | 182 | */ |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 185 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 186 | * |
<> | 144:ef7eb2e8f9f7 | 187 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 188 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 189 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 190 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 191 | [..] This subsection provides a set of functions allowing to initialize and |
<> | 144:ef7eb2e8f9f7 | 192 | de-initialiaze the I2Sx peripheral in simplex mode: |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | (+) User must Implement HAL_I2S_MspInit() function in which he configures |
<> | 144:ef7eb2e8f9f7 | 195 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
<> | 144:ef7eb2e8f9f7 | 196 | |
<> | 144:ef7eb2e8f9f7 | 197 | (+) Call the function HAL_I2S_Init() to configure the selected device with |
<> | 144:ef7eb2e8f9f7 | 198 | the selected configuration: |
<> | 144:ef7eb2e8f9f7 | 199 | (++) Mode |
<> | 144:ef7eb2e8f9f7 | 200 | (++) Standard |
<> | 144:ef7eb2e8f9f7 | 201 | (++) Data Format |
<> | 144:ef7eb2e8f9f7 | 202 | (++) MCLK Output |
<> | 144:ef7eb2e8f9f7 | 203 | (++) Audio frequency |
<> | 144:ef7eb2e8f9f7 | 204 | (++) Polarity |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | (+) Call the function HAL_I2S_DeInit() to restore the default configuration |
<> | 144:ef7eb2e8f9f7 | 207 | of the selected I2Sx periperal. |
<> | 144:ef7eb2e8f9f7 | 208 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 209 | * @{ |
<> | 144:ef7eb2e8f9f7 | 210 | */ |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | /** |
<> | 144:ef7eb2e8f9f7 | 213 | * @brief Initializes the I2S according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 214 | * in the I2S_InitTypeDef and create the associated handle. |
<> | 144:ef7eb2e8f9f7 | 215 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 216 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 217 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 218 | */ |
<> | 144:ef7eb2e8f9f7 | 219 | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 220 | { |
<> | 144:ef7eb2e8f9f7 | 221 | uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; |
<> | 144:ef7eb2e8f9f7 | 222 | uint32_t tmp = 0, i2sclk = 0; |
<> | 144:ef7eb2e8f9f7 | 223 | |
<> | 144:ef7eb2e8f9f7 | 224 | /* Check the I2S handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 225 | if(hi2s == NULL) |
<> | 144:ef7eb2e8f9f7 | 226 | { |
<> | 144:ef7eb2e8f9f7 | 227 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 228 | } |
<> | 144:ef7eb2e8f9f7 | 229 | |
<> | 144:ef7eb2e8f9f7 | 230 | /* Check the I2S parameters */ |
<> | 144:ef7eb2e8f9f7 | 231 | assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); |
<> | 144:ef7eb2e8f9f7 | 232 | assert_param(IS_I2S_MODE(hi2s->Init.Mode)); |
<> | 144:ef7eb2e8f9f7 | 233 | assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); |
<> | 144:ef7eb2e8f9f7 | 234 | assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); |
<> | 144:ef7eb2e8f9f7 | 235 | assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); |
<> | 144:ef7eb2e8f9f7 | 236 | assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); |
<> | 144:ef7eb2e8f9f7 | 237 | assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | if(hi2s->State == HAL_I2S_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 240 | { |
<> | 144:ef7eb2e8f9f7 | 241 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 242 | hi2s->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ |
<> | 144:ef7eb2e8f9f7 | 245 | HAL_I2S_MspInit(hi2s); |
<> | 144:ef7eb2e8f9f7 | 246 | } |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | hi2s->State = HAL_I2S_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/ |
<> | 144:ef7eb2e8f9f7 | 251 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ |
<> | 144:ef7eb2e8f9f7 | 252 | hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ |
<> | 144:ef7eb2e8f9f7 | 253 | SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ |
<> | 144:ef7eb2e8f9f7 | 254 | SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); |
<> | 144:ef7eb2e8f9f7 | 255 | hi2s->Instance->I2SPR = 0x0002; |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | /* Get the I2SCFGR register value */ |
<> | 144:ef7eb2e8f9f7 | 258 | tmpreg = hi2s->Instance->I2SCFGR; |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ |
<> | 144:ef7eb2e8f9f7 | 261 | if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) |
<> | 144:ef7eb2e8f9f7 | 262 | { |
<> | 144:ef7eb2e8f9f7 | 263 | i2sodd = (uint16_t)0; |
<> | 144:ef7eb2e8f9f7 | 264 | i2sdiv = (uint16_t)2; |
<> | 144:ef7eb2e8f9f7 | 265 | } |
<> | 144:ef7eb2e8f9f7 | 266 | /* If the requested audio frequency is not the default, compute the prescaler */ |
<> | 144:ef7eb2e8f9f7 | 267 | else |
<> | 144:ef7eb2e8f9f7 | 268 | { |
<> | 144:ef7eb2e8f9f7 | 269 | /* Check the frame length (For the Prescaler computing) *******************/ |
<> | 144:ef7eb2e8f9f7 | 270 | if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) |
<> | 144:ef7eb2e8f9f7 | 271 | { |
<> | 144:ef7eb2e8f9f7 | 272 | /* Packet length is 16 bits */ |
<> | 144:ef7eb2e8f9f7 | 273 | packetlength = 1; |
<> | 144:ef7eb2e8f9f7 | 274 | } |
<> | 144:ef7eb2e8f9f7 | 275 | else |
<> | 144:ef7eb2e8f9f7 | 276 | { |
<> | 144:ef7eb2e8f9f7 | 277 | /* Packet length is 32 bits */ |
<> | 144:ef7eb2e8f9f7 | 278 | packetlength = 2; |
<> | 144:ef7eb2e8f9f7 | 279 | } |
<> | 144:ef7eb2e8f9f7 | 280 | |
<> | 144:ef7eb2e8f9f7 | 281 | /* Get I2S source Clock frequency ****************************************/ |
<> | 144:ef7eb2e8f9f7 | 282 | i2sclk = HAL_RCC_GetSysClockFreq(); |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | /* Compute the Real divider depending on the MCLK output state, with a floating point */ |
<> | 144:ef7eb2e8f9f7 | 285 | if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 286 | { |
<> | 144:ef7eb2e8f9f7 | 287 | /* MCLK output is enabled */ |
<> | 144:ef7eb2e8f9f7 | 288 | tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); |
<> | 144:ef7eb2e8f9f7 | 289 | } |
<> | 144:ef7eb2e8f9f7 | 290 | else |
<> | 144:ef7eb2e8f9f7 | 291 | { |
<> | 144:ef7eb2e8f9f7 | 292 | /* MCLK output is disabled */ |
<> | 144:ef7eb2e8f9f7 | 293 | tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); |
<> | 144:ef7eb2e8f9f7 | 294 | } |
<> | 144:ef7eb2e8f9f7 | 295 | |
<> | 144:ef7eb2e8f9f7 | 296 | /* Remove the flatting point */ |
<> | 144:ef7eb2e8f9f7 | 297 | tmp = tmp / 10; |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | /* Check the parity of the divider */ |
<> | 144:ef7eb2e8f9f7 | 300 | i2sodd = (uint32_t)(tmp & (uint32_t)1); |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | /* Compute the i2sdiv prescaler */ |
<> | 144:ef7eb2e8f9f7 | 303 | i2sdiv = (uint32_t)((tmp - i2sodd) / 2); |
<> | 144:ef7eb2e8f9f7 | 304 | |
<> | 144:ef7eb2e8f9f7 | 305 | /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ |
<> | 144:ef7eb2e8f9f7 | 306 | i2sodd = (uint32_t) (i2sodd << 8); |
<> | 144:ef7eb2e8f9f7 | 307 | } |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | /* Test if the divider is 1 or 0 or greater than 0xFF */ |
<> | 144:ef7eb2e8f9f7 | 310 | if((i2sdiv < 2) || (i2sdiv > 0xFF)) |
<> | 144:ef7eb2e8f9f7 | 311 | { |
<> | 144:ef7eb2e8f9f7 | 312 | /* Set the default values */ |
<> | 144:ef7eb2e8f9f7 | 313 | i2sdiv = 2; |
<> | 144:ef7eb2e8f9f7 | 314 | i2sodd = 0; |
<> | 144:ef7eb2e8f9f7 | 315 | } |
<> | 144:ef7eb2e8f9f7 | 316 | |
<> | 144:ef7eb2e8f9f7 | 317 | /* Write to SPIx I2SPR register the computed value */ |
<> | 144:ef7eb2e8f9f7 | 318 | hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); |
<> | 144:ef7eb2e8f9f7 | 319 | |
<> | 144:ef7eb2e8f9f7 | 320 | /* Configure the I2S with the I2S_InitStruct values */ |
<> | 144:ef7eb2e8f9f7 | 321 | tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL); |
<> | 144:ef7eb2e8f9f7 | 322 | |
<> | 144:ef7eb2e8f9f7 | 323 | /* Write to SPIx I2SCFGR */ |
<> | 144:ef7eb2e8f9f7 | 324 | hi2s->Instance->I2SCFGR = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 325 | |
<> | 144:ef7eb2e8f9f7 | 326 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 327 | hi2s->State= HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 328 | |
<> | 144:ef7eb2e8f9f7 | 329 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 330 | } |
<> | 144:ef7eb2e8f9f7 | 331 | |
<> | 144:ef7eb2e8f9f7 | 332 | /** |
<> | 144:ef7eb2e8f9f7 | 333 | * @brief DeInitializes the I2S peripheral |
<> | 144:ef7eb2e8f9f7 | 334 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 335 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 336 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 337 | */ |
<> | 144:ef7eb2e8f9f7 | 338 | HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 339 | { |
<> | 144:ef7eb2e8f9f7 | 340 | /* Check the I2S handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 341 | if(hi2s == NULL) |
<> | 144:ef7eb2e8f9f7 | 342 | { |
<> | 144:ef7eb2e8f9f7 | 343 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 344 | } |
<> | 144:ef7eb2e8f9f7 | 345 | |
<> | 144:ef7eb2e8f9f7 | 346 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 347 | assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | hi2s->State = HAL_I2S_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 350 | |
<> | 144:ef7eb2e8f9f7 | 351 | /* Disable the I2S Peripheral Clock */ |
<> | 144:ef7eb2e8f9f7 | 352 | __HAL_I2S_DISABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
<> | 144:ef7eb2e8f9f7 | 355 | HAL_I2S_MspDeInit(hi2s); |
<> | 144:ef7eb2e8f9f7 | 356 | |
<> | 144:ef7eb2e8f9f7 | 357 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 358 | hi2s->State = HAL_I2S_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 359 | |
<> | 144:ef7eb2e8f9f7 | 360 | /* Release Lock */ |
<> | 144:ef7eb2e8f9f7 | 361 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 364 | } |
<> | 144:ef7eb2e8f9f7 | 365 | |
<> | 144:ef7eb2e8f9f7 | 366 | /** |
<> | 144:ef7eb2e8f9f7 | 367 | * @brief I2S MSP Init |
<> | 144:ef7eb2e8f9f7 | 368 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 369 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 370 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 371 | */ |
<> | 144:ef7eb2e8f9f7 | 372 | __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 373 | { |
<> | 144:ef7eb2e8f9f7 | 374 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 375 | UNUSED(hi2s); |
<> | 144:ef7eb2e8f9f7 | 376 | |
<> | 144:ef7eb2e8f9f7 | 377 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 378 | the HAL_I2S_MspInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 379 | */ |
<> | 144:ef7eb2e8f9f7 | 380 | } |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | /** |
<> | 144:ef7eb2e8f9f7 | 383 | * @brief I2S MSP DeInit |
<> | 144:ef7eb2e8f9f7 | 384 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 385 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 386 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 387 | */ |
<> | 144:ef7eb2e8f9f7 | 388 | __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 389 | { |
<> | 144:ef7eb2e8f9f7 | 390 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 391 | UNUSED(hi2s); |
<> | 144:ef7eb2e8f9f7 | 392 | |
<> | 144:ef7eb2e8f9f7 | 393 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 394 | the HAL_I2S_MspDeInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 395 | */ |
<> | 144:ef7eb2e8f9f7 | 396 | } |
<> | 144:ef7eb2e8f9f7 | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | /** |
<> | 144:ef7eb2e8f9f7 | 399 | * @} |
<> | 144:ef7eb2e8f9f7 | 400 | */ |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | /** @defgroup I2S_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 403 | * @brief Data transfers functions |
<> | 144:ef7eb2e8f9f7 | 404 | * |
<> | 144:ef7eb2e8f9f7 | 405 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 406 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 407 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 408 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 409 | [..] |
<> | 144:ef7eb2e8f9f7 | 410 | This subsection provides a set of functions allowing to manage the I2S data |
<> | 144:ef7eb2e8f9f7 | 411 | transfers. |
<> | 144:ef7eb2e8f9f7 | 412 | |
<> | 144:ef7eb2e8f9f7 | 413 | (#) There are two modes of transfer: |
<> | 144:ef7eb2e8f9f7 | 414 | (++) Blocking mode : The communication is performed in the polling mode. |
<> | 144:ef7eb2e8f9f7 | 415 | The status of all data processing is returned by the same function |
<> | 144:ef7eb2e8f9f7 | 416 | after finishing transfer. |
<> | 144:ef7eb2e8f9f7 | 417 | (++) No-Blocking mode : The communication is performed using Interrupts |
<> | 144:ef7eb2e8f9f7 | 418 | or DMA. These functions return the status of the transfer startup. |
<> | 144:ef7eb2e8f9f7 | 419 | The end of the data processing will be indicated through the |
<> | 144:ef7eb2e8f9f7 | 420 | dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when |
<> | 144:ef7eb2e8f9f7 | 421 | using DMA mode. |
<> | 144:ef7eb2e8f9f7 | 422 | |
<> | 144:ef7eb2e8f9f7 | 423 | (#) Blocking mode functions are : |
<> | 144:ef7eb2e8f9f7 | 424 | (++) HAL_I2S_Transmit() |
<> | 144:ef7eb2e8f9f7 | 425 | (++) HAL_I2S_Receive() |
<> | 144:ef7eb2e8f9f7 | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | (#) No-Blocking mode functions with Interrupt are : |
<> | 144:ef7eb2e8f9f7 | 428 | (++) HAL_I2S_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 429 | (++) HAL_I2S_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | (#) No-Blocking mode functions with DMA are : |
<> | 144:ef7eb2e8f9f7 | 432 | (++) HAL_I2S_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 433 | (++) HAL_I2S_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 434 | |
<> | 144:ef7eb2e8f9f7 | 435 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
<> | 144:ef7eb2e8f9f7 | 436 | (++) HAL_I2S_TxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 437 | (++) HAL_I2S_RxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 438 | (++) HAL_I2S_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 439 | |
<> | 144:ef7eb2e8f9f7 | 440 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 441 | * @{ |
<> | 144:ef7eb2e8f9f7 | 442 | */ |
<> | 144:ef7eb2e8f9f7 | 443 | |
<> | 144:ef7eb2e8f9f7 | 444 | /** |
<> | 144:ef7eb2e8f9f7 | 445 | * @brief Transmit an amount of data in blocking mode |
<> | 144:ef7eb2e8f9f7 | 446 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 447 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 448 | * @param pData: a 16-bit pointer to data buffer. |
<> | 144:ef7eb2e8f9f7 | 449 | * @param Size: number of data sample to be sent: |
<> | 144:ef7eb2e8f9f7 | 450 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
<> | 144:ef7eb2e8f9f7 | 451 | * configuration phase, the Size parameter means the number of 16-bit data length |
<> | 144:ef7eb2e8f9f7 | 452 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
<> | 144:ef7eb2e8f9f7 | 453 | * the Size parameter means the number of 16-bit data length. |
<> | 144:ef7eb2e8f9f7 | 454 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 455 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
<> | 144:ef7eb2e8f9f7 | 456 | * between Master and Slave(example: audio streaming). |
<> | 144:ef7eb2e8f9f7 | 457 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 458 | */ |
<> | 144:ef7eb2e8f9f7 | 459 | HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 460 | { |
<> | 144:ef7eb2e8f9f7 | 461 | if((pData == NULL ) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 462 | { |
<> | 144:ef7eb2e8f9f7 | 463 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 464 | } |
<> | 144:ef7eb2e8f9f7 | 465 | |
<> | 144:ef7eb2e8f9f7 | 466 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 467 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 468 | |
<> | 144:ef7eb2e8f9f7 | 469 | if(hi2s->State == HAL_I2S_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 470 | { |
<> | 144:ef7eb2e8f9f7 | 471 | if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ |
<> | 144:ef7eb2e8f9f7 | 472 | ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) |
<> | 144:ef7eb2e8f9f7 | 473 | { |
<> | 144:ef7eb2e8f9f7 | 474 | hi2s->TxXferSize = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 475 | hi2s->TxXferCount = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 476 | } |
<> | 144:ef7eb2e8f9f7 | 477 | else |
<> | 144:ef7eb2e8f9f7 | 478 | { |
<> | 144:ef7eb2e8f9f7 | 479 | hi2s->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 480 | hi2s->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 481 | } |
<> | 144:ef7eb2e8f9f7 | 482 | |
<> | 144:ef7eb2e8f9f7 | 483 | /* Set state and reset error code */ |
<> | 144:ef7eb2e8f9f7 | 484 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 485 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 486 | hi2s->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 487 | |
<> | 144:ef7eb2e8f9f7 | 488 | /* Check if the I2S is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 489 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
<> | 144:ef7eb2e8f9f7 | 490 | { |
<> | 144:ef7eb2e8f9f7 | 491 | /* Enable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 492 | __HAL_I2S_ENABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 493 | } |
<> | 144:ef7eb2e8f9f7 | 494 | |
<> | 144:ef7eb2e8f9f7 | 495 | while(hi2s->TxXferCount > 0) |
<> | 144:ef7eb2e8f9f7 | 496 | { |
<> | 144:ef7eb2e8f9f7 | 497 | /* Wait until TXE flag is set */ |
<> | 144:ef7eb2e8f9f7 | 498 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 499 | { |
<> | 144:ef7eb2e8f9f7 | 500 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 501 | } |
<> | 144:ef7eb2e8f9f7 | 502 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 503 | hi2s->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 504 | } |
<> | 144:ef7eb2e8f9f7 | 505 | |
<> | 144:ef7eb2e8f9f7 | 506 | /* Wait until TXE flag is set, to confirm the end of the transcation */ |
<> | 144:ef7eb2e8f9f7 | 507 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 508 | { |
<> | 144:ef7eb2e8f9f7 | 509 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 510 | } |
<> | 144:ef7eb2e8f9f7 | 511 | /* Wait until Busy flag is reset */ |
<> | 144:ef7eb2e8f9f7 | 512 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 513 | { |
<> | 144:ef7eb2e8f9f7 | 514 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 515 | } |
<> | 144:ef7eb2e8f9f7 | 516 | |
<> | 144:ef7eb2e8f9f7 | 517 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 518 | |
<> | 144:ef7eb2e8f9f7 | 519 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 520 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 521 | |
<> | 144:ef7eb2e8f9f7 | 522 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 523 | } |
<> | 144:ef7eb2e8f9f7 | 524 | else |
<> | 144:ef7eb2e8f9f7 | 525 | { |
<> | 144:ef7eb2e8f9f7 | 526 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 527 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 528 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 529 | } |
<> | 144:ef7eb2e8f9f7 | 530 | } |
<> | 144:ef7eb2e8f9f7 | 531 | |
<> | 144:ef7eb2e8f9f7 | 532 | /** |
<> | 144:ef7eb2e8f9f7 | 533 | * @brief Receive an amount of data in blocking mode |
<> | 144:ef7eb2e8f9f7 | 534 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 535 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 536 | * @param pData: a 16-bit pointer to data buffer. |
<> | 144:ef7eb2e8f9f7 | 537 | * @param Size: number of data sample to be sent: |
<> | 144:ef7eb2e8f9f7 | 538 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
<> | 144:ef7eb2e8f9f7 | 539 | * configuration phase, the Size parameter means the number of 16-bit data length |
<> | 144:ef7eb2e8f9f7 | 540 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
<> | 144:ef7eb2e8f9f7 | 541 | * the Size parameter means the number of 16-bit data length. |
<> | 144:ef7eb2e8f9f7 | 542 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 543 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
<> | 144:ef7eb2e8f9f7 | 544 | * between Master and Slave(example: audio streaming). |
<> | 144:ef7eb2e8f9f7 | 545 | * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate |
<> | 144:ef7eb2e8f9f7 | 546 | * in continouse way and as the I2S is not disabled at the end of the I2S transaction. |
<> | 144:ef7eb2e8f9f7 | 547 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 548 | */ |
<> | 144:ef7eb2e8f9f7 | 549 | HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 550 | { |
<> | 144:ef7eb2e8f9f7 | 551 | if((pData == NULL ) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 552 | { |
<> | 144:ef7eb2e8f9f7 | 553 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 554 | } |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 557 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 558 | |
<> | 144:ef7eb2e8f9f7 | 559 | if(hi2s->State == HAL_I2S_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 560 | { |
<> | 144:ef7eb2e8f9f7 | 561 | if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ |
<> | 144:ef7eb2e8f9f7 | 562 | ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) |
<> | 144:ef7eb2e8f9f7 | 563 | { |
<> | 144:ef7eb2e8f9f7 | 564 | hi2s->RxXferSize = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 565 | hi2s->RxXferCount = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 566 | } |
<> | 144:ef7eb2e8f9f7 | 567 | else |
<> | 144:ef7eb2e8f9f7 | 568 | { |
<> | 144:ef7eb2e8f9f7 | 569 | hi2s->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 570 | hi2s->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 571 | } |
<> | 144:ef7eb2e8f9f7 | 572 | |
<> | 144:ef7eb2e8f9f7 | 573 | /* Set state and reset error code */ |
<> | 144:ef7eb2e8f9f7 | 574 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 575 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 576 | hi2s->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 577 | |
<> | 144:ef7eb2e8f9f7 | 578 | /* Check if the I2S is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 579 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
<> | 144:ef7eb2e8f9f7 | 580 | { |
<> | 144:ef7eb2e8f9f7 | 581 | /* Enable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 582 | __HAL_I2S_ENABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 583 | } |
<> | 144:ef7eb2e8f9f7 | 584 | |
<> | 144:ef7eb2e8f9f7 | 585 | /* Receive data */ |
<> | 144:ef7eb2e8f9f7 | 586 | while(hi2s->RxXferCount > 0) |
<> | 144:ef7eb2e8f9f7 | 587 | { |
<> | 144:ef7eb2e8f9f7 | 588 | /* Wait until RXNE flag is set */ |
<> | 144:ef7eb2e8f9f7 | 589 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 590 | { |
<> | 144:ef7eb2e8f9f7 | 591 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 592 | } |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 595 | hi2s->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 596 | } |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 601 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 604 | } |
<> | 144:ef7eb2e8f9f7 | 605 | else |
<> | 144:ef7eb2e8f9f7 | 606 | { |
<> | 144:ef7eb2e8f9f7 | 607 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 608 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 609 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 610 | } |
<> | 144:ef7eb2e8f9f7 | 611 | } |
<> | 144:ef7eb2e8f9f7 | 612 | |
<> | 144:ef7eb2e8f9f7 | 613 | /** |
<> | 144:ef7eb2e8f9f7 | 614 | * @brief Transmit an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 615 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 616 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 617 | * @param pData: a 16-bit pointer to data buffer. |
<> | 144:ef7eb2e8f9f7 | 618 | * @param Size: number of data sample to be sent: |
<> | 144:ef7eb2e8f9f7 | 619 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
<> | 144:ef7eb2e8f9f7 | 620 | * configuration phase, the Size parameter means the number of 16-bit data length |
<> | 144:ef7eb2e8f9f7 | 621 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
<> | 144:ef7eb2e8f9f7 | 622 | * the Size parameter means the number of 16-bit data length. |
<> | 144:ef7eb2e8f9f7 | 623 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
<> | 144:ef7eb2e8f9f7 | 624 | * between Master and Slave(example: audio streaming). |
<> | 144:ef7eb2e8f9f7 | 625 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 626 | */ |
<> | 144:ef7eb2e8f9f7 | 627 | HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 628 | { |
<> | 144:ef7eb2e8f9f7 | 629 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 630 | { |
<> | 144:ef7eb2e8f9f7 | 631 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 632 | } |
<> | 144:ef7eb2e8f9f7 | 633 | |
<> | 144:ef7eb2e8f9f7 | 634 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 635 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | if(hi2s->State == HAL_I2S_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 638 | { |
<> | 144:ef7eb2e8f9f7 | 639 | hi2s->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 640 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 641 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 642 | |
<> | 144:ef7eb2e8f9f7 | 643 | if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ |
<> | 144:ef7eb2e8f9f7 | 644 | ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) |
<> | 144:ef7eb2e8f9f7 | 645 | { |
<> | 144:ef7eb2e8f9f7 | 646 | hi2s->TxXferSize = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 647 | hi2s->TxXferCount = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 648 | } |
<> | 144:ef7eb2e8f9f7 | 649 | else |
<> | 144:ef7eb2e8f9f7 | 650 | { |
<> | 144:ef7eb2e8f9f7 | 651 | hi2s->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 652 | hi2s->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 653 | } |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | /* Enable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 656 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 657 | |
<> | 144:ef7eb2e8f9f7 | 658 | /* Check if the I2S is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 659 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
<> | 144:ef7eb2e8f9f7 | 660 | { |
<> | 144:ef7eb2e8f9f7 | 661 | /* Enable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 662 | __HAL_I2S_ENABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 663 | } |
<> | 144:ef7eb2e8f9f7 | 664 | |
<> | 144:ef7eb2e8f9f7 | 665 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 666 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 669 | } |
<> | 144:ef7eb2e8f9f7 | 670 | else |
<> | 144:ef7eb2e8f9f7 | 671 | { |
<> | 144:ef7eb2e8f9f7 | 672 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 673 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 674 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 675 | } |
<> | 144:ef7eb2e8f9f7 | 676 | } |
<> | 144:ef7eb2e8f9f7 | 677 | |
<> | 144:ef7eb2e8f9f7 | 678 | /** |
<> | 144:ef7eb2e8f9f7 | 679 | * @brief Receive an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 680 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 681 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 682 | * @param pData: a 16-bit pointer to the Receive data buffer. |
<> | 144:ef7eb2e8f9f7 | 683 | * @param Size: number of data sample to be sent: |
<> | 144:ef7eb2e8f9f7 | 684 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
<> | 144:ef7eb2e8f9f7 | 685 | * configuration phase, the Size parameter means the number of 16-bit data length |
<> | 144:ef7eb2e8f9f7 | 686 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
<> | 144:ef7eb2e8f9f7 | 687 | * the Size parameter means the number of 16-bit data length. |
<> | 144:ef7eb2e8f9f7 | 688 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
<> | 144:ef7eb2e8f9f7 | 689 | * between Master and Slave(example: audio streaming). |
<> | 144:ef7eb2e8f9f7 | 690 | * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation |
<> | 144:ef7eb2e8f9f7 | 691 | * between Master and Slave otherwise the I2S interrupt should be optimized. |
<> | 144:ef7eb2e8f9f7 | 692 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 693 | */ |
<> | 144:ef7eb2e8f9f7 | 694 | HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 695 | { |
<> | 144:ef7eb2e8f9f7 | 696 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 697 | { |
<> | 144:ef7eb2e8f9f7 | 698 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 699 | } |
<> | 144:ef7eb2e8f9f7 | 700 | |
<> | 144:ef7eb2e8f9f7 | 701 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 702 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 703 | |
<> | 144:ef7eb2e8f9f7 | 704 | if(hi2s->State == HAL_I2S_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 705 | { |
<> | 144:ef7eb2e8f9f7 | 706 | hi2s->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 707 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 708 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 709 | |
<> | 144:ef7eb2e8f9f7 | 710 | if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ |
<> | 144:ef7eb2e8f9f7 | 711 | ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) |
<> | 144:ef7eb2e8f9f7 | 712 | { |
<> | 144:ef7eb2e8f9f7 | 713 | hi2s->RxXferSize = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 714 | hi2s->RxXferCount = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 715 | } |
<> | 144:ef7eb2e8f9f7 | 716 | else |
<> | 144:ef7eb2e8f9f7 | 717 | { |
<> | 144:ef7eb2e8f9f7 | 718 | hi2s->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 719 | hi2s->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 720 | } |
<> | 144:ef7eb2e8f9f7 | 721 | |
<> | 144:ef7eb2e8f9f7 | 722 | /* Enable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 723 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 724 | |
<> | 144:ef7eb2e8f9f7 | 725 | /* Check if the I2S is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 726 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
<> | 144:ef7eb2e8f9f7 | 727 | { |
<> | 144:ef7eb2e8f9f7 | 728 | /* Enable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 729 | __HAL_I2S_ENABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 730 | } |
<> | 144:ef7eb2e8f9f7 | 731 | |
<> | 144:ef7eb2e8f9f7 | 732 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 733 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 734 | |
<> | 144:ef7eb2e8f9f7 | 735 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 736 | } |
<> | 144:ef7eb2e8f9f7 | 737 | else |
<> | 144:ef7eb2e8f9f7 | 738 | { |
<> | 144:ef7eb2e8f9f7 | 739 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 740 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 741 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 742 | } |
<> | 144:ef7eb2e8f9f7 | 743 | } |
<> | 144:ef7eb2e8f9f7 | 744 | |
<> | 144:ef7eb2e8f9f7 | 745 | /** |
<> | 144:ef7eb2e8f9f7 | 746 | * @brief Transmit an amount of data in non-blocking mode with DMA |
<> | 144:ef7eb2e8f9f7 | 747 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 748 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 749 | * @param pData: a 16-bit pointer to the Transmit data buffer. |
<> | 144:ef7eb2e8f9f7 | 750 | * @param Size: number of data sample to be sent: |
<> | 144:ef7eb2e8f9f7 | 751 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
<> | 144:ef7eb2e8f9f7 | 752 | * configuration phase, the Size parameter means the number of 16-bit data length |
<> | 144:ef7eb2e8f9f7 | 753 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
<> | 144:ef7eb2e8f9f7 | 754 | * the Size parameter means the number of 16-bit data length. |
<> | 144:ef7eb2e8f9f7 | 755 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
<> | 144:ef7eb2e8f9f7 | 756 | * between Master and Slave(example: audio streaming). |
<> | 144:ef7eb2e8f9f7 | 757 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 758 | */ |
<> | 144:ef7eb2e8f9f7 | 759 | HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 760 | { |
<> | 144:ef7eb2e8f9f7 | 761 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 762 | { |
<> | 144:ef7eb2e8f9f7 | 763 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 767 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 768 | |
<> | 144:ef7eb2e8f9f7 | 769 | if(hi2s->State == HAL_I2S_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 770 | { |
<> | 144:ef7eb2e8f9f7 | 771 | hi2s->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 772 | hi2s->State = HAL_I2S_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 773 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 774 | |
<> | 144:ef7eb2e8f9f7 | 775 | if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ |
<> | 144:ef7eb2e8f9f7 | 776 | ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) |
<> | 144:ef7eb2e8f9f7 | 777 | { |
<> | 144:ef7eb2e8f9f7 | 778 | hi2s->TxXferSize = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 779 | hi2s->TxXferCount = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 780 | } |
<> | 144:ef7eb2e8f9f7 | 781 | else |
<> | 144:ef7eb2e8f9f7 | 782 | { |
<> | 144:ef7eb2e8f9f7 | 783 | hi2s->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 784 | hi2s->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 785 | } |
<> | 144:ef7eb2e8f9f7 | 786 | |
<> | 144:ef7eb2e8f9f7 | 787 | /* Set the I2S Tx DMA Half transfert complete callback */ |
<> | 144:ef7eb2e8f9f7 | 788 | hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; |
<> | 144:ef7eb2e8f9f7 | 789 | |
<> | 144:ef7eb2e8f9f7 | 790 | /* Set the I2S Tx DMA transfert complete callback */ |
<> | 144:ef7eb2e8f9f7 | 791 | hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; |
<> | 144:ef7eb2e8f9f7 | 792 | |
<> | 144:ef7eb2e8f9f7 | 793 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 794 | hi2s->hdmatx->XferErrorCallback = I2S_DMAError; |
<> | 144:ef7eb2e8f9f7 | 795 | |
<> | 144:ef7eb2e8f9f7 | 796 | /* Enable the Tx DMA Channel */ |
<> | 144:ef7eb2e8f9f7 | 797 | HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); |
<> | 144:ef7eb2e8f9f7 | 798 | |
<> | 144:ef7eb2e8f9f7 | 799 | /* Check if the I2S is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 800 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
<> | 144:ef7eb2e8f9f7 | 801 | { |
<> | 144:ef7eb2e8f9f7 | 802 | /* Enable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 803 | __HAL_I2S_ENABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 804 | } |
<> | 144:ef7eb2e8f9f7 | 805 | |
<> | 144:ef7eb2e8f9f7 | 806 | /* Check if the I2S Tx request is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 807 | if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) |
<> | 144:ef7eb2e8f9f7 | 808 | { |
<> | 144:ef7eb2e8f9f7 | 809 | /* Enable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 810 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 811 | } |
<> | 144:ef7eb2e8f9f7 | 812 | |
<> | 144:ef7eb2e8f9f7 | 813 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 814 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 815 | |
<> | 144:ef7eb2e8f9f7 | 816 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 817 | } |
<> | 144:ef7eb2e8f9f7 | 818 | else |
<> | 144:ef7eb2e8f9f7 | 819 | { |
<> | 144:ef7eb2e8f9f7 | 820 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 821 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 822 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 823 | } |
<> | 144:ef7eb2e8f9f7 | 824 | } |
<> | 144:ef7eb2e8f9f7 | 825 | |
<> | 144:ef7eb2e8f9f7 | 826 | /** |
<> | 144:ef7eb2e8f9f7 | 827 | * @brief Receive an amount of data in non-blocking mode with DMA |
<> | 144:ef7eb2e8f9f7 | 828 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 829 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 830 | * @param pData: a 16-bit pointer to the Receive data buffer. |
<> | 144:ef7eb2e8f9f7 | 831 | * @param Size: number of data sample to be sent: |
<> | 144:ef7eb2e8f9f7 | 832 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
<> | 144:ef7eb2e8f9f7 | 833 | * configuration phase, the Size parameter means the number of 16-bit data length |
<> | 144:ef7eb2e8f9f7 | 834 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
<> | 144:ef7eb2e8f9f7 | 835 | * the Size parameter means the number of 16-bit data length. |
<> | 144:ef7eb2e8f9f7 | 836 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
<> | 144:ef7eb2e8f9f7 | 837 | * between Master and Slave(example: audio streaming). |
<> | 144:ef7eb2e8f9f7 | 838 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 839 | */ |
<> | 144:ef7eb2e8f9f7 | 840 | HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 841 | { |
<> | 144:ef7eb2e8f9f7 | 842 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 843 | { |
<> | 144:ef7eb2e8f9f7 | 844 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 845 | } |
<> | 144:ef7eb2e8f9f7 | 846 | |
<> | 144:ef7eb2e8f9f7 | 847 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 848 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 849 | |
<> | 144:ef7eb2e8f9f7 | 850 | if(hi2s->State == HAL_I2S_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 851 | { |
<> | 144:ef7eb2e8f9f7 | 852 | hi2s->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 853 | hi2s->State = HAL_I2S_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 854 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 855 | |
<> | 144:ef7eb2e8f9f7 | 856 | if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ |
<> | 144:ef7eb2e8f9f7 | 857 | ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) |
<> | 144:ef7eb2e8f9f7 | 858 | { |
<> | 144:ef7eb2e8f9f7 | 859 | hi2s->RxXferSize = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 860 | hi2s->RxXferCount = (Size << 1); |
<> | 144:ef7eb2e8f9f7 | 861 | } |
<> | 144:ef7eb2e8f9f7 | 862 | else |
<> | 144:ef7eb2e8f9f7 | 863 | { |
<> | 144:ef7eb2e8f9f7 | 864 | hi2s->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 865 | hi2s->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 866 | } |
<> | 144:ef7eb2e8f9f7 | 867 | |
<> | 144:ef7eb2e8f9f7 | 868 | |
<> | 144:ef7eb2e8f9f7 | 869 | /* Set the I2S Rx DMA Half transfert complete callback */ |
<> | 144:ef7eb2e8f9f7 | 870 | hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; |
<> | 144:ef7eb2e8f9f7 | 871 | |
<> | 144:ef7eb2e8f9f7 | 872 | /* Set the I2S Rx DMA transfert complete callback */ |
<> | 144:ef7eb2e8f9f7 | 873 | hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; |
<> | 144:ef7eb2e8f9f7 | 874 | |
<> | 144:ef7eb2e8f9f7 | 875 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 876 | hi2s->hdmarx->XferErrorCallback = I2S_DMAError; |
<> | 144:ef7eb2e8f9f7 | 877 | |
<> | 144:ef7eb2e8f9f7 | 878 | /* Check if Master Receiver mode is selected */ |
<> | 144:ef7eb2e8f9f7 | 879 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
<> | 144:ef7eb2e8f9f7 | 880 | { |
<> | 144:ef7eb2e8f9f7 | 881 | /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read |
<> | 144:ef7eb2e8f9f7 | 882 | access to the SPI_SR register. */ |
<> | 144:ef7eb2e8f9f7 | 883 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
<> | 144:ef7eb2e8f9f7 | 884 | } |
<> | 144:ef7eb2e8f9f7 | 885 | |
<> | 144:ef7eb2e8f9f7 | 886 | /* Enable the Rx DMA Channel */ |
<> | 144:ef7eb2e8f9f7 | 887 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize); |
<> | 144:ef7eb2e8f9f7 | 888 | |
<> | 144:ef7eb2e8f9f7 | 889 | /* Check if the I2S is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 890 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
<> | 144:ef7eb2e8f9f7 | 891 | { |
<> | 144:ef7eb2e8f9f7 | 892 | /* Enable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 893 | __HAL_I2S_ENABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 894 | } |
<> | 144:ef7eb2e8f9f7 | 895 | |
<> | 144:ef7eb2e8f9f7 | 896 | /* Check if the I2S Rx request is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 897 | if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) |
<> | 144:ef7eb2e8f9f7 | 898 | { |
<> | 144:ef7eb2e8f9f7 | 899 | /* Enable Rx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 900 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 901 | } |
<> | 144:ef7eb2e8f9f7 | 902 | |
<> | 144:ef7eb2e8f9f7 | 903 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 904 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 905 | |
<> | 144:ef7eb2e8f9f7 | 906 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 907 | } |
<> | 144:ef7eb2e8f9f7 | 908 | else |
<> | 144:ef7eb2e8f9f7 | 909 | { |
<> | 144:ef7eb2e8f9f7 | 910 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 911 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 912 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 913 | } |
<> | 144:ef7eb2e8f9f7 | 914 | } |
<> | 144:ef7eb2e8f9f7 | 915 | |
<> | 144:ef7eb2e8f9f7 | 916 | /** |
<> | 144:ef7eb2e8f9f7 | 917 | * @brief Pauses the audio stream playing from the Media. |
<> | 144:ef7eb2e8f9f7 | 918 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 919 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 920 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 921 | */ |
<> | 144:ef7eb2e8f9f7 | 922 | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 923 | { |
<> | 144:ef7eb2e8f9f7 | 924 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 925 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 926 | |
<> | 144:ef7eb2e8f9f7 | 927 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 928 | { |
<> | 144:ef7eb2e8f9f7 | 929 | /* Disable the I2S DMA Tx request */ |
<> | 144:ef7eb2e8f9f7 | 930 | hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 931 | } |
<> | 144:ef7eb2e8f9f7 | 932 | else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 933 | { |
<> | 144:ef7eb2e8f9f7 | 934 | /* Disable the I2S DMA Rx request */ |
<> | 144:ef7eb2e8f9f7 | 935 | hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 936 | } |
<> | 144:ef7eb2e8f9f7 | 937 | |
<> | 144:ef7eb2e8f9f7 | 938 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 939 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 940 | |
<> | 144:ef7eb2e8f9f7 | 941 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 942 | } |
<> | 144:ef7eb2e8f9f7 | 943 | |
<> | 144:ef7eb2e8f9f7 | 944 | /** |
<> | 144:ef7eb2e8f9f7 | 945 | * @brief Resumes the audio stream playing from the Media. |
<> | 144:ef7eb2e8f9f7 | 946 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 947 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 948 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 949 | */ |
<> | 144:ef7eb2e8f9f7 | 950 | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 951 | { |
<> | 144:ef7eb2e8f9f7 | 952 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 953 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 954 | |
<> | 144:ef7eb2e8f9f7 | 955 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 956 | { |
<> | 144:ef7eb2e8f9f7 | 957 | /* Enable the I2S DMA Tx request */ |
<> | 144:ef7eb2e8f9f7 | 958 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 959 | } |
<> | 144:ef7eb2e8f9f7 | 960 | else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 961 | { |
<> | 144:ef7eb2e8f9f7 | 962 | /* Enable the I2S DMA Rx request */ |
<> | 144:ef7eb2e8f9f7 | 963 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 964 | } |
<> | 144:ef7eb2e8f9f7 | 965 | |
<> | 144:ef7eb2e8f9f7 | 966 | /* If the I2S peripheral is still not enabled, enable it */ |
<> | 144:ef7eb2e8f9f7 | 967 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) |
<> | 144:ef7eb2e8f9f7 | 968 | { |
<> | 144:ef7eb2e8f9f7 | 969 | /* Enable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 970 | __HAL_I2S_ENABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 971 | } |
<> | 144:ef7eb2e8f9f7 | 972 | |
<> | 144:ef7eb2e8f9f7 | 973 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 974 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 975 | |
<> | 144:ef7eb2e8f9f7 | 976 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 977 | } |
<> | 144:ef7eb2e8f9f7 | 978 | |
<> | 144:ef7eb2e8f9f7 | 979 | /** |
<> | 144:ef7eb2e8f9f7 | 980 | * @brief Resumes the audio stream playing from the Media. |
<> | 144:ef7eb2e8f9f7 | 981 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 982 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 983 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 984 | */ |
<> | 144:ef7eb2e8f9f7 | 985 | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 986 | { |
<> | 144:ef7eb2e8f9f7 | 987 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 988 | __HAL_LOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 989 | |
<> | 144:ef7eb2e8f9f7 | 990 | /* Disable the I2S Tx/Rx DMA requests */ |
<> | 144:ef7eb2e8f9f7 | 991 | hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 992 | hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 993 | |
<> | 144:ef7eb2e8f9f7 | 994 | /* Abort the I2S DMA tx channel */ |
<> | 144:ef7eb2e8f9f7 | 995 | if(hi2s->hdmatx != NULL) |
<> | 144:ef7eb2e8f9f7 | 996 | { |
<> | 144:ef7eb2e8f9f7 | 997 | /* Disable the I2S DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 998 | __HAL_DMA_DISABLE(hi2s->hdmatx); |
<> | 144:ef7eb2e8f9f7 | 999 | HAL_DMA_Abort(hi2s->hdmatx); |
<> | 144:ef7eb2e8f9f7 | 1000 | } |
<> | 144:ef7eb2e8f9f7 | 1001 | /* Abort the I2S DMA rx channel */ |
<> | 144:ef7eb2e8f9f7 | 1002 | if(hi2s->hdmarx != NULL) |
<> | 144:ef7eb2e8f9f7 | 1003 | { |
<> | 144:ef7eb2e8f9f7 | 1004 | /* Disable the I2S DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1005 | __HAL_DMA_DISABLE(hi2s->hdmarx); |
<> | 144:ef7eb2e8f9f7 | 1006 | HAL_DMA_Abort(hi2s->hdmarx); |
<> | 144:ef7eb2e8f9f7 | 1007 | } |
<> | 144:ef7eb2e8f9f7 | 1008 | |
<> | 144:ef7eb2e8f9f7 | 1009 | /* Disable I2S peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1010 | __HAL_I2S_DISABLE(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1011 | |
<> | 144:ef7eb2e8f9f7 | 1012 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1013 | |
<> | 144:ef7eb2e8f9f7 | 1014 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1015 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1016 | |
<> | 144:ef7eb2e8f9f7 | 1017 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1018 | } |
<> | 144:ef7eb2e8f9f7 | 1019 | |
<> | 144:ef7eb2e8f9f7 | 1020 | /** |
<> | 144:ef7eb2e8f9f7 | 1021 | * @brief This function handles I2S interrupt request. |
<> | 144:ef7eb2e8f9f7 | 1022 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1023 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1024 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1025 | */ |
<> | 144:ef7eb2e8f9f7 | 1026 | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1027 | { |
<> | 144:ef7eb2e8f9f7 | 1028 | uint32_t i2ssr = hi2s->Instance->SR; |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 144:ef7eb2e8f9f7 | 1030 | /* I2S in mode Receiver ------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1031 | if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) && |
<> | 144:ef7eb2e8f9f7 | 1032 | ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1033 | { |
<> | 144:ef7eb2e8f9f7 | 1034 | I2S_Receive_IT(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1035 | return; |
<> | 144:ef7eb2e8f9f7 | 1036 | } |
<> | 144:ef7eb2e8f9f7 | 1037 | |
<> | 144:ef7eb2e8f9f7 | 1038 | /* I2S in mode Tramitter -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1039 | if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1040 | { |
<> | 144:ef7eb2e8f9f7 | 1041 | I2S_Transmit_IT(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1042 | return; |
<> | 144:ef7eb2e8f9f7 | 1043 | } |
<> | 144:ef7eb2e8f9f7 | 1044 | |
<> | 144:ef7eb2e8f9f7 | 1045 | /* I2S Overrun error interrupt occured ---------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1046 | if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1047 | { |
<> | 144:ef7eb2e8f9f7 | 1048 | /* Disable RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1049 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1050 | |
<> | 144:ef7eb2e8f9f7 | 1051 | /* Set the I2S State ready */ |
<> | 144:ef7eb2e8f9f7 | 1052 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1053 | |
<> | 144:ef7eb2e8f9f7 | 1054 | /* Set the error code and execute error callback*/ |
<> | 144:ef7eb2e8f9f7 | 1055 | hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; |
<> | 144:ef7eb2e8f9f7 | 1056 | HAL_I2S_ErrorCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1057 | } |
<> | 144:ef7eb2e8f9f7 | 1058 | |
<> | 144:ef7eb2e8f9f7 | 1059 | /* I2S Underrun error interrupt occured --------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1060 | if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1061 | { |
<> | 144:ef7eb2e8f9f7 | 1062 | /* Disable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1063 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1064 | |
<> | 144:ef7eb2e8f9f7 | 1065 | /* Set the I2S State ready */ |
<> | 144:ef7eb2e8f9f7 | 1066 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1067 | |
<> | 144:ef7eb2e8f9f7 | 1068 | /* Set the error code and execute error callback*/ |
<> | 144:ef7eb2e8f9f7 | 1069 | hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; |
<> | 144:ef7eb2e8f9f7 | 1070 | HAL_I2S_ErrorCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1071 | } |
<> | 144:ef7eb2e8f9f7 | 1072 | } |
<> | 144:ef7eb2e8f9f7 | 1073 | |
<> | 144:ef7eb2e8f9f7 | 1074 | /** |
<> | 144:ef7eb2e8f9f7 | 1075 | * @brief Tx Transfer Half completed callbacks |
<> | 144:ef7eb2e8f9f7 | 1076 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1077 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1078 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1079 | */ |
<> | 144:ef7eb2e8f9f7 | 1080 | __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1081 | { |
<> | 144:ef7eb2e8f9f7 | 1082 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1083 | UNUSED(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1084 | |
<> | 144:ef7eb2e8f9f7 | 1085 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1086 | the HAL_I2S_TxHalfCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1087 | */ |
<> | 144:ef7eb2e8f9f7 | 1088 | } |
<> | 144:ef7eb2e8f9f7 | 1089 | |
<> | 144:ef7eb2e8f9f7 | 1090 | /** |
<> | 144:ef7eb2e8f9f7 | 1091 | * @brief Tx Transfer completed callbacks |
<> | 144:ef7eb2e8f9f7 | 1092 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1093 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1094 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1095 | */ |
<> | 144:ef7eb2e8f9f7 | 1096 | __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1097 | { |
<> | 144:ef7eb2e8f9f7 | 1098 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1099 | UNUSED(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1100 | |
<> | 144:ef7eb2e8f9f7 | 1101 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1102 | the HAL_I2S_TxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1103 | */ |
<> | 144:ef7eb2e8f9f7 | 1104 | } |
<> | 144:ef7eb2e8f9f7 | 1105 | |
<> | 144:ef7eb2e8f9f7 | 1106 | /** |
<> | 144:ef7eb2e8f9f7 | 1107 | * @brief Rx Transfer half completed callbacks |
<> | 144:ef7eb2e8f9f7 | 1108 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1109 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1110 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1111 | */ |
<> | 144:ef7eb2e8f9f7 | 1112 | __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1113 | { |
<> | 144:ef7eb2e8f9f7 | 1114 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1115 | UNUSED(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1116 | |
<> | 144:ef7eb2e8f9f7 | 1117 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1118 | the HAL_I2S_RxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1119 | */ |
<> | 144:ef7eb2e8f9f7 | 1120 | } |
<> | 144:ef7eb2e8f9f7 | 1121 | |
<> | 144:ef7eb2e8f9f7 | 1122 | /** |
<> | 144:ef7eb2e8f9f7 | 1123 | * @brief Rx Transfer completed callbacks |
<> | 144:ef7eb2e8f9f7 | 1124 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1125 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1126 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1127 | */ |
<> | 144:ef7eb2e8f9f7 | 1128 | __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1129 | { |
<> | 144:ef7eb2e8f9f7 | 1130 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1131 | UNUSED(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1132 | |
<> | 144:ef7eb2e8f9f7 | 1133 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1134 | the HAL_I2S_RxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1135 | */ |
<> | 144:ef7eb2e8f9f7 | 1136 | } |
<> | 144:ef7eb2e8f9f7 | 1137 | |
<> | 144:ef7eb2e8f9f7 | 1138 | /** |
<> | 144:ef7eb2e8f9f7 | 1139 | * @brief I2S error callbacks |
<> | 144:ef7eb2e8f9f7 | 1140 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1141 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1142 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1143 | */ |
<> | 144:ef7eb2e8f9f7 | 1144 | __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1145 | { |
<> | 144:ef7eb2e8f9f7 | 1146 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1147 | UNUSED(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1148 | |
<> | 144:ef7eb2e8f9f7 | 1149 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1150 | the HAL_I2S_ErrorCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1151 | */ |
<> | 144:ef7eb2e8f9f7 | 1152 | } |
<> | 144:ef7eb2e8f9f7 | 1153 | |
<> | 144:ef7eb2e8f9f7 | 1154 | /** |
<> | 144:ef7eb2e8f9f7 | 1155 | * @} |
<> | 144:ef7eb2e8f9f7 | 1156 | */ |
<> | 144:ef7eb2e8f9f7 | 1157 | |
<> | 144:ef7eb2e8f9f7 | 1158 | /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions |
<> | 144:ef7eb2e8f9f7 | 1159 | * @brief Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1160 | * |
<> | 144:ef7eb2e8f9f7 | 1161 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1162 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1163 | ##### Peripheral State and Errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1164 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1165 | [..] |
<> | 144:ef7eb2e8f9f7 | 1166 | This subsection permits to get in run-time the status of the peripheral |
<> | 144:ef7eb2e8f9f7 | 1167 | and the data flow. |
<> | 144:ef7eb2e8f9f7 | 1168 | |
<> | 144:ef7eb2e8f9f7 | 1169 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1170 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1171 | */ |
<> | 144:ef7eb2e8f9f7 | 1172 | |
<> | 144:ef7eb2e8f9f7 | 1173 | /** |
<> | 144:ef7eb2e8f9f7 | 1174 | * @brief Return the I2S state |
<> | 144:ef7eb2e8f9f7 | 1175 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1176 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1177 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 1178 | */ |
<> | 144:ef7eb2e8f9f7 | 1179 | HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1180 | { |
<> | 144:ef7eb2e8f9f7 | 1181 | return hi2s->State; |
<> | 144:ef7eb2e8f9f7 | 1182 | } |
<> | 144:ef7eb2e8f9f7 | 1183 | |
<> | 144:ef7eb2e8f9f7 | 1184 | /** |
<> | 144:ef7eb2e8f9f7 | 1185 | * @brief Return the I2S error code |
<> | 144:ef7eb2e8f9f7 | 1186 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1187 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1188 | * @retval I2S Error Code |
<> | 144:ef7eb2e8f9f7 | 1189 | */ |
<> | 144:ef7eb2e8f9f7 | 1190 | uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1191 | { |
<> | 144:ef7eb2e8f9f7 | 1192 | return hi2s->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1193 | } |
<> | 144:ef7eb2e8f9f7 | 1194 | /** |
<> | 144:ef7eb2e8f9f7 | 1195 | * @} |
<> | 144:ef7eb2e8f9f7 | 1196 | */ |
<> | 144:ef7eb2e8f9f7 | 1197 | |
<> | 144:ef7eb2e8f9f7 | 1198 | /** |
<> | 144:ef7eb2e8f9f7 | 1199 | * @} |
<> | 144:ef7eb2e8f9f7 | 1200 | */ |
<> | 144:ef7eb2e8f9f7 | 1201 | |
<> | 144:ef7eb2e8f9f7 | 1202 | /** @addtogroup I2S_Private_Functions I2S Private Functions |
<> | 144:ef7eb2e8f9f7 | 1203 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1204 | */ |
<> | 144:ef7eb2e8f9f7 | 1205 | /** |
<> | 144:ef7eb2e8f9f7 | 1206 | * @brief DMA I2S transmit process complete callback |
<> | 144:ef7eb2e8f9f7 | 1207 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1208 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1209 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1210 | */ |
<> | 144:ef7eb2e8f9f7 | 1211 | static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1212 | { |
<> | 144:ef7eb2e8f9f7 | 1213 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1214 | |
<> | 144:ef7eb2e8f9f7 | 1215 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) |
<> | 144:ef7eb2e8f9f7 | 1216 | { |
<> | 144:ef7eb2e8f9f7 | 1217 | /* Disable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1218 | hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1219 | |
<> | 144:ef7eb2e8f9f7 | 1220 | hi2s->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1221 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1222 | } |
<> | 144:ef7eb2e8f9f7 | 1223 | HAL_I2S_TxCpltCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1224 | } |
<> | 144:ef7eb2e8f9f7 | 1225 | |
<> | 144:ef7eb2e8f9f7 | 1226 | /** |
<> | 144:ef7eb2e8f9f7 | 1227 | * @brief DMA I2S transmit process half complete callback |
<> | 144:ef7eb2e8f9f7 | 1228 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1229 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1230 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1231 | */ |
<> | 144:ef7eb2e8f9f7 | 1232 | static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1233 | { |
<> | 144:ef7eb2e8f9f7 | 1234 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1235 | |
<> | 144:ef7eb2e8f9f7 | 1236 | HAL_I2S_TxHalfCpltCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1237 | } |
<> | 144:ef7eb2e8f9f7 | 1238 | |
<> | 144:ef7eb2e8f9f7 | 1239 | /** |
<> | 144:ef7eb2e8f9f7 | 1240 | * @brief DMA I2S receive process complete callback |
<> | 144:ef7eb2e8f9f7 | 1241 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1242 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1243 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1244 | */ |
<> | 144:ef7eb2e8f9f7 | 1245 | static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1246 | { |
<> | 144:ef7eb2e8f9f7 | 1247 | I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1248 | |
<> | 144:ef7eb2e8f9f7 | 1249 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) |
<> | 144:ef7eb2e8f9f7 | 1250 | { |
<> | 144:ef7eb2e8f9f7 | 1251 | /* Disable Rx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1252 | hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1253 | hi2s->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1254 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1255 | } |
<> | 144:ef7eb2e8f9f7 | 1256 | HAL_I2S_RxCpltCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1257 | } |
<> | 144:ef7eb2e8f9f7 | 1258 | |
<> | 144:ef7eb2e8f9f7 | 1259 | /** |
<> | 144:ef7eb2e8f9f7 | 1260 | * @brief DMA I2S receive process half complete callback |
<> | 144:ef7eb2e8f9f7 | 1261 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1262 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1263 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1264 | */ |
<> | 144:ef7eb2e8f9f7 | 1265 | static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1266 | { |
<> | 144:ef7eb2e8f9f7 | 1267 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1268 | |
<> | 144:ef7eb2e8f9f7 | 1269 | HAL_I2S_RxHalfCpltCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1270 | } |
<> | 144:ef7eb2e8f9f7 | 1271 | |
<> | 144:ef7eb2e8f9f7 | 1272 | /** |
<> | 144:ef7eb2e8f9f7 | 1273 | * @brief DMA I2S communication error callback |
<> | 144:ef7eb2e8f9f7 | 1274 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1275 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1276 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1277 | */ |
<> | 144:ef7eb2e8f9f7 | 1278 | static void I2S_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1279 | { |
<> | 144:ef7eb2e8f9f7 | 1280 | I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1281 | |
<> | 144:ef7eb2e8f9f7 | 1282 | /* Disable Rx and Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1283 | hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); |
<> | 144:ef7eb2e8f9f7 | 1284 | hi2s->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1285 | hi2s->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1286 | |
<> | 144:ef7eb2e8f9f7 | 1287 | hi2s->State= HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1288 | |
<> | 144:ef7eb2e8f9f7 | 1289 | /* Set the error code and execute error callback*/ |
<> | 144:ef7eb2e8f9f7 | 1290 | hi2s->ErrorCode |= HAL_I2S_ERROR_DMA; |
<> | 144:ef7eb2e8f9f7 | 1291 | HAL_I2S_ErrorCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1292 | } |
<> | 144:ef7eb2e8f9f7 | 1293 | |
<> | 144:ef7eb2e8f9f7 | 1294 | /** |
<> | 144:ef7eb2e8f9f7 | 1295 | * @brief Transmit an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1296 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1297 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1298 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1299 | */ |
<> | 144:ef7eb2e8f9f7 | 1300 | static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1301 | { |
<> | 144:ef7eb2e8f9f7 | 1302 | /* Transmit data */ |
<> | 144:ef7eb2e8f9f7 | 1303 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 1304 | hi2s->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 1305 | |
<> | 144:ef7eb2e8f9f7 | 1306 | if(hi2s->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 1307 | { |
<> | 144:ef7eb2e8f9f7 | 1308 | /* Disable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1309 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1310 | |
<> | 144:ef7eb2e8f9f7 | 1311 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1312 | HAL_I2S_TxCpltCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1313 | } |
<> | 144:ef7eb2e8f9f7 | 1314 | } |
<> | 144:ef7eb2e8f9f7 | 1315 | |
<> | 144:ef7eb2e8f9f7 | 1316 | /** |
<> | 144:ef7eb2e8f9f7 | 1317 | * @brief Receive an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1318 | * @param hi2s: I2S handle |
<> | 144:ef7eb2e8f9f7 | 1319 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1320 | */ |
<> | 144:ef7eb2e8f9f7 | 1321 | static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) |
<> | 144:ef7eb2e8f9f7 | 1322 | { |
<> | 144:ef7eb2e8f9f7 | 1323 | /* Receive data */ |
<> | 144:ef7eb2e8f9f7 | 1324 | (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 1325 | hi2s->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 1326 | |
<> | 144:ef7eb2e8f9f7 | 1327 | if(hi2s->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 1328 | { |
<> | 144:ef7eb2e8f9f7 | 1329 | /* Disable RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1330 | __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1331 | |
<> | 144:ef7eb2e8f9f7 | 1332 | hi2s->State = HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1333 | HAL_I2S_RxCpltCallback(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1334 | } |
<> | 144:ef7eb2e8f9f7 | 1335 | } |
<> | 144:ef7eb2e8f9f7 | 1336 | |
<> | 144:ef7eb2e8f9f7 | 1337 | |
<> | 144:ef7eb2e8f9f7 | 1338 | /** |
<> | 144:ef7eb2e8f9f7 | 1339 | * @brief This function handles I2S Communication Timeout. |
<> | 144:ef7eb2e8f9f7 | 1340 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1341 | * the configuration information for I2S module |
<> | 144:ef7eb2e8f9f7 | 1342 | * @param Flag: Flag checked |
<> | 144:ef7eb2e8f9f7 | 1343 | * @param State: Value of the flag expected |
<> | 144:ef7eb2e8f9f7 | 1344 | * @param Timeout: Duration of the timeout |
<> | 144:ef7eb2e8f9f7 | 1345 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1346 | */ |
<> | 144:ef7eb2e8f9f7 | 1347 | static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1348 | { |
<> | 144:ef7eb2e8f9f7 | 1349 | uint32_t tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1350 | |
<> | 144:ef7eb2e8f9f7 | 1351 | /* Wait until flag is set */ |
<> | 144:ef7eb2e8f9f7 | 1352 | if(State == RESET) |
<> | 144:ef7eb2e8f9f7 | 1353 | { |
<> | 144:ef7eb2e8f9f7 | 1354 | while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1355 | { |
<> | 144:ef7eb2e8f9f7 | 1356 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1357 | { |
<> | 144:ef7eb2e8f9f7 | 1358 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1359 | { |
<> | 144:ef7eb2e8f9f7 | 1360 | /* Set the I2S State ready */ |
<> | 144:ef7eb2e8f9f7 | 1361 | hi2s->State= HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1362 | |
<> | 144:ef7eb2e8f9f7 | 1363 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1364 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1365 | |
<> | 144:ef7eb2e8f9f7 | 1366 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1367 | } |
<> | 144:ef7eb2e8f9f7 | 1368 | } |
<> | 144:ef7eb2e8f9f7 | 1369 | } |
<> | 144:ef7eb2e8f9f7 | 1370 | } |
<> | 144:ef7eb2e8f9f7 | 1371 | else |
<> | 144:ef7eb2e8f9f7 | 1372 | { |
<> | 144:ef7eb2e8f9f7 | 1373 | while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1374 | { |
<> | 144:ef7eb2e8f9f7 | 1375 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1376 | { |
<> | 144:ef7eb2e8f9f7 | 1377 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1378 | { |
<> | 144:ef7eb2e8f9f7 | 1379 | /* Set the I2S State ready */ |
<> | 144:ef7eb2e8f9f7 | 1380 | hi2s->State= HAL_I2S_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1381 | |
<> | 144:ef7eb2e8f9f7 | 1382 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1383 | __HAL_UNLOCK(hi2s); |
<> | 144:ef7eb2e8f9f7 | 1384 | |
<> | 144:ef7eb2e8f9f7 | 1385 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1386 | } |
<> | 144:ef7eb2e8f9f7 | 1387 | } |
<> | 144:ef7eb2e8f9f7 | 1388 | } |
<> | 144:ef7eb2e8f9f7 | 1389 | } |
<> | 144:ef7eb2e8f9f7 | 1390 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1391 | } |
<> | 144:ef7eb2e8f9f7 | 1392 | |
<> | 144:ef7eb2e8f9f7 | 1393 | /** |
<> | 144:ef7eb2e8f9f7 | 1394 | * @} |
<> | 144:ef7eb2e8f9f7 | 1395 | */ |
<> | 144:ef7eb2e8f9f7 | 1396 | |
<> | 144:ef7eb2e8f9f7 | 1397 | /** |
<> | 144:ef7eb2e8f9f7 | 1398 | * @} |
<> | 144:ef7eb2e8f9f7 | 1399 | */ |
<> | 144:ef7eb2e8f9f7 | 1400 | |
<> | 144:ef7eb2e8f9f7 | 1401 | /** |
<> | 144:ef7eb2e8f9f7 | 1402 | * @} |
<> | 144:ef7eb2e8f9f7 | 1403 | */ |
<> | 144:ef7eb2e8f9f7 | 1404 | |
<> | 144:ef7eb2e8f9f7 | 1405 | #endif /* defined(STM32F031x6) || defined(STM32F038xx) || */ |
<> | 144:ef7eb2e8f9f7 | 1406 | /* defined(STM32F051x8) || defined(STM32F058xx) || */ |
<> | 144:ef7eb2e8f9f7 | 1407 | /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ |
<> | 144:ef7eb2e8f9f7 | 1408 | /* defined(STM32F042x6) || defined(STM32F048xx) || */ |
<> | 144:ef7eb2e8f9f7 | 1409 | /* defined(STM32F091xC) || defined(STM32F098xx) */ |
<> | 144:ef7eb2e8f9f7 | 1410 | |
<> | 144:ef7eb2e8f9f7 | 1411 | #endif /* HAL_I2S_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 1412 | |
<> | 144:ef7eb2e8f9f7 | 1413 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |