Fawwaz Nadzmy / mbed-STM

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_sdmmc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_sdmmc.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief Header file of SDMMC HAL module.
<> 149:156823d33999 8 ******************************************************************************
<> 149:156823d33999 9 * @attention
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 12 *
<> 149:156823d33999 13 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 14 * are permitted provided that the following conditions are met:
<> 149:156823d33999 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer.
<> 149:156823d33999 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 18 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 19 * and/or other materials provided with the distribution.
<> 149:156823d33999 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 21 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 22 * without specific prior written permission.
<> 149:156823d33999 23 *
<> 149:156823d33999 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 34 *
<> 149:156823d33999 35 ******************************************************************************
<> 149:156823d33999 36 */
<> 149:156823d33999 37
<> 149:156823d33999 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 39 #ifndef __STM32L1xx_LL_SD_H
<> 149:156823d33999 40 #define __STM32L1xx_LL_SD_H
<> 149:156823d33999 41
<> 149:156823d33999 42 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
<> 149:156823d33999 43
<> 149:156823d33999 44 #ifdef __cplusplus
<> 149:156823d33999 45 extern "C" {
<> 149:156823d33999 46 #endif
<> 149:156823d33999 47
<> 149:156823d33999 48 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 49 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 50
<> 149:156823d33999 51 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 52 * @{
<> 149:156823d33999 53 */
<> 149:156823d33999 54
<> 149:156823d33999 55 /** @addtogroup SDMMC_LL
<> 149:156823d33999 56 * @{
<> 149:156823d33999 57 */
<> 149:156823d33999 58
<> 149:156823d33999 59 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 60 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
<> 149:156823d33999 61 * @{
<> 149:156823d33999 62 */
<> 149:156823d33999 63
<> 149:156823d33999 64 /**
<> 149:156823d33999 65 * @brief SDMMC Configuration Structure definition
<> 149:156823d33999 66 */
<> 149:156823d33999 67 typedef struct
<> 149:156823d33999 68 {
<> 149:156823d33999 69 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
<> 149:156823d33999 70 This parameter can be a value of @ref SDIO_Clock_Edge */
<> 149:156823d33999 71
<> 149:156823d33999 72 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
<> 149:156823d33999 73 enabled or disabled.
<> 149:156823d33999 74 This parameter can be a value of @ref SDIO_Clock_Bypass */
<> 149:156823d33999 75
<> 149:156823d33999 76 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
<> 149:156823d33999 77 disabled when the bus is idle.
<> 149:156823d33999 78 This parameter can be a value of @ref SDIO_Clock_Power_Save */
<> 149:156823d33999 79
<> 149:156823d33999 80 uint32_t BusWide; /*!< Specifies the SDIO bus width.
<> 149:156823d33999 81 This parameter can be a value of @ref SDIO_Bus_Wide */
<> 149:156823d33999 82
<> 149:156823d33999 83 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
<> 149:156823d33999 84 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
<> 149:156823d33999 85
<> 149:156823d33999 86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
<> 149:156823d33999 87 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 149:156823d33999 88
<> 149:156823d33999 89 }SDIO_InitTypeDef;
<> 149:156823d33999 90
<> 149:156823d33999 91
<> 149:156823d33999 92 /**
<> 149:156823d33999 93 * @brief SDIO Command Control structure
<> 149:156823d33999 94 */
<> 149:156823d33999 95 typedef struct
<> 149:156823d33999 96 {
<> 149:156823d33999 97 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
<> 149:156823d33999 98 to a card as part of a command message. If a command
<> 149:156823d33999 99 contains an argument, it must be loaded into this register
<> 149:156823d33999 100 before writing the command to the command register. */
<> 149:156823d33999 101
<> 149:156823d33999 102 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
<> 149:156823d33999 103 Max_Data = 64 */
<> 149:156823d33999 104
<> 149:156823d33999 105 uint32_t Response; /*!< Specifies the SDIO response type.
<> 149:156823d33999 106 This parameter can be a value of @ref SDIO_Response_Type */
<> 149:156823d33999 107
<> 149:156823d33999 108 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
<> 149:156823d33999 109 enabled or disabled.
<> 149:156823d33999 110 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
<> 149:156823d33999 111
<> 149:156823d33999 112 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
<> 149:156823d33999 113 is enabled or disabled.
<> 149:156823d33999 114 This parameter can be a value of @ref SDIO_CPSM_State */
<> 149:156823d33999 115 }SDIO_CmdInitTypeDef;
<> 149:156823d33999 116
<> 149:156823d33999 117
<> 149:156823d33999 118 /**
<> 149:156823d33999 119 * @brief SDIO Data Control structure
<> 149:156823d33999 120 */
<> 149:156823d33999 121 typedef struct
<> 149:156823d33999 122 {
<> 149:156823d33999 123 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
<> 149:156823d33999 124
<> 149:156823d33999 125 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
<> 149:156823d33999 126
<> 149:156823d33999 127 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
<> 149:156823d33999 128 This parameter can be a value of @ref SDIO_Data_Block_Size */
<> 149:156823d33999 129
<> 149:156823d33999 130 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
<> 149:156823d33999 131 is a read or write.
<> 149:156823d33999 132 This parameter can be a value of @ref SDIO_Transfer_Direction */
<> 149:156823d33999 133
<> 149:156823d33999 134 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
<> 149:156823d33999 135 This parameter can be a value of @ref SDIO_Transfer_Type */
<> 149:156823d33999 136
<> 149:156823d33999 137 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
<> 149:156823d33999 138 is enabled or disabled.
<> 149:156823d33999 139 This parameter can be a value of @ref SDIO_DPSM_State */
<> 149:156823d33999 140 }SDIO_DataInitTypeDef;
<> 149:156823d33999 141
<> 149:156823d33999 142 /**
<> 149:156823d33999 143 * @}
<> 149:156823d33999 144 */
<> 149:156823d33999 145
<> 149:156823d33999 146 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 147 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
<> 149:156823d33999 148 * @{
<> 149:156823d33999 149 */
<> 149:156823d33999 150
<> 149:156823d33999 151 /** @defgroup SDIO_Clock_Edge Clock Edge
<> 149:156823d33999 152 * @{
<> 149:156823d33999 153 */
<> 149:156823d33999 154 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
<> 149:156823d33999 155 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
<> 149:156823d33999 156
<> 149:156823d33999 157 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
<> 149:156823d33999 158 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
<> 149:156823d33999 159 /**
<> 149:156823d33999 160 * @}
<> 149:156823d33999 161 */
<> 149:156823d33999 162
<> 149:156823d33999 163 /** @defgroup SDIO_Clock_Bypass Clock Bypass
<> 149:156823d33999 164 * @{
<> 149:156823d33999 165 */
<> 149:156823d33999 166 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
<> 149:156823d33999 167 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
<> 149:156823d33999 168
<> 149:156823d33999 169 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
<> 149:156823d33999 170 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
<> 149:156823d33999 171 /**
<> 149:156823d33999 172 * @}
<> 149:156823d33999 173 */
<> 149:156823d33999 174
<> 149:156823d33999 175 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
<> 149:156823d33999 176 * @{
<> 149:156823d33999 177 */
<> 149:156823d33999 178 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
<> 149:156823d33999 179 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
<> 149:156823d33999 180
<> 149:156823d33999 181 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
<> 149:156823d33999 182 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
<> 149:156823d33999 183 /**
<> 149:156823d33999 184 * @}
<> 149:156823d33999 185 */
<> 149:156823d33999 186
<> 149:156823d33999 187 /** @defgroup SDIO_Bus_Wide Bus Width
<> 149:156823d33999 188 * @{
<> 149:156823d33999 189 */
<> 149:156823d33999 190 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
<> 149:156823d33999 191 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
<> 149:156823d33999 192 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
<> 149:156823d33999 193
<> 149:156823d33999 194 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
<> 149:156823d33999 195 ((WIDE) == SDIO_BUS_WIDE_4B) || \
<> 149:156823d33999 196 ((WIDE) == SDIO_BUS_WIDE_8B))
<> 149:156823d33999 197 /**
<> 149:156823d33999 198 * @}
<> 149:156823d33999 199 */
<> 149:156823d33999 200
<> 149:156823d33999 201 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
<> 149:156823d33999 202 * @{
<> 149:156823d33999 203 */
<> 149:156823d33999 204 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
<> 149:156823d33999 205 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
<> 149:156823d33999 206
<> 149:156823d33999 207 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
<> 149:156823d33999 208 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
<> 149:156823d33999 209 /**
<> 149:156823d33999 210 * @}
<> 149:156823d33999 211 */
<> 149:156823d33999 212
<> 149:156823d33999 213 /** @defgroup SDIO_Clock_Division Clock Division
<> 149:156823d33999 214 * @{
<> 149:156823d33999 215 */
<> 149:156823d33999 216 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
<> 149:156823d33999 217 /**
<> 149:156823d33999 218 * @}
<> 149:156823d33999 219 */
<> 149:156823d33999 220
<> 149:156823d33999 221 /** @defgroup SDIO_Command_Index Command Index
<> 149:156823d33999 222 * @{
<> 149:156823d33999 223 */
<> 149:156823d33999 224 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
<> 149:156823d33999 225 /**
<> 149:156823d33999 226 * @}
<> 149:156823d33999 227 */
<> 149:156823d33999 228
<> 149:156823d33999 229 /** @defgroup SDIO_Response_Type Response Type
<> 149:156823d33999 230 * @{
<> 149:156823d33999 231 */
<> 149:156823d33999 232 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
<> 149:156823d33999 233 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
<> 149:156823d33999 234 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
<> 149:156823d33999 235
<> 149:156823d33999 236 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
<> 149:156823d33999 237 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
<> 149:156823d33999 238 ((RESPONSE) == SDIO_RESPONSE_LONG))
<> 149:156823d33999 239 /**
<> 149:156823d33999 240 * @}
<> 149:156823d33999 241 */
<> 149:156823d33999 242
<> 149:156823d33999 243 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
<> 149:156823d33999 244 * @{
<> 149:156823d33999 245 */
<> 149:156823d33999 246 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
<> 149:156823d33999 247 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
<> 149:156823d33999 248 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
<> 149:156823d33999 249
<> 149:156823d33999 250 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
<> 149:156823d33999 251 ((WAIT) == SDIO_WAIT_IT) || \
<> 149:156823d33999 252 ((WAIT) == SDIO_WAIT_PEND))
<> 149:156823d33999 253 /**
<> 149:156823d33999 254 * @}
<> 149:156823d33999 255 */
<> 149:156823d33999 256
<> 149:156823d33999 257 /** @defgroup SDIO_CPSM_State CPSM State
<> 149:156823d33999 258 * @{
<> 149:156823d33999 259 */
<> 149:156823d33999 260 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
<> 149:156823d33999 261 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
<> 149:156823d33999 262
<> 149:156823d33999 263 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
<> 149:156823d33999 264 ((CPSM) == SDIO_CPSM_ENABLE))
<> 149:156823d33999 265 /**
<> 149:156823d33999 266 * @}
<> 149:156823d33999 267 */
<> 149:156823d33999 268
<> 149:156823d33999 269 /** @defgroup SDIO_Response_Registers Response Register
<> 149:156823d33999 270 * @{
<> 149:156823d33999 271 */
<> 149:156823d33999 272 #define SDIO_RESP1 ((uint32_t)0x00000000)
<> 149:156823d33999 273 #define SDIO_RESP2 ((uint32_t)0x00000004)
<> 149:156823d33999 274 #define SDIO_RESP3 ((uint32_t)0x00000008)
<> 149:156823d33999 275 #define SDIO_RESP4 ((uint32_t)0x0000000C)
<> 149:156823d33999 276
<> 149:156823d33999 277 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
<> 149:156823d33999 278 ((RESP) == SDIO_RESP2) || \
<> 149:156823d33999 279 ((RESP) == SDIO_RESP3) || \
<> 149:156823d33999 280 ((RESP) == SDIO_RESP4))
<> 149:156823d33999 281 /**
<> 149:156823d33999 282 * @}
<> 149:156823d33999 283 */
<> 149:156823d33999 284
<> 149:156823d33999 285 /** @defgroup SDIO_Data_Length Data Lenght
<> 149:156823d33999 286 * @{
<> 149:156823d33999 287 */
<> 149:156823d33999 288 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
<> 149:156823d33999 289 /**
<> 149:156823d33999 290 * @}
<> 149:156823d33999 291 */
<> 149:156823d33999 292
<> 149:156823d33999 293 /** @defgroup SDIO_Data_Block_Size Data Block Size
<> 149:156823d33999 294 * @{
<> 149:156823d33999 295 */
<> 149:156823d33999 296 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
<> 149:156823d33999 297 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
<> 149:156823d33999 298 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
<> 149:156823d33999 299 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
<> 149:156823d33999 300 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
<> 149:156823d33999 301 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
<> 149:156823d33999 302 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
<> 149:156823d33999 303 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
<> 149:156823d33999 304 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
<> 149:156823d33999 305 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
<> 149:156823d33999 306 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
<> 149:156823d33999 307 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
<> 149:156823d33999 308 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
<> 149:156823d33999 309 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
<> 149:156823d33999 310 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
<> 149:156823d33999 311
<> 149:156823d33999 312 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
<> 149:156823d33999 313 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
<> 149:156823d33999 314 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
<> 149:156823d33999 315 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
<> 149:156823d33999 316 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
<> 149:156823d33999 317 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
<> 149:156823d33999 318 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
<> 149:156823d33999 319 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
<> 149:156823d33999 320 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
<> 149:156823d33999 321 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
<> 149:156823d33999 322 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
<> 149:156823d33999 323 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
<> 149:156823d33999 324 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
<> 149:156823d33999 325 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
<> 149:156823d33999 326 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
<> 149:156823d33999 327 /**
<> 149:156823d33999 328 * @}
<> 149:156823d33999 329 */
<> 149:156823d33999 330
<> 149:156823d33999 331 /** @defgroup SDIO_Transfer_Direction Transfer Direction
<> 149:156823d33999 332 * @{
<> 149:156823d33999 333 */
<> 149:156823d33999 334 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
<> 149:156823d33999 335 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
<> 149:156823d33999 336
<> 149:156823d33999 337 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
<> 149:156823d33999 338 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
<> 149:156823d33999 339 /**
<> 149:156823d33999 340 * @}
<> 149:156823d33999 341 */
<> 149:156823d33999 342
<> 149:156823d33999 343 /** @defgroup SDIO_Transfer_Type Transfer Type
<> 149:156823d33999 344 * @{
<> 149:156823d33999 345 */
<> 149:156823d33999 346 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
<> 149:156823d33999 347 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
<> 149:156823d33999 348
<> 149:156823d33999 349 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
<> 149:156823d33999 350 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
<> 149:156823d33999 351 /**
<> 149:156823d33999 352 * @}
<> 149:156823d33999 353 */
<> 149:156823d33999 354
<> 149:156823d33999 355 /** @defgroup SDIO_DPSM_State DPSM State
<> 149:156823d33999 356 * @{
<> 149:156823d33999 357 */
<> 149:156823d33999 358 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
<> 149:156823d33999 359 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
<> 149:156823d33999 360
<> 149:156823d33999 361 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
<> 149:156823d33999 362 ((DPSM) == SDIO_DPSM_ENABLE))
<> 149:156823d33999 363 /**
<> 149:156823d33999 364 * @}
<> 149:156823d33999 365 */
<> 149:156823d33999 366
<> 149:156823d33999 367 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
<> 149:156823d33999 368 * @{
<> 149:156823d33999 369 */
<> 149:156823d33999 370 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
<> 149:156823d33999 371 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
<> 149:156823d33999 372
<> 149:156823d33999 373 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
<> 149:156823d33999 374 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
<> 149:156823d33999 375 /**
<> 149:156823d33999 376 * @}
<> 149:156823d33999 377 */
<> 149:156823d33999 378
<> 149:156823d33999 379 /** @defgroup SDIO_Interrupt_sources Interrupt Sources
<> 149:156823d33999 380 * @{
<> 149:156823d33999 381 */
<> 149:156823d33999 382 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
<> 149:156823d33999 383 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
<> 149:156823d33999 384 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
<> 149:156823d33999 385 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
<> 149:156823d33999 386 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
<> 149:156823d33999 387 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
<> 149:156823d33999 388 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
<> 149:156823d33999 389 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
<> 149:156823d33999 390 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
<> 149:156823d33999 391 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
<> 149:156823d33999 392 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
<> 149:156823d33999 393 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
<> 149:156823d33999 394 #define SDIO_IT_TXACT SDIO_STA_TXACT
<> 149:156823d33999 395 #define SDIO_IT_RXACT SDIO_STA_RXACT
<> 149:156823d33999 396 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
<> 149:156823d33999 397 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
<> 149:156823d33999 398 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
<> 149:156823d33999 399 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
<> 149:156823d33999 400 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
<> 149:156823d33999 401 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
<> 149:156823d33999 402 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
<> 149:156823d33999 403 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
<> 149:156823d33999 404 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
<> 149:156823d33999 405 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
<> 149:156823d33999 406 /**
<> 149:156823d33999 407 * @}
<> 149:156823d33999 408 */
<> 149:156823d33999 409
<> 149:156823d33999 410 /** @defgroup SDIO_Flags Flags
<> 149:156823d33999 411 * @{
<> 149:156823d33999 412 */
<> 149:156823d33999 413 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
<> 149:156823d33999 414 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
<> 149:156823d33999 415 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
<> 149:156823d33999 416 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
<> 149:156823d33999 417 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
<> 149:156823d33999 418 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
<> 149:156823d33999 419 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
<> 149:156823d33999 420 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
<> 149:156823d33999 421 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
<> 149:156823d33999 422 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
<> 149:156823d33999 423 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
<> 149:156823d33999 424 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
<> 149:156823d33999 425 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
<> 149:156823d33999 426 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
<> 149:156823d33999 427 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
<> 149:156823d33999 428 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
<> 149:156823d33999 429 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
<> 149:156823d33999 430 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
<> 149:156823d33999 431 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
<> 149:156823d33999 432 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
<> 149:156823d33999 433 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
<> 149:156823d33999 434 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
<> 149:156823d33999 435 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
<> 149:156823d33999 436 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
<> 149:156823d33999 437 /**
<> 149:156823d33999 438 * @}
<> 149:156823d33999 439 */
<> 149:156823d33999 440
<> 149:156823d33999 441 /**
<> 149:156823d33999 442 * @}
<> 149:156823d33999 443 */
<> 149:156823d33999 444 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 445 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
<> 149:156823d33999 446 * @{
<> 149:156823d33999 447 */
<> 149:156823d33999 448
<> 149:156823d33999 449 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
<> 149:156823d33999 450 * @{
<> 149:156823d33999 451 */
<> 149:156823d33999 452 /* ------------ SDIO registers bit address in the alias region -------------- */
<> 149:156823d33999 453 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
<> 149:156823d33999 454
<> 149:156823d33999 455 /* --- CLKCR Register ---*/
<> 149:156823d33999 456 /* Alias word address of CLKEN bit */
<> 149:156823d33999 457 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
<> 149:156823d33999 458 #define CLKEN_BITNUMBER 0x08
<> 149:156823d33999 459 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
<> 149:156823d33999 460
<> 149:156823d33999 461 /* --- CMD Register ---*/
<> 149:156823d33999 462 /* Alias word address of SDIOSUSPEND bit */
<> 149:156823d33999 463 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
<> 149:156823d33999 464 #define SDIOSUSPEND_BITNUMBER 0x0B
<> 149:156823d33999 465 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
<> 149:156823d33999 466
<> 149:156823d33999 467 /* Alias word address of ENCMDCOMPL bit */
<> 149:156823d33999 468 #define ENCMDCOMPL_BITNUMBER 0x0C
<> 149:156823d33999 469 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
<> 149:156823d33999 470
<> 149:156823d33999 471 /* Alias word address of NIEN bit */
<> 149:156823d33999 472 #define NIEN_BITNUMBER 0x0D
<> 149:156823d33999 473 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
<> 149:156823d33999 474
<> 149:156823d33999 475 /* Alias word address of ATACMD bit */
<> 149:156823d33999 476 #define ATACMD_BITNUMBER 0x0E
<> 149:156823d33999 477 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
<> 149:156823d33999 478
<> 149:156823d33999 479 /* --- DCTRL Register ---*/
<> 149:156823d33999 480 /* Alias word address of DMAEN bit */
<> 149:156823d33999 481 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
<> 149:156823d33999 482 #define DMAEN_BITNUMBER 0x03
<> 149:156823d33999 483 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
<> 149:156823d33999 484
<> 149:156823d33999 485 /* Alias word address of RWSTART bit */
<> 149:156823d33999 486 #define RWSTART_BITNUMBER 0x08
<> 149:156823d33999 487 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
<> 149:156823d33999 488
<> 149:156823d33999 489 /* Alias word address of RWSTOP bit */
<> 149:156823d33999 490 #define RWSTOP_BITNUMBER 0x09
<> 149:156823d33999 491 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
<> 149:156823d33999 492
<> 149:156823d33999 493 /* Alias word address of RWMOD bit */
<> 149:156823d33999 494 #define RWMOD_BITNUMBER 0x0A
<> 149:156823d33999 495 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
<> 149:156823d33999 496
<> 149:156823d33999 497 /* Alias word address of SDIOEN bit */
<> 149:156823d33999 498 #define SDIOEN_BITNUMBER 0x0B
<> 149:156823d33999 499 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
<> 149:156823d33999 500 /**
<> 149:156823d33999 501 * @}
<> 149:156823d33999 502 */
<> 149:156823d33999 503
<> 149:156823d33999 504 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
<> 149:156823d33999 505 * @brief SDMMC_LL registers bit address in the alias region
<> 149:156823d33999 506 * @{
<> 149:156823d33999 507 */
<> 149:156823d33999 508
<> 149:156823d33999 509 /* ---------------------- SDIO registers bit mask --------------------------- */
<> 149:156823d33999 510 /* --- CLKCR Register ---*/
<> 149:156823d33999 511 /* CLKCR register clear mask */
<> 149:156823d33999 512 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
<> 149:156823d33999 513 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
<> 149:156823d33999 514 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
<> 149:156823d33999 515
<> 149:156823d33999 516 /* --- PWRCTRL Register ---*/
<> 149:156823d33999 517 /* --- DCTRL Register ---*/
<> 149:156823d33999 518 /* SDIO DCTRL Clear Mask */
<> 149:156823d33999 519 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
<> 149:156823d33999 520 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
<> 149:156823d33999 521
<> 149:156823d33999 522 /* --- CMD Register ---*/
<> 149:156823d33999 523 /* CMD Register clear mask */
<> 149:156823d33999 524 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
<> 149:156823d33999 525 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
<> 149:156823d33999 526 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
<> 149:156823d33999 527
<> 149:156823d33999 528 /* SDIO RESP Registers Address */
<> 149:156823d33999 529 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
<> 149:156823d33999 530
<> 149:156823d33999 531 /* SDIO Initialization Frequency (400KHz max) */
<> 149:156823d33999 532 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
<> 149:156823d33999 533
<> 149:156823d33999 534 /* SDIO Data Transfer Frequency */
<> 149:156823d33999 535 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
<> 149:156823d33999 536
<> 149:156823d33999 537 /**
<> 149:156823d33999 538 * @}
<> 149:156823d33999 539 */
<> 149:156823d33999 540
<> 149:156823d33999 541 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
<> 149:156823d33999 542 * @brief macros to handle interrupts and specific clock configurations
<> 149:156823d33999 543 * @{
<> 149:156823d33999 544 */
<> 149:156823d33999 545
<> 149:156823d33999 546 /**
<> 149:156823d33999 547 * @brief Enable the SDIO device.
<> 149:156823d33999 548 * @retval None
<> 149:156823d33999 549 */
<> 149:156823d33999 550 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
<> 149:156823d33999 551
<> 149:156823d33999 552 /**
<> 149:156823d33999 553 * @brief Disable the SDIO device.
<> 149:156823d33999 554 * @retval None
<> 149:156823d33999 555 */
<> 149:156823d33999 556 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
<> 149:156823d33999 557
<> 149:156823d33999 558 /**
<> 149:156823d33999 559 * @brief Enable the SDIO DMA transfer.
<> 149:156823d33999 560 * @retval None
<> 149:156823d33999 561 */
<> 149:156823d33999 562 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
<> 149:156823d33999 563
<> 149:156823d33999 564 /**
<> 149:156823d33999 565 * @brief Disable the SDIO DMA transfer.
<> 149:156823d33999 566 * @retval None
<> 149:156823d33999 567 */
<> 149:156823d33999 568 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
<> 149:156823d33999 569
<> 149:156823d33999 570 /**
<> 149:156823d33999 571 * @brief Enable the SDIO device interrupt.
<> 149:156823d33999 572 * @param __INSTANCE__ : Pointer to SDIO register base
<> 149:156823d33999 573 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
<> 149:156823d33999 574 * This parameter can be one or a combination of the following values:
<> 149:156823d33999 575 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 149:156823d33999 576 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 149:156823d33999 577 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 149:156823d33999 578 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 149:156823d33999 579 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 149:156823d33999 580 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 149:156823d33999 581 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 149:156823d33999 582 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 149:156823d33999 583 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 149:156823d33999 584 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 149:156823d33999 585 * bus mode interrupt
<> 149:156823d33999 586 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 149:156823d33999 587 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 149:156823d33999 588 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 149:156823d33999 589 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 149:156823d33999 590 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 149:156823d33999 591 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 149:156823d33999 592 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 149:156823d33999 593 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 149:156823d33999 594 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 149:156823d33999 595 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 149:156823d33999 596 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 149:156823d33999 597 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 149:156823d33999 598 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 149:156823d33999 599 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 149:156823d33999 600 * @retval None
<> 149:156823d33999 601 */
<> 149:156823d33999 602 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
<> 149:156823d33999 603
<> 149:156823d33999 604 /**
<> 149:156823d33999 605 * @brief Disable the SDIO device interrupt.
<> 149:156823d33999 606 * @param __INSTANCE__ : Pointer to SDIO register base
<> 149:156823d33999 607 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
<> 149:156823d33999 608 * This parameter can be one or a combination of the following values:
<> 149:156823d33999 609 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 149:156823d33999 610 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 149:156823d33999 611 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 149:156823d33999 612 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 149:156823d33999 613 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 149:156823d33999 614 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 149:156823d33999 615 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 149:156823d33999 616 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 149:156823d33999 617 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 149:156823d33999 618 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 149:156823d33999 619 * bus mode interrupt
<> 149:156823d33999 620 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 149:156823d33999 621 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 149:156823d33999 622 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 149:156823d33999 623 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 149:156823d33999 624 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 149:156823d33999 625 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 149:156823d33999 626 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 149:156823d33999 627 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 149:156823d33999 628 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 149:156823d33999 629 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 149:156823d33999 630 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 149:156823d33999 631 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 149:156823d33999 632 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 149:156823d33999 633 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 149:156823d33999 634 * @retval None
<> 149:156823d33999 635 */
<> 149:156823d33999 636 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
<> 149:156823d33999 637
<> 149:156823d33999 638 /**
<> 149:156823d33999 639 * @brief Checks whether the specified SDIO flag is set or not.
<> 149:156823d33999 640 * @param __INSTANCE__ : Pointer to SDIO register base
<> 149:156823d33999 641 * @param __FLAG__: specifies the flag to check.
<> 149:156823d33999 642 * This parameter can be one of the following values:
<> 149:156823d33999 643 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 149:156823d33999 644 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 149:156823d33999 645 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 149:156823d33999 646 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 149:156823d33999 647 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 149:156823d33999 648 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 149:156823d33999 649 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 149:156823d33999 650 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 149:156823d33999 651 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 149:156823d33999 652 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
<> 149:156823d33999 653 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 149:156823d33999 654 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
<> 149:156823d33999 655 * @arg SDIO_FLAG_TXACT: Data transmit in progress
<> 149:156823d33999 656 * @arg SDIO_FLAG_RXACT: Data receive in progress
<> 149:156823d33999 657 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<> 149:156823d33999 658 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
<> 149:156823d33999 659 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
<> 149:156823d33999 660 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
<> 149:156823d33999 661 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
<> 149:156823d33999 662 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
<> 149:156823d33999 663 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
<> 149:156823d33999 664 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
<> 149:156823d33999 665 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 149:156823d33999 666 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<> 149:156823d33999 667 * @retval The new state of SDIO_FLAG (SET or RESET).
<> 149:156823d33999 668 */
<> 149:156823d33999 669 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
<> 149:156823d33999 670
<> 149:156823d33999 671
<> 149:156823d33999 672 /**
<> 149:156823d33999 673 * @brief Clears the SDIO pending flags.
<> 149:156823d33999 674 * @param __INSTANCE__ : Pointer to SDIO register base
<> 149:156823d33999 675 * @param __FLAG__: specifies the flag to clear.
<> 149:156823d33999 676 * This parameter can be one or a combination of the following values:
<> 149:156823d33999 677 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 149:156823d33999 678 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 149:156823d33999 679 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 149:156823d33999 680 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 149:156823d33999 681 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 149:156823d33999 682 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 149:156823d33999 683 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 149:156823d33999 684 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 149:156823d33999 685 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 149:156823d33999 686 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
<> 149:156823d33999 687 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 149:156823d33999 688 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 149:156823d33999 689 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<> 149:156823d33999 690 * @retval None
<> 149:156823d33999 691 */
<> 149:156823d33999 692 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
<> 149:156823d33999 693
<> 149:156823d33999 694 /**
<> 149:156823d33999 695 * @brief Checks whether the specified SDIO interrupt has occurred or not.
<> 149:156823d33999 696 * @param __INSTANCE__ : Pointer to SDIO register base
<> 149:156823d33999 697 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
<> 149:156823d33999 698 * This parameter can be one of the following values:
<> 149:156823d33999 699 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 149:156823d33999 700 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 149:156823d33999 701 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 149:156823d33999 702 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 149:156823d33999 703 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 149:156823d33999 704 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 149:156823d33999 705 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 149:156823d33999 706 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 149:156823d33999 707 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 149:156823d33999 708 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 149:156823d33999 709 * bus mode interrupt
<> 149:156823d33999 710 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 149:156823d33999 711 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 149:156823d33999 712 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 149:156823d33999 713 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 149:156823d33999 714 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 149:156823d33999 715 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 149:156823d33999 716 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 149:156823d33999 717 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 149:156823d33999 718 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 149:156823d33999 719 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 149:156823d33999 720 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 149:156823d33999 721 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 149:156823d33999 722 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 149:156823d33999 723 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 149:156823d33999 724 * @retval The new state of SDIO_IT (SET or RESET).
<> 149:156823d33999 725 */
<> 149:156823d33999 726 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
<> 149:156823d33999 727
<> 149:156823d33999 728 /**
<> 149:156823d33999 729 * @brief Clears the SDIO's interrupt pending bits.
<> 149:156823d33999 730 * @param __INSTANCE__ : Pointer to SDIO register base
<> 149:156823d33999 731 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 149:156823d33999 732 * This parameter can be one or a combination of the following values:
<> 149:156823d33999 733 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 149:156823d33999 734 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 149:156823d33999 735 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 149:156823d33999 736 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 149:156823d33999 737 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 149:156823d33999 738 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 149:156823d33999 739 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 149:156823d33999 740 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 149:156823d33999 741 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
<> 149:156823d33999 742 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 149:156823d33999 743 * bus mode interrupt
<> 149:156823d33999 744 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 149:156823d33999 745 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
<> 149:156823d33999 746 * @retval None
<> 149:156823d33999 747 */
<> 149:156823d33999 748 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
<> 149:156823d33999 749
<> 149:156823d33999 750 /**
<> 149:156823d33999 751 * @brief Enable Start the SD I/O Read Wait operation.
<> 149:156823d33999 752 * @retval None
<> 149:156823d33999 753 */
<> 149:156823d33999 754 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
<> 149:156823d33999 755
<> 149:156823d33999 756 /**
<> 149:156823d33999 757 * @brief Disable Start the SD I/O Read Wait operations.
<> 149:156823d33999 758 * @retval None
<> 149:156823d33999 759 */
<> 149:156823d33999 760 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
<> 149:156823d33999 761
<> 149:156823d33999 762 /**
<> 149:156823d33999 763 * @brief Enable Start the SD I/O Read Wait operation.
<> 149:156823d33999 764 * @retval None
<> 149:156823d33999 765 */
<> 149:156823d33999 766 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
<> 149:156823d33999 767
<> 149:156823d33999 768 /**
<> 149:156823d33999 769 * @brief Disable Stop the SD I/O Read Wait operations.
<> 149:156823d33999 770 * @retval None
<> 149:156823d33999 771 */
<> 149:156823d33999 772 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
<> 149:156823d33999 773
<> 149:156823d33999 774 /**
<> 149:156823d33999 775 * @brief Enable the SD I/O Mode Operation.
<> 149:156823d33999 776 * @retval None
<> 149:156823d33999 777 */
<> 149:156823d33999 778 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
<> 149:156823d33999 779
<> 149:156823d33999 780 /**
<> 149:156823d33999 781 * @brief Disable the SD I/O Mode Operation.
<> 149:156823d33999 782 * @retval None
<> 149:156823d33999 783 */
<> 149:156823d33999 784 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
<> 149:156823d33999 785
<> 149:156823d33999 786 /**
<> 149:156823d33999 787 * @brief Enable the SD I/O Suspend command sending.
<> 149:156823d33999 788 * @retval None
<> 149:156823d33999 789 */
<> 149:156823d33999 790 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
<> 149:156823d33999 791
<> 149:156823d33999 792 /**
<> 149:156823d33999 793 * @brief Disable the SD I/O Suspend command sending.
<> 149:156823d33999 794 * @retval None
<> 149:156823d33999 795 */
<> 149:156823d33999 796 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
<> 149:156823d33999 797
<> 149:156823d33999 798 /**
<> 149:156823d33999 799 * @brief Enable the command completion signal.
<> 149:156823d33999 800 * @retval None
<> 149:156823d33999 801 */
<> 149:156823d33999 802 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
<> 149:156823d33999 803
<> 149:156823d33999 804 /**
<> 149:156823d33999 805 * @brief Disable the command completion signal.
<> 149:156823d33999 806 * @retval None
<> 149:156823d33999 807 */
<> 149:156823d33999 808 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
<> 149:156823d33999 809
<> 149:156823d33999 810 /**
<> 149:156823d33999 811 * @brief Enable the CE-ATA interrupt.
<> 149:156823d33999 812 * @retval None
<> 149:156823d33999 813 */
<> 149:156823d33999 814 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
<> 149:156823d33999 815
<> 149:156823d33999 816 /**
<> 149:156823d33999 817 * @brief Disable the CE-ATA interrupt.
<> 149:156823d33999 818 * @retval None
<> 149:156823d33999 819 */
<> 149:156823d33999 820 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
<> 149:156823d33999 821
<> 149:156823d33999 822 /**
<> 149:156823d33999 823 * @brief Enable send CE-ATA command (CMD61).
<> 149:156823d33999 824 * @retval None
<> 149:156823d33999 825 */
<> 149:156823d33999 826 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
<> 149:156823d33999 827
<> 149:156823d33999 828 /**
<> 149:156823d33999 829 * @brief Disable send CE-ATA command (CMD61).
<> 149:156823d33999 830 * @retval None
<> 149:156823d33999 831 */
<> 149:156823d33999 832 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
<> 149:156823d33999 833
<> 149:156823d33999 834 /**
<> 149:156823d33999 835 * @}
<> 149:156823d33999 836 */
<> 149:156823d33999 837
<> 149:156823d33999 838 /**
<> 149:156823d33999 839 * @}
<> 149:156823d33999 840 */
<> 149:156823d33999 841
<> 149:156823d33999 842 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 843 /** @addtogroup SDMMC_LL_Exported_Functions
<> 149:156823d33999 844 * @{
<> 149:156823d33999 845 */
<> 149:156823d33999 846
<> 149:156823d33999 847 /* Initialization/de-initialization functions **********************************/
<> 149:156823d33999 848 /** @addtogroup HAL_SDMMC_LL_Group1
<> 149:156823d33999 849 * @{
<> 149:156823d33999 850 */
<> 149:156823d33999 851 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
<> 149:156823d33999 852 /**
<> 149:156823d33999 853 * @}
<> 149:156823d33999 854 */
<> 149:156823d33999 855
<> 149:156823d33999 856 /* I/O operation functions *****************************************************/
<> 149:156823d33999 857 /** @addtogroup HAL_SDMMC_LL_Group2
<> 149:156823d33999 858 * @{
<> 149:156823d33999 859 */
<> 149:156823d33999 860 /* Blocking mode: Polling */
<> 149:156823d33999 861 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
<> 149:156823d33999 862 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
<> 149:156823d33999 863 /**
<> 149:156823d33999 864 * @}
<> 149:156823d33999 865 */
<> 149:156823d33999 866
<> 149:156823d33999 867 /* Peripheral Control functions ************************************************/
<> 149:156823d33999 868 /** @addtogroup HAL_SDMMC_LL_Group3
<> 149:156823d33999 869 * @{
<> 149:156823d33999 870 */
<> 149:156823d33999 871 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
<> 149:156823d33999 872 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
<> 149:156823d33999 873 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
<> 149:156823d33999 874
<> 149:156823d33999 875 /* Command path state machine (CPSM) management functions */
<> 149:156823d33999 876 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
<> 149:156823d33999 877 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
<> 149:156823d33999 878 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
<> 149:156823d33999 879
<> 149:156823d33999 880 /* Data path state machine (DPSM) management functions */
<> 149:156823d33999 881 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
<> 149:156823d33999 882 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
<> 149:156823d33999 883 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
<> 149:156823d33999 884
<> 149:156823d33999 885 /* SDIO IO Cards mode management functions */
<> 149:156823d33999 886 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
<> 149:156823d33999 887
<> 149:156823d33999 888 /**
<> 149:156823d33999 889 * @}
<> 149:156823d33999 890 */
<> 149:156823d33999 891
<> 149:156823d33999 892 /**
<> 149:156823d33999 893 * @}
<> 149:156823d33999 894 */
<> 149:156823d33999 895
<> 149:156823d33999 896 /**
<> 149:156823d33999 897 * @}
<> 149:156823d33999 898 */
<> 149:156823d33999 899
<> 149:156823d33999 900 /**
<> 149:156823d33999 901 * @}
<> 149:156823d33999 902 */
<> 149:156823d33999 903
<> 149:156823d33999 904 #ifdef __cplusplus
<> 149:156823d33999 905 }
<> 149:156823d33999 906 #endif
<> 149:156823d33999 907
<> 149:156823d33999 908 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
<> 149:156823d33999 909
<> 149:156823d33999 910 #endif /* __STM32L1xx_LL_SD_H */
<> 149:156823d33999 911
<> 149:156823d33999 912 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/