mbed library sources. Supersedes mbed-src.
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targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | ****************************************************************************** |
<> | 149:156823d33999 | 3 | * @file uart_16c550_map.h |
<> | 149:156823d33999 | 4 | * @brief UART module hardware register map. |
<> | 149:156823d33999 | 5 | * @internal |
<> | 149:156823d33999 | 6 | * @author ON Semiconductor. |
<> | 149:156823d33999 | 7 | * $Rev: 2615 $ |
<> | 149:156823d33999 | 8 | * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $ |
<> | 149:156823d33999 | 9 | ****************************************************************************** |
<> | 149:156823d33999 | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a ON Semiconductor). |
<> | 149:156823d33999 | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
<> | 149:156823d33999 | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
<> | 149:156823d33999 | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
<> | 149:156823d33999 | 14 | * (ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software) and |
<> | 149:156823d33999 | 15 | * if applicable the software license agreement. Do not use this software and/or |
<> | 149:156823d33999 | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
<> | 149:156823d33999 | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
<> | 149:156823d33999 | 18 | * terms and conditions. |
<> | 149:156823d33999 | 19 | * |
<> | 149:156823d33999 | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
<> | 149:156823d33999 | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
<> | 149:156823d33999 | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
<> | 149:156823d33999 | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
<> | 149:156823d33999 | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
<> | 149:156823d33999 | 25 | * @endinternal |
<> | 149:156823d33999 | 26 | * |
<> | 149:156823d33999 | 27 | * @ingroup uart_16c550 |
<> | 149:156823d33999 | 28 | * |
<> | 149:156823d33999 | 29 | * @details |
<> | 149:156823d33999 | 30 | * <h1> Reference document(s) </h1> |
<> | 149:156823d33999 | 31 | * <p> |
<> | 149:156823d33999 | 32 | * <a href="../pdf/IPC7202_UART_APB_DS_v1P4.pdf" target="_blank"> |
<> | 149:156823d33999 | 33 | * IPC7202 APB UART Design Specification v1.4 </a> |
<> | 149:156823d33999 | 34 | * </p> |
<> | 149:156823d33999 | 35 | */ |
<> | 149:156823d33999 | 36 | |
<> | 149:156823d33999 | 37 | #ifndef UART_16C550_MAP_H_ |
<> | 149:156823d33999 | 38 | #define UART_16C550_MAP_H_ |
<> | 149:156823d33999 | 39 | |
<> | 149:156823d33999 | 40 | #include "architecture.h" |
<> | 149:156823d33999 | 41 | |
<> | 149:156823d33999 | 42 | #if defined ( __CC_ARM ) |
<> | 149:156823d33999 | 43 | #pragma anon_unions |
<> | 149:156823d33999 | 44 | #endif |
<> | 149:156823d33999 | 45 | |
<> | 149:156823d33999 | 46 | #define DCTS (uint8_t)0x01 |
<> | 149:156823d33999 | 47 | #define DDSR (uint8_t)0x02 |
<> | 149:156823d33999 | 48 | #define TERI (uint8_t)0x04 |
<> | 149:156823d33999 | 49 | #define DDCD (uint8_t)0x08 |
<> | 149:156823d33999 | 50 | //#define CTS (uint8_t)0x10 |
<> | 149:156823d33999 | 51 | #define DSR (uint8_t)0x20 |
<> | 149:156823d33999 | 52 | #define RI (uint8_t)0x40 |
<> | 149:156823d33999 | 53 | #define DCD (uint8_t)0x80 |
<> | 149:156823d33999 | 54 | #define IER_PWRDNENACTIVE ((uint8_t)(1<<5)) |
<> | 149:156823d33999 | 55 | #define IER_MSI ((uint8_t)(1<<3)) |
<> | 149:156823d33999 | 56 | #define IER_RLSI ((uint8_t)(1<<2)) |
<> | 149:156823d33999 | 57 | #define IER_THRI ((uint8_t)(1<<1)) |
<> | 149:156823d33999 | 58 | #define IER_RDAI ((uint8_t)(1<<0)) |
<> | 149:156823d33999 | 59 | #define FCR_RXFIFOTRIGGERLEVEL_1 ((uint8_t)(0x00)) |
<> | 149:156823d33999 | 60 | #define FCR_RXFIFOTRIGGERLEVEL_4 ((uint8_t)(0x40)) |
<> | 149:156823d33999 | 61 | #define FCR_RXFIFOTRIGGERLEVEL_8 ((uint8_t)(0x80)) |
<> | 149:156823d33999 | 62 | #define FCR_RXFIFOTRIGGERLEVEL_14 ((uint8_t)(0xC0)) |
<> | 149:156823d33999 | 63 | #define FCR_DMA_MODE_0 ((uint8_t)(0<<3)) |
<> | 149:156823d33999 | 64 | #define FCR_DMA_MODE_1 ((uint8_t)(1<<3)) |
<> | 149:156823d33999 | 65 | #define FCR_TXFIFO_RESET ((uint8_t)(1<<2)) |
<> | 149:156823d33999 | 66 | #define FCR_RXFIFO_RESET ((uint8_t)(1<<1)) |
<> | 149:156823d33999 | 67 | #define FCR_FIFO_ENABLE ((uint8_t)(1<<0)) |
<> | 149:156823d33999 | 68 | |
<> | 149:156823d33999 | 69 | /** UART HW Structure Overlay */ |
<> | 149:156823d33999 | 70 | typedef struct { |
<> | 149:156823d33999 | 71 | /** Base address + 0x0: Receive, transmit and divisor_LSB offset */ |
<> | 149:156823d33999 | 72 | union { |
<> | 149:156823d33999 | 73 | __I uint32_t RBR; /**< Received data (8 bits wide) / read only */ |
<> | 149:156823d33999 | 74 | __O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */ |
<> | 149:156823d33999 | 75 | __IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */ |
<> | 149:156823d33999 | 76 | }; |
<> | 149:156823d33999 | 77 | /** Base address + 0x4: Interrupt enable and divisor_MSB offset */ |
<> | 149:156823d33999 | 78 | union { |
<> | 149:156823d33999 | 79 | union { |
<> | 149:156823d33999 | 80 | struct { |
<> | 149:156823d33999 | 81 | __IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */ |
<> | 149:156823d33999 | 82 | __IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */ |
<> | 149:156823d33999 | 83 | __IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */ |
<> | 149:156823d33999 | 84 | __IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */ |
<> | 149:156823d33999 | 85 | __IO uint32_t PAD0 :1; |
<> | 149:156823d33999 | 86 | __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */ |
<> | 149:156823d33999 | 87 | __IO uint32_t PAD1 :2; |
<> | 149:156823d33999 | 88 | } BITS; |
<> | 149:156823d33999 | 89 | __IO uint32_t WORD; |
<> | 149:156823d33999 | 90 | } IER; /** Interrupt enable offset 0x04 */ |
<> | 149:156823d33999 | 91 | __IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */ |
<> | 149:156823d33999 | 92 | }; |
<> | 149:156823d33999 | 93 | /** Base address + 0x8: Interrupt status and fifo control offset*/ |
<> | 149:156823d33999 | 94 | union { |
<> | 149:156823d33999 | 95 | union { |
<> | 149:156823d33999 | 96 | struct { |
<> | 149:156823d33999 | 97 | __I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */ |
<> | 149:156823d33999 | 98 | __I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/ |
<> | 149:156823d33999 | 99 | __I uint32_t PAD0 :2; |
<> | 149:156823d33999 | 100 | __I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */ |
<> | 149:156823d33999 | 101 | } BITS; |
<> | 149:156823d33999 | 102 | __I uint32_t WORD; |
<> | 149:156823d33999 | 103 | } IIR; /** Interrupt status and fifo status offset 0x08 */ |
<> | 149:156823d33999 | 104 | union { |
<> | 149:156823d33999 | 105 | struct { |
<> | 149:156823d33999 | 106 | __O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */ |
<> | 149:156823d33999 | 107 | __O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */ |
<> | 149:156823d33999 | 108 | __O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */ |
<> | 149:156823d33999 | 109 | __O uint32_t DMA_SEL :1; /**< DMA mode select */ |
<> | 149:156823d33999 | 110 | __O uint32_t PAD0 :2; |
<> | 149:156823d33999 | 111 | __O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */ |
<> | 149:156823d33999 | 112 | } BITS; |
<> | 149:156823d33999 | 113 | __O uint32_t WORD; |
<> | 149:156823d33999 | 114 | } FCR; /** Fifo control offset 0x08 */ |
<> | 149:156823d33999 | 115 | }; |
<> | 149:156823d33999 | 116 | /** Base address + 0xC: Line control offset */ |
<> | 149:156823d33999 | 117 | union { |
<> | 149:156823d33999 | 118 | struct { |
<> | 149:156823d33999 | 119 | __IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */ |
<> | 149:156823d33999 | 120 | __IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */ |
<> | 149:156823d33999 | 121 | __IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */ |
<> | 149:156823d33999 | 122 | __IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */ |
<> | 149:156823d33999 | 123 | __IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */ |
<> | 149:156823d33999 | 124 | } BITS; |
<> | 149:156823d33999 | 125 | __IO uint32_t WORD; |
<> | 149:156823d33999 | 126 | } LCR; /** Line control offset 0x0C */ |
<> | 149:156823d33999 | 127 | /** Base address + 0x10: Modem control offset */ |
<> | 149:156823d33999 | 128 | union { |
<> | 149:156823d33999 | 129 | struct { |
<> | 149:156823d33999 | 130 | __IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */ |
<> | 149:156823d33999 | 131 | __IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */ |
<> | 149:156823d33999 | 132 | __IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */ |
<> | 149:156823d33999 | 133 | __IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */ |
<> | 149:156823d33999 | 134 | __IO uint32_t PAD0 :3; |
<> | 149:156823d33999 | 135 | __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */ |
<> | 149:156823d33999 | 136 | } BITS; |
<> | 149:156823d33999 | 137 | __IO uint32_t WORD; |
<> | 149:156823d33999 | 138 | } MCR; /**< Modem control offset 0x10 */ |
<> | 149:156823d33999 | 139 | /** Base address + 0x14: Line status offset */ |
<> | 149:156823d33999 | 140 | union { |
<> | 149:156823d33999 | 141 | struct { |
<> | 149:156823d33999 | 142 | __O uint32_t READY :1; /**< Rx data available */ |
<> | 149:156823d33999 | 143 | __O uint32_t OVERRUN_ERR :1; /**< Overrun error */ |
<> | 149:156823d33999 | 144 | __O uint32_t PARITY_ERR :1; /**< Parity error */ |
<> | 149:156823d33999 | 145 | __O uint32_t FRAME_ERR :1; /**< Framing error */ |
<> | 149:156823d33999 | 146 | __O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */ |
<> | 149:156823d33999 | 147 | __O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */ |
<> | 149:156823d33999 | 148 | __O uint32_t TX_EMPTY :1; /**< Transmitter empty */ |
<> | 149:156823d33999 | 149 | __O uint32_t FIFO_ERR :1; /**< Receive fifo error */ |
<> | 149:156823d33999 | 150 | } BITS; |
<> | 149:156823d33999 | 151 | __O uint32_t WORD; |
<> | 149:156823d33999 | 152 | } LSR; /**< Line status offset 0x14 */ |
<> | 149:156823d33999 | 153 | /** Base address + 0x18: Modem status offset */ |
<> | 149:156823d33999 | 154 | union { |
<> | 149:156823d33999 | 155 | struct { |
<> | 149:156823d33999 | 156 | __O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */ |
<> | 149:156823d33999 | 157 | __O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */ |
<> | 149:156823d33999 | 158 | __O uint32_t CHG_RIN :1; /**< RI change since last MSR read */ |
<> | 149:156823d33999 | 159 | __O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */ |
<> | 149:156823d33999 | 160 | __O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */ |
<> | 149:156823d33999 | 161 | __O uint32_t CURR_DSRN :1; /**< DSR current state */ |
<> | 149:156823d33999 | 162 | __O uint32_t CURR_RIN :1; /**< RI current state */ |
<> | 149:156823d33999 | 163 | __O uint32_t CURR_DCDN :1; /**< DCD current state */ |
<> | 149:156823d33999 | 164 | } BITS; |
<> | 149:156823d33999 | 165 | __O uint32_t WORD; |
<> | 149:156823d33999 | 166 | } MSR; /**< Modem status offset 0x18 */ |
<> | 149:156823d33999 | 167 | /** Base address + 0x1C: Scratch offset*/ |
<> | 149:156823d33999 | 168 | __IO uint32_t SCR; /**< Scratch pad register */ |
<> | 149:156823d33999 | 169 | } Uart16C550Reg_t, *Uart16C550Reg_pt; |
<> | 149:156823d33999 | 170 | |
<> | 149:156823d33999 | 171 | #endif /* UART_16C550_MAP_H_ */ |