Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 ;/* File: startup_ncs36510.s
<> 149:156823d33999 2 ; * Purpose: startup file for Cortex-M3 devices. Should use with
<> 149:156823d33999 3 ; * ARMGCC for ARM Embedded Processors
<> 149:156823d33999 4 ; * Version: V2.00
<> 149:156823d33999 5 ; * Date: 25 Feb 2016
<> 149:156823d33999 6 ; *
<> 149:156823d33999 7 ; */
<> 149:156823d33999 8 ;/* Copyright (c) 2011 - 2014 ARM LIMITED
<> 149:156823d33999 9 ;
<> 149:156823d33999 10 ; All rights reserved.
<> 149:156823d33999 11 ; Redistribution and use in source and binary forms, with or without
<> 149:156823d33999 12 ; modification, are permitted provided that the following conditions are met:
<> 149:156823d33999 13 ; - Redistributions of source code must retain the above copyright
<> 149:156823d33999 14 ; notice, this list of conditions and the following disclaimer.
<> 149:156823d33999 15 ; - Redistributions in binary form must reproduce the above copyright
<> 149:156823d33999 16 ; notice, this list of conditions and the following disclaimer in the
<> 149:156823d33999 17 ; documentation and/or other materials provided with the distribution.
<> 149:156823d33999 18 ; - Neither the name of ARM nor the names of its contributors may be used
<> 149:156823d33999 19 ; to endorse or promote products derived from this software without
<> 149:156823d33999 20 ; specific prior written permission.
<> 149:156823d33999 21 ; *
<> 149:156823d33999 22 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 149:156823d33999 25 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 149:156823d33999 26 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 149:156823d33999 27 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 149:156823d33999 28 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 149:156823d33999 29 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 149:156823d33999 30 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 149:156823d33999 31 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 149:156823d33999 32 ; POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 33 ; ---------------------------------------------------------------------------*/
<> 149:156823d33999 34
<> 149:156823d33999 35
<> 149:156823d33999 36 PRESERVE8
<> 149:156823d33999 37 THUMB
<> 149:156823d33999 38
<> 149:156823d33999 39
<> 149:156823d33999 40 ; Vector Table Mapped to Address 0x3000 at Reset
<> 149:156823d33999 41
<> 149:156823d33999 42 AREA RESET, DATA, READONLY
<> 149:156823d33999 43 EXPORT __Vectors
<> 149:156823d33999 44 EXPORT __Vectors_End
<> 149:156823d33999 45 EXPORT __Vectors_Size
<> 149:156823d33999 46 IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
<> 149:156823d33999 47
<> 149:156823d33999 48 __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
<> 149:156823d33999 49 DCD Reset_Handler ; Reset Handler
<> 149:156823d33999 50 DCD NMI_Handler ; NMI Handler
<> 149:156823d33999 51 DCD HardFault_Handler ; Hard Fault Handler
<> 149:156823d33999 52 DCD MemManage_Handler ; MPU Fault Handler
<> 149:156823d33999 53 DCD BusFault_Handler ; Bus Fault Handler
<> 149:156823d33999 54 DCD UsageFault_Handler ; Usage Fault Handler
<> 149:156823d33999 55 DCD 0 ; Reserved
<> 149:156823d33999 56 DCD 0 ; Reserved
<> 149:156823d33999 57 DCD 0 ; Reserved
<> 149:156823d33999 58 DCD 0 ; Reserved
<> 149:156823d33999 59 DCD SVC_Handler ; SVCall Handler
<> 149:156823d33999 60 DCD DebugMon_Handler ; Debug Monitor Handler
<> 149:156823d33999 61 DCD 0 ; Reserved
<> 149:156823d33999 62 DCD PendSV_Handler ; PendSV Handler
<> 149:156823d33999 63 DCD SysTick_Handler ; SysTick Handler
<> 149:156823d33999 64
<> 149:156823d33999 65 ; External Interrupts
<> 149:156823d33999 66 DCD fIrqTim0Handler
<> 149:156823d33999 67 DCD fIrqTim1Handler
<> 149:156823d33999 68 DCD fIrqTim2Handler
<> 149:156823d33999 69 DCD fIrqUart1Handler
<> 149:156823d33999 70 DCD fIrqSpiHandler
<> 149:156823d33999 71 DCD fIrqI2CHandler
<> 149:156823d33999 72 DCD fIrqGpioHandler
<> 149:156823d33999 73 DCD fIrqRtcHandler
<> 149:156823d33999 74 DCD fIrqFlashHandler
<> 149:156823d33999 75 DCD fIrqMacHwHandler
<> 149:156823d33999 76 DCD fIrqAesHandler
<> 149:156823d33999 77 DCD fIrqAdcHandler
<> 149:156823d33999 78 DCD fIrqClockCalHandler
<> 149:156823d33999 79 DCD fIrqUart2Handler
<> 149:156823d33999 80 DCD fIrqUviHandler
<> 149:156823d33999 81 DCD fIrqDmaHandler
<> 149:156823d33999 82 DCD fIrqDbgPwrUpHandler
<> 149:156823d33999 83 DCD fIrqSpi2Handler
<> 149:156823d33999 84 DCD fIrqI2C2Handler
<> 149:156823d33999 85 DCD fIrqFVDDHCompHandler
<> 149:156823d33999 86 __Vectors_End
<> 149:156823d33999 87
<> 149:156823d33999 88 __Vectors_Size EQU __Vectors_End - __Vectors
<> 149:156823d33999 89
<> 149:156823d33999 90 AREA |.text|, CODE, READONLY
<> 149:156823d33999 91
<> 149:156823d33999 92 ; Reset Handler
<> 149:156823d33999 93
<> 149:156823d33999 94 Reset_Handler PROC
<> 149:156823d33999 95 EXPORT Reset_Handler [WEAK]
<> 149:156823d33999 96 IMPORT SystemInit
<> 149:156823d33999 97 IMPORT __main
<> 149:156823d33999 98 LDR R0, =SystemInit
<> 149:156823d33999 99 BLX R0
<> 149:156823d33999 100 LDR R0, =__main
<> 149:156823d33999 101 BX R0
<> 149:156823d33999 102 ENDP
<> 149:156823d33999 103
<> 149:156823d33999 104
<> 149:156823d33999 105 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 149:156823d33999 106
<> 149:156823d33999 107 NMI_Handler PROC
<> 149:156823d33999 108 EXPORT NMI_Handler [WEAK]
<> 149:156823d33999 109 B .
<> 149:156823d33999 110 ENDP
<> 149:156823d33999 111 HardFault_Handler\
<> 149:156823d33999 112 PROC
<> 149:156823d33999 113 EXPORT HardFault_Handler [WEAK]
<> 149:156823d33999 114 B .
<> 149:156823d33999 115 ENDP
<> 149:156823d33999 116 MemManage_Handler\
<> 149:156823d33999 117 PROC
<> 149:156823d33999 118 EXPORT MemManage_Handler [WEAK]
<> 149:156823d33999 119 B .
<> 149:156823d33999 120 ENDP
<> 149:156823d33999 121 BusFault_Handler\
<> 149:156823d33999 122 PROC
<> 149:156823d33999 123 EXPORT BusFault_Handler [WEAK]
<> 149:156823d33999 124 B .
<> 149:156823d33999 125 ENDP
<> 149:156823d33999 126 UsageFault_Handler\
<> 149:156823d33999 127 PROC
<> 149:156823d33999 128 EXPORT UsageFault_Handler [WEAK]
<> 149:156823d33999 129 B .
<> 149:156823d33999 130 ENDP
<> 149:156823d33999 131 SVC_Handler PROC
<> 149:156823d33999 132 EXPORT SVC_Handler [WEAK]
<> 149:156823d33999 133 B .
<> 149:156823d33999 134 ENDP
<> 149:156823d33999 135 DebugMon_Handler\
<> 149:156823d33999 136 PROC
<> 149:156823d33999 137 EXPORT DebugMon_Handler [WEAK]
<> 149:156823d33999 138 B .
<> 149:156823d33999 139 ENDP
<> 149:156823d33999 140 PendSV_Handler PROC
<> 149:156823d33999 141 EXPORT PendSV_Handler [WEAK]
<> 149:156823d33999 142 B .
<> 149:156823d33999 143 ENDP
<> 149:156823d33999 144 SysTick_Handler PROC
<> 149:156823d33999 145 EXPORT SysTick_Handler [WEAK]
<> 149:156823d33999 146 B .
<> 149:156823d33999 147 ENDP
<> 149:156823d33999 148
<> 149:156823d33999 149 Default_Handler PROC
<> 149:156823d33999 150 EXPORT fIrqTim0Handler [WEAK]
<> 149:156823d33999 151 EXPORT fIrqTim1Handler [WEAK]
<> 149:156823d33999 152 EXPORT fIrqTim2Handler [WEAK]
<> 149:156823d33999 153 EXPORT fIrqUart1Handler [WEAK]
<> 149:156823d33999 154 EXPORT fIrqSpiHandler [WEAK]
<> 149:156823d33999 155 EXPORT fIrqI2CHandler [WEAK]
<> 149:156823d33999 156 EXPORT fIrqGpioHandler [WEAK]
<> 149:156823d33999 157 EXPORT fIrqRtcHandler [WEAK]
<> 149:156823d33999 158 EXPORT fIrqFlashHandler [WEAK]
<> 149:156823d33999 159 EXPORT fIrqMacHwHandler [WEAK]
<> 149:156823d33999 160 EXPORT fIrqAesHandler [WEAK]
<> 149:156823d33999 161 EXPORT fIrqAdcHandler [WEAK]
<> 149:156823d33999 162 EXPORT fIrqClockCalHandler [WEAK]
<> 149:156823d33999 163 EXPORT fIrqUart2Handler [WEAK]
<> 149:156823d33999 164 EXPORT fIrqUviHandler [WEAK]
<> 149:156823d33999 165 EXPORT fIrqDmaHandler [WEAK]
<> 149:156823d33999 166 EXPORT fIrqDbgPwrUpHandler [WEAK]
<> 149:156823d33999 167 EXPORT fIrqSpi2Handler [WEAK]
<> 149:156823d33999 168 EXPORT fIrqI2C2Handler [WEAK]
<> 149:156823d33999 169 EXPORT fIrqFVDDHCompHandler [WEAK]
<> 149:156823d33999 170
<> 149:156823d33999 171 fIrqTim0Handler
<> 149:156823d33999 172 fIrqTim1Handler
<> 149:156823d33999 173 fIrqTim2Handler
<> 149:156823d33999 174 fIrqUart1Handler
<> 149:156823d33999 175 fIrqSpiHandler
<> 149:156823d33999 176 fIrqI2CHandler
<> 149:156823d33999 177 fIrqGpioHandler
<> 149:156823d33999 178 fIrqRtcHandler
<> 149:156823d33999 179 fIrqFlashHandler
<> 149:156823d33999 180 fIrqMacHwHandler
<> 149:156823d33999 181 fIrqAesHandler
<> 149:156823d33999 182 fIrqAdcHandler
<> 149:156823d33999 183 fIrqClockCalHandler
<> 149:156823d33999 184 fIrqUart2Handler
<> 149:156823d33999 185 fIrqUviHandler
<> 149:156823d33999 186 fIrqDmaHandler
<> 149:156823d33999 187 fIrqDbgPwrUpHandler
<> 149:156823d33999 188 fIrqSpi2Handler
<> 149:156823d33999 189 fIrqI2C2Handler
<> 149:156823d33999 190 fIrqFVDDHCompHandler
<> 149:156823d33999 191 DefaultISR
<> 149:156823d33999 192
<> 149:156823d33999 193 B .
<> 149:156823d33999 194
<> 149:156823d33999 195 ENDP
<> 149:156823d33999 196
<> 149:156823d33999 197 EXPORT __user_initial_stackheap
<> 149:156823d33999 198 IMPORT |Image$$ARM_LIB_HEAP$$Base|
<> 149:156823d33999 199 IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit|
<> 149:156823d33999 200
<> 149:156823d33999 201 __user_initial_stackheap PROC
<> 149:156823d33999 202 LDR R0, = |Image$$ARM_LIB_HEAP$$Base|
<> 149:156823d33999 203 LDR R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit|
<> 149:156823d33999 204 BX LR
<> 149:156823d33999 205 ENDP
<> 149:156823d33999 206
<> 149:156823d33999 207 ALIGN
<> 149:156823d33999 208 END