mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/TARGET_NXP/TARGET_LPC408X/gpio_irq_api.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_irq_api.c@144:ef7eb2e8f9f7
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 17 | #include "gpio_irq_api.h" |
<> | 144:ef7eb2e8f9f7 | 18 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 19 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | #define CHANNEL_NUM 64 |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
<> | 144:ef7eb2e8f9f7 | 24 | static gpio_irq_handler irq_handler; |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | static void handle_interrupt_in(void) { |
<> | 144:ef7eb2e8f9f7 | 27 | // Read in all current interrupt registers. We do this once as the |
<> | 144:ef7eb2e8f9f7 | 28 | // GPIO interrupt registers are on the APB bus, and this is slow. |
<> | 144:ef7eb2e8f9f7 | 29 | uint32_t rise0 = LPC_GPIOINT->IO0IntStatR; |
<> | 144:ef7eb2e8f9f7 | 30 | uint32_t fall0 = LPC_GPIOINT->IO0IntStatF; |
<> | 144:ef7eb2e8f9f7 | 31 | uint32_t rise2 = LPC_GPIOINT->IO2IntStatR; |
<> | 144:ef7eb2e8f9f7 | 32 | uint32_t fall2 = LPC_GPIOINT->IO2IntStatF; |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | uint8_t bitloc; |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | // Continue as long as there are interrupts pending |
<> | 144:ef7eb2e8f9f7 | 37 | while(rise0 > 0) { |
<> | 144:ef7eb2e8f9f7 | 38 | // CLZ returns number of leading zeros, 31 minus that is location of |
<> | 144:ef7eb2e8f9f7 | 39 | // first pending interrupt |
<> | 144:ef7eb2e8f9f7 | 40 | bitloc = 31 - __CLZ(rise0); |
<> | 144:ef7eb2e8f9f7 | 41 | if (channel_ids[bitloc] != 0) |
<> | 144:ef7eb2e8f9f7 | 42 | irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | // Both clear the interrupt with clear register, and remove it from |
<> | 144:ef7eb2e8f9f7 | 45 | // our local copy of the interrupt pending register |
<> | 144:ef7eb2e8f9f7 | 46 | LPC_GPIOINT->IO0IntClr = 1 << bitloc; |
<> | 144:ef7eb2e8f9f7 | 47 | rise0 -= 1<<bitloc; |
<> | 144:ef7eb2e8f9f7 | 48 | } |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | // Continue as long as there are interrupts pending |
<> | 144:ef7eb2e8f9f7 | 51 | while(fall0 > 0) { |
<> | 144:ef7eb2e8f9f7 | 52 | // CLZ returns number of leading zeros, 31 minus that is location of |
<> | 144:ef7eb2e8f9f7 | 53 | // first pending interrupt |
<> | 144:ef7eb2e8f9f7 | 54 | bitloc = 31 - __CLZ(fall0); |
<> | 144:ef7eb2e8f9f7 | 55 | if (channel_ids[bitloc] != 0) |
<> | 144:ef7eb2e8f9f7 | 56 | irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | // Both clear the interrupt with clear register, and remove it from |
<> | 144:ef7eb2e8f9f7 | 59 | // our local copy of the interrupt pending register |
<> | 144:ef7eb2e8f9f7 | 60 | LPC_GPIOINT->IO0IntClr = 1 << bitloc; |
<> | 144:ef7eb2e8f9f7 | 61 | fall0 -= 1<<bitloc; |
<> | 144:ef7eb2e8f9f7 | 62 | } |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | // Same for port 2 |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | // Continue as long as there are interrupts pending |
<> | 144:ef7eb2e8f9f7 | 67 | while(rise2 > 0) { |
<> | 144:ef7eb2e8f9f7 | 68 | // CLZ returns number of leading zeros, 31 minus that is location of |
<> | 144:ef7eb2e8f9f7 | 69 | // first pending interrupt |
<> | 144:ef7eb2e8f9f7 | 70 | bitloc = 31 - __CLZ(rise2); |
<> | 144:ef7eb2e8f9f7 | 71 | if (channel_ids[bitloc+32] != 0) |
<> | 144:ef7eb2e8f9f7 | 72 | irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | // Both clear the interrupt with clear register, and remove it from |
<> | 144:ef7eb2e8f9f7 | 75 | // our local copy of the interrupt pending register |
<> | 144:ef7eb2e8f9f7 | 76 | LPC_GPIOINT->IO2IntClr = 1 << bitloc; |
<> | 144:ef7eb2e8f9f7 | 77 | rise2 -= 1<<bitloc; |
<> | 144:ef7eb2e8f9f7 | 78 | } |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | // Continue as long as there are interrupts pending |
<> | 144:ef7eb2e8f9f7 | 81 | while(fall2 > 0) { |
<> | 144:ef7eb2e8f9f7 | 82 | // CLZ returns number of leading zeros, 31 minus that is location of |
<> | 144:ef7eb2e8f9f7 | 83 | // first pending interrupt |
<> | 144:ef7eb2e8f9f7 | 84 | bitloc = 31 - __CLZ(fall2); |
<> | 144:ef7eb2e8f9f7 | 85 | if (channel_ids[bitloc+32] != 0) |
<> | 144:ef7eb2e8f9f7 | 86 | irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | // Both clear the interrupt with clear register, and remove it from |
<> | 144:ef7eb2e8f9f7 | 89 | // our local copy of the interrupt pending register |
<> | 144:ef7eb2e8f9f7 | 90 | LPC_GPIOINT->IO2IntClr = 1 << bitloc; |
<> | 144:ef7eb2e8f9f7 | 91 | fall2 -= 1<<bitloc; |
<> | 144:ef7eb2e8f9f7 | 92 | } |
<> | 144:ef7eb2e8f9f7 | 93 | } |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { |
<> | 144:ef7eb2e8f9f7 | 96 | if (pin == NC) return -1; |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | irq_handler = handler; |
<> | 144:ef7eb2e8f9f7 | 99 | |
<> | 144:ef7eb2e8f9f7 | 100 | obj->port = ((int)(LPC_GPIO0_BASE+pin) & ~0x1F); |
<> | 144:ef7eb2e8f9f7 | 101 | obj->pin = (int)pin % 32; |
<> | 144:ef7eb2e8f9f7 | 102 | |
<> | 144:ef7eb2e8f9f7 | 103 | // Interrupts available only on GPIO0 and GPIO2 |
<> | 144:ef7eb2e8f9f7 | 104 | if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) { |
<> | 144:ef7eb2e8f9f7 | 105 | error("pins on this port cannot generate interrupts"); |
<> | 144:ef7eb2e8f9f7 | 106 | } |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | // put us in the interrupt table |
<> | 144:ef7eb2e8f9f7 | 109 | int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32; |
<> | 144:ef7eb2e8f9f7 | 110 | channel_ids[index] = id; |
<> | 144:ef7eb2e8f9f7 | 111 | obj->ch = index; |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in); |
<> | 144:ef7eb2e8f9f7 | 114 | NVIC_EnableIRQ(GPIO_IRQn); |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | return 0; |
<> | 144:ef7eb2e8f9f7 | 117 | } |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | void gpio_irq_free(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 120 | channel_ids[obj->ch] = 0; |
<> | 144:ef7eb2e8f9f7 | 121 | } |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
<> | 144:ef7eb2e8f9f7 | 124 | // ensure nothing is pending |
<> | 144:ef7eb2e8f9f7 | 125 | switch (obj->port) { |
<> | 144:ef7eb2e8f9f7 | 126 | case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break; |
<> | 144:ef7eb2e8f9f7 | 127 | case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break; |
<> | 144:ef7eb2e8f9f7 | 128 | } |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | // enable the pin interrupt |
<> | 144:ef7eb2e8f9f7 | 131 | if (event == IRQ_RISE) { |
<> | 144:ef7eb2e8f9f7 | 132 | switch (obj->port) { |
<> | 144:ef7eb2e8f9f7 | 133 | case LPC_GPIO0_BASE: |
<> | 144:ef7eb2e8f9f7 | 134 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 135 | LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin; |
<> | 144:ef7eb2e8f9f7 | 136 | } else { |
<> | 144:ef7eb2e8f9f7 | 137 | LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin); |
<> | 144:ef7eb2e8f9f7 | 138 | } |
<> | 144:ef7eb2e8f9f7 | 139 | break; |
<> | 144:ef7eb2e8f9f7 | 140 | case LPC_GPIO2_BASE: |
<> | 144:ef7eb2e8f9f7 | 141 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 142 | LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin; |
<> | 144:ef7eb2e8f9f7 | 143 | } else { |
<> | 144:ef7eb2e8f9f7 | 144 | LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin); |
<> | 144:ef7eb2e8f9f7 | 145 | } |
<> | 144:ef7eb2e8f9f7 | 146 | break; |
<> | 144:ef7eb2e8f9f7 | 147 | } |
<> | 144:ef7eb2e8f9f7 | 148 | } else { |
<> | 144:ef7eb2e8f9f7 | 149 | switch (obj->port) { |
<> | 144:ef7eb2e8f9f7 | 150 | case LPC_GPIO0_BASE: |
<> | 144:ef7eb2e8f9f7 | 151 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 152 | LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin; |
<> | 144:ef7eb2e8f9f7 | 153 | } else { |
<> | 144:ef7eb2e8f9f7 | 154 | LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin); |
<> | 144:ef7eb2e8f9f7 | 155 | } |
<> | 144:ef7eb2e8f9f7 | 156 | break; |
<> | 144:ef7eb2e8f9f7 | 157 | case LPC_GPIO2_BASE: |
<> | 144:ef7eb2e8f9f7 | 158 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 159 | LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin; |
<> | 144:ef7eb2e8f9f7 | 160 | } else { |
<> | 144:ef7eb2e8f9f7 | 161 | LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin); |
<> | 144:ef7eb2e8f9f7 | 162 | } |
<> | 144:ef7eb2e8f9f7 | 163 | break; |
<> | 144:ef7eb2e8f9f7 | 164 | } |
<> | 144:ef7eb2e8f9f7 | 165 | } |
<> | 144:ef7eb2e8f9f7 | 166 | } |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | void gpio_irq_enable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 169 | NVIC_EnableIRQ(GPIO_IRQn); |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | void gpio_irq_disable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 173 | NVIC_DisableIRQ(GPIO_IRQn); |
<> | 144:ef7eb2e8f9f7 | 174 | } |