Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "gpio_irq_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_INTERRUPTIN
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "gpio_api.h"
<> 149:156823d33999 22 #include "cmsis.h"
<> 149:156823d33999 23 #include "pinmap.h"
<> 149:156823d33999 24 #include "PeripheralPins.h"
<> 149:156823d33999 25 #include "nu_bitutil.h"
<> 149:156823d33999 26
<> 149:156823d33999 27 #define NU_MAX_PIN_PER_PORT 16
<> 149:156823d33999 28
<> 149:156823d33999 29 struct nu_gpio_irq_var {
<> 149:156823d33999 30 gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
<> 149:156823d33999 31 IRQn_Type irq_n;
<> 149:156823d33999 32 void (*vec)(void);
<> 149:156823d33999 33 };
<> 149:156823d33999 34
<> 149:156823d33999 35 static void gpio_irq_0_vec(void);
<> 149:156823d33999 36 static void gpio_irq_1_vec(void);
<> 149:156823d33999 37 static void gpio_irq_2_vec(void);
<> 149:156823d33999 38 static void gpio_irq_3_vec(void);
<> 149:156823d33999 39 static void gpio_irq_4_vec(void);
<> 149:156823d33999 40 static void gpio_irq_5_vec(void);
<> 149:156823d33999 41 static void gpio_irq_6_vec(void);
<> 149:156823d33999 42 static void gpio_irq_7_vec(void);
<> 149:156823d33999 43 static void gpio_irq_8_vec(void);
<> 149:156823d33999 44 static void gpio_irq(struct nu_gpio_irq_var *var);
<> 149:156823d33999 45
<> 149:156823d33999 46 //EINT0_IRQn
<> 149:156823d33999 47 static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
<> 149:156823d33999 48 {{NULL}, GPA_IRQn, gpio_irq_0_vec},
<> 149:156823d33999 49 {{NULL}, GPB_IRQn, gpio_irq_1_vec},
<> 149:156823d33999 50 {{NULL}, GPC_IRQn, gpio_irq_2_vec},
<> 149:156823d33999 51 {{NULL}, GPD_IRQn, gpio_irq_3_vec},
<> 149:156823d33999 52 {{NULL}, GPE_IRQn, gpio_irq_4_vec},
<> 149:156823d33999 53 {{NULL}, GPF_IRQn, gpio_irq_5_vec},
<> 149:156823d33999 54 {{NULL}, GPG_IRQn, gpio_irq_6_vec},
<> 149:156823d33999 55 {{NULL}, GPH_IRQn, gpio_irq_7_vec},
<> 149:156823d33999 56 {{NULL}, GPI_IRQn, gpio_irq_8_vec}
<> 149:156823d33999 57 };
<> 149:156823d33999 58
<> 149:156823d33999 59 #define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
<> 149:156823d33999 60
<> 149:156823d33999 61 #ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
<> 149:156823d33999 62 #define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
<> 149:156823d33999 63 #else
<> 149:156823d33999 64 #define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
<> 149:156823d33999 65 #endif
<> 149:156823d33999 66
<> 149:156823d33999 67 #ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
<> 149:156823d33999 68 #define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
<> 149:156823d33999 69 #else
<> 149:156823d33999 70 #define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
<> 149:156823d33999 71 #endif
<> 149:156823d33999 72
<> 149:156823d33999 73 #ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
<> 149:156823d33999 74 #define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
<> 149:156823d33999 75 #else
<> 149:156823d33999 76 #define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
<> 149:156823d33999 77 #endif
<> 149:156823d33999 78
<> 149:156823d33999 79 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
<> 149:156823d33999 80 {
<> 149:156823d33999 81 if (pin == NC) {
<> 149:156823d33999 82 return -1;
<> 149:156823d33999 83 }
<> 149:156823d33999 84
<> 149:156823d33999 85 uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
<> 149:156823d33999 86 uint32_t port_index = NU_PINNAME_TO_PORT(pin);
<> 149:156823d33999 87 if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
<> 149:156823d33999 88 return -1;
<> 149:156823d33999 89 }
<> 149:156823d33999 90
<> 149:156823d33999 91 obj->pin = pin;
<> 149:156823d33999 92 obj->irq_handler = (uint32_t) handler;
<> 149:156823d33999 93 obj->irq_id = id;
<> 149:156823d33999 94
<> 149:156823d33999 95 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
<> 149:156823d33999 96 //gpio_set(pin);
<> 149:156823d33999 97
<> 149:156823d33999 98 #if NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
<> 149:156823d33999 99 // Configure de-bounce clock source and sampling cycle time
<> 149:156823d33999 100 GPIO_SET_DEBOUNCE_TIME(NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
<> 149:156823d33999 101 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
<> 149:156823d33999 102 #else
<> 149:156823d33999 103 GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
<> 149:156823d33999 104 #endif
<> 149:156823d33999 105
<> 149:156823d33999 106 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 107
<> 149:156823d33999 108 var->obj_arr[pin_index] = obj;
<> 149:156823d33999 109
<> 149:156823d33999 110 // NOTE: InterruptIn requires IRQ enabled by default.
<> 149:156823d33999 111 gpio_irq_enable(obj);
<> 149:156823d33999 112
<> 149:156823d33999 113 return 0;
<> 149:156823d33999 114 }
<> 149:156823d33999 115
<> 149:156823d33999 116 void gpio_irq_free(gpio_irq_t *obj)
<> 149:156823d33999 117 {
<> 149:156823d33999 118 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 119 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 120 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 121
<> 149:156823d33999 122 NVIC_DisableIRQ(var->irq_n);
<> 149:156823d33999 123 NU_PORT_BASE(port_index)->INTEN = 0;
<> 149:156823d33999 124
<> 149:156823d33999 125 MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
<> 149:156823d33999 126 var->obj_arr[pin_index] = NULL;
<> 149:156823d33999 127 }
<> 149:156823d33999 128
<> 149:156823d33999 129 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 149:156823d33999 130 {
<> 149:156823d33999 131 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 132 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 133 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
<> 149:156823d33999 134
<> 149:156823d33999 135 switch (event) {
<> 149:156823d33999 136 case IRQ_RISE:
<> 149:156823d33999 137 if (enable) {
<> 149:156823d33999 138 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
<> 149:156823d33999 139 }
<> 149:156823d33999 140 else {
<> 149:156823d33999 141 gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
<> 149:156823d33999 142 }
<> 149:156823d33999 143 break;
<> 149:156823d33999 144
<> 149:156823d33999 145 case IRQ_FALL:
<> 149:156823d33999 146 if (enable) {
<> 149:156823d33999 147 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
<> 149:156823d33999 148 }
<> 149:156823d33999 149 else {
<> 149:156823d33999 150 gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
<> 149:156823d33999 151 }
<> 149:156823d33999 152 break;
<> 149:156823d33999 153 }
<> 149:156823d33999 154 }
<> 149:156823d33999 155
<> 149:156823d33999 156 void gpio_irq_enable(gpio_irq_t *obj)
<> 149:156823d33999 157 {
<> 149:156823d33999 158 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 159 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 160 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 161
<> 149:156823d33999 162 NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
<> 149:156823d33999 163 NVIC_EnableIRQ(var->irq_n);
<> 149:156823d33999 164 }
<> 149:156823d33999 165
<> 149:156823d33999 166 void gpio_irq_disable(gpio_irq_t *obj)
<> 149:156823d33999 167 {
<> 149:156823d33999 168 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
<> 149:156823d33999 169 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
<> 149:156823d33999 170 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
<> 149:156823d33999 171
<> 149:156823d33999 172 NVIC_DisableIRQ(var->irq_n);
<> 149:156823d33999 173 }
<> 149:156823d33999 174
<> 149:156823d33999 175 static void gpio_irq_0_vec(void)
<> 149:156823d33999 176 {
<> 149:156823d33999 177 gpio_irq(gpio_irq_var_arr + 0);
<> 149:156823d33999 178 }
<> 149:156823d33999 179 static void gpio_irq_1_vec(void)
<> 149:156823d33999 180 {
<> 149:156823d33999 181 gpio_irq(gpio_irq_var_arr + 1);
<> 149:156823d33999 182 }
<> 149:156823d33999 183 static void gpio_irq_2_vec(void)
<> 149:156823d33999 184 {
<> 149:156823d33999 185 gpio_irq(gpio_irq_var_arr + 2);
<> 149:156823d33999 186 }
<> 149:156823d33999 187 static void gpio_irq_3_vec(void)
<> 149:156823d33999 188 {
<> 149:156823d33999 189 gpio_irq(gpio_irq_var_arr + 3);
<> 149:156823d33999 190 }
<> 149:156823d33999 191 static void gpio_irq_4_vec(void)
<> 149:156823d33999 192 {
<> 149:156823d33999 193 gpio_irq(gpio_irq_var_arr + 4);
<> 149:156823d33999 194 }
<> 149:156823d33999 195 static void gpio_irq_5_vec(void)
<> 149:156823d33999 196 {
<> 149:156823d33999 197 gpio_irq(gpio_irq_var_arr + 5);
<> 149:156823d33999 198 }
<> 149:156823d33999 199 static void gpio_irq_6_vec(void)
<> 149:156823d33999 200 {
<> 149:156823d33999 201 gpio_irq(gpio_irq_var_arr + 6);
<> 149:156823d33999 202 }
<> 149:156823d33999 203 static void gpio_irq_7_vec(void)
<> 149:156823d33999 204 {
<> 149:156823d33999 205 gpio_irq(gpio_irq_var_arr + 7);
<> 149:156823d33999 206 }
<> 149:156823d33999 207 static void gpio_irq_8_vec(void)
<> 149:156823d33999 208 {
<> 149:156823d33999 209 gpio_irq(gpio_irq_var_arr + 8);
<> 149:156823d33999 210 }
<> 149:156823d33999 211
<> 149:156823d33999 212 static void gpio_irq(struct nu_gpio_irq_var *var)
<> 149:156823d33999 213 {
<> 149:156823d33999 214 uint32_t port_index = var->irq_n - GPA_IRQn;
<> 149:156823d33999 215 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
<> 149:156823d33999 216
<> 149:156823d33999 217 uint32_t intsrc = gpio_base->INTSRC;
<> 149:156823d33999 218 uint32_t inten = gpio_base->INTEN;
<> 149:156823d33999 219 while (intsrc) {
<> 149:156823d33999 220 int pin_index = nu_ctz(intsrc);
<> 149:156823d33999 221 gpio_irq_t *obj = var->obj_arr[pin_index];
<> 149:156823d33999 222 if (inten & (GPIO_INT_RISING << pin_index)) {
<> 149:156823d33999 223 if (GPIO_PIN_ADDR(port_index, pin_index)) {
<> 149:156823d33999 224 if (obj->irq_handler) {
<> 149:156823d33999 225 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
<> 149:156823d33999 226 }
<> 149:156823d33999 227 }
<> 149:156823d33999 228 }
<> 149:156823d33999 229
<> 149:156823d33999 230 if (inten & (GPIO_INT_FALLING << pin_index)) {
<> 149:156823d33999 231 if (! GPIO_PIN_ADDR(port_index, pin_index)) {
<> 149:156823d33999 232 if (obj->irq_handler) {
<> 149:156823d33999 233 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
<> 149:156823d33999 234 }
<> 149:156823d33999 235 }
<> 149:156823d33999 236 }
<> 149:156823d33999 237
<> 149:156823d33999 238 intsrc &= ~(1 << pin_index);
<> 149:156823d33999 239 }
<> 149:156823d33999 240 // Clear all interrupt flags
<> 149:156823d33999 241 gpio_base->INTSRC = gpio_base->INTSRC;
<> 149:156823d33999 242 }
<> 149:156823d33999 243
<> 149:156823d33999 244 #endif