Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_scuart.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_scuart.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file sc.h
<> 144:ef7eb2e8f9f7 3 * @version V1.00
<> 144:ef7eb2e8f9f7 4 * $Revision: 8 $
<> 144:ef7eb2e8f9f7 5 * $Date: 14/05/29 1:13p $
<> 144:ef7eb2e8f9f7 6 * @brief NUC472/NUC442 Smartcard UART mode (SCUART) driver header file
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *****************************************************************************/
<> 144:ef7eb2e8f9f7 11 #ifndef __SCUART_H__
<> 144:ef7eb2e8f9f7 12 #define __SCUART_H__
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 15 extern "C"
<> 144:ef7eb2e8f9f7 16 {
<> 144:ef7eb2e8f9f7 17 #endif
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
<> 144:ef7eb2e8f9f7 21 @{
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 /** @addtogroup NUC472_442_SCUART_Driver SCUART Driver
<> 144:ef7eb2e8f9f7 25 @{
<> 144:ef7eb2e8f9f7 26 */
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 /** @addtogroup NUC472_442_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
<> 144:ef7eb2e8f9f7 29 @{
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31 #define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */
<> 144:ef7eb2e8f9f7 32 #define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */
<> 144:ef7eb2e8f9f7 33 #define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */
<> 144:ef7eb2e8f9f7 34 #define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits \hideinitializer */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */
<> 144:ef7eb2e8f9f7 37 #define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */
<> 144:ef7eb2e8f9f7 38 #define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity \hideinitializer */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */
<> 144:ef7eb2e8f9f7 41 #define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits \hideinitializer */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /*@}*/ /* end of group NUC472_442_SCUART_EXPORTED_CONSTANTS */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup NUC472_442_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
<> 144:ef7eb2e8f9f7 48 @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* TX Macros */
<> 144:ef7eb2e8f9f7 52 /**
<> 144:ef7eb2e8f9f7 53 * @brief Write Data to Tx data register
<> 144:ef7eb2e8f9f7 54 * @param[in] sc The base address of smartcard module.
<> 144:ef7eb2e8f9f7 55 * @param[in] u8Data Data byte to transmit
<> 144:ef7eb2e8f9f7 56 * @return None
<> 144:ef7eb2e8f9f7 57 * \hideinitializer
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59 #define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief Get TX FIFO empty flag status from register
<> 144:ef7eb2e8f9f7 63 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 64 * @return Transmit FIFO empty status
<> 144:ef7eb2e8f9f7 65 * @retval 0 Transmit FIFO is not empty
<> 144:ef7eb2e8f9f7 66 * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
<> 144:ef7eb2e8f9f7 67 * \hideinitializer
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69 #define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /**
<> 144:ef7eb2e8f9f7 72 * @brief Get TX FIFO full flag status from register
<> 144:ef7eb2e8f9f7 73 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 74 * @return Transmit FIFO full status
<> 144:ef7eb2e8f9f7 75 * @retval 0 Transmit FIFO is not full
<> 144:ef7eb2e8f9f7 76 * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
<> 144:ef7eb2e8f9f7 77 * \hideinitializer
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 #define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /**
<> 144:ef7eb2e8f9f7 82 * @brief Wait specified smartcard port transmission complete
<> 144:ef7eb2e8f9f7 83 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 84 * @return None
<> 144:ef7eb2e8f9f7 85 * @note This Macro blocks until transmit complete.
<> 144:ef7eb2e8f9f7 86 * \hideinitializer
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 #define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief Check specified smartcard port transmit FIFO is full or not
<> 144:ef7eb2e8f9f7 92 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 93 * @return Transmit FIFO full status
<> 144:ef7eb2e8f9f7 94 * @retval 0 Transmit FIFO is not full
<> 144:ef7eb2e8f9f7 95 * @retval 1 Transmit FIFO is full
<> 144:ef7eb2e8f9f7 96 * \hideinitializer
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98 #define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @brief Check specified smartcard port transmission is over
<> 144:ef7eb2e8f9f7 102 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 103 * @return Transmit complete status
<> 144:ef7eb2e8f9f7 104 * @retval 0 Transmit is not complete
<> 144:ef7eb2e8f9f7 105 * @retval 1 Transmit complete
<> 144:ef7eb2e8f9f7 106 * \hideinitializer
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 #define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* RX Macros */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /**
<> 144:ef7eb2e8f9f7 114 * @brief Read Rx data register
<> 144:ef7eb2e8f9f7 115 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 116 * @return The oldest data byte in RX FIFO
<> 144:ef7eb2e8f9f7 117 * \hideinitializer
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 #define SCUART_READ(sc) ((sc)->DAT)
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @brief Get RX FIFO empty flag status from register
<> 144:ef7eb2e8f9f7 123 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 124 * @return Receive FIFO empty status
<> 144:ef7eb2e8f9f7 125 * @retval 0 Receive FIFO is not empty
<> 144:ef7eb2e8f9f7 126 * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
<> 144:ef7eb2e8f9f7 127 * \hideinitializer
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 #define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief Get RX FIFO full flag status from register
<> 144:ef7eb2e8f9f7 134 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 135 * @return Receive FIFO full status
<> 144:ef7eb2e8f9f7 136 * @retval 0 Receive FIFO is not full
<> 144:ef7eb2e8f9f7 137 * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full
<> 144:ef7eb2e8f9f7 138 * \hideinitializer
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 #define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @brief Check if receive data number in FIFO reach FIFO trigger level or not
<> 144:ef7eb2e8f9f7 144 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 145 * @return Receive FIFO data status
<> 144:ef7eb2e8f9f7 146 * @retval 0 The number of bytes in receive FIFO is less than trigger level
<> 144:ef7eb2e8f9f7 147 * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
<> 144:ef7eb2e8f9f7 148 * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO
<> 144:ef7eb2e8f9f7 149 * \hideinitializer
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 #define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief Check specified smartcard port receive FIFO is full or not
<> 144:ef7eb2e8f9f7 155 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 156 * @return Receive FIFO full status
<> 144:ef7eb2e8f9f7 157 * @retval 0 Receive FIFO is not full
<> 144:ef7eb2e8f9f7 158 * @retval 1 Receive FIFO is full
<> 144:ef7eb2e8f9f7 159 * \hideinitializer
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 #define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_SR_RX_FULL_F_Msk ? 1 : 0)
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Interrupt Macros */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @brief Enable specified interrupts
<> 144:ef7eb2e8f9f7 167 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 168 * @param[in] u32Mask Interrupt masks to enable, a combination of following bits
<> 144:ef7eb2e8f9f7 169 * - \ref SC_INTEN_RXTOIF_Msk
<> 144:ef7eb2e8f9f7 170 * - \ref SC_INTEN_TERRIEN_Msk
<> 144:ef7eb2e8f9f7 171 * - \ref SC_INTEN_TBEIEN_Msk
<> 144:ef7eb2e8f9f7 172 * - \ref SC_INTEN_RDAIEN_Msk
<> 144:ef7eb2e8f9f7 173 * @return None
<> 144:ef7eb2e8f9f7 174 * \hideinitializer
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 #define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @brief Disable specified interrupts
<> 144:ef7eb2e8f9f7 180 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 181 * @param[in] u32Mask Interrupt masks to disable, a combination of following bits
<> 144:ef7eb2e8f9f7 182 * - \ref SC_INTEN_RXTOIF_Msk
<> 144:ef7eb2e8f9f7 183 * - \ref SC_INTEN_TERRIEN_Msk
<> 144:ef7eb2e8f9f7 184 * - \ref SC_INTEN_TBEIEN_Msk
<> 144:ef7eb2e8f9f7 185 * - \ref SC_INTEN_RDAIEN_Msk
<> 144:ef7eb2e8f9f7 186 * @return None
<> 144:ef7eb2e8f9f7 187 * \hideinitializer
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 #define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief Get specified interrupt flag/status
<> 144:ef7eb2e8f9f7 193 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 194 * @param[in] u32Type Interrupt flag/status to check, could be one of following value
<> 144:ef7eb2e8f9f7 195 * - \ref SC_INTSTS_RBTOIF_Msk
<> 144:ef7eb2e8f9f7 196 * - \ref SC_INTSTS_TERRIF_Msk
<> 144:ef7eb2e8f9f7 197 * - \ref SC_INTSTS_TBEIF_Msk
<> 144:ef7eb2e8f9f7 198 * - \ref SC_INTSTS_RDAIF_Msk
<> 144:ef7eb2e8f9f7 199 * @return The status of specified interrupt
<> 144:ef7eb2e8f9f7 200 * @retval 0 Specified interrupt does not happened
<> 144:ef7eb2e8f9f7 201 * @retval 1 Specified interrupt happened
<> 144:ef7eb2e8f9f7 202 * \hideinitializer
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 #define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & u32Type ? 1 : 0)
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief Clear specified interrupt flag/status
<> 144:ef7eb2e8f9f7 208 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 209 * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
<> 144:ef7eb2e8f9f7 210 * - \ref SC_INTSTS_RBTOIF_Msk
<> 144:ef7eb2e8f9f7 211 * - \ref SC_INTSTS_TERRIF_Msk
<> 144:ef7eb2e8f9f7 212 * - \ref SC_INTSTS_TBEIF_Msk
<> 144:ef7eb2e8f9f7 213 * @return None
<> 144:ef7eb2e8f9f7 214 * \hideinitializer
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 #define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = u32Type)
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @brief Get receive error flag/status
<> 144:ef7eb2e8f9f7 220 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 221 * @return Current receive error status, could one of following errors:
<> 144:ef7eb2e8f9f7 222 * @retval SC_STATUS_PEF_Msk Parity error
<> 144:ef7eb2e8f9f7 223 * @retval SC_STATUS_FEF_Msk Frame error
<> 144:ef7eb2e8f9f7 224 * @retval SC_STATUS_BEF_Msk Break error
<> 144:ef7eb2e8f9f7 225 * \hideinitializer
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 #define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /**
<> 144:ef7eb2e8f9f7 230 * @brief Clear specified receive error flag/status
<> 144:ef7eb2e8f9f7 231 * @param[in] sc The base address of smartcard module
<> 144:ef7eb2e8f9f7 232 * @param[in] u32Mask Receive error flag/status to clear, combination following values
<> 144:ef7eb2e8f9f7 233 * - \ref SC_STATUS_PEF_Msk
<> 144:ef7eb2e8f9f7 234 * - \ref SC_STATUS_FEF_Msk
<> 144:ef7eb2e8f9f7 235 * - \ref SC_STATUS_BEF_Msk
<> 144:ef7eb2e8f9f7 236 * @return None
<> 144:ef7eb2e8f9f7 237 * \hideinitializer
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 #define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = u32Mask)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 void SCUART_Close(SC_T* sc);
<> 144:ef7eb2e8f9f7 242 uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
<> 144:ef7eb2e8f9f7 243 uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
<> 144:ef7eb2e8f9f7 244 uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
<> 144:ef7eb2e8f9f7 245 void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
<> 144:ef7eb2e8f9f7 246 void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /*@}*/ /* end of group NUC472_442_SCUART_EXPORTED_FUNCTIONS */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /*@}*/ /* end of group NUC472_442_SCUART_Driver */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /*@}*/ /* end of group NUC472_442_Device_Driver */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256 #endif
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 #endif //__SCUART_H__
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/