Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_pwm.c@144:ef7eb2e8f9f7
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file PWM.c
<> 144:ef7eb2e8f9f7 3 * @version V1.00
<> 144:ef7eb2e8f9f7 4 * $Revision: 22 $
<> 144:ef7eb2e8f9f7 5 * $Date: 14/10/02 9:21a $
<> 144:ef7eb2e8f9f7 6 * @brief NUC472/NUC442 PWM driver source file
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *****************************************************************************/
<> 144:ef7eb2e8f9f7 11 #include "NUC472_442.h"
<> 144:ef7eb2e8f9f7 12
<> 144:ef7eb2e8f9f7 13 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
<> 144:ef7eb2e8f9f7 14 @{
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 /** @addtogroup NUC472_442_PWM_Driver PWM Driver
<> 144:ef7eb2e8f9f7 18 @{
<> 144:ef7eb2e8f9f7 19 */
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 /** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
<> 144:ef7eb2e8f9f7 23 @{
<> 144:ef7eb2e8f9f7 24 */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 /**
<> 144:ef7eb2e8f9f7 27 * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
<> 144:ef7eb2e8f9f7 28 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 29 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 30 * @param[in] u32Frequency Target generator frequency
<> 144:ef7eb2e8f9f7 31 * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
<> 144:ef7eb2e8f9f7 32 * @return Nearest frequency clock in nano second
<> 144:ef7eb2e8f9f7 33 * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
<> 144:ef7eb2e8f9f7 34 * existing frequency of other channel.
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36 uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
<> 144:ef7eb2e8f9f7 37 uint32_t u32ChannelNum,
<> 144:ef7eb2e8f9f7 38 uint32_t u32Frequency,
<> 144:ef7eb2e8f9f7 39 uint32_t u32DutyCycle)
<> 144:ef7eb2e8f9f7 40 {
<> 144:ef7eb2e8f9f7 41 return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
<> 144:ef7eb2e8f9f7 42 }
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /**
<> 144:ef7eb2e8f9f7 45 * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
<> 144:ef7eb2e8f9f7 46 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 47 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 48 * @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
<> 144:ef7eb2e8f9f7 49 * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
<> 144:ef7eb2e8f9f7 50 * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
<> 144:ef7eb2e8f9f7 51 * @return Nearest frequency clock in nano second
<> 144:ef7eb2e8f9f7 52 * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
<> 144:ef7eb2e8f9f7 53 * existing frequency of other channel.
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
<> 144:ef7eb2e8f9f7 56 uint32_t u32ChannelNum,
<> 144:ef7eb2e8f9f7 57 uint32_t u32Frequency,
<> 144:ef7eb2e8f9f7 58 uint32_t u32DutyCycle,
<> 144:ef7eb2e8f9f7 59 uint32_t u32Frequency2)
<> 144:ef7eb2e8f9f7 60 {
<> 144:ef7eb2e8f9f7 61 uint32_t i;
<> 144:ef7eb2e8f9f7 62 uint32_t u32PWM_CLock;
<> 144:ef7eb2e8f9f7 63 uint8_t u8Divider = 1, u8Prescale = 0xFF;
<> 144:ef7eb2e8f9f7 64 uint16_t u16CNR = 0xFFFF;
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 if (pwm == PWM0) {
<> 144:ef7eb2e8f9f7 67 if (u32ChannelNum < 2) {
<> 144:ef7eb2e8f9f7 68 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
<> 144:ef7eb2e8f9f7 69 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 70 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
<> 144:ef7eb2e8f9f7 71 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 72 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
<> 144:ef7eb2e8f9f7 73 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 74 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
<> 144:ef7eb2e8f9f7 75 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 76 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
<> 144:ef7eb2e8f9f7 77 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 78 } else if (u32ChannelNum < 4) {
<> 144:ef7eb2e8f9f7 79 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 80 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 81 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 82 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 83 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 84 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 85 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 86 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 87 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 88 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 89 } else if (u32ChannelNum < 6) {
<> 144:ef7eb2e8f9f7 90 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 91 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 92 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 93 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 94 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 95 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 96 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 97 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 98 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 99 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101 } else if (pwm == PWM1) {
<> 144:ef7eb2e8f9f7 102 if (u32ChannelNum < 2) {
<> 144:ef7eb2e8f9f7 103 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
<> 144:ef7eb2e8f9f7 104 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 105 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
<> 144:ef7eb2e8f9f7 106 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 107 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
<> 144:ef7eb2e8f9f7 108 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 109 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
<> 144:ef7eb2e8f9f7 110 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 111 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
<> 144:ef7eb2e8f9f7 112 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 113 } else if (u32ChannelNum < 4) {
<> 144:ef7eb2e8f9f7 114 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 115 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 116 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 117 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 118 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 119 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 120 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 121 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 122 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 123 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 124 } else if (u32ChannelNum < 6) {
<> 144:ef7eb2e8f9f7 125 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 126 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 127 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 128 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 129 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 130 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 131 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 132 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 133 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 134 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
<> 144:ef7eb2e8f9f7 139 // Note: Support frequency < 1
<> 144:ef7eb2e8f9f7 140 i = (uint64_t) u32PWM_CLock * u32Frequency2 / u32Frequency / u8Divider;
<> 144:ef7eb2e8f9f7 141 // If target value is larger than CNR * prescale, need to use a larger divider
<> 144:ef7eb2e8f9f7 142 if(i > (0x10000 * 0x100))
<> 144:ef7eb2e8f9f7 143 continue;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
<> 144:ef7eb2e8f9f7 146 u8Prescale = (i + 0xFFFF)/ 0x10000;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 // u8Prescale must at least be 2, otherwise the output stop
<> 144:ef7eb2e8f9f7 149 if(u8Prescale < 3)
<> 144:ef7eb2e8f9f7 150 u8Prescale = 2;
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 i /= u8Prescale;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 if(i <= 0x10000) {
<> 144:ef7eb2e8f9f7 155 if(i == 1)
<> 144:ef7eb2e8f9f7 156 u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
<> 144:ef7eb2e8f9f7 157 else
<> 144:ef7eb2e8f9f7 158 u16CNR = i;
<> 144:ef7eb2e8f9f7 159 break;
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163 // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
<> 144:ef7eb2e8f9f7 164 i = u32PWM_CLock / (u8Prescale * u8Divider * u16CNR);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 u8Prescale -= 1;
<> 144:ef7eb2e8f9f7 167 u16CNR -= 1;
<> 144:ef7eb2e8f9f7 168 // convert to real register value
<> 144:ef7eb2e8f9f7 169 if(u8Divider == 1)
<> 144:ef7eb2e8f9f7 170 u8Divider = 4;
<> 144:ef7eb2e8f9f7 171 else if (u8Divider == 2)
<> 144:ef7eb2e8f9f7 172 u8Divider = 0;
<> 144:ef7eb2e8f9f7 173 else if (u8Divider == 4)
<> 144:ef7eb2e8f9f7 174 u8Divider = 1;
<> 144:ef7eb2e8f9f7 175 else if (u8Divider == 8)
<> 144:ef7eb2e8f9f7 176 u8Divider = 2;
<> 144:ef7eb2e8f9f7 177 else // 16
<> 144:ef7eb2e8f9f7 178 u8Divider = 3;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 // every two channels share a prescaler
<> 144:ef7eb2e8f9f7 181 while((pwm->SBS[u32ChannelNum] & 1) == 1);
<> 144:ef7eb2e8f9f7 182 pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
<> 144:ef7eb2e8f9f7 183 pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
<> 144:ef7eb2e8f9f7 184 pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
<> 144:ef7eb2e8f9f7 185 if(u32DutyCycle == 0)
<> 144:ef7eb2e8f9f7 186 pwm->CMPDAT[u32ChannelNum] = 0;
<> 144:ef7eb2e8f9f7 187 else
<> 144:ef7eb2e8f9f7 188 pwm->CMPDAT[u32ChannelNum] = u32DutyCycle * (u16CNR + 1) / 100 - 1;
<> 144:ef7eb2e8f9f7 189 pwm->PERIOD[u32ChannelNum] = u16CNR;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 return(i);
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @brief This function config PWM capture and get the nearest unit time
<> 144:ef7eb2e8f9f7 196 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 197 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 198 * @param[in] u32UnitTimeNsec Unit time of counter
<> 144:ef7eb2e8f9f7 199 * @param[in] u32CaptureEdge Condition to latch the counter
<> 144:ef7eb2e8f9f7 200 * @return Nearest unit time in nano second
<> 144:ef7eb2e8f9f7 201 * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
<> 144:ef7eb2e8f9f7 202 * existing frequency of other channel.
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
<> 144:ef7eb2e8f9f7 205 uint32_t u32ChannelNum,
<> 144:ef7eb2e8f9f7 206 uint32_t u32UnitTimeNsec,
<> 144:ef7eb2e8f9f7 207 uint32_t u32CaptureEdge)
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 uint32_t i;
<> 144:ef7eb2e8f9f7 210 uint32_t u32PWM_CLock;
<> 144:ef7eb2e8f9f7 211 uint8_t u8Divider = 1, u8Prescale = 0xFF;
<> 144:ef7eb2e8f9f7 212 uint16_t u16CNR = 0xFFFF;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 if (pwm == PWM0) {
<> 144:ef7eb2e8f9f7 215 if (u32ChannelNum < 2) {
<> 144:ef7eb2e8f9f7 216 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
<> 144:ef7eb2e8f9f7 217 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 218 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
<> 144:ef7eb2e8f9f7 219 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 220 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
<> 144:ef7eb2e8f9f7 221 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 222 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
<> 144:ef7eb2e8f9f7 223 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 224 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
<> 144:ef7eb2e8f9f7 225 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 226 } else if (u32ChannelNum < 4) {
<> 144:ef7eb2e8f9f7 227 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 228 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 229 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 230 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 231 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 232 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 233 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 234 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 235 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 236 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 237 } else if (u32ChannelNum < 6) {
<> 144:ef7eb2e8f9f7 238 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 239 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 240 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 241 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 242 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 243 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 244 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 245 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 246 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 247 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249 } else if (pwm == PWM1) {
<> 144:ef7eb2e8f9f7 250 if (u32ChannelNum < 2) {
<> 144:ef7eb2e8f9f7 251 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
<> 144:ef7eb2e8f9f7 252 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 253 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
<> 144:ef7eb2e8f9f7 254 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 255 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
<> 144:ef7eb2e8f9f7 256 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 257 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
<> 144:ef7eb2e8f9f7 258 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 259 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
<> 144:ef7eb2e8f9f7 260 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 261 } else if (u32ChannelNum < 4) {
<> 144:ef7eb2e8f9f7 262 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 263 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 264 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 265 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 266 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 267 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 268 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 269 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 270 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
<> 144:ef7eb2e8f9f7 271 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 272 } else if (u32ChannelNum < 6) {
<> 144:ef7eb2e8f9f7 273 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 274 u32PWM_CLock = __HXT;
<> 144:ef7eb2e8f9f7 275 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 276 u32PWM_CLock = __LXT;
<> 144:ef7eb2e8f9f7 277 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 278 u32PWM_CLock = SystemCoreClock;
<> 144:ef7eb2e8f9f7 279 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 280 u32PWM_CLock = __HIRC;
<> 144:ef7eb2e8f9f7 281 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
<> 144:ef7eb2e8f9f7 282 u32PWM_CLock = __LIRC;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
<> 144:ef7eb2e8f9f7 287 i = ((u32PWM_CLock / u8Divider) * u32UnitTimeNsec) / 1000000000;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 // If target value is larger than 0xFF, need to use a larger divider
<> 144:ef7eb2e8f9f7 290 if(i > (0xFF))
<> 144:ef7eb2e8f9f7 291 continue;
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 u8Prescale = i;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 // u8Prescale must at least be 2, otherwise the output stop
<> 144:ef7eb2e8f9f7 296 if(u8Prescale < 3)
<> 144:ef7eb2e8f9f7 297 u8Prescale = 2;
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 break;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
<> 144:ef7eb2e8f9f7 303 i = (u8Prescale * u8Divider) * 1000000000/ u32PWM_CLock;
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 u8Prescale -= 1;
<> 144:ef7eb2e8f9f7 306 u16CNR -= 1;
<> 144:ef7eb2e8f9f7 307 // convert to real register value
<> 144:ef7eb2e8f9f7 308 if(u8Divider == 1)
<> 144:ef7eb2e8f9f7 309 u8Divider = 4;
<> 144:ef7eb2e8f9f7 310 else if (u8Divider == 2)
<> 144:ef7eb2e8f9f7 311 u8Divider = 0;
<> 144:ef7eb2e8f9f7 312 else if (u8Divider == 4)
<> 144:ef7eb2e8f9f7 313 u8Divider = 1;
<> 144:ef7eb2e8f9f7 314 else if (u8Divider == 8)
<> 144:ef7eb2e8f9f7 315 u8Divider = 2;
<> 144:ef7eb2e8f9f7 316 else // 16
<> 144:ef7eb2e8f9f7 317 u8Divider = 3;
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 // every two channels share a prescaler
<> 144:ef7eb2e8f9f7 320 while((pwm->SBS[u32ChannelNum] & 1) == 1);
<> 144:ef7eb2e8f9f7 321 pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
<> 144:ef7eb2e8f9f7 322 pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
<> 144:ef7eb2e8f9f7 323 pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
<> 144:ef7eb2e8f9f7 324 pwm->PERIOD[u32ChannelNum] = u16CNR;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 return(i);
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief This function start PWM module
<> 144:ef7eb2e8f9f7 331 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 332 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
<> 144:ef7eb2e8f9f7 333 * Bit 0 is channel 0, bit 1 is channel 1...
<> 144:ef7eb2e8f9f7 334 * @return None
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 pwm->CNTEN |= u32ChannelMask;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @brief This function stop PWM module
<> 144:ef7eb2e8f9f7 343 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 344 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
<> 144:ef7eb2e8f9f7 345 * Bit 0 is channel 0, bit 1 is channel 1...
<> 144:ef7eb2e8f9f7 346 * @return None
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 uint32_t i;
<> 144:ef7eb2e8f9f7 351 for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
<> 144:ef7eb2e8f9f7 352 if(u32ChannelMask & (1 << i)) {
<> 144:ef7eb2e8f9f7 353 *(__IO uint32_t *) (&pwm->CNTEN + 1 * i) = 0;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @brief This function stop PWM generation immediately by clear channel enable bit
<> 144:ef7eb2e8f9f7 361 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 362 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
<> 144:ef7eb2e8f9f7 363 * Bit 0 is channel 0, bit 1 is channel 1...
<> 144:ef7eb2e8f9f7 364 * @return None
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 pwm->CNTEN &= ~u32ChannelMask;
<> 144:ef7eb2e8f9f7 369 }
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @brief This function enable selected channel to trigger ADC
<> 144:ef7eb2e8f9f7 373 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 374 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 375 * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
<> 144:ef7eb2e8f9f7 376 * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
<> 144:ef7eb2e8f9f7 377 * - \ref PWM_TRIGGER_ADC_CENTER_POINT
<> 144:ef7eb2e8f9f7 378 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
<> 144:ef7eb2e8f9f7 379 * - \ref PWM_TRIGGER_ADC_RISING_EDGE_POINT
<> 144:ef7eb2e8f9f7 380 * @return None
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
<> 144:ef7eb2e8f9f7 385 PWM_TRIGGER_ADC_CENTER_POINT |
<> 144:ef7eb2e8f9f7 386 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
<> 144:ef7eb2e8f9f7 387 PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum))) | (u32Condition << (1 * u32ChannelNum));
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief This function disable selected channel to trigger ADC
<> 144:ef7eb2e8f9f7 392 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 393 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 394 * @return None
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
<> 144:ef7eb2e8f9f7 399 PWM_TRIGGER_ADC_CENTER_POINT |
<> 144:ef7eb2e8f9f7 400 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
<> 144:ef7eb2e8f9f7 401 PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum)));
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @brief This function clear selected channel trigger ADC flag
<> 144:ef7eb2e8f9f7 406 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 407 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 408 * @param[in] u32Condition PWM triggered ADC flag to be cleared. A combination of following flags:
<> 144:ef7eb2e8f9f7 409 * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
<> 144:ef7eb2e8f9f7 410 * - \ref PWM_TRIGGER_ADC_CENTER_POINT
<> 144:ef7eb2e8f9f7 411 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
<> 144:ef7eb2e8f9f7 412 * - \ref PWM_TRIGGER_ADC_RISING_EDGE_POINT
<> 144:ef7eb2e8f9f7 413 * @return None
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 pwm->TRGADCSTS |= (u32Condition << (1 * u32ChannelNum));
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @brief This function get selected channel trigger ADC flag
<> 144:ef7eb2e8f9f7 422 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 423 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 424 * @return Combination of following trigger conditions which triggered ADC
<> 144:ef7eb2e8f9f7 425 * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
<> 144:ef7eb2e8f9f7 426 * - \ref PWM_TRIGGER_ADC_CENTER_POINT
<> 144:ef7eb2e8f9f7 427 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
<> 144:ef7eb2e8f9f7 428 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 uint32_t u32Ret;
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 u32Ret = pwm->TRGADCSTS >> u32ChannelNum;
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 return (u32Ret & (PWM_TRIGGER_ADC_PERIOD_POINT |
<> 144:ef7eb2e8f9f7 437 PWM_TRIGGER_ADC_CENTER_POINT |
<> 144:ef7eb2e8f9f7 438 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
<> 144:ef7eb2e8f9f7 439 PWM_TRIGGER_ADC_FALLING_EDGE_POINT));
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /**
<> 144:ef7eb2e8f9f7 443 * @brief This function enable fault brake of selected channels
<> 144:ef7eb2e8f9f7 444 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 445 * @param[in] u32ChannelMask This parameter is not used
<> 144:ef7eb2e8f9f7 446 * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
<> 144:ef7eb2e8f9f7 447 * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
<> 144:ef7eb2e8f9f7 448 * , bit 6 represent D6, and bit 7 represents D7
<> 144:ef7eb2e8f9f7 449 * @param[in] u32BrakeSource Fault brake source, could be one of following source
<> 144:ef7eb2e8f9f7 450 * - \ref PWM_BRK0_BKP0
<> 144:ef7eb2e8f9f7 451 * - \ref PWM_BRK0_CPO0
<> 144:ef7eb2e8f9f7 452 * - \ref PWM_BRK0_CPO1
<> 144:ef7eb2e8f9f7 453 * - \ref PWM_BRK0_CPO2
<> 144:ef7eb2e8f9f7 454 * - \ref PWM_BK1SEL_BKP1
<> 144:ef7eb2e8f9f7 455 * - \ref PWM_BK1SEL_CPO0
<> 144:ef7eb2e8f9f7 456 * - \ref PWM_BK1SEL_CPO1
<> 144:ef7eb2e8f9f7 457 * @return None
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 void PWM_EnableFaultBrake (PWM_T *pwm,
<> 144:ef7eb2e8f9f7 460 uint32_t u32ChannelMask,
<> 144:ef7eb2e8f9f7 461 uint32_t u32LevelMask,
<> 144:ef7eb2e8f9f7 462 uint32_t u32BrakeSource)
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 if ((u32BrakeSource == PWM_BRK0_BKP0)||(u32BrakeSource == PWM_BRK0_CPO0)||(u32BrakeSource == PWM_BRK0_CPO1)||(u32BrakeSource == PWM_BRK0_CPO2))
<> 144:ef7eb2e8f9f7 465 pwm->BRKCTL |= (u32BrakeSource | PWM_BRKCTL_BRK0EN_Msk);
<> 144:ef7eb2e8f9f7 466 else
<> 144:ef7eb2e8f9f7 467 pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BK1SEL_Msk) | u32BrakeSource | PWM_BRKCTL_BRK1EN_Msk;
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @brief This function clear fault brake flag
<> 144:ef7eb2e8f9f7 472 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 473 * @param[in] u32BrakeSource This parameter is not used
<> 144:ef7eb2e8f9f7 474 * @return None
<> 144:ef7eb2e8f9f7 475 * @note After fault brake occurred, application must clear fault brake source before re-enable PWM output
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 pwm->INTSTS = PWM_INTSTS_BRKLK0_Msk;
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @brief This function enables PWM capture of selected channels
<> 144:ef7eb2e8f9f7 484 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 485 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
<> 144:ef7eb2e8f9f7 486 * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
<> 144:ef7eb2e8f9f7 487 * @return None
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489 void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 pwm->CAPCTL |= u32ChannelMask;
<> 144:ef7eb2e8f9f7 492 pwm->CAPINEN |= u32ChannelMask;
<> 144:ef7eb2e8f9f7 493 pwm->CTL |= (u32ChannelMask << PWM_CTL_CNTMODE_Pos);
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @brief This function disables PWM capture of selected channels
<> 144:ef7eb2e8f9f7 498 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 499 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
<> 144:ef7eb2e8f9f7 500 * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
<> 144:ef7eb2e8f9f7 501 * @return None
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503 void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 pwm->CAPCTL &= ~u32ChannelMask;
<> 144:ef7eb2e8f9f7 506 pwm->CAPINEN &= ~u32ChannelMask;
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @brief This function enables PWM output generation of selected channels
<> 144:ef7eb2e8f9f7 511 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 512 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
<> 144:ef7eb2e8f9f7 513 * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
<> 144:ef7eb2e8f9f7 514 * @return None
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516 void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 pwm->POEN |= u32ChannelMask;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /**
<> 144:ef7eb2e8f9f7 522 * @brief This function disables PWM output generation of selected channels
<> 144:ef7eb2e8f9f7 523 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 524 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
<> 144:ef7eb2e8f9f7 525 * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
<> 144:ef7eb2e8f9f7 526 * @return None
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 pwm->POEN &= ~u32ChannelMask;
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief This function enable Dead zone of selected channel
<> 144:ef7eb2e8f9f7 535 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 536 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 537 * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no
<> 144:ef7eb2e8f9f7 538 * dead zone.
<> 144:ef7eb2e8f9f7 539 * @return None
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 // every two channels shares the same setting
<> 144:ef7eb2e8f9f7 544 u32ChannelNum >>= 1;
<> 144:ef7eb2e8f9f7 545 // set duration
<> 144:ef7eb2e8f9f7 546 pwm->DTCTL = (pwm->DTCTL & ~(PWM_DTCTL_DTCNT01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
<> 144:ef7eb2e8f9f7 547 // enable dead zone
<> 144:ef7eb2e8f9f7 548 pwm->DTCTL |= (PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /**
<> 144:ef7eb2e8f9f7 552 * @brief This function disable Dead zone of selected channel
<> 144:ef7eb2e8f9f7 553 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 554 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 555 * @return None
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 // every two channels shares the same setting
<> 144:ef7eb2e8f9f7 560 u32ChannelNum >>= 1;
<> 144:ef7eb2e8f9f7 561 // enable dead zone
<> 144:ef7eb2e8f9f7 562 pwm->DTCTL &= ~(PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /**
<> 144:ef7eb2e8f9f7 566 * @brief This function enable capture interrupt of selected channel
<> 144:ef7eb2e8f9f7 567 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 568 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 569 * @param[in] u32Edge Capture interrupt type. It could be either
<> 144:ef7eb2e8f9f7 570 * - \ref PWM_FALLING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 571 * - \ref PWM_RISING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 572 * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 573 * @return None
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575 void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 // enable capture interrupt
<> 144:ef7eb2e8f9f7 578 pwm->INTEN |= (u32Edge << u32ChannelNum);
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief This function disable capture interrupt of selected channel
<> 144:ef7eb2e8f9f7 583 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 584 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 585 * @param[in] u32Edge Capture interrupt type. It could be either
<> 144:ef7eb2e8f9f7 586 * - \ref PWM_FALLING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 587 * - \ref PWM_RISING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 588 * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 589 * @return None
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 // disable capture interrupt
<> 144:ef7eb2e8f9f7 594 pwm->INTEN &= ~(u32Edge << u32ChannelNum);
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /**
<> 144:ef7eb2e8f9f7 598 * @brief This function clear capture interrupt flag of selected channel
<> 144:ef7eb2e8f9f7 599 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 600 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 601 * @param[in] u32Edge Capture interrupt type. It could be either
<> 144:ef7eb2e8f9f7 602 * - \ref PWM_FALLING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 603 * - \ref PWM_RISING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 604 * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
<> 144:ef7eb2e8f9f7 605 * @return None
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 // disable capture interrupt flag
<> 144:ef7eb2e8f9f7 610 pwm->INTSTS = (u32Edge << u32ChannelNum);
<> 144:ef7eb2e8f9f7 611 }
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /**
<> 144:ef7eb2e8f9f7 614 * @brief This function get capture interrupt flag of selected channel
<> 144:ef7eb2e8f9f7 615 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 616 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 617 * @return Capture interrupt flag of specified channel
<> 144:ef7eb2e8f9f7 618 * @retval 0 Capture interrupt did not occurred
<> 144:ef7eb2e8f9f7 619 * @retval PWM_RISING_LATCH_INT_FLAG Rising edge latch interrupt occurred
<> 144:ef7eb2e8f9f7 620 * @retval PWM_FALLING_LATCH_INT_FLAG Falling edge latch interrupt occurred
<> 144:ef7eb2e8f9f7 621 * @retval PWM_RISING_FALLING_LATCH_INT_FLAG Rising and falling edge latch interrupt occurred
<> 144:ef7eb2e8f9f7 622 */
<> 144:ef7eb2e8f9f7 623 uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 return ((pwm->INTSTS >> u32ChannelNum) & PWM_RISING_FALLING_LATCH_INT_FLAG);
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @brief This function enable duty interrupt of selected channel
<> 144:ef7eb2e8f9f7 630 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 631 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 632 * @param[in] u32IntDutyType Duty interrupt type. It could be either
<> 144:ef7eb2e8f9f7 633 * - \ref PWM_DUTY_INT_MATCH_CMR_UP
<> 144:ef7eb2e8f9f7 634 * - \ref PWM_DUTY_INT_MATCH_CMR_DN
<> 144:ef7eb2e8f9f7 635 * @return None
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 void PWM_EnableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 // set duty interrupt type
<> 144:ef7eb2e8f9f7 640 pwm->INTCTL = (pwm->INTCTL & ~(PWM_DUTY_INT_MATCH_CMR_UP << u32ChannelNum)) | (u32IntDutyType << u32ChannelNum);
<> 144:ef7eb2e8f9f7 641 // enable duty interrupt
<> 144:ef7eb2e8f9f7 642 pwm->INTEN |= ((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /**
<> 144:ef7eb2e8f9f7 646 * @brief This function disable duty interrupt of selected channel
<> 144:ef7eb2e8f9f7 647 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 648 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 649 * @return None
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 void PWM_DisableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 pwm->INTEN &= ~((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /**
<> 144:ef7eb2e8f9f7 657 * @brief This function clears duty interrupt flag of selected channel
<> 144:ef7eb2e8f9f7 658 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 659 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 660 * @return None
<> 144:ef7eb2e8f9f7 661 */
<> 144:ef7eb2e8f9f7 662 void PWM_ClearDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 // write 1 clear
<> 144:ef7eb2e8f9f7 665 pwm->INTSTS = (1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum;
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @brief This function get duty interrupt flag of selected channel
<> 144:ef7eb2e8f9f7 670 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 671 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 672 * @return Duty interrupt flag of specified channel
<> 144:ef7eb2e8f9f7 673 * @retval 0 Duty interrupt did not occurred
<> 144:ef7eb2e8f9f7 674 * @retval 1 Duty interrupt occurred
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676 uint32_t PWM_GetDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 return(pwm->INTSTS & ((1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum) ? 1 : 0);
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @brief This function enable fault brake interrupt
<> 144:ef7eb2e8f9f7 683 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 684 * @param[in] u32BrakeSource This parameter is not used
<> 144:ef7eb2e8f9f7 685 * @return None
<> 144:ef7eb2e8f9f7 686 */
<> 144:ef7eb2e8f9f7 687 void PWM_EnableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 pwm->INTEN |= PWM_INTEN_BRKIEN_Msk;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /**
<> 144:ef7eb2e8f9f7 693 * @brief This function disable fault brake interrupt
<> 144:ef7eb2e8f9f7 694 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 695 * @param[in] u32BrakeSource This parameter is not used
<> 144:ef7eb2e8f9f7 696 * @return None
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698 void PWM_DisableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 pwm->INTEN &= ~PWM_INTEN_BRKIEN_Msk;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /**
<> 144:ef7eb2e8f9f7 704 * @brief This function clear fault brake interrupt of selected source
<> 144:ef7eb2e8f9f7 705 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 706 * @param[in] u32BrakeSource Fault brake source, could be either
<> 144:ef7eb2e8f9f7 707 * - \ref PWM_INTSTS_BRKIF0_Msk, or
<> 144:ef7eb2e8f9f7 708 * - \ref PWM_INTSTS_BRKIF1_Msk
<> 144:ef7eb2e8f9f7 709 * @return None
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 void PWM_ClearFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 pwm->INTSTS = u32BrakeSource;
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /**
<> 144:ef7eb2e8f9f7 717 * @brief This function get fault brake interrupt of selected source
<> 144:ef7eb2e8f9f7 718 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 719 * @param[in] u32BrakeSource Fault brake source, could be either
<> 144:ef7eb2e8f9f7 720 * - \ref PWM_INTSTS_BRKIF0_Msk, or
<> 144:ef7eb2e8f9f7 721 * - \ref PWM_INTSTS_BRKIF1_Msk
<> 144:ef7eb2e8f9f7 722 * @return Fault brake interrupt flag of specified source
<> 144:ef7eb2e8f9f7 723 * @retval 0 Fault brake interrupt did not occurred
<> 144:ef7eb2e8f9f7 724 * @retval 1 Fault brake interrupt occurred
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 uint32_t PWM_GetFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 return (pwm->INTSTS & u32BrakeSource ? 1 : 0);
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /**
<> 144:ef7eb2e8f9f7 732 * @brief This function enable period interrupt of selected channel
<> 144:ef7eb2e8f9f7 733 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 734 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 735 * @param[in] u32IntPeriodType Period interrupt type, could be either
<> 144:ef7eb2e8f9f7 736 * - \ref PWM_PERIOD_INT_UNDERFLOW
<> 144:ef7eb2e8f9f7 737 * - \ref PWM_PERIOD_INT_MATCH_CNR
<> 144:ef7eb2e8f9f7 738 * @return None
<> 144:ef7eb2e8f9f7 739 * @note All channels share the same period interrupt type setting.
<> 144:ef7eb2e8f9f7 740 */
<> 144:ef7eb2e8f9f7 741 void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 // set period interrupt type
<> 144:ef7eb2e8f9f7 744 pwm->INTCTL = (pwm->INTCTL & ~(PWM_PERIOD_INT_MATCH_CNR << u32ChannelNum)) | (u32IntPeriodType << u32ChannelNum);
<> 144:ef7eb2e8f9f7 745 // enable period interrupt
<> 144:ef7eb2e8f9f7 746 pwm->INTEN |= ((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /**
<> 144:ef7eb2e8f9f7 750 * @brief This function disable period interrupt of selected channel
<> 144:ef7eb2e8f9f7 751 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 752 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 753 * @return None
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755 void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 pwm->INTEN &= ~((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /**
<> 144:ef7eb2e8f9f7 761 * @brief This function clear period interrupt of selected channel
<> 144:ef7eb2e8f9f7 762 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 763 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 764 * @return None
<> 144:ef7eb2e8f9f7 765 */
<> 144:ef7eb2e8f9f7 766 void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 // write 1 clear
<> 144:ef7eb2e8f9f7 769 pwm->INTSTS = ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum);
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /**
<> 144:ef7eb2e8f9f7 773 * @brief This function get period interrupt of selected channel
<> 144:ef7eb2e8f9f7 774 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 775 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 776 * @return Period interrupt flag of specified channel
<> 144:ef7eb2e8f9f7 777 * @retval 0 Period interrupt did not occurred
<> 144:ef7eb2e8f9f7 778 * @retval 1 Period interrupt occurred
<> 144:ef7eb2e8f9f7 779 */
<> 144:ef7eb2e8f9f7 780 uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 return(pwm->INTSTS & ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum) ? 1 : 0);
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /*@}*/ /* end of group NUC472_442_PWM_Driver */
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /*@}*/ /* end of group NUC472_442_Device_Driver */
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/