Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_gpio.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**************************************************************************//**
<> 149:156823d33999 2 * @file GPIO.h
<> 149:156823d33999 3 * @version V3.00
<> 149:156823d33999 4 * $Revision: 21 $
<> 149:156823d33999 5 * $Date: 15/08/11 10:26a $
<> 149:156823d33999 6 * @brief M451 series GPIO driver header file
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 *
<> 149:156823d33999 11 ******************************************************************************/
<> 149:156823d33999 12 #ifndef __GPIO_H__
<> 149:156823d33999 13 #define __GPIO_H__
<> 149:156823d33999 14
<> 149:156823d33999 15
<> 149:156823d33999 16 #ifdef __cplusplus
<> 149:156823d33999 17 extern "C"
<> 149:156823d33999 18 {
<> 149:156823d33999 19 #endif
<> 149:156823d33999 20
<> 149:156823d33999 21 /** @addtogroup Standard_Driver Standard Driver
<> 149:156823d33999 22 @{
<> 149:156823d33999 23 */
<> 149:156823d33999 24
<> 149:156823d33999 25 /** @addtogroup GPIO_Driver GPIO Driver
<> 149:156823d33999 26 @{
<> 149:156823d33999 27 */
<> 149:156823d33999 28
<> 149:156823d33999 29 /** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
<> 149:156823d33999 30 @{
<> 149:156823d33999 31 */
<> 149:156823d33999 32
<> 149:156823d33999 33
<> 149:156823d33999 34 #define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */
<> 149:156823d33999 35
<> 149:156823d33999 36
<> 149:156823d33999 37 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 38 /* GPIO_MODE Constant Definitions */
<> 149:156823d33999 39 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 40 #define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
<> 149:156823d33999 41 #define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
<> 149:156823d33999 42 #define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
<> 149:156823d33999 43 #define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
<> 149:156823d33999 44
<> 149:156823d33999 45
<> 149:156823d33999 46 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 47 /* GPIO Interrupt Type Constant Definitions */
<> 149:156823d33999 48 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 49 #define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
<> 149:156823d33999 50 #define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
<> 149:156823d33999 51 #define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
<> 149:156823d33999 52 #define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
<> 149:156823d33999 53 #define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
<> 149:156823d33999 54
<> 149:156823d33999 55
<> 149:156823d33999 56 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 57 /* GPIO_INTTYPE Constant Definitions */
<> 149:156823d33999 58 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 59 #define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */
<> 149:156823d33999 60 #define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */
<> 149:156823d33999 61
<> 149:156823d33999 62
<> 149:156823d33999 63 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 64 /* GPIO_DBCTL Constant Definitions */
<> 149:156823d33999 65 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 66 #define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */
<> 149:156823d33999 67 #define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
<> 149:156823d33999 68
<> 149:156823d33999 69 #define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
<> 149:156823d33999 70 #define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */
<> 149:156823d33999 71
<> 149:156823d33999 72 #define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */
<> 149:156823d33999 73 #define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */
<> 149:156823d33999 74 #define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */
<> 149:156823d33999 75 #define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */
<> 149:156823d33999 76 #define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */
<> 149:156823d33999 77 #define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */
<> 149:156823d33999 78 #define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */
<> 149:156823d33999 79 #define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */
<> 149:156823d33999 80 #define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */
<> 149:156823d33999 81 #define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */
<> 149:156823d33999 82 #define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */
<> 149:156823d33999 83 #define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */
<> 149:156823d33999 84 #define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */
<> 149:156823d33999 85 #define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */
<> 149:156823d33999 86 #define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */
<> 149:156823d33999 87 #define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */
<> 149:156823d33999 88
<> 149:156823d33999 89
<> 149:156823d33999 90 /* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
<> 149:156823d33999 91 Example 1:
<> 149:156823d33999 92
<> 149:156823d33999 93 PA0 = 1;
<> 149:156823d33999 94
<> 149:156823d33999 95 It is used to set GPIO PA.0 to high;
<> 149:156823d33999 96
<> 149:156823d33999 97 Example 2:
<> 149:156823d33999 98
<> 149:156823d33999 99 if (PA0)
<> 149:156823d33999 100 PA0 = 0;
<> 149:156823d33999 101
<> 149:156823d33999 102 If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
<> 149:156823d33999 103 */
<> 149:156823d33999 104 #define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
<> 149:156823d33999 105 #define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
<> 149:156823d33999 106 #define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
<> 149:156823d33999 107 #define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
<> 149:156823d33999 108 #define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
<> 149:156823d33999 109 #define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
<> 149:156823d33999 110 #define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
<> 149:156823d33999 111 #define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
<> 149:156823d33999 112 #define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
<> 149:156823d33999 113 #define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
<> 149:156823d33999 114 #define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
<> 149:156823d33999 115 #define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
<> 149:156823d33999 116 #define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
<> 149:156823d33999 117 #define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
<> 149:156823d33999 118 #define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
<> 149:156823d33999 119 #define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
<> 149:156823d33999 120 #define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
<> 149:156823d33999 121 #define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
<> 149:156823d33999 122 #define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
<> 149:156823d33999 123 #define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
<> 149:156823d33999 124 #define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
<> 149:156823d33999 125 #define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
<> 149:156823d33999 126 #define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
<> 149:156823d33999 127 #define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
<> 149:156823d33999 128 #define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
<> 149:156823d33999 129 #define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
<> 149:156823d33999 130 #define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
<> 149:156823d33999 131 #define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
<> 149:156823d33999 132 #define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
<> 149:156823d33999 133 #define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
<> 149:156823d33999 134 #define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
<> 149:156823d33999 135 #define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
<> 149:156823d33999 136 #define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
<> 149:156823d33999 137 #define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
<> 149:156823d33999 138 #define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
<> 149:156823d33999 139 #define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
<> 149:156823d33999 140 #define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
<> 149:156823d33999 141 #define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
<> 149:156823d33999 142 #define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
<> 149:156823d33999 143 #define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
<> 149:156823d33999 144 #define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
<> 149:156823d33999 145 #define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
<> 149:156823d33999 146 #define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
<> 149:156823d33999 147 #define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
<> 149:156823d33999 148 #define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
<> 149:156823d33999 149 #define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
<> 149:156823d33999 150 #define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
<> 149:156823d33999 151 #define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */
<> 149:156823d33999 152 #define PC15 GPIO_PIN_DATA(2, 15) /*!< Specify PC.15 Pin Data Input/Output */
<> 149:156823d33999 153 #define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
<> 149:156823d33999 154 #define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
<> 149:156823d33999 155 #define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
<> 149:156823d33999 156 #define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
<> 149:156823d33999 157 #define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
<> 149:156823d33999 158 #define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
<> 149:156823d33999 159 #define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
<> 149:156823d33999 160 #define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
<> 149:156823d33999 161 #define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
<> 149:156823d33999 162 #define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
<> 149:156823d33999 163 #define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
<> 149:156823d33999 164 #define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
<> 149:156823d33999 165 #define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
<> 149:156823d33999 166 #define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
<> 149:156823d33999 167 #define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
<> 149:156823d33999 168 #define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */
<> 149:156823d33999 169 #define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
<> 149:156823d33999 170 #define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
<> 149:156823d33999 171 #define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
<> 149:156823d33999 172 #define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
<> 149:156823d33999 173 #define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
<> 149:156823d33999 174 #define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
<> 149:156823d33999 175 #define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
<> 149:156823d33999 176 #define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
<> 149:156823d33999 177 #define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
<> 149:156823d33999 178 #define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
<> 149:156823d33999 179 #define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
<> 149:156823d33999 180 #define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
<> 149:156823d33999 181 #define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
<> 149:156823d33999 182 #define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
<> 149:156823d33999 183 #define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
<> 149:156823d33999 184 #define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
<> 149:156823d33999 185 #define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
<> 149:156823d33999 186 #define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
<> 149:156823d33999 187 #define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
<> 149:156823d33999 188 #define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
<> 149:156823d33999 189 #define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
<> 149:156823d33999 190 #define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
<> 149:156823d33999 191 #define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
<> 149:156823d33999 192
<> 149:156823d33999 193
<> 149:156823d33999 194 /*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
<> 149:156823d33999 195
<> 149:156823d33999 196
<> 149:156823d33999 197 /** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
<> 149:156823d33999 198 @{
<> 149:156823d33999 199 */
<> 149:156823d33999 200
<> 149:156823d33999 201 /**
<> 149:156823d33999 202 * @brief Clear GPIO Pin Interrupt Flag
<> 149:156823d33999 203 *
<> 149:156823d33999 204 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 205 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 206 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 207 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 208 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 209 *
<> 149:156823d33999 210 * @return None
<> 149:156823d33999 211 *
<> 149:156823d33999 212 * @details Clear the interrupt status of specified GPIO pin.
<> 149:156823d33999 213 */
<> 149:156823d33999 214 #define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
<> 149:156823d33999 215
<> 149:156823d33999 216 /**
<> 149:156823d33999 217 * @brief Disable Pin De-bounce Function
<> 149:156823d33999 218 *
<> 149:156823d33999 219 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 220 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 221 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 222 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 223 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 224 *
<> 149:156823d33999 225 * @return None
<> 149:156823d33999 226 *
<> 149:156823d33999 227 * @details Disable the interrupt de-bounce function of specified GPIO pin.
<> 149:156823d33999 228 */
<> 149:156823d33999 229 #define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
<> 149:156823d33999 230
<> 149:156823d33999 231 /**
<> 149:156823d33999 232 * @brief Enable Pin De-bounce Function
<> 149:156823d33999 233 *
<> 149:156823d33999 234 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 235 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 236 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 237 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 238 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 239 * @return None
<> 149:156823d33999 240 *
<> 149:156823d33999 241 * @details Enable the interrupt de-bounce function of specified GPIO pin.
<> 149:156823d33999 242 */
<> 149:156823d33999 243 #define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
<> 149:156823d33999 244
<> 149:156823d33999 245 /**
<> 149:156823d33999 246 * @brief Disable I/O Digital Input Path
<> 149:156823d33999 247 *
<> 149:156823d33999 248 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 249 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 250 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 251 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 252 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 253 *
<> 149:156823d33999 254 * @return None
<> 149:156823d33999 255 *
<> 149:156823d33999 256 * @details Disable I/O digital input path of specified GPIO pin.
<> 149:156823d33999 257 */
<> 149:156823d33999 258 #define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
<> 149:156823d33999 259
<> 149:156823d33999 260 /**
<> 149:156823d33999 261 * @brief Enable I/O Digital Input Path
<> 149:156823d33999 262 *
<> 149:156823d33999 263 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 264 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 265 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 266 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 267 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 268 *
<> 149:156823d33999 269 * @return None
<> 149:156823d33999 270 *
<> 149:156823d33999 271 * @details Enable I/O digital input path of specified GPIO pin.
<> 149:156823d33999 272 */
<> 149:156823d33999 273 #define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
<> 149:156823d33999 274
<> 149:156823d33999 275 /**
<> 149:156823d33999 276 * @brief Disable I/O DOUT mask
<> 149:156823d33999 277 *
<> 149:156823d33999 278 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 279 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 280 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 281 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 282 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 283 *
<> 149:156823d33999 284 * @return None
<> 149:156823d33999 285 *
<> 149:156823d33999 286 * @details Disable I/O DOUT mask of specified GPIO pin.
<> 149:156823d33999 287 */
<> 149:156823d33999 288 #define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
<> 149:156823d33999 289
<> 149:156823d33999 290 /**
<> 149:156823d33999 291 * @brief Enable I/O DOUT mask
<> 149:156823d33999 292 *
<> 149:156823d33999 293 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 294 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 295 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 296 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 297 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 298 *
<> 149:156823d33999 299 * @return None
<> 149:156823d33999 300 *
<> 149:156823d33999 301 * @details Enable I/O DOUT mask of specified GPIO pin.
<> 149:156823d33999 302 */
<> 149:156823d33999 303 #define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
<> 149:156823d33999 304
<> 149:156823d33999 305 /**
<> 149:156823d33999 306 * @brief Get GPIO Pin Interrupt Flag
<> 149:156823d33999 307 *
<> 149:156823d33999 308 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 309 * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
<> 149:156823d33999 310 * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
<> 149:156823d33999 311 * It could be BIT0 ~ BIT14 for PE.
<> 149:156823d33999 312 * It could be BIT0 ~ BIT7 for PF.
<> 149:156823d33999 313 *
<> 149:156823d33999 314 * @retval 0 No interrupt at specified GPIO pin
<> 149:156823d33999 315 * @retval 1 The specified GPIO pin generate an interrupt
<> 149:156823d33999 316 *
<> 149:156823d33999 317 * @details Get the interrupt status of specified GPIO pin.
<> 149:156823d33999 318 */
<> 149:156823d33999 319 #define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
<> 149:156823d33999 320
<> 149:156823d33999 321 /**
<> 149:156823d33999 322 * @brief Set De-bounce Sampling Cycle Time
<> 149:156823d33999 323 *
<> 149:156823d33999 324 * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
<> 149:156823d33999 325 * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
<> 149:156823d33999 326 * - \ref GPIO_DBCTL_DBCLKSEL_1
<> 149:156823d33999 327 * - \ref GPIO_DBCTL_DBCLKSEL_2
<> 149:156823d33999 328 * - \ref GPIO_DBCTL_DBCLKSEL_4
<> 149:156823d33999 329 * - \ref GPIO_DBCTL_DBCLKSEL_8
<> 149:156823d33999 330 * - \ref GPIO_DBCTL_DBCLKSEL_16
<> 149:156823d33999 331 * - \ref GPIO_DBCTL_DBCLKSEL_32
<> 149:156823d33999 332 * - \ref GPIO_DBCTL_DBCLKSEL_64
<> 149:156823d33999 333 * - \ref GPIO_DBCTL_DBCLKSEL_128
<> 149:156823d33999 334 * - \ref GPIO_DBCTL_DBCLKSEL_256
<> 149:156823d33999 335 * - \ref GPIO_DBCTL_DBCLKSEL_512
<> 149:156823d33999 336 * - \ref GPIO_DBCTL_DBCLKSEL_1024
<> 149:156823d33999 337 * - \ref GPIO_DBCTL_DBCLKSEL_2048
<> 149:156823d33999 338 * - \ref GPIO_DBCTL_DBCLKSEL_4096
<> 149:156823d33999 339 * - \ref GPIO_DBCTL_DBCLKSEL_8192
<> 149:156823d33999 340 * - \ref GPIO_DBCTL_DBCLKSEL_16384
<> 149:156823d33999 341 * - \ref GPIO_DBCTL_DBCLKSEL_32768
<> 149:156823d33999 342 *
<> 149:156823d33999 343 * @return None
<> 149:156823d33999 344 *
<> 149:156823d33999 345 * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
<> 149:156823d33999 346 * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
<> 149:156823d33999 347 * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
<> 149:156823d33999 348 * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
<> 149:156823d33999 349 * and system will sampling interrupt input once per 00 us.
<> 149:156823d33999 350 */
<> 149:156823d33999 351 #define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
<> 149:156823d33999 352
<> 149:156823d33999 353 /**
<> 149:156823d33999 354 * @brief Get GPIO Port IN Data
<> 149:156823d33999 355 *
<> 149:156823d33999 356 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 357 *
<> 149:156823d33999 358 * @return The specified port data
<> 149:156823d33999 359 *
<> 149:156823d33999 360 * @details Get the PIN register of specified GPIO port.
<> 149:156823d33999 361 */
<> 149:156823d33999 362 #define GPIO_GET_IN_DATA(port) ((port)->PIN)
<> 149:156823d33999 363
<> 149:156823d33999 364 /**
<> 149:156823d33999 365 * @brief Set GPIO Port OUT Data
<> 149:156823d33999 366 *
<> 149:156823d33999 367 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 368 * @param[in] u32Data GPIO port data.
<> 149:156823d33999 369 *
<> 149:156823d33999 370 * @return None
<> 149:156823d33999 371 *
<> 149:156823d33999 372 * @details Set the Data into specified GPIO port.
<> 149:156823d33999 373 */
<> 149:156823d33999 374 #define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
<> 149:156823d33999 375
<> 149:156823d33999 376 /**
<> 149:156823d33999 377 * @brief Toggle Specified GPIO pin
<> 149:156823d33999 378 *
<> 149:156823d33999 379 * @param[in] u32Pin Pxy
<> 149:156823d33999 380 *
<> 149:156823d33999 381 * @return None
<> 149:156823d33999 382 *
<> 149:156823d33999 383 * @details Toggle the specified GPIO pint.
<> 149:156823d33999 384 */
<> 149:156823d33999 385 #define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
<> 149:156823d33999 386
<> 149:156823d33999 387
<> 149:156823d33999 388 /**
<> 149:156823d33999 389 * @brief Enable External GPIO interrupt
<> 149:156823d33999 390 *
<> 149:156823d33999 391 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 392 * @param[in] u32Pin The pin of specified GPIO port.
<> 149:156823d33999 393 * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
<> 149:156823d33999 394 * It could be 0 ~ 14 for PE GPIO port.
<> 149:156823d33999 395 * It could be 0 ~ 7 for PF GPIO port.
<> 149:156823d33999 396 * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
<> 149:156823d33999 397 * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
<> 149:156823d33999 398 *
<> 149:156823d33999 399 * @return None
<> 149:156823d33999 400 *
<> 149:156823d33999 401 * @details This function is used to enable specified GPIO pin interrupt.
<> 149:156823d33999 402 */
<> 149:156823d33999 403 #define GPIO_EnableEINT GPIO_EnableInt
<> 149:156823d33999 404
<> 149:156823d33999 405 /**
<> 149:156823d33999 406 * @brief Disable External GPIO interrupt
<> 149:156823d33999 407 *
<> 149:156823d33999 408 * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
<> 149:156823d33999 409 * @param[in] u32Pin The pin of specified GPIO port.
<> 149:156823d33999 410 * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
<> 149:156823d33999 411 * It could be 0 ~ 14 for PE GPIO port.
<> 149:156823d33999 412 * It could be 0 ~ 7 for PF GPIO port.
<> 149:156823d33999 413 *
<> 149:156823d33999 414 * @return None
<> 149:156823d33999 415 *
<> 149:156823d33999 416 * @details This function is used to enable specified GPIO pin interrupt.
<> 149:156823d33999 417 */
<> 149:156823d33999 418 #define GPIO_DisableEINT GPIO_DisableInt
<> 149:156823d33999 419
<> 149:156823d33999 420
<> 149:156823d33999 421 void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
<> 149:156823d33999 422 void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
<> 149:156823d33999 423 void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
<> 149:156823d33999 424
<> 149:156823d33999 425
<> 149:156823d33999 426 /*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
<> 149:156823d33999 427
<> 149:156823d33999 428 /*@}*/ /* end of group GPIO_Driver */
<> 149:156823d33999 429
<> 149:156823d33999 430 /*@}*/ /* end of group Standard_Driver */
<> 149:156823d33999 431
<> 149:156823d33999 432
<> 149:156823d33999 433 #ifdef __cplusplus
<> 149:156823d33999 434 }
<> 149:156823d33999 435 #endif
<> 149:156823d33999 436
<> 149:156823d33999 437 #endif // __GPIO_H__
<> 149:156823d33999 438
<> 149:156823d33999 439 /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/